Pixel circuit

Abstract

A pixel circuit is provided. The pixel circuit includes a first scanning TFT, a first storage capacitor, a first driving TFT, a first light-emitting device, a second scanning TFT, a second driving TFT, and a second light-emitting device. The first scanning TFT receives a first data voltage. The first storage capacitor maintains a first gate voltage corresponding to the first data voltage. The first driving TFT has a gate connected to the first storage capacitor and controls the amount of a first driving current based on the first gate voltage. The first light-emitting device emits light according to the first driving current. The second scanning TFT receives a second data voltage in response to a transmission control signal. The second driving TFT has a gate connected to the gate of the first driving TFT and a source for receiving the second data voltage. The second driving TFT controls the amount of a second driving current based on the difference between the first gate voltage and the second gate voltage. The second light-emitting device emits light according to the second driving current.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0071859, filed on June 12, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] One or more implementations relate to pixel circuits and organic light-emitting displays, and more specifically, to a plurality of pixel circuits that are adjacent to each other. Background Technology

[0004] Organic light-emitting displays (OLEDs) include light-emitting devices with brightness that varies with current, such as organic light-emitting diodes (OLEDs). The pixel circuitry of an OLED includes an OLED, a drive transistor that controls the amount of current output to the OLED based on the voltage between its gate and source, a switching transistor that transmits a data voltage used to control the brightness of the OLED to the drive transistor, and a storage capacitor that stores the data voltage.

[0005] As the applications of display devices diversify and users' viewing angles become more advanced, the proportion of the total area occupied by the display area for displaying images is continuously increasing. Therefore, research is underway to add various functions to the display area beyond simply displaying images. To operate these additional functions, transmissive areas can be arranged within the corresponding regions. Furthermore, methods to reduce the area of ​​pixels within these corresponding regions are needed.

[0006] The information disclosed in this background section is only for understanding the background of the concept of the present invention, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0007] One or more embodiments include pixel circuits capable of reducing the area of ​​pixels and organic light-emitting displays including pixel circuits.

[0008] Additional aspects will be set forth in part in the detailed description below, and will be apparent in part from this description, or may be learned by practicing this embodiment.

[0009] According to one or more embodiments, a pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuit may include a first scanning thin-film transistor (TFT), a first storage capacitor, a first driving TFT, and a first light-emitting device. The first scanning TFT receives a first data voltage in response to a first scanning signal. The first storage capacitor maintains a first gate voltage corresponding to the first data voltage. The first driving TFT has a gate connected to the first storage capacitor and controls the amount of a first driving current based on the first gate voltage. The first light-emitting device emits light according to the first driving current. The second pixel circuit may include a second scanning TFT, a second driving TFT, and a second light-emitting device. The second scanning TFT receives a second data voltage in response to a transmission control signal. The second driving TFT has a gate connected to the gate of the first driving TFT and a source that receives the second data voltage through the second scanning TFT. The second driving TFT controls the amount of a second driving current based on the difference between the first gate voltage and the second data voltage. The second light-emitting device emits light according to the second driving current.

[0010] According to one or more embodiments, an organic light-emitting display includes a substrate, a first pixel, and a second pixel. A first display area and a second display area are defined on the substrate. The first pixel is disposed in the first display area and is implemented as a first pixel circuit. The second pixel is disposed in the second display area and includes two pixels, each implemented as a first pixel circuit and a second pixel circuit. The first pixel circuit may include a first scanning TFT, a first storage capacitor, a first driving TFT, and a first light-emitting device. The first scanning TFT receives a first data voltage in response to a first scanning signal. The first storage capacitor maintains a first gate voltage corresponding to the first data voltage. The first driving TFT has a gate connected to the first storage capacitor and controls the amount of a first driving current based on the first gate voltage. The first light-emitting device emits light according to the first driving current. The second pixel circuit may include a second scanning TFT, a second driving TFT, and a second light-emitting device. The second scanning TFT receives a second data voltage in response to a transmission control signal. The second driving TFT has a gate connected to the gate of the first driving TFT and a source that receives the second data voltage through the second scanning TFT. The second driving TFT controls the amount of a second driving current based on the difference between the first gate voltage and the second gate voltage. The second light-emitting device emits light according to the second driving current.

[0011] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0012] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a perspective view showing an electronic device including a display device according to an embodiment;

[0014] Figure 2 This is a cross-sectional view showing a portion of an electronic device including a display device according to an embodiment;

[0015] Figure 3 This is a block diagram illustrating an organic light-emitting display according to an embodiment;

[0016] Figure 4 This is a view showing the pixel circuitry of the first pixel according to an embodiment;

[0017] Figure 5 It is used for operation during a frame. Figure 4 The timing diagram of the control signals for the first pixel shown;

[0018] Figure 6 This is a view showing the pixel circuitry of the second pixel according to an embodiment;

[0019] Figure 7 This is a view showing the pixel circuitry of the second pixel according to another embodiment;

[0020] Figure 8 This is a view showing the pixel circuitry of the second pixel according to another embodiment;

[0021] Figure 9 This is a view showing the pixel circuitry of the second pixel according to another embodiment;

[0022] Figure 10 This is a view showing the pixel circuitry of a second pixel according to another embodiment; and

[0023] Figure 11 This is a view showing the pixel circuitry of the second pixel according to another embodiment. Detailed Implementation

[0024] In the following description, numerous specific details are set forth for purposes of explanation to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “implementation” and “method” are interchangeable terms and are non-limiting examples of devices or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without specific details or in one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, a particular shape, configuration, and characteristic of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0025] Unless otherwise specified, the exemplary embodiments shown should be understood as exemplary features providing details of variations in some ways that enable the implementation of the inventive concept in practice. Therefore, unless otherwise specified, features, components, modules, layers, films, panels, areas and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0026] Crosshairs and / or shading are typically provided in the accompanying drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, properties, performance, etc., of the elements. Additionally, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, similar reference numerals denote similar elements.

[0027] The D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system (such as the x, y, and z axes) and can be interpreted in a broader sense. For example, the D1, D2, and D3 axes may be perpendicular to each other or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from a cluster of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] Spatial relative terms such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein for descriptive purposes and, therefore, to describe the relationship between one element and another as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the exemplary term “below” can cover both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or otherwise), and thus, the spatial relative descriptive terms used herein are interpreted accordingly.

[0029] The technical terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used herein are intended to include the plural forms as well. Furthermore, when the terms “comprise,” “comprising,” “include,” and / or “including” are used in this specification, they indicate the presence of stated features, integers, steps, operations, elements, components, and / or clusters thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or clusters thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and similar terms are used as approximations rather than terms of degree, and are thus utilized to account for inherent deviations in measured, calculated, and / or provided values ​​that would be recognized by those skilled in the art.

[0030] Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms, such as those defined in common dictionaries, should be interpreted as having the meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0031] Referring now to the embodiments, examples of which are illustrated in the accompanying drawings, where similar reference numerals consistently indicate similar elements. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments are described below solely by reference to the accompanying drawings to explain various aspects of this specification. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all or variations thereof of a, b, and c.

[0032] Because this disclosure can be implemented in various ways, preferred embodiments are shown in the accompanying drawings and described in detail. The effects and features of this disclosure, as well as the methods of implementing them, will become apparent when referring to the embodiments described with reference to the accompanying drawings. However, this disclosure can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0033] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Exemplary embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used to indicate the same elements, and repeated descriptions thereof will be omitted.

[0034] It will be understood that while terms such as “first,” “second,” and “third” may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. Unless they have a clearly different meaning in the context, singular expressions cover plural expressions. It will be understood that when a unit is referred to as “connected” to another element, it may be “directly connected” to the other element or “electrically connected” to the other element in the presence of an intermediate element. Furthermore, it will be understood that when a unit is referred to as “comprising” another element, it may include other elements rather than exclude them, unless specifically indicated to the contrary.

[0035] Figure 1 This is a perspective view showing an electronic device 1000 including a display device according to an embodiment.

[0036] Reference Figure 1The electronic device 1000 includes a display area DA and a non-display area NDA. The non-display area NDA may be outside the display area DA. The electronic device 1000 may display an image by means of a plurality of pixels P1 and P2 arranged in a matrix in the display area DA. The plurality of pixels P1 and P2 may include a first pixel P1 arranged in a first display area DA1 and a second pixel P2 arranged in a second display area DA2.

[0037] The electronic device 1000 can display a first image by using light emitted from a first pixel P1 arranged in a first display area DA1, and can display a second image by using light emitted from a second pixel P2 arranged in a second display area DA2. According to some embodiments, the electronic device 1000 can display a single image by combining the first image and the second image. According to some embodiments, the electronic device 1000 can display a first image and a second image that are independent of each other.

[0038] The second display area DA2 may include a transmissive region TA located between the second pixels P2. The transmissive region TA is a region through which light can pass, and no pixels are arranged in the transmissive region TA.

[0039] The non-display area NDA is the area where no image is displayed and may completely surround the display area DA. Driving circuitry configured to provide electrical signals to the first pixel P1 and the second pixel P2, or power wiring configured to supply power to the first pixel P1 and the second pixel P2, may be arranged in the non-display area NDA. Pads may be arranged in the non-display area NDA, and electronic devices or printed circuit boards may be electrically connected to the pads.

[0040] like Figure 1 As shown, on a plane, the second display area DA2 may have a circular or elliptical shape. According to another example, the second display area DA2 may have a polygonal shape such as a square or a bar shape.

[0041] like Figure 1 As shown, the second display area DA2 may be inside the first display area DA1. According to another example, the second display area DA2 may, for example, be within... Figure 1 On one side of the first display area DA1 in the y-axis direction.

[0042] like Figure 1 As shown, the second display area DA2 can be completely surrounded by the first display area DA1. According to another example, the second display area DA2 can be partially surrounded by the first display area DA1. For example, the second display area DA2 can be located at a corner of the first display area DA1, and in this case, the second display area DA2 can be partially surrounded by the first display area DA1.

[0043] The area of ​​the first display area DA1 may be significantly larger than the area of ​​the second display area DA2. The first display area DA1 may be referred to as the main display area, and the second display area DA2 may be referred to as the under-panel camera (UPC) area. The electronic device 1000 may include, for example... Figure 1 The second display area DA2 shown may include two or more second display areas DA2.

[0044] Electronic device 1000 may include mobile phones, tablet PCs, laptop computers, and smartwatches or smart watchbands worn on the wrist.

[0045] Figure 2 This is a cross-sectional view showing a portion of an electronic device 1000 including a display device 100 according to an embodiment.

[0046] Reference Figure 2 The electronic device 1000 includes a display device 100 and a component 200. The component 200 may be arranged to overlap with the display device 100.

[0047] The display device 100 may include a substrate 10, a display layer 20, a thin film encapsulation layer 30, an input sensing layer 40, an optical functional layer 50, an anti-reflection layer 60, and a window 70.

[0048] Component 200 may be located in the second display area DA2. Component 200 may be an electronic device that inputs or outputs light or sound. For example, the electronic device may be a sensor for measuring distance (such as a proximity sensor), a sensor for identifying a part of a user's body (e.g., fingerprint, iris, face, etc.), a small light outputting light, an image sensor for capturing images (e.g., a camera), and the like. The electronic device may use light of various wavelength bands, such as visible light, infrared light, and ultraviolet light. The electronic device may use ultrasonic waves or other frequency bands of sound. According to some embodiments, component 200 may include sub-components, such as a light emitter and a light receiver. The light emitter and the light receiver may have an integral structure, or a pair of light emitters and light receivers may constitute a single component 200 in physically separate structures.

[0049] Substrate 10 may comprise glass or a polymeric resin. For example, the polymeric resin may comprise polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, and the like. Substrate 10 comprising a polymeric resin may be flexible, rollable, or bendable. Substrate 10 may have a multilayer structure comprising a layer containing the polymeric resin and an inorganic layer (not shown).

[0050] The lower protective film 80 may be on the rear surface of the substrate 10. The lower protective film 80 may be attached to the rear surface of the substrate 10. An adhesive layer may be present between the lower protective film 80 and the substrate 10. According to another embodiment, the lower protective film 80 may be formed directly on the rear surface of the substrate 10.

[0051] The lower protective film 80 supports and protects the substrate 10. An opening 80OP corresponding to the second display area DA2 can be located within the lower protective film 80. The opening 80OP of the lower protective film 80 is a recess formed by removing a portion of the lower protective film 80 in its thickness direction. Figure 2 As shown, the opening 80OP may have a shape such as a through hole, while a portion of the lower protective film 80 is completely removed in the thickness direction of the lower protective film 80. According to another example, the opening 80OP may have a shape of a blind hole in which a portion of the lower protective film 80 is removed in the thickness direction of the lower protective film 80 and one side is blocked.

[0052] By forming an opening 80OP in the lower protective film 80, the transmittance of the second display area DA2 can be improved, for example, the transmittance of the transmission area TA. The lower protective film 80 may include an organic insulating material, such as polyethylene terephthalate (PET) or polyimide (PI).

[0053] Display layer 20 may be located on the front surface of substrate 10. Display layer 20 may include multiple pixels. Each pixel may include a display device or light-emitting device that emits red, green, or blue light. The display device may include an organic light-emitting diode (OLED).

[0054] The display layer 20 may include a display device layer, a circuit device layer, and multiple insulating layers 11 and 1L. The display device layer includes an organic light-emitting diode (OLED) as a display device, and the circuit device layer includes a thin-film transistor (TFT) electrically connected to the OLED. The TFT and the OLED electrically connected to the TFT may be arranged in a first display area DA1 and a second display area DA2, respectively.

[0055] The second display area DA2 may include a transmissive area TA that is not equipped with thin-film transistors (TFTs) and organic light-emitting diodes (OLEDs). The transmissive area TA is a region through which light emitted from and / or guided to the component 200 can pass. In the display device 100, the transmittance of the transmissive area TA may be about 30% or greater, about 40% or greater, about 50% or greater, about 60% or greater, about 70% or greater, about 75% or greater, about 80% or greater, about 85% or greater, or about 90% or greater.

[0056] A back metal layer (BML) may be located between the substrate 10 and the display layer 20, for example, between the substrate 10 and the thin-film transistor (TFT). The back metal layer BML may include vias BML-TH through which light emitted from or directed to the component 200 may pass. The vias BML-TH of the back metal layer BML are positioned corresponding to the transmissive region TA. The back metal layer BML prevents diffraction of light through narrow gaps between pixel circuits or wiring arranged in the second display region DA2 and can improve the characteristics of the thin-film transistor (TFT). The back metal layer BML may not be disposed within the transmissive region TA. For example, the back metal layer BML may include vias corresponding to the transmissive region TA.

[0057] The display layer 20 can be sealed with a sealing member. According to an embodiment, the sealing member may include, for example... Figure 2 The thin-film encapsulation layer 30 shown is disposed on the display layer 20. The thin-film encapsulation layer 30 may include at least one inorganic film and at least one organic film. According to an example, the thin-film encapsulation layer 30 may include a first inorganic film 31 and a second inorganic film 33, and an organic film 32 therebetween.

[0058] According to another embodiment, the sealing member may include an encapsulation substrate. The encapsulation substrate may be on the display layer 20, and the display layer 20 may be between the substrate 10 and the encapsulation substrate. A gap may exist between the encapsulation substrate and the display layer 20. The encapsulation substrate may include glass. A sealant may be between the substrate 10 and the encapsulation substrate, and the sealant may be disposed on... Figure 1 The non-display area NDA is shown in the diagram. A sealant is arranged around the display area DA to prevent moisture from penetrating into the display area DA through the side surfaces.

[0059] The input sensing layer 40 detects external input, such as touch from an object like a finger or stylus, so that the electronic device 1000 can obtain coordinate information corresponding to the touch location. The input sensing layer 40 may include touch electrodes and traces connected to the touch electrodes. The input sensing layer 40 may use mutual capacitance or self-capacitance methods to detect external input.

[0060] The input sensing layer 40 may be on the sealing member. According to one example, the input sensing layer 40 may be formed directly on the thin-film encapsulation layer 30 or the encapsulation substrate. According to another example, the input sensing layer 40 may be formed separately and then bonded to the sealing member by an adhesive layer such as an optically clear adhesive OCA.

[0061] The optical functional layer 50 can improve light efficiency. For example, the optical functional layer 50 can improve the front light efficiency and / or side visibility of light emitted from the organic light-emitting diode OLED. In addition, it can minimize or prevent diffraction of light that passes through the transmission region TA and is directed toward or emitted from the component 200.

[0062] The antireflective layer 60 reduces the reflectivity of light (external light) incident from the outside toward the display device 100. According to an example, the antireflective layer 60 may include an optical plate such as a retarder and / or a polarizer. The retarder may be a film-type or liquid crystal-coated type, and may be a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film-type or liquid crystal-coated type. A film-type polarizer may include a stretched synthetic resin film, and a liquid crystal-coated polarizer may include liquid crystals arranged in a specific layout.

[0063] According to an example, the antireflective layer 60 may include a filter, such as a black matrix and / or a color filter. According to an example, the antireflective layer 60 may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer on respective layers. First reflected light and second reflected light reflected by the first reflective layer and the second reflective layer, respectively, can destructively interfere, and thus reduce external light reflectivity.

[0064] Window 70 may be on antireflective layer 60 and may be bonded to antireflective layer 60 by an adhesive layer such as optically clear adhesive OCA. Although in Figure 2 The central window 70 is shown arranged on the anti-reflective layer 60, but according to another embodiment, the positions of the anti-reflective layer 60 and the optical functional layer 50 can be changed. In this case, the window 70 can be bonded to the optical functional layer 50 by an adhesive layer such as optically clear adhesive OCA. According to another embodiment, the optically clear adhesive OCA can be omitted below the window 70.

[0065] A component 200 may be located in the second display area DA2, or multiple components 200 may be arranged therein. When the electronic device 1000 includes multiple components 200, the number of second display areas DA2 of the electronic device 1000 may correspond to the number of components 200. For example, the electronic device 1000 may include multiple second display areas DA2 that are separated from each other. According to another example, multiple components 200 may be arranged in one second display area DA2. For example, the electronic device 1000 may include a strip-shaped second display area DA2, and multiple components 200 may be arranged along the length of the second display area DA2 (e.g., Figure 1 They are separated from each other in the x-direction.

[0066] exist Figure 2 The present invention illustrates an embodiment in which a display device 100 includes an organic light-emitting diode (OLED) as a display device, but the display device 100 is not limited thereto. According to another embodiment, the display device 100 may be a light-emitting display (inorganic light-emitting display or inorganic EL display) including an inorganic light-emitting device such as a micro-LED, or a light-emitting display device such as a quantum dot light-emitting display. For example, the light-emitting layer of the display element disposed in the display device 100 may include organic matter, inorganic matter, quantum dots, organic matter and quantum dots, or inorganic matter and quantum dots.

[0067] Figure 3 This is a block diagram illustrating an organic light-emitting display 100 according to an embodiment.

[0068] Reference Figure 3 The organic light-emitting display 100 includes a display unit 110, a gate driver 120, a data driver 130, a timing controller 140, and a voltage generator 150.

[0069] Display unit 110 includes pixels, such as a first pixel PX1ij located in the i-th row and j-th column, where i is a natural number of 1 or greater and m or less, and j is a natural number of 1 or greater and n or less. For ease of understanding, in Figure 3 Only one first pixel PX1ij is shown, but the display unit 110 includes, for example, components arranged in a matrix in the first display area. Figure 1 The first pixel P1 in DA1 and the second pixel P2 arranged in the second display area DA2 are collectively referred to as pixels. The following will refer to... Figures 4 to 11 A more detailed description is given for each of the first pixel P1 and the second pixel P2.

[0070] Multiple pixels are connected to multiple first scan lines SL1_1 to SL1_m, multiple second scan lines SL2_1 to SL2_m+1, multiple transmit control lines EML_1 to EML_m, and multiple data lines DL_1 to DL_n. Multiple pixels are also connected to multiple power lines PL_1 to PL_n and multiple voltage lines VL_1 to VL_m. For example, as... Figure 3 As shown, the first pixel PX1ij can be connected to the first scan line SL1_i, the second scan line SL2_i, the transmit control line EML_i, the data line DL_j, the power line PL_j, the voltage line VL_i, and the second scan line SL2_i+1. The second scan line SL2_i+1 can be referred to as the third scan line relative to the first pixel PX1ij.

[0071] Multiple first scan lines SL1_1 to SL1_m, multiple second scan lines SL2_1 to SL2_m+1, multiple emitter control lines EML_1 to EML_m, and multiple voltage lines VL_1 to VL_m may extend in a first direction (e.g., row direction) and connect to pixels located in the same row. Multiple data lines DL_1 to DL_n and multiple power lines PL_1 to PL_n may extend in a second direction (e.g., column direction) and connect to pixels located in the same column.

[0072] Multiple first scan lines SL1_1 to SL1_m transmit multiple first scan signals GW_1 to GW_m output from gate driver 120 to pixels in the same row, respectively. Multiple second scan lines SL2_1 to SL2_m transmit multiple second scan signals GI_1 to GI_m output from gate driver 120 to pixels in the same row, respectively. Multiple second scan lines SL2_2 to SL2_m+1 transmit multiple third scan signals GB_1 to GB_m output from gate driver 120 to pixels in the same row, respectively. The second scan signal GI_i and the third scan signal GB_i-1 are transmitted through the second scan line SL2_i and can actually be the same signal.

[0073] Multiple transmit control lines EML_1 to EML_m transmit transmit control signals EM_1 to EM_m output from gate driver 120 to pixels in the same row, respectively. Multiple data lines DL_1 to DL_n transmit multiple data voltages D1 to Dn output from data driver 130 to pixels in the same column, respectively. The first pixel PX1ij receives the first scan signal GW_i, the second scan signal GI_i, the third scan signal GB_i, the data voltage Dj, and the transmit control signal EM_i.

[0074] Multiple power lines PL_1 to PL_n transmit the first driving voltage ELVDD output from voltage generator 150 to pixels in the same column, respectively. Multiple voltage lines VL_1 to VL_m transmit the initialization voltage VINT output from voltage generator 150 to pixels in the same row.

[0075] The first pixel PX1ij includes a light-emitting device and a driving TFT that controls the amount of current flowing to the light-emitting device based on a data voltage Dj. The data voltage Dj is output from a data driver 130 and received by the first pixel PX1ij via a data line DL_j. The light-emitting device may be, for example, an organic light-emitting diode (OLED). Because the light-emitting device emits light with a brightness corresponding to the amount of current received from the driving TFT, the first pixel PX1ij can represent a grayscale level corresponding to the data voltage Dj. A pixel may correspond to a portion of a unit pixel capable of displaying full color, for example, a sub-pixel. The first pixel PX1ij may also include at least one switching TFT and at least one capacitor. Reference will be made below. Figure 4 and Figure 5 A more detailed description is given of the first pixel PX1ij.

[0076] Voltage generator 150 can generate voltages configured to drive the first pixel PX1ij. For example, voltage generator 150 can generate a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT. The level of the first driving voltage ELVDD can be higher than the level of the second driving voltage ELVSS. The level of the initialization voltage VINT can be higher than the level of the second driving voltage ELVSS. The level difference between the initialization voltage VINT and the second driving voltage ELVSS can be less than the threshold voltage for light emission by the light-emitting device of the pixel.

[0077] Voltage generator 150 generates a first gate voltage VGH and a second gate voltage VGL configured to control a switching transistor of the first pixel PX1ij, and provides the generated first gate voltage VGH and second gate voltage VGL to gate driver 120. When the first gate voltage VGH is applied to the gate of the switching transistor, the switching transistor can be turned off, and when the second gate voltage VGL is applied to the gate of the switching transistor, the switching transistor can be turned on. The first gate voltage VGH may be referred to as the gate turn-off voltage, and the second gate voltage VGL may be referred to as the gate turn-on voltage. The switching transistor of the first pixel PX1ij may be a p-type MOSFET, and the level of the first gate voltage VGH may be higher than the level of the second gate voltage VGL. Although in Figure 3 It is not shown in the figure, but voltage generator 150 can generate gamma reference voltages and provide them to data driver 130.

[0078] The timing controller 140 controls the display unit 110 by controlling the operating timing of the gate driver 120 and the data driver 130. Pixels of the display unit 110 can receive a new data voltage and emit light with a brightness corresponding to the new data voltage in each frame period, thereby displaying an image corresponding to the RGB image source data of a frame. According to an embodiment, a frame period may include a gate initialization period, a data writing and anode initialization period, and a light emission period. During the initialization period, an initialization voltage VINT can be applied to the pixel synchronously with a plurality of second scan signals GI_1 to GI_m. During the data writing and anode initialization period, a plurality of data voltages D1 to Dn are provided to the pixel synchronously with a plurality of first scan signals GW_1 to GW_m, and the initialization voltage VINT can be applied to the pixel synchronously with a plurality of third scan signals GB_1 to GB_m. During the light emission period, the pixels of the display unit 110 can emit light.

[0079] The timing controller 140 receives image source data RGB and control signal CONT from an external source. Based on the characteristics of the display unit 110 and the pixels, the timing controller 140 converts the image source data RGB into image data DATA. The timing controller 140 then provides the image data DATA to the data driver 130.

[0080] The control signal CONT may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The timing controller 140 can use the control signal CONT to control the operating timing of the gate driver 120 and the data driver 130. The timing controller 140 can determine the frame period by counting the data enable signals for a horizontal scan period. In this case, the externally supplied vertical and horizontal synchronization signals can be omitted. The image source data RGB includes pixel brightness information. The brightness may have a specific number, for example, 1024 (=2). 10 ), 256 (=2 8 ) or 64 (=2 6 () gray level.

[0081] The timing controller 140 can generate control signals including a gate timing control signal GDC configured to control the operating timing of the gate driver 120 and a data timing control signal DDC configured to control the operating timing of the data driver 130.

[0082] The gate timing control signal GDC may include a gate start pulse, a gate shift clock, a gate output enable signal, and the like. The gate start pulse is supplied to the gate driver 120, which generates a first scan signal at the beginning of a scan period. The gate shift clock is a clock signal normally input to the gate driver 120 and is configured to shift the gate start pulse. The gate output enable signal controls the output of the gate driver 120.

[0083] The data timing control signal (DDC) may include a source start pulse, a source sampling clock, a source output enable signal, and the like. The source start pulse controls the start point of data sampling in the data driver 130 and is provided to the data driver 130 at the beginning of a scan period. The source sampling clock is a clock signal that controls the sampling operation of data in the data driver 130 based on the rising or falling edge. The source output enable signal controls the output of the data driver 130. Meanwhile, depending on the data transmission method, the source start pulse supplied to the data driver 130 may be omitted.

[0084] By using a first gate voltage VGH and a second gate voltage VGL provided from a voltage generator 150, and in response to a gate timing control signal GDC supplied from a timing controller 140, the gate driver 120 sequentially generates a plurality of first scan signals GW_1 to GW_m, a plurality of second scan signals GI_1 to GI_m, and a plurality of third scan signals GB_1 to GB_m.

[0085] Data driver 130 samples and latches image data DATA supplied from timing controller 140 in response to data timing control signal DDC supplied from timing controller 140, and converts the image data DATA into data in a parallel data system. While converting data in the parallel data system, data driver 130 converts the image data DATA into a gamma reference voltage and then converts the gamma reference voltage into an analog data voltage. Data driver 130 provides multiple data voltages D1 to Dn to the pixel via multiple data lines DL_1 to DL_n. The pixel receives the multiple data voltages D1 to Dn in response to multiple first scan signals GW_1 to GW_m.

[0086] Figure 4 This is a view showing the pixel circuit of the first pixel PX1ij according to an embodiment.

[0087] Reference Figure 4 The first pixel PX1ij is connected to a first scan line GWL_i, a second scan line GIL_i, and a third scan line GBL_i, respectively configured to transmit a first scan signal GW_i, a second scan signal GI_i, and a third scan signal GB_i; a data line DL_j configured to transmit a data voltage Dj; and a transmit control line EML_i configured to transmit a transmit control signal EM_i. The first pixel PX1ij is also connected to a power line PL_j configured to transmit a first drive voltage ELVDD and a voltage line VL_i configured to transmit an initialization voltage VINT. The first pixel PX1ij is connected to a common electrode to which a second drive voltage ELVSS is applied. The first pixel PX1ij may correspond to... Figure 3 The first pixel PX1ij.

[0088] The first scan line GWL_i corresponds to Figure 3 The first scan line SL1_i, the second scan line GIL_i corresponds to Figure 3 The second scan line SL2_i, and the third scan line GBL_i corresponds to Figure 3 The second scan line SL2_i+1.

[0089] The first pixel PX1ij includes a light-emitting device (OLED), first TFTs T1 to seventh TFTs T7, and a storage capacitor Cst. The light-emitting device OLED may be an organic light-emitting diode having an anode and a cathode. The cathode may be a common electrode to which a second driving voltage ELVSS is applied.

[0090] The first TFT T1 is a drive transistor whose drain current is determined based on the source-gate voltage, and the second TFT T2 to the seventh TFT T7 can be switching transistors that are turned on / off based on the source-gate voltage and essentially the gate voltage.

[0091] The first TFT T1 can be called the driving TFT, the second TFT T2 can be called the scanning TFT, the third TFT T3 can be called the compensation TFT, the fourth TFT T4 can be called the gate initialization TFT, the fifth TFT T5 can be called the first emission control TFT, the sixth TFT T6 can be called the second emission control TFT, and the seventh TFT T7 can be called the anode initialization TFT.

[0092] The driving TFT T1 can control the amount of driving current Id flowing from the power line PL_j to the light-emitting device OLED according to the gate voltage. The driving TFT T1 may have a gate connected to the lower electrode of the storage capacitor Cst, a source connected to the power line PL_j via a first emission control TFT T5, and a drain connected to the light-emitting device OLED via a second emission control TFT T6.

[0093] The driving TFT T1 outputs a driving current Id to the OLED light-emitting device. The amount of the driving current Id can be determined based on the gate voltage of the driving TFT T1. For example, the amount of the driving current Id can be determined based on the difference between the source-gate voltage and the threshold voltage of the driving TFT T1. The source-gate voltage of the driving TFT T1 corresponds to the difference between the gate voltage and the source voltage. The OLED light-emitting device can receive the driving current Id from the driving TFT T1 and emit light with brightness according to the amount of the driving current Id.

[0094] The scanning TFT T2 receives the data voltage Dj in response to the first scan signal GW_i. The scanning TFT T2 also transmits the data voltage Dj to the source of the driving TFT T1 in response to the first scan signal GW_i. The scanning TFT T2 may have a gate connected to the first scan line GWL_i, a source connected to the data line DL_j, and a drain connected to the source of the driving TFT T1.

[0095] A storage capacitor Cst is connected between the power line PL_j and the gate of the driving TFT T1. The storage capacitor Cst may have an upper electrode connected to the power line PL_j and a lower electrode connected to the gate of the driving TFT T1. The storage capacitor Cst can store the difference between the first driving voltage ELVDD applied to the power line PL_j and the gate voltage of the driving TFT T1, and can maintain the gate voltage of the driving TFT T1.

[0096] The compensation TFT T3 is connected in series between the drain and gate of the driving TFT T1, and the drain and gate of the driving TFT T1 can be connected to each other in response to the first scan signal GW_i. The compensation TFT T3 may have a gate connected to the first scan line GW_i, a source connected to the drain of the driving TFT T1, and a drain connected to the gate of the driving TFT T1. The compensation TFT T3 may be composed of multiple TFTs connected in series and synchronously controlled by the first scan signal GW_i.

[0097] When the compensation TFT T3 is turned on in response to the first scan signal GW_i, the drain and gate of the driving TFT T1 are connected to each other, allowing the driving TFT T1 to be connected by a diode. The source of the driving TFT T1 receives the data voltage Dj through the scanning TFT T2 in response to the first scan signal GW_i, and the data voltage Dj is transmitted to the gate of the driving TFT T1 through the diode-connected driving TFT T1. When the gate voltage of the driving TFT T1 becomes equal to the voltage equal to the data voltage Dj minus the threshold voltage of the driving TFT T1, the driving TFT T1 is turned off, and the gate voltage of the driving TFT T1 equal to the voltage equal to the data voltage Dj minus the threshold voltage of the driving TFT T1 is stored in the storage capacitor Cst.

[0098] The gate initialization TFT T4 applies an initialization voltage VINT to the gate of the driving TFT T1 in response to the second scan signal GI_i. The gate initialization TFT T4 may have a gate connected to the second scan line GIL_i, a source connected to the gate of the driving TFT T1, and a drain connected to the voltage line VL_i. The gate initialization TFT T4 may be composed of multiple TFTs connected in series and synchronously controlled by the second scan signal GI_i.

[0099] The anode initialization TFT T7 applies an initialization voltage VINT to the anode of the OLED in response to the third scan signal GB_i. The anode initialization TFT T7 may have a gate connected to the third scan line GBL_i, a source connected to the anode of the OLED, and a drain connected to the voltage line VL_i.

[0100] The first emission control TFT T5 can connect the power line PL_j and the source of the driving TFT T1 to each other in response to the emission control signal EM_i. The first emission control TFT T5 may have a gate connected to the emission control line EML_i, a source connected to the power line PL_j, and a drain connected to the source of the driving TFT T1.

[0101] The second emission control TFT T6 can connect the drain of the driving TFT T1 and the anode of the light-emitting device OLED to each other in response to the emission control signal EM_i. The second emission control TFT T6 may have a gate connected to the emission control line EML_i, a source connected to the drain of the driving TFT T1, and a drain connected to the anode of the light-emitting device OLED.

[0102] Figure 5 It is configured to operate during a frame. Figure 4 The timing diagram of the control signal for the first pixel PX1ij is shown.

[0103] and Figure 4 Refer to together Figure 5 During the period when the emission control signal EM_i is high, the first emission control TFT T5 and the second emission control TFT T6 are turned off, and the OLED does not emit light. The period when the emission control signal EM_i is high can be referred to as the non-emission period.

[0104] First, the second scan signal GI_i is low. At this time, the gate initialization TFT T4 is turned on, and the initialization voltage VINT is applied to the gate of the driving TFT T1. The period during which the second scan signal GI_i is low can be referred to as the gate initialization period.

[0105] After the second scan signal GI_i goes high again, the first scan signal GW_i goes low. At this time, as the data voltage Dj is received through the data line DL_j and the scan TFT T2 and compensation TFT T3 are turned on, the gate voltage corresponding to the data voltage Dj is stored in the storage capacitor Cst. The period during which the first scan signal GW_i is low can be referred to as the data write period.

[0106] The third scan signal GB_i is low. At this time, the anode initialization TFT T7 is turned on, and the initialization voltage VINT is applied to the anode of the OLED. The period during which the third scan signal GB_i is low can be referred to as the anode initialization period.

[0107] Subsequently, as the first scan signal GW_i and the third scan signal GB_i transition to high level and the emission control signal EM_i goes low level, the first emission control TFT T5 and the second emission control TFT T6 are turned on. The driving TFT T1 outputs a driving current Id based on the gate voltage stored in the storage capacitor Cst, and the light-emitting device OLED emits light according to the driving current Id. The period during which the emission control signal EM_i is low can be referred to as the emission period.

[0108] The second scan signal GI_i can be substantially synchronized with the first scan signal GW_i-1 of the previous row. The third scan signal GB_i can be substantially synchronized with the first scan signal GW_i. According to another example, the third scan signal GB_i can be substantially synchronized with the first scan signal GW_i+1 of the next row.

[0109] The detailed operation of the first pixel PX1ij of the organic light-emitting display 100 according to the embodiment will be described in detail below.

[0110] First, when a high-level transmit control signal EM_i is received, the first transmit control TFT T5 and the second transmit control TFT T6 are turned off, and the drive TFT T1 stops outputting the drive current Id, and the light-emitting device OLED stops emitting light.

[0111] Subsequently, during the gate initialization period upon receiving the low-level second scan signal GI_i, the gate initialization TFTT4 is turned on, and the initialization voltage VINT is applied to the gate of the driving TFT T1, i.e., the lower electrode of the storage capacitor Cst. The difference between the first driving voltage ELVDD and the initialization voltage VINT (ELVDD-VINT) is stored in the storage capacitor Cst.

[0112] Subsequently, during the data writing period when the first low-level scan signal GW_i is received, scan TFT T2 and compensation TFT T3 are turned on, and the data voltage Dj is received by the source of drive TFT T1. Drive TFT T1 is connected to the compensation TFT T3 diode and is biased in the forward direction. The gate voltage of drive TFT T1 rises at the initialization voltage VINT. When the gate voltage of drive TFT T1 is equal to the voltage Dj-|Vth| minus the threshold voltage Vth of drive TFT T1 from the data voltage Dj, drive TFT T1 is turned off, and the increase of the gate voltage of drive TFT T1 stops. Accordingly, the gate voltage of drive TFT T1 becomes Dj-|Vth|, and the difference between the first drive voltage ELVDD and the gate voltage Dj-|Vth| (ELVDD-Dj+|Vth|) is stored in the storage capacitor Cst.

[0113] Furthermore, during the anode initialization period when the low-level third scan signal GB_i is received, the anode initialization TFTT7 is turned on, and the initialization voltage VINT is applied to the anode of the OLED. By applying the initialization voltage VINT to the anode of the OLED to completely prevent light emission, the phenomenon of the OLED precisely emitting light corresponding to black grayscale in the next frame can be eliminated.

[0114] Subsequently, when a low-level transmit control signal EM_i is received, the first transmit control TFT T5 and the second transmit control TFT T6 are turned on, driving TFT T1 to output a drive current Id with an amount corresponding to the voltage stored in the storage capacitor Cst (i.e., the voltage ELVDD-Dj obtained by subtracting the threshold voltage |Vth| of the drive TFT T1 from the source-gate voltage ELVDD-Dj+|Vth| of the drive TFT T1), and the light-emitting device OLED can emit light with a brightness corresponding to the amount of drive current Id.

[0115] Figure 6 This is a view showing the pixel circuit of the second pixel P2 according to an embodiment.

[0116] Reference Figure 6 ,like Figure 1 The second pixel P2 shown includes a first pixel circuit PX2a and a second pixel circuit PX2b. Each of the first pixel circuit PX2a and the second pixel circuit PX2b can constitute a sub-pixel. For example, the first pixel circuit PX2a can be a green sub-pixel, and the second pixel circuit PX2b can be a red or blue sub-pixel. The first pixel circuit PX2a and the second pixel circuit PX2b can be arranged adjacent to each other. (See reference...) Figure 1 As described, the second pixel P2 can be arranged in the second display area DA2.

[0117] The first pixel circuit PX2a and Figure 4 The first pixel PX1ij shown is essentially the same. The first pixel circuit PX2a is connected to the first scan line to the third scan line, which transmits the first scan signal GW, the second scan signal GI, and the third scan signal GB; the data line, which transmits the first data voltage DATAa; and the transmit control line, which transmits the transmit control signal EM. The first pixel circuit PX2a is connected to the power line, which transmits the first drive voltage ELVDD, and the voltage line, which transmits the initialization voltage VINT. The first pixel circuit PX2a is connected to the common electrode to which the second drive voltage ELVSS is applied.

[0118] The first scan signal GW, the second scan signal GI, the third scan signal GB, the first data voltage DATAa, and the transmit control signal EM applied to the first pixel circuit PX2a correspond to the signals applied to the first pixel circuit PX2a, respectively. Figure 4 The first pixel PX1ij has a first scan signal GW_i, a second scan signal GI_i, a third scan signal GB_i, a data voltage Dj, and a transmit control signal EM_i. A first drive voltage ELVDD, an initialization voltage VINT, and a second drive voltage ELVSS are commonly applied to... Figure 4The pixel circuit of the first pixel PX1ij, the first pixel circuit PX2a, and the second pixel circuit PX2b.

[0119] Similar to the first pixel PX1ij, the first pixel circuit PX2a includes a first light-emitting device OLEDa, first TFTs T1a to seventh TFTs T7a, and a first storage capacitor Csta. Although Figure 6 The first pixel circuit PX2a shown includes seven transistors and a capacitor, but this is exemplary and other circuit configurations are possible. For example, the first pixel circuit PX2a may include two transistors and a capacitor.

[0120] The first pixel circuit PX2a includes a first scanning TFT T2a, a first storage capacitor Csta, a first driving TFT T1a, and a first light-emitting device OLEDa. The first scanning TFT T2a receives a first data voltage DATAa in response to a first scanning signal GW. The first storage capacitor Csta maintains a first gate voltage corresponding to the first data voltage DATAa. The first driving TFT T1a has a gate connected to the first storage capacitor Csta and controls the amount of a first driving current Ida based on the first gate voltage. The first light-emitting device OLEDa emits light according to the first driving current Ida.

[0121] The first pixel circuit PX2a may further include a first compensation TFT T3a, a first gate initialization TFT T4a, and a first anode initialization TFT T7a. The first compensation TFT T3a connects the drain and gate of the first driving TFT T1a to each other in response to the first scan signal GW. The first gate initialization TFT T4a applies an initialization voltage VINT to the gate of the first driving TFT T1a in response to the second scan signal GI. The first anode initialization TFT T7a applies an initialization voltage VINT to the anode of the first light-emitting device OLEDa in response to the third scan signal GB.

[0122] The first pixel circuit PX2a may further include a first emission control TFT T5a and a second emission control TFT T6a. The first emission control TFT T5a applies a first driving voltage ELVDD to the source of the first driving TFT T1a in response to the emission control signal EM, and the second emission control TFT T6a transmits a first driving current Ida from the first driving TFT T1a to the first light-emitting device OLEDa in response to the emission control signal EM.

[0123] Since the first pixel circuit PX2a has essentially the same configuration as the first pixel PX1ij, a detailed description of the circuit configuration will not be repeated. The first pixel circuit PX2a also... Figure 5The timing diagram is driven by control signals. First, the operation of the first pixel circuit PX2a will be briefly described.

[0124] When a high-level transmit control signal EM is received, the first transmit control TFT T5a and the second transmit control TFT T6a are turned off. The first driving TFT T1a stops outputting the first driving current Ida, and the first light-emitting device OLEDa stops emitting light.

[0125] When a low-level second scan signal GI is received, the first gate initialization TFT T4a is turned on, and the initialization voltage VINT is applied to the gate of the first driving TFT T1a.

[0126] When a low-level first scan signal GW and a first data voltage DATAa are received, the first scan TFT T2a and the first compensation TFT T3a are turned on, and the first data voltage DATAa is applied to the source of the first driving TFT T1a through the first scan TFT T2a. The first driving TFT T1a is connected to the first compensation TFT T3a via a diode. When the gate voltage of the first driving TFT T1a becomes equal to the voltage DATAa-|Vth| minus the threshold voltage Vth of the first driving TFT T1a from the first data voltage DATAa, the first driving TFT T1a is turned off. Accordingly, the difference between the first driving voltage ELVDD and the first gate voltage DATAa-|Vth| (ELVDD-DATAa+|Vth|) is stored in the storage capacitor Cst. Hereinafter, the gate voltage of the first driving TFT T1a held by the storage capacitor Cst is referred to as the first gate voltage DATAa-|Vth|.

[0127] When a low-level third scan signal GB is received, the first anode initialization TFT T7a is turned on, and the initialization voltage VINT is applied to the anode of the first light-emitting device OLEDa.

[0128] When a low-level transmit control signal EM is received, the first transmit control TFT T5a and the second transmit control TFT T6a are turned on. The first drive TFT T1a outputs a first drive current Ida with an amount corresponding to the voltage ELVDD-DATAa obtained by subtracting the threshold voltage |Vth| of the first drive TFT T1a from the source-gate voltage ELVDD-DATAa+|Vth|, and the first light-emitting device OLEDa emits light with a brightness corresponding to the amount of the first drive current Ida.

[0129] The second pixel circuit PX2b includes a second driving TFT T1b, a second scanning TFT T2b, and a second light-emitting device OLEDb.

[0130] The second scanning TFT T2b receives the second data voltage DATAb in response to the emission control signal EM. During the period when the second light-emitting device OLEDb emits light, i.e., during the light-emitting period, the second data voltage DATAb is applied to the second pixel circuit PX2b. The second scanning TFT T2b may apply the second data voltage DATAb to the source of the second driving TFT T1b in response to the emission control signal EM. The second scanning TFT T2b may have a gate for receiving the emission control signal EM, a source for receiving the second data voltage DATAb, and a drain connected to the source of the second driving TFT T1b. The emission control signal EM received by the second pixel circuit PX2b is the same as the emission control signal EM received by the first pixel circuit PX2a.

[0131] The second driving TFT T1b may have a gate connected to the gate of the first driving TFT T1a of the first pixel circuit PX2a, a source receiving the second data voltage DATAb through the second scanning TFT T2b, and a drain connected to the second light-emitting device OLEDb through the first current transmission TFT T6b. The second driving TFT T1b controls the amount of the second driving current Idb based on the difference between the first gate voltage DATAa-|Vth| stored by the first storage capacitor Csta of the first pixel circuit PX2a and the second data voltage DATAb (i.e., DATAb-DATAa+|Vth|). The second driving TFT T1b outputs a second driving current Idb with an amount corresponding to the voltage DATAb-DATAa+|Vth|-|Vth'| obtained by subtracting the threshold voltage |Vth'| of the second driving TFT T1b from the source-gate voltage DATAb-DATAa+|Vth|.

[0132] The second driving TFT T1b may have a planar shape that is substantially the same as or symmetrical to the first driving TFT T1a. Because the second driving TFT T1b and the first driving TFT T1a have corresponding shapes and are arranged adjacent to each other, they have substantially the same process tolerances and substantially similar transistor characteristics. Accordingly, there is no significant difference between the threshold voltage |Vth| of the first driving TFT T1a and the threshold voltage |Vth'| of the second driving TFT T1b, and the amount of the second driving current Idb can be determined by the difference (DATAb-DATAa) between the second data voltage DATAb and the first data voltage DATAa. That is, as the threshold voltages |Vth| of the first driving TFT T1a and |Vth'| of the second driving TFT T1b cancel each other out, the amount of the second driving current Idb is unaffected by the threshold voltages |Vth| of the first driving TFT T1a and |Vth'| of the second driving TFT T1b.

[0133] The second light-emitting device OLEDb can emit light with a brightness corresponding to the amount of the second driving current Idb. The second light-emitting device OLEDb can be an organic light-emitting diode having an anode and a cathode. The cathode can be a common electrode to which the second driving voltage ELVSS is applied.

[0134] The second pixel circuit PX2b may further include a second anode initialization TFT T7b. The second anode initialization TFT T7b may apply an initialization voltage VINT to the anode of the second light-emitting device OLEDb in response to a third scan signal GB. The second anode initialization TFT T7b may have a gate for receiving the third scan signal GB, a source connected to the anode of the second light-emitting device OLEDb, and a drain for receiving the initialization voltage VINT. The third scan signal GB applied to the second pixel circuit PX2b is the same as the third scan signal GB applied to the first pixel circuit PX2a.

[0135] The second pixel circuit PX2b may further include a first current transfer TFT T6b. The first current transfer TFT T6b may transfer a second driving current Idb output from the second driving TFT T1b to the second light-emitting device OLEDb in response to the emission control signal EM. The first current transfer TFT T6b may have a gate for receiving the emission control signal EM, a source connected to the drain of the second driving TFT T1b, and a drain connected to the anode of the second light-emitting device OLEDb.

[0136] In the first pixel circuit PX2a, the first driving TFT T1a outputs a first driving current Ida with an amount corresponding to the difference (ELVDD-DATAa) between the first driving voltage ELVDD and the first data voltage DATAa, and the first light-emitting device OLEDa emits light with a brightness corresponding to the first driving current Ida. In the second pixel circuit PX2b, the second driving TFT T1b outputs a second driving current Idb with an amount corresponding to the difference (DATAb-DATAa) between the second data voltage DATAb and the first data voltage DATAa, and the second light-emitting device OLEDb emits light with a brightness corresponding to the second driving current Idb. The first pixel circuit PX2a and the second pixel circuit PX2b can respectively generate a first driving current Ida and a second driving current Idb that are unaffected by the threshold voltages of the first driving TFT T1a and the second driving TFT T1b. The second pixel circuit PX2b can omit some of the multiple TFTs by sharing the gate of the first driving TFT T1a of the first pixel circuit PX2a. Figure 6In this example, the first pixel circuit PX2a includes seven TFTs and one capacitor, while the second pixel circuit PX2b includes only four TFTs. Accordingly, the second pixel circuit PX2b can be formed in a smaller area and can ensure a relatively wide transmission area. Figure 1 (TA in the middle).

[0137] Figure 7 This is a view showing the pixel circuitry of the second pixel P2 according to another embodiment.

[0138] Reference Figure 7 The second pixel P2 includes the first pixel circuit PX2a and the second pixel circuit PX2b. Because the first pixel circuit PX2a and... Figure 6 The first pixel circuit PX2a shown is the same, therefore the description of the first pixel circuit PX2a will be omitted. The second pixel circuit PX2b is the same as... Figure 6 The difference in the second pixel circuit PX2b shown is that it also includes a second storage capacitor Cstb and a second compensation TFT T3b. The following description describes the differences.

[0139] The second pixel circuit PX2b may further include a second compensation TFT T3b that connects the gate of the second driving TFT T1b to the gate of the first driving TFT T1a in response to the first scan signal GW. The second compensation TFT T3b may have a gate receiving the first scan signal GW, a source connected to the gate of the first driving TFT T1a, and a drain connected to the gate of the second driving TFT T1b. The second compensation TFT T3b may be formed by a plurality of TFTs connected in series and synchronously controlled by the first scan signal GW. The first scan signal GW applied to the second pixel circuit PX2b is the same as the first scan signal GW applied to the first pixel circuit PX2a.

[0140] The second pixel circuit PX2b may further include a second storage capacitor Cstb connected to the gate of the second driving TFT T1b and holding a first gate voltage DATAa-|Vth|. The second storage capacitor Cstb may have a first electrode to which the first driving voltage ELVDD is applied and a second electrode connected to the gate of the second driving TFT T1b. During the data writing period, the second storage capacitor Cstb may store the difference between the first driving voltage ELVDD and the first gate voltage DATAa-|Vth| (ELVDD-DATAa+|Vth|), and may maintain this difference during the light-emitting period.

[0141] During the data writing period, a low-level first scan signal GW and a first data voltage DATAa are received. In response to the low-level first scan signal GW, the first scan TFT T2a, the first compensation TFT T3a, and the second compensation TFT T3b are turned on. The drain and gate of the first driving TFT T1a are connected to each other such that the first driving TFT T1a is diode-connected, and the gate of the first driving TFT T1a and the gate of the second driving TFT T1b are also connected to each other. The first data voltage DATAa is transmitted through the diode-connected first driving TFT T1a to the gates of the first driving TFT T1a and the second driving TFT T1b, and the first gate voltage DATAa-|Vth| is stored in both the first storage capacitor Csta and the second storage capacitor Cstb.

[0142] Because the first gate voltage DATAa-|Vth| is maintained independently by the first storage capacitor Csta and the second storage capacitor Cstb, each of the first pixel circuit PX2a and the second pixel circuit PX2b can operate more reliably and independently.

[0143] Figure 8 This is a view showing the pixel circuitry of the second pixel P2 according to another embodiment.

[0144] Reference Figure 8 The second pixel P2 includes the first pixel circuit PX2a and the second pixel circuit PX2b. Because the first pixel circuit PX2a and... Figure 6 The first pixel circuit PX2a shown is the same, therefore the description of the first pixel circuit PX2a will be omitted. Figure 6 Compared to the second pixel circuit PX2b shown, the second pixel circuit PX2b differs in its connection relationship with the second anode initialization TFT T7b. The differences are described below.

[0145] The second anode initialization TFT T7b can connect the anode of the second light-emitting device OLEDb to the anode of the first light-emitting device OLEDa in response to the third scan signal GB. The second anode initialization TFT T7b may have a gate for receiving the third scan signal GB, a source connected to the anode of the second light-emitting device OLEDb, and a drain connected to the anode of the first light-emitting device OLEDa.

[0146] In response to the low-level third scan signal GB, the first anode initialization TFT T7a and the second anode initialization TFT T7b are turned on, and the initialization voltage VINT is applied to the anode of the first light-emitting device OLEDa and the anode of the second light-emitting device OLEDb.

[0147] The initialization voltage VINT applied to the anode of the second light-emitting device OLEDb via the first anode initialization TFT T7a and the second anode initialization TFT T7b can be higher than the initialization voltage VINT applied to the anode of the first light-emitting device OLEDa via the first anode initialization TFT T7a. The first light-emitting device OLEDa and the second light-emitting device OLEDb may include light-emitting materials that emit different colors of light. By applying different levels of initialization voltage VINT according to the material properties of the first light-emitting device OLEDa and the second light-emitting device OLEDb, problems such as delayed emission of specific colors of light can be solved.

[0148] Figure 9 This is a view showing the pixel circuitry of the second pixel P2 according to another embodiment.

[0149] Reference Figure 9 The second pixel P2 includes the first pixel circuit PX2a and the second pixel circuit PX2b. Because the first pixel circuit PX2a and... Figure 6 The first pixel circuit PX2a shown is the same, therefore the description of the first pixel circuit PX2a will be omitted. Figure 7 Compared to the second pixel circuit PX2b shown, the second pixel circuit PX2b differs in its connection relationship with the second anode initialization TFT T7b. The differences are discussed in the following description.

[0150] The second anode initialization TFT T7b can connect the anode of the second light-emitting device OLEDb to the anode of the first light-emitting device OLEDa in response to the third scan signal GB. The second anode initialization TFT T7b may have a gate for receiving the third scan signal GB, a source connected to the anode of the second light-emitting device OLEDb, and a drain connected to the anode of the first light-emitting device OLEDa. In response to the low-level third scan signal GB, the first anode initialization TFT T7a and the second anode initialization TFT T7b are turned on, and an initialization voltage VINT is applied to the anodes of the first light-emitting device OLEDa and the second light-emitting device OLEDb.

[0151] Figure 10 This is a view showing the pixel circuitry of the second pixel P2 according to another embodiment.

[0152] Reference Figure 10 The second pixel P2 includes a first pixel circuit PX2a, a second pixel circuit PX2b, and a third pixel circuit PX2c. Because the first pixel circuit PX2a and the second pixel circuit PX2b are... Figure 6The first pixel circuit PX2a and the second pixel circuit PX2b shown are identical, therefore the descriptions of the first pixel circuit PX2a and the second pixel circuit PX2b will be omitted. The third pixel circuit PX2c will be described below.

[0153] The third pixel circuit PX2c includes a third driving TFT T1c, a third scanning TFT T2c, and a third light-emitting device OLEDc. The first pixel circuit PX2a can form a sub-pixel of a first color (e.g., green), the second pixel circuit PX2b can form a sub-pixel of a second color (e.g., red), and the third pixel circuit PX2c can form a sub-pixel of a third color (e.g., blue).

[0154] The third scanning TFT T2c receives a third data voltage DATAc in response to the emission control signal EM. During the period when the third light-emitting device OLEDc emits light, i.e., during the light-emitting period, the third data voltage DATAc is applied to the third pixel circuit PX2c. The third scanning TFT T2c may apply the third data voltage DATAc to the third driving TFT T1c in response to the emission control signal EM. The third scanning TFT T2c may have a gate for receiving the emission control signal EM, a source for receiving the third data voltage DATAc, and a drain connected to the source of the third driving TFT T1c. The emission control signal EM received by the third pixel circuit PX2c is the same as the emission control signal EM received by the first pixel circuit PX2a and the second pixel circuit PX2b.

[0155] The third driving TFT T1c may have a gate connected to the gate of the first driving TFT T1a of the first pixel circuit PX2a, a source that receives the third data voltage DATAc through the third scanning TFT T2c, and a drain connected to the third light-emitting device OLEDc through the second current transmission TFT T6c. The third driving TFT T1c controls the amount of the third driving current Idc based on the difference (DATAc-DATAa+|Vth|) between the first gate voltage DATAa-|Vth| stored by the first storage capacitor Csta of the first pixel circuit PX2a. The third driving TFT T1c outputs a third driving current Idc with an amount corresponding to the voltage DATAc-DATAa+|Vth|-|Vth”| obtained by subtracting the threshold voltage |Vth”| of the third driving TFT T1c from the source-gate voltage DATAc-DATAa+|Vth|.

[0156] The third driving TFT T1c may have a planar shape that is substantially the same as or symmetrical to the first driving TFT T1a. Because the third driving TFT T1c and the first driving TFT T1a have corresponding shapes and are arranged adjacent to each other, they have substantially the same process tolerances and substantially similar transistor characteristics. Accordingly, there is no significant difference between the threshold voltage |Vth| of the first driving TFT T1a and the threshold voltage |Vth”| of the third driving TFT T1c, and the amount of the third driving current Idc can be determined by the difference (DATAc-DATAa) between the third data voltage DATAc and the first data voltage DATAa. That is, as the threshold voltages |Vth| of the first driving TFT T1a and |Vth”| of the third driving TFT T1c cancel each other out, the amount of the third driving current Idc is unaffected by the threshold voltages |Vth| of the first driving TFT T1a and |Vth”| of the third driving TFT T1c.

[0157] The third light-emitting device, OLEDc, can emit light with a brightness corresponding to the amount of the third driving current, Idc. The third light-emitting device, OLEDc, can be an organic light-emitting diode having an anode and a cathode. The cathode can be a common electrode to which a second driving voltage, ELVSS, is applied.

[0158] The third pixel circuit PX2c may further include a third anode initialization TFT T7c. The third anode initialization TFT T7c can connect the anode of the third light-emitting device OLEDc to the anode of the first light-emitting device OLEDa in response to a third scan signal GB. The third anode initialization TFT T7c may have a gate for receiving the third scan signal GB, a source connected to the anode of the third light-emitting device OLEDc, and a drain connected to the anode of the first light-emitting device OLEDa. The third scan signal GB applied to the third pixel circuit PX2c is the same as the third scan signal GB applied to the first pixel circuit PX2a and the second pixel circuit PX2b.

[0159] The third pixel circuit PX2c may further include a second current transfer TFT T6c. The second current transfer TFT T6c may, in response to an emission control signal EM, transfer a third driving current Idc output from the third driving TFT T1c to the third light-emitting device OLEDc. The second current transfer TFT T6c may have a gate for receiving the emission control signal EM, a source connected to the drain of the third driving TFT T1c, and a drain connected to the anode of the third light-emitting device OLEDc.

[0160] In the first pixel circuit PX2a, the first driving TFT T1a outputs a first driving current Ida with an amount corresponding to the difference (ELVDD-DATAa) between the first driving voltage ELVDD and the first data voltage DATAa, and the first light-emitting device OLEDa emits light with a brightness corresponding to the first driving current Ida. In the second pixel circuit PX2b, the second driving TFT T1b outputs a second driving current Idb with an amount corresponding to the difference (DATAb-DATAa) between the second data voltage DATAb and the first data voltage DATAa, and the second light-emitting device OLEDb emits light with a brightness corresponding to the second driving current Idb. In the third pixel circuit PX2c, the third driving TFT T1c outputs a third driving current Idc with an amount corresponding to the difference (DATAc-DATAa) between the third data voltage DATAc and the first data voltage DATAa, and the third light-emitting device OLEDc emits light with a brightness corresponding to the third driving current Idc.

[0161] The first pixel circuit PX2a, the second pixel circuit PX2b, and the third pixel circuit PX2c can respectively generate a first driving current Ida, a second driving current Idb, and a third driving current Idc, which are unaffected by the threshold voltages of the first driving TFT T1a, the second driving TFT T1b, and the third driving TFT T1c. The second pixel circuit PX2b and the third pixel circuit PX2c can omit some of the multiple TFTs by sharing the gate of the first driving TFT T1a of the first pixel circuit PX2a. Figure 10 In this example, the first pixel circuit PX2a includes seven TFTs and one capacitor, while the second pixel circuit PX2b and the third pixel circuit PX2c each include only four TFTs. Accordingly, the second pixel circuit PX2b and the third pixel circuit PX2c can be formed in a smaller area, and a relatively wide transmission area can be ensured. Figure 1 (TA in the middle).

[0162] Figure 11 This is a view showing the pixel circuitry of the second pixel P2 according to another embodiment.

[0163] Reference Figure 11 The second pixel P2 includes a first pixel circuit PX2a, a second pixel circuit PX2b, and a third pixel circuit PX2c. Because the first pixel circuit PX2a and the second pixel circuit PX2b are... Figure 7 The first pixel circuit PX2a and the second pixel circuit PX2b shown are identical, therefore the descriptions of the first pixel circuit PX2a and the second pixel circuit PX2b will be omitted. The third pixel circuit PX2c is the same as... Figure 10The difference in the third pixel circuit PX2c shown is that it also includes a third storage capacitor Cstc and a third compensation TFT T3c. The following description discusses the differences.

[0164] The third pixel circuit PX2c may further include a third compensation TFT T3c that connects the gate of the third driving TFT T1c to the drain of the first driving TFT T1a in response to the first scan signal GW. The third compensation TFT T3c may have a gate for receiving the first scan signal GW, a source connected to the drain of the first driving TFT T1a, and a drain connected to the gate of the third driving TFT T1c. The third compensation TFT T3c may be formed by a plurality of TFTs connected in series with each other and synchronously controlled by the first scan signal GW.

[0165] The third pixel circuit PX2c may further include a third storage capacitor Cstc connected to the gate of the third driving TFT T1c and maintaining a first gate voltage DATAa-|Vth|. The third storage capacitor Cstc may have a first electrode to which the first driving voltage ELVDD is applied and a third electrode connected to the gate of the third driving TFT T1c. During the data writing period, the third storage capacitor Cstc may store the difference between the first driving voltage ELVDD and the first gate voltage DATAa-|Vth| (ELVDD-DATAa+|Vth|), and may maintain this difference during the light-emitting period.

[0166] During the data writing period, a low-level first scan signal GW and a first data voltage DATAa are received. In response to the low-level first scan signal GW, the first scan TFT T2a, the first compensation TFT T3a, and the second compensation TFT T3b are turned on. The drain and gate of the first driving TFT T1a are connected to each other such that the first driving TFT T1a is diode-connected, and the gates of the first driving TFT T1a, the second driving TFT T1b, and the third driving TFT T1c are also connected to each other. The first data voltage DATAa is transmitted through the diode-connected first driving TFT T1a to the gates of the first driving TFT T1a and the third driving TFT T1c, and the first gate voltage DATAa-|Vth| is stored in the first storage capacitor Csta, the second storage capacitor Cstb, and the third storage capacitor Cstc, respectively.

[0167] Because the first gate voltage DATAa-|Vth| is held independently by the first storage capacitor Csta, the second storage capacitor Cstb, and the third storage capacitor Cstc, each of the first pixel circuit PX2a, the second pixel circuit PX2b, and the third pixel circuit PX2c can operate more reliably and independently.

[0168] According to various embodiments of this disclosure, because the pixel area can be reduced in areas where other functions are added, a relatively wide transmissive area can be arranged. Accordingly, the display device can provide various functions while maintaining the original display quality.

[0169] It should be understood that the embodiments described herein should be considered descriptively only and not for limiting purposes. Descriptions of features or aspects within each embodiment should generally be considered as other similar features or aspects applicable to other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope and spirit defined in the appended claims.

Claims

1. A pixel circuit, comprising a first pixel circuit and a second pixel circuit, in, The first pixel circuit includes: A first scanning thin-film transistor receives a first data voltage in response to a first scanning signal; A first storage capacitor, wherein the first storage capacitor maintains a first gate voltage corresponding to the first data voltage; A first driving thin-film transistor, the first driving thin-film transistor having a gate connected to the first storage capacitor and controlling the amount of a first driving current based on the first gate voltage; and The first light-emitting device emits light according to the first driving current, and The second pixel circuit includes: The second scanning thin-film transistor receives the second data voltage in response to the transmit control signal; A second driving thin-film transistor has a gate directly connected to the gate of the first driving thin-film transistor and a source that receives the second data voltage through a second scanning thin-film transistor, and the second driving thin-film transistor controls the amount of a second driving current based on the difference between the first gate voltage and the second data voltage; and The second light-emitting device emits light according to the second driving current.

2. The pixel circuit as described in claim 1, wherein, The first pixel circuit also includes: A first compensation thin-film transistor, which connects the drain of the first driving thin-film transistor and the gate of the first driving thin-film transistor to each other in response to the first scan signal. A first gate initialization thin-film transistor, which, in response to a second scan signal, applies an initialization voltage to the gate of the first driving thin-film transistor; and The first anode initialization thin-film transistor applies the initialization voltage to the anode of the first light-emitting device in response to the third scan signal.

3. The pixel circuit as described in claim 2, wherein, The second pixel circuit also includes: The second anode initialization thin-film transistor applies the initialization voltage to the anode of the second light-emitting device in response to the third scan signal.

4. The pixel circuit as described in claim 2, wherein, The second pixel circuit also includes: The second anode initialization thin-film transistor connects the anode of the second light-emitting device to the anode of the first light-emitting device in response to the third scan signal.

5. The pixel circuit as described in claim 1, wherein, The first pixel circuit also includes: A first emission control thin-film transistor, wherein the first emission control thin-film transistor applies a first driving voltage to the source of the first driving thin-film transistor in response to the emission control signal; and A second emission control thin-film transistor, in response to the emission control signal, transmits the first driving current from the first driving thin-film transistor to the first light-emitting device.

6. The pixel circuit as described in claim 1, wherein, The second pixel circuit also includes: A first current-transfer thin-film transistor transmits the second driving current from the second driving thin-film transistor to the second light-emitting device in response to the emission control signal.

7. The pixel circuit as described in claim 1, further comprising: The third pixel circuit includes: A third scanning thin-film transistor receives a third data voltage in response to the transmit control signal; A third driving thin-film transistor has a gate connected to the gate of the first driving thin-film transistor and a source that receives the third data voltage through the third scanning thin-film transistor, and the third driving thin-film transistor controls the amount of a third driving current based on the difference between the first gate voltage and the third data voltage; and A third light-emitting device emits light according to the third driving current.

8. The pixel circuit as described in claim 7, wherein, The third pixel circuit also includes: A third anode initialization thin-film transistor, which, in response to a third scan signal, connects the anode of the third light-emitting device to the anode of the first light-emitting device; and The second current-transfer thin-film transistor transmits the third driving current from the third driving thin-film transistor to the third light-emitting device in response to the emission control signal.

9. The pixel circuit as described in claim 1, wherein, The second pixel circuit also includes: A second compensation thin-film transistor, which, in response to the first scan signal, connects the gate of the second driving thin-film transistor to the gate of the first driving thin-film transistor; and A second storage capacitor is connected to the gate of the second driving thin-film transistor and maintains the first gate voltage.

10. The pixel circuit of claim 9, further comprising: The third pixel circuit includes: A third scanning thin-film transistor receives a third data voltage in response to the transmit control signal; A third compensation thin-film transistor receives the first gate voltage in response to the first scan signal; A third driving thin-film transistor has a gate that receives the first gate voltage through the third compensation thin-film transistor and a source that receives the third data voltage through the third scan thin-film transistor, and the third driving thin-film transistor controls the amount of a third driving current based on the difference between the first gate voltage and the third data voltage. A third storage capacitor, connected to the gate of the third driving thin-film transistor and maintaining the first gate voltage; and A third light-emitting device emits light according to the third driving current.

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