Display device

Abstract

A display device of the present application includes a pixel including a pixel drive transistor and a pixel switch transistor, the pixel drive transistor including: a first active layer including a first channel region having a first length; a first gate insulating layer disposed on the first active layer; a first gate electrode disposed on the first gate insulating layer; a first source electrode disposed on the first gate electrode and connected to a source region of the first active layer; and a first drain electrode connected to a drain region of the first active layer, the pixel switch transistor including: a second active layer including a second channel region having a second length shorter than the first length; a second gate insulating layer disposed on the second active layer; a second gate electrode disposed on the second gate insulating layer; a second source electrode disposed on the second gate electrode and connected to a source region of the second active layer; and a second drain electrode disposed on the second gate electrode and connected to a drain region of the second active layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device, and more particularly, to a display device including a plurality of transistors. BACKGROUND

[0002] With the miniaturization of display devices, efforts to minimize a bezel area, which is a peripheral portion of a display area, are continuing in order to increase the size of the display area. In general, there are limitations in minimizing the bezel area because a wiring and a driving circuit for driving the display device are disposed in the bezel area, which corresponds to a non-display area. Therefore, research into the miniaturization of display devices is being conducted by reducing the size of thin film transistors of the display devices.

[0003] However, as the driving frequency of the display device increases or the resolution increases, it becomes difficult to secure a driving voltage of the thin film transistor, and there can be a problem in which the time for charging the thin film transistor becomes short. SUMMARY

[0004] The technical problem of the present application is focused on these aspects, and an object of the present application is to provide a display device having improved display quality.

[0005] However, the problem to be solved by the present application is not limited to the above-mentioned problem, and various extensions can be made without departing from the scope of the concept and field of the present application.

[0006] It can be that a display device according to an embodiment for achieving the above-mentioned object of the present application includes a pixel including a pixel driving transistor and a pixel switching transistor, the pixel driving transistor including a first active layer doped with a third group element and including a first channel region having a first length, a first gate insulating layer disposed on the first active layer, a first gate electrode disposed on the first gate insulating layer, a first source electrode disposed on the first gate electrode and connected to a source region of the first active layer, and a first drain electrode disposed on the first gate electrode and connected to a drain region of the first active layer. In addition, it can be that the pixel switching transistor includes a second active layer doped with a fifth group element and including a second channel region having a second length shorter than the first length, a second gate insulating layer disposed on the second active layer, a second gate electrode disposed on the second gate insulating layer, a second source electrode disposed on the second gate electrode and connected to a source region of the second active layer, and a second drain electrode disposed on the second gate electrode and connected to a drain region of the second active layer. Here, it can be that the pixel driving transistor and the pixel switching transistor are PMOS transistors.

[0007] In an embodiment, the first gate insulating layer and the second gate insulating layer can be disposed in the same layer, the first gate insulating layer can be a single layer including a silicon oxide-based substance, and the second gate insulating layer can be a multi-layer including a 2-1 gate insulating layer including the silicon oxide-based substance and a 2-2 gate insulating layer disposed on the 2-1 gate insulating layer and including a silicon nitride-based substance.

[0008] In an embodiment, the first length can be 10 um to 30 um, and the second length can be 1 um to 5 um.

[0009] In an embodiment, the pixel can further include a capacitor electrode disposed on the first gate electrode and disposed under the first source electrode and the first drain electrode.

[0010] In an embodiment, the pixel can further include an organic light emitting diode connected to the pixel driving transistor, the organic light emitting diode including a lower electrode connected to the first drain electrode, an intermediate layer disposed on the lower electrode, and an upper electrode disposed on the intermediate layer.

[0011] In an embodiment, the display device can further include a scan driving portion that provides a scan signal to the pixel and includes a scan buffer transistor and a scan circuit transistor, the scan circuit transistor including a third active layer doped with the third group element and including a third channel region having the first length, a third gate insulating layer disposed on the third active layer, a third gate electrode disposed on the third gate insulating layer, a third source electrode disposed on the third gate electrode and connected to a source region of the third active layer, and a third drain electrode disposed on the third gate electrode and connected to a drain region of the third active layer. In addition, the scan buffer transistor can include a fourth active layer doped with the fifth group element and including a fourth channel region having the second length, a fourth gate insulating layer disposed on the fourth active layer, a fourth gate electrode disposed on the fourth gate insulating layer, a fourth source electrode disposed on the fourth gate electrode and connected to a source region of the fourth active layer, and a fourth drain electrode disposed on the fourth gate electrode and connected to a drain region of the fourth active layer.

[0012] In an embodiment, the third gate insulating layer can be a single layer including a silicon oxide-based substance, and the fourth gate insulating layer can be a multi-layer including a 4-1 gate insulating layer including the silicon oxide-based substance and a 4-2 gate insulating layer disposed on the 4-1 gate insulating layer and including a silicon nitride-based substance.

[0013] In an embodiment, the scan buffer transistor can be connected to a scan signal output portion of the scan driving portion.

[0014] In an embodiment, the scan circuit transistor can be disposed on the scan buffer transistor.

[0015] In an embodiment, the display device can further include a light emitting driving portion that provides a light emitting control signal to the pixel and includes a light emitting buffer transistor and a light emitting circuit transistor, the light emitting circuit transistor including a fifth active layer doped with the third group element and including a fifth channel region having the first length, a fifth gate insulating layer disposed on the fifth active layer, a fifth gate electrode disposed on the fifth gate insulating layer, a fifth source electrode disposed on the fifth gate electrode and connected to a source region of the fifth active layer, and a fifth drain electrode disposed on the fifth gate electrode and connected to a drain region of the fifth active layer. In addition, the light emitting buffer transistor includes a sixth active layer doped with the fifth group element and including a sixth channel region having the second length, a sixth gate insulating layer disposed on the sixth active layer, a sixth gate electrode disposed on the sixth gate insulating layer, a sixth source electrode disposed on the sixth gate electrode and connected to a source region of the sixth active layer, and a sixth drain electrode disposed on the sixth gate electrode and connected to a drain region of the sixth active layer.

[0016] In an embodiment, the fifth gate insulating layer can be a single layer including a silicon oxide-based substance, and the sixth gate insulating layer can be a multi-layer including a 6-1 gate insulating layer including the silicon oxide-based substance and a 6-2 gate insulating layer disposed on the 6-1 gate insulating layer and including a silicon nitride-based substance.

[0017] In an embodiment, the light emitting buffer transistor can be connected to a light emitting control signal output portion of the light emitting driving portion.

[0018] In an embodiment, the light emitting circuit transistor can be disposed on the light emitting buffer transistor.

[0019] In an embodiment, the pixel switch transistor can be disposed on the pixel drive transistor.

[0020] In an embodiment, the first gate insulating layer can be a single layer including a silicon oxide-based substance, and the second gate insulating layer can be a multi-layer including a 2-1 gate insulating layer including the silicon oxide-based substance and a 2-2 gate insulating layer disposed on the 2-1 gate insulating layer and including a silicon nitride-based substance.

[0021] In an embodiment, the pixel can further include an organic light emitting diode connected to the pixel drive transistor, the organic light emitting diode including a lower electrode connected to the first drain electrode, an intermediate layer disposed on the lower electrode, and an upper electrode disposed on the intermediate layer.

[0022] In an embodiment, the pixel drive transistor can further include a connection electrode disposed between the first gate electrode and the first drain electrode, the connection electrode connecting the first drain electrode and the drain region of the first active layer.

[0023] In an embodiment, the connection electrode can overlap the first gate electrode.

[0024] In an embodiment, the pixel drive transistor can overlap at least a portion of the pixel switch transistor.

[0025] A display device according to an embodiment for achieving the object of the present application described above can include a pixel including a pixel drive transistor and a pixel switch transistor, the pixel drive transistor including a first active layer doped with a fifth group element and including a first channel region having a first length, a first gate insulating layer disposed on the first active layer, a first gate electrode disposed on the first gate insulating layer, a first source electrode disposed on the first gate electrode and connected to a source region of the first active layer, and a first drain electrode disposed on the first gate electrode and connected to a drain region of the first active layer. In addition, the pixel switch transistor can include a second active layer doped with a third group element and including a second channel region having a second length shorter than the first length, a second gate insulating layer disposed on the second active layer, a second gate electrode disposed on the second gate insulating layer, a second source electrode disposed on the second gate electrode and connected to a source region of the second active layer, and a second drain electrode disposed on the second gate electrode and connected to a drain region of the second active layer. Here, the pixel drive transistor and the pixel switch transistor can be NMOS transistors.

[0026] (EFFECT OF INVENTION)

[0027] The display device according to an embodiment of the present application can include a pixel driving transistor doped with a third group element and including a first active layer having a first channel region having a first length and a first gate insulating layer disposed on the first active layer and configured in a single layer, and a pixel switching transistor doped with a fifth group element and including a second active layer having a second channel region having a second length shorter than the first length and a second gate insulating layer disposed on the second active layer and configured in a plurality of layers.

[0028] Thus, it is possible to secure a wide driving voltage range of the pixel driving transistor driving the pixel, to secure a charging time of the pixel switching transistor, and to delay a reaction time required at the time of turning on / off.

[0029] However, the effects of the present application are not limited to the above-mentioned effects, and various extensions can be made without departing from the concept and scope of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present application.

[0031] Figure 2 is a circuit diagram illustrating a pixel circuit and an organic light emitting diode included in a pixel of Figure 1 .

[0032] Figure 3 is a cross-sectional view illustrating an embodiment of a transistor disposed in a display device of Figure 1 .

[0033] Figure 4 is a cross-sectional view illustrating an embodiment of a transistor disposed in a display device of Figure 1 .

[0034] Figure 5 is a circuit diagram illustrating an embodiment of a scan circuit disposed in a scan driving part of Figure 1 .

[0035] Figure 6 is a circuit diagram illustrating an embodiment of a light emitting circuit disposed in a light emitting driving part of Figure 1 .

[0036] Figure 7 is a cross-sectional view illustrating an embodiment of a transistor disposed in a scan driving part and a light emitting driving part of Figure 1 .

[0037] (REFERENCE NUMERALS)

[0038] 100: display device 110: display portion

[0039] 120: timing controller 130: data driver

[0040] 140: scan driver 150: light-emitting driver

[0041] 230a, 430, 850: first active layer

[0042] 230b, 490, 915: second active layer

[0043] 240a, 440, 840: first gate insulating layer

[0044] 240d, 510, 900: second gate insulating layer

[0045] SW TFT1, SW TFT2: first and second pixel switching transistors

[0046] DR TFT1, DR TFT2: first and second pixel driving transistors

[0047] BUF TFT: buffer transistor

[0048] CIRCUIT TFT: circuit transistor DETAILED DESCRIPTION

[0049] Embodiments of the present application will be described below in detail with reference to the accompanying drawings. For the same constituent elements in the drawings, the same reference numerals are used, and repetitive description will be omitted.

[0050] Figure 1 is a block diagram showing a display device according to an embodiment of the present application.

[0051] Referring to Figure 1 , the display device 100 can include a display portion 110, a timing controller 120, a data driver 130, a scan driver 140, and a light-emitting driver 150.

[0052] The display portion 110 can include a plurality of pixels P. The plurality of pixels P can be connected to a plurality of scan lines SL1,..., SLN, a plurality of data lines DL1,..., DLM, and a plurality of light-emitting control lines EL1,..., ELN (N and M are natural numbers).

[0053] The data lines DL1,..., DLM can be connected to the data driving part 130 to transmit data voltages to the pixels P. The scan lines SL1,..., SLN can be connected to the scan driving part 140 to transmit scan signals to the pixels P. The emission control lines EL1,..., ELN can be connected to the emission driving part 150 to transmit emission control signals to the pixels P.

[0054] The pixels P can receive a first power voltage ELVDD and a second power voltage ELVSS. The pixels P can receive the data voltages in response to the scan signals. The pixels P can generate light of a gray level corresponding to the data voltages using the first power voltage ELVDD and the second power voltage ELVSS.

[0055] The timing controller 120 can receive a data signal DATA and a control signal CONT from an external device. In an embodiment, the data signal DATA can include red, green, and blue image data. The control signal CONT can include a horizontal synchronization signal, a vertical synchronization signal, a main clock signal, etc.

[0056] The timing controller 120 can transform the data signal DATA with reference to a specification such as a pixel structure and a resolution of the display part 110, etc., and output to the data driving part 130.

[0057] The timing controller 120 can generate a first control signal CONT1 for driving the data driving part 130, a second control signal CONT2 for driving the scan driving part 140, and a third control signal CONT3 for driving the emission driving part 150 based on the control signal CONT.

[0058] The data driving part 130 can convert the data signal DATA into the data voltages in response to the first control signal CONT1, and output the data voltages to the data lines DL1,..., DLM.

[0059] The scan driving part 140 can generate a plurality of scan signals in response to the second control signal CONT2. The emission driving part 150 can generate a plurality of emission control signals in response to the third control signal CONT3.

[0060] Figure 2 is a circuit diagram showing a pixel circuit and an organic light emitting diode included in a pixel P of Figure 1

[0061] Referring to Figure 1 and Figure 2 ​Each of the pixels P can include a pixel circuit and an organic light emitting diode OLED. The pixel circuit can include a first to seventh transistors TR1, TR2, TR3, TR4, TR5, TR6, TR7 and a storage capacitor CST, a first power voltage ELVDD wire, a second power voltage ELVSS wire, an initialization voltage VINT wire, a data signal DATA wire, a scan signal GW wire, a data initialization signal GI wire, an emission control signal EM wire, a diode initialization signal GB wire. The pixel circuit can be connected to the organic light emitting diode OLED.

[0062] The organic light emitting diode OLED can emit light based on a driving current ID. The organic light emitting diode OLED can include a first terminal and a second terminal. In an embodiment, the second terminal of the organic light emitting diode OLED can receive supply of the second power voltage ELVSS. For example, it can be that the first terminal of the organic light emitting diode OLED is a positive terminal and the second terminal of the organic light emitting diode OLED is a negative terminal. Alternatively, it can be that the first terminal of the organic light emitting diode OLED is a negative terminal and the second terminal of the organic light emitting diode OLED is a positive terminal.

[0063] The first transistor TR1 can include a gate terminal, a first terminal and a second terminal. In an embodiment, it can be that the first terminal of the first transistor TR1 is a source terminal and the second terminal of the first transistor TR1 is a drain terminal. Alternatively, it can be that the first terminal of the first transistor TR1 is a drain terminal and the second terminal of the first transistor TR1 is a source terminal. The same can apply identically to the second to seventh transistors TR2, TR3, TR4, TR5, TR6, TR7 described below. Thus, the description related thereto is omitted below.

[0064] The first transistor TR1 can generate a driving current ID. In an embodiment, the first transistor TR1 can be defined as a pixel driving transistor for driving a pixel. The first transistor TR1 can generate the driving current ID based on a voltage difference between the gate terminal and the source terminal. In addition, a gray scale can be represented in the pixel P based on a magnitude of the driving current ID supplied to the organic light emitting diode OLED.

[0065] The second transistor TR2 can include a gate terminal, a first terminal and a second terminal. The gate terminal of the second transistor TR2 can receive supply of a scan signal GW. The first terminal of the second transistor TR2 can receive supply of a data voltage V_DATA. The second terminal of the second transistor TR2 can be connected to the first terminal of the first transistor TR1.

[0066] The second transistor TR2 can supply the data voltage V_DATA to the first terminal of the first transistor TR1 during an activation interval of the scan signal GW.

[0067] The third transistor TR3 can include a gate terminal, a first terminal, and a second terminal. The gate terminal of the third transistor TR3 can receive a supply of the scan signal GW. The first terminal of the third transistor TR3 can be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 can be connected to the second terminal of the first transistor TR1.

[0068] The third transistor TR3 can connect the gate terminal of the first transistor TR1 and the second terminal of the first transistor TR1 during an activation interval of the scan signal GW. The third transistor TR3 can diode-connect the first transistor TR1 during the activation interval of the scan signal GW. As a result of the diode-connection of the first transistor TR1, a voltage difference of a threshold voltage magnitude of the first transistor TR1 can be generated between the first terminal of the first transistor TR1 and the gate terminal of the first transistor TR1. As a result, a voltage in which the data voltage V_DATA supplied to the first terminal of the first transistor TR1 is added to the voltage difference (i.e., threshold voltage) can be supplied to the gate terminal of the first transistor TR1 during the activation interval of the scan signal GW. That is, the data voltage V_DATA can compensate for the threshold voltage of the first transistor TR1, and the compensated data voltage V_DATA can be supplied to the gate terminal of the first transistor TR1.

[0069] The fourth transistor TR4 can include a gate terminal, a first terminal, and a second terminal. Here, the gate terminal of the fourth transistor TR4 can receive a supply of a data initialization signal GI. The first terminal of the fourth transistor TR4 can receive a supply of the initialization voltage VINT. The second terminal of the fourth transistor TR4 can be connected to the gate terminal of the first transistor TR1.

[0070] The fourth transistor TR4 can supply the initialization voltage VINT to the gate terminal of the first transistor TR1 during an activation interval of the data initialization signal GI. That is, the fourth transistor TR4 can initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT during the activation interval of the data initialization signal GI.

[0071] The fifth transistor TR5 can supply the first power voltage ELVDD to the first terminal of the first transistor TR1 during an active interval of the emission control signal EM. In contrast, the fifth transistor TR5 can cut off the supply of the first power voltage ELVDD during an inactive interval of the emission control signal EM. The fifth transistor TR5 supplies the first power voltage ELVDD to the first terminal of the first transistor TR1 during the active interval of the emission control signal EM, so that the first transistor TR1 can generate the driving current ID. In addition, the fifth transistor TR5 cuts off the supply of the first power voltage ELVDD during the inactive interval of the emission control signal EM, so that the data voltage V_DATA supplied to the first terminal of the first transistor TR1 can be supplied to the gate terminal of the first transistor TR1.

[0072] The sixth transistor TR6 can include a gate terminal, a first terminal, and a second terminal. The gate terminal of the sixth transistor TR6 can receive the supply of the emission control signal EM. The first terminal of the sixth transistor TR6 can be connected to the second terminal of the first transistor TR1. The second terminal of the sixth transistor TR6 can be connected to the first terminal of the organic light emitting diode OLED.

[0073] The sixth transistor TR6 can supply the driving current ID to the organic light emitting diode OLED during the active interval of the emission control signal EM. The sixth transistor TR6 supplies the driving current ID to the organic light emitting diode OLED during the active interval of the emission control signal EM, so that the organic light emitting diode OLED can output light. In addition, the sixth transistor TR6 can electrically separate the first transistor TR1 and the organic light emitting diode OLED from each other during the inactive interval of the emission control signal EM. Thereby, the data voltage V_DATA supplied to the second terminal of the first transistor TR1 can be supplied to the gate terminal of the first transistor TR1.

[0074] The seventh transistor TR7 can include a gate terminal, a first terminal, and a second terminal. The gate terminal of the seventh transistor TR7 can receive the supply of the diode initialization signal GB. The first terminal of the seventh transistor TR7 can receive the supply of the initialization voltage VINT. The second terminal of the seventh transistor TR7 can be connected to the first terminal of the organic light emitting diode OLED.

[0075] The seventh transistor TR7 can supply the initialization voltage VINT to the first terminal of the organic light emitting diode OLED during an activation interval of the diode initialization signal GB. The seventh transistor TR7 can cause the first terminal of the organic light emitting diode OLED to be initialized to the initialization voltage VINT during the activation interval of the diode initialization signal GB.

[0076] The storage capacitor CST can include a first terminal and a second terminal. The storage capacitor CST can be connected between the first power supply voltage ELVDD wiring and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST can be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST can be connected to the first power supply voltage ELVDD wiring. The storage capacitor CST can maintain a voltage level of the gate terminal of the first transistor TR1 during a non-activation interval of the scan signal GW. The non-activation interval of the scan signal GW can include an activation interval of the emission control signal EM. The drive current ID can be supplied to the organic light emitting diode OLED during the activation interval of the emission control signal EM. Accordingly, the drive current ID can be supplied to the organic light emitting diode OLED based on the voltage level maintained by the storage capacitor CST.

[0077] In an embodiment, the second to seventh transistors TR2, TR3, TR4, TR5, TR6, TR7 can be defined as pixel switching transistors.

[0078] Figure 3 is a cross-sectional view illustrating an embodiment of a transistor configured in a display portion of Figure 1 .

[0079] Referring to Figure 1 and Figure 3 , the display device 100 can include a substrate 210, a buffer layer 220, a capacitor electrode CST1, a first interlayer insulating layer 260, a second interlayer insulating layer 270, a via insulating layer 290, a first pixel driving transistor DR_TFT1, a first pixel switching transistor SW_TFT1, a pixel definition layer PDL, and an organic light emitting diode OLED.

[0080] The first pixel driving transistor DR_TFT1 can include a first active layer 230a, a first gate insulating layer 240a, a first gate electrode 250a, a first source electrode 280a, and a first drain electrode 280b. In an embodiment, the first pixel driving transistor DR_TFT1 can correspond to the first transistor TR1 of Figure 2 .

[0081] The first pixel switch transistor SW TFT1 can include a second active layer 230b, a second gate insulating layer 240b, a second gate electrode 250b, a second source electrode 280c, and a second drain electrode 280d. Here, the second gate insulating layer 240b can be a multi-layer including a 2-1 gate insulating layer 240c and a 2-2 gate insulating layer 240d. In an embodiment, the first pixel switch transistor SW TFT1 can correspond to Figure 2 a second to a seventh transistor TR2, TR3, TR4, TR5, TR6, TR7 of FIG. 1.

[0082] The substrate 210 can include a transparent or non-transparent material. For example, the substrate 210 can include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda lime glass substrate, an alkali-free glass substrate, etc. Alternatively, the substrate 210 can also be composed of a transparent resin substrate having flexibility.

[0083] The buffer layer 220 can be disposed on the substrate 210. The buffer layer 220 can prevent a phenomenon of diffusion of metal atoms or impurities from the substrate 210 to the transistor DR TFT1, SW TFT1.

[0084] The first active layer 230a and the second active layer 230b can be disposed on the buffer layer 220. The first active layer 230a and the second active layer 230b can include an inorganic semiconductor (e.g., polysilicon, etc.). The first active layer 230a can include a first channel region 235a having a first length a. In an embodiment, the first length a can be about 10 um to about 30 um. The second active layer 230b can include a second channel region 235b having a second length b shorter than the first length a. In an embodiment, the second length b can be about 1 um to about 5 um. To secure driving voltage and improve afterimage, the first channel region 235a can have the first length a relatively longer than the second length b. To reduce charging time, the second channel region 235b can have the second length b relatively shorter than the first length a.

[0085] In an embodiment, the first channel region 235a can be doped with a group III element. For example, the group III element can include boron (B), aluminum (Al), gallium (Ga), indium (In), etc. In a case where the first pixel driving transistor DR TFT1 is a PMOS transistor, the first channel region 235a can be doped with the group III element. In an embodiment, in a case where the first pixel driving transistor DR TFT1 is an NMOS transistor, the first channel region 235a can be doped with a group V element. In an embodiment, the second channel region 235b can be doped with a group V element. For example, the group V element can include nitrogen (N), phosphorus (P), arsenic (As), etc. In a case where the first pixel switching transistor SW TFT1 is a PMOS transistor, the second channel region 235b can be doped with the group V element. In an embodiment, in a case where the first pixel switching transistor SW TFT1 is an NMOS transistor, the second channel region 235b can be doped with the group III element.

[0086] The first pixel driving transistor DR TFT1 and the first pixel switching transistor SW TFT1 can have different driving ranges from each other. For example, the driving range of the first pixel driving transistor DR TFT1 can be about 3 V to about 3.5 V. The driving range of the first pixel switching transistor SW TFT1 can be narrower than the driving range of the first pixel driving transistor DR TFT1. As the second channel region 235b is doped with the group V element, a reaction time required when the first pixel switching transistor SW TFT1 is turned on / off can be delayed.

[0087] The first gate insulating layer 240a can cover the first active layer 230a and be disposed on the buffer layer 220. The first gate insulating layer 240a can be a single layer including silicon oxide (SiO x ).

[0088] The second gate insulating layer 240b can cover the second active layer 230b and be disposed on the buffer layer 220. The 2-1 gate insulating layer 240c can be disposed on the second active layer 230b. The 2-1 gate insulating layer 240c can be a single layer including silicon oxide (SiO x ). The 2-2 gate insulating layer 240d can be disposed on the 2-1 gate insulating layer 240c. The 2-2 gate insulating layer 240d can be a single layer including silicon nitride (SiN x ).

[0089] In an embodiment, the first gate insulating layer 240a and the second gate insulating layer 240b can be configured in the same layer. In addition, the thickness of the first gate insulating layer 240a and the second gate insulating layer 240b can be the same. As the first pixel switch transistor SW TFT1 has a relatively short second length b, it can be more affected by signals flowing in the second source electrode 280c and the second drain electrode 280d. However, as the second gate insulating layer 240b has a multi-layer structure including the silicon oxide (SiO x ) and the silicon nitride (SiN x ), the second gate insulating layer 240b can have a reduced dielectric constant compared to when it includes only the silicon oxide (SiO x ). Thus, the second gate electrode 250b can be more affected than the second source electrode 280c and the second drain electrode 280d.

[0090] The first gate electrode 250a can be configured on the first gate insulating layer 240a. The first gate electrode 250a can overlap the first active layer 230a. The second gate electrode 250b can be configured on the second gate insulating layer 240b. The second gate electrode 250b can overlap the second active layer 230b. The first gate electrode 250a and the second gate electrode 250b can include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc.

[0091] The first interlayer insulating layer 260, which covers the first gate electrode 250a on the first gate insulating layer 240a and covers the second gate electrode 250b on the second gate insulating layer 240b, can be configured. The first interlayer insulating layer 260 can include a silicon compound, a metal oxide, etc.

[0092] The capacitor electrode CST1 can be configured on the first interlayer insulating layer 260. The capacitor electrode CST1 can overlap the first gate electrode 250a. The capacitor electrode CST1 can include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc.

[0093] The second interlayer insulating layer 270, which covers the capacitor electrode CST1, can be configured on the first interlayer insulating layer 260. The second interlayer insulating layer 270 can include a silicon compound, a metal oxide, etc.

[0094] The first source electrode 280a and the first drain electrode 280b can be connected to a source region of the first active layer 230a and a drain region of the first active layer 230a, respectively, through contact holes. The second source electrode 280c and the second drain electrode 280d can be connected to a source region of the second active layer 230b and a drain region of the second active layer 230b, respectively, through contact holes. The first source electrode 280a, the first drain electrode 280b, the second source electrode 280c, and the second drain electrode 280d can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, or the like.

[0095] The via insulating layer 290 can be configured to cover the first source electrode 280a, the first drain electrode 280b, the second source electrode 280c, and the second drain electrode 280d on the second interlayer insulating layer 270. The via insulating layer 290 can include an organic substance or an inorganic substance.

[0096] The lower electrode 310 can be configured on the via insulating layer 290. The lower electrode 310 can be connected to the first drain electrode 280b through a contact hole. In an embodiment, the lower electrode 310 can be a positive electrode. Alternatively, the lower electrode 310 can also be a negative electrode. The lower electrode 310 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, or the like.

[0097] The pixel defining film PDL can be configured on the via insulating layer 290. The pixel defining film PDL can have an opening that exposes an upper surface of the lower electrode 310. The pixel defining film PDL can be composed of an organic substance or an inorganic substance.

[0098] The intermediate layer 320 can be configured on the lower electrode 310 exposed through the pixel defining film PDL. The intermediate layer 320 can include at least one selected from a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer.

[0099] The upper electrode 330 can be disposed on the intermediate layer 320 and the pixel defining film PDL. The upper electrode 330 can be disposed on the entire surface of the substrate 210 to cover the intermediate layer 320 and the pixel defining film PDL. In an embodiment, the upper electrode 330 can be a cathode. Alternatively, the upper electrode 330 can be an anode. The upper electrode 330 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, or the like.

[0100] Figure 4 is a cross-sectional view illustrating another embodiment of a transistor disposed in a display portion of Figure 1 .

[0101] Referring to Figure 1 and Figure 4 , the display device 100 can include a substrate 410, a buffer layer 420, a first interlayer insulating layer 460, a second interlayer insulating layer 480, a third interlayer insulating layer 530, a via insulating layer 550, a second pixel driving transistor DR_TFT2, a second pixel switching transistor SW_TFT2, a pixel defining film PDL, and an organic light emitting diode OLED.

[0102] The second pixel driving transistor DR_TFT2 can include a first active layer 430, a first gate insulating layer 440, a first gate electrode 450, a connection electrode 470, a first source electrode 540a, and a first drain electrode 540b. The second pixel driving transistor DR_TFT2 can correspond to a first transistor TR1 of Figure 2 .

[0103] The second pixel switching transistor SW_TFT2 can include a second active layer 490, a second gate insulating layer 510, a second gate electrode 520, a second source electrode 540c, and a second drain electrode 540d. Here, the second gate insulating layer 510 can include a 2-1 gate insulating layer 500 and a 2-2 gate insulating layer 505. The second pixel switching transistor SW_TFT2 can correspond to a second transistor to a seventh transistor TR2, TR3, TR4, TR5, TR6, TR7 of Figure 2 .

[0104] The substrate 410 can include a transparent or non-transparent material. For example, the substrate 410 can include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda lime glass substrate, an alkali-free glass substrate, or the like. Alternatively, the substrate 410 can also be composed of a transparent resin substrate having flexibility.

[0105] The buffer layer 420 can be disposed on the substrate 410. The buffer layer 420 can prevent a phenomenon in which metal atoms or impurities diffuse from the substrate 410 to the transistor DR TFT2, SW TFT2.

[0106] The first active layer 430 can be disposed on the buffer layer 420. The first active layer 430 can include an inorganic semiconductor (e.g., polysilicon, etc.). The first active layer 430 can include a first channel region 435 having the first length a. In an embodiment, the first channel region 435 can be doped with a third group element. In a case where the second pixel driving transistor DR TFT2 is a PMOS transistor, the first channel region 435 can be doped with the third group element. In an embodiment, in a case where the second pixel driving transistor DR TFT2 is an NMOS transistor, the first channel region 435 can be doped with a fifth group element.

[0107] The first gate insulating layer 440 can be disposed on the buffer layer 420 to cover the first active layer 430. The first gate insulating layer 440 can be a single layer including silicon oxide (SiO x ).

[0108] The first gate electrode 450 can be disposed on the first gate insulating layer 440. The first gate electrode 450 can overlap the first active layer 430. The first gate electrode 450 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, etc.

[0109] The first interlayer insulating layer 460 covering the first gate electrode 450 can be disposed on the first gate insulating layer 440. The first interlayer insulating layer 460 can include a silicon compound, a metal oxide, etc.

[0110] The connection electrode 470 can be disposed on the first interlayer insulating layer 460. The connection electrode 470 can overlap the first gate electrode 450. The connection electrode 470 can be connected with a drain region of the first active layer 430. The connection electrode 470 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, etc.

[0111] The second interlayer insulating layer 480 covering the connection electrode 470 can be disposed on the first interlayer insulating layer 460. The second interlayer insulating layer 480 can include a silicon compound, a metal oxide, etc.

[0112] The second active layer 490 can be disposed on the second interlayer insulating layer 480. The second active layer 490 can include an inorganic semiconductor (e.g., polysilicon, etc.). The second active layer 490 can include a second channel region 495 having a second length b shorter than the first length a. In an embodiment, the second channel region 495 can be doped with a fifth group element. In a case where the second pixel switching transistor SW TFT2 is a PMOS transistor, the second channel region 495 can be doped with the fifth group element. In an embodiment, in a case where the second pixel switching transistor SW TFT2 is an NMOS transistor, the second channel region 495 can be doped with a third group element.

[0113] To secure driving voltage and improve residual image, the first channel region 435 can have the first length a longer than the second length b. To reduce charging time, the second channel region 495 can have the second length b shorter than the first length a.

[0114] The 2-1 gate insulating layer 500 can be disposed on the second interlayer insulating layer 480 to cover the second active layer 490. The 2-1 gate insulating layer 500 can be a single layer including silicon oxide (SiO x ) on the 2-1 gate insulating layer 500. The 2-2 gate insulating layer 505 can be disposed on the 2-1 gate insulating layer 500. The 2-2 gate insulating layer 505 can be a single layer including silicon nitride (SiN x ) on the 2-1 gate insulating layer 500. In an embodiment, the second gate insulating layer 510 can be a multi-layer including the 2-1 gate insulating layer 500 and the 2-2 gate insulating layer 505.

[0115] The second gate electrode 520 can be disposed on the second gate insulating layer 510. The second gate electrode 520 can overlap the second active layer 490. The second gate electrode 520 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, etc.

[0116] The third interlayer insulating layer 530 covering the second gate electrode 520 can be disposed on the second gate insulating layer 510. The third interlayer insulating layer 530 can include a silicon compound, a metal oxide, etc.

[0117] The first source electrode 540a, the first drain electrode 540b, the second source electrode 540c, and the second drain electrode 540d can be provided over the third interlayer insulating layer 530. The first source electrode 540a can be connected to a source region of the first active layer 430. The first drain electrode 540b can be connected to a drain region of the first active layer 430 through the connection electrode 470. The first drain electrode 540b can be connected to the lower electrode 610. In Figure 4 The first source electrode 540a and the first drain electrode 540b are shown as being provided over the third interlayer insulating layer 530, but are not limited thereto. For example, the first source electrode 540a and the first drain electrode 540b can be provided in the same layer as the second gate electrode 520. In this case, the first drain electrode 540b can be connected to the lower electrode 610 through another conductive pattern.

[0118] The second source electrode 540c can be connected to a source region of the second active layer 490. The second drain electrode 540d can be connected to a drain region of the second active layer 490. The first source electrode 540a, the first drain electrode 540b, the second source electrode 540c, and the second drain electrode 540d can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, or the like.

[0119] The via insulating layer 550 can be provided over the third interlayer insulating layer 530 so as to cover the first source electrode 540a, the first drain electrode 540b, the second source electrode 540c, and the second drain electrode 540d. The via insulating layer 550 can include an organic substance or an inorganic substance.

[0120] The lower electrode 610 can be provided over the via insulating layer 550. The lower electrode 610 can be connected to the first drain electrode 540b. In an embodiment, the lower electrode 610 can be a positive electrode. Alternatively, the lower electrode 610 can be a negative electrode. The lower electrode 610 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, or the like.

[0121] The pixel defining film PDL can be provided over the via insulating layer 550. The pixel defining film PDL can have an opening that exposes an upper surface of the lower electrode 610. The pixel defining film PDL can be formed of an organic substance or an inorganic substance.

[0122] The intermediate layer 620 can be disposed on the lower electrode 610 exposed through the pixel definition layer PDL. The intermediate layer 620 can include a light emitting substance capable of generating different color light such as red light, green light, blue light, etc.

[0123] The upper electrode 630 can be disposed on the intermediate layer 620 and the pixel definition layer PDL. The upper electrode 630 can be integrally disposed on the substrate 410 to cover the intermediate layer 620 and the pixel definition layer PDL. In an embodiment, the upper electrode 630 can be a cathode. Alternatively, the upper electrode 630 can be an anode. The upper electrode 630 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, etc.

[0124] As such, the second pixel switch transistor SW TFT2 is disposed on the second pixel driving transistor DR TFT2, so that the second pixel switch transistor SW TFT2 can overlap at least a portion of the second pixel driving transistor DR TFT2. Thereby, a dead space of the display device 100 can be reduced.

[0125] Figure 5 is a circuit diagram illustrating an embodiment of a scan circuit of a scan driving part disposed on Figure 1 .

[0126] Referring to Figure 1 and Figure 5 , the scan driving part 140 according to an embodiment of the present application can include a plurality of stages, each of which can include a scan circuit. The scan circuit can include a first input part 710, a second input part 720, a first output part 730, and a second output part 740. In an embodiment, the scan circuit can further include a holding part 750, a synchronization driving control part 760, and a stabilization part 770.

[0127] The first input part 710 can transfer an input signal to a set node NQ in response to a second clock signal CLK2. For example, the first input part 710 of a first stage of the scan driving part 140 can receive a start signal FLM as the input signal, and the remaining stages can receive a previous scan signal PSCAN as the input signal. In an embodiment, the first input part 710 can include a first input transistor T1 including a gate terminal receiving the second clock signal CLK2, a first terminal receiving the input signal, and a second terminal connected to the set node NQ.

[0128] The second input portion 720 can transfer the first clock signal CLK1 to the reset node NQB in response to the input signal and the second clock signal CLK2. For example, when the input signal and the second clock signal CLK2 have an active level, the second input portion 720 can transfer the first clock signal CLK1 having an inactive level to the reset node NQB. In an embodiment, the second input portion 720 can include a second input transistor T2_1 including a gate terminal receiving the input signal, a first terminal receiving the first clock signal CLK1, and a second terminal, and a third input transistor T2_2 including a gate terminal receiving the second clock signal CLK2, a first terminal connected to the second terminal of the second input transistor T2_1, and a second terminal connected to the reset node NQB.

[0129] The holding portion 750 can hold a voltage of the reset node NQB in response to the first clock signal CLK1. For example, when the first clock signal CLK1 has a low level, the holding portion 750 can hold the voltage of the reset node NQB as the low level. In an embodiment, the holding portion 750 can include a holding transistor T5 including a gate terminal receiving the first clock signal CLK1, a first terminal receiving the first clock signal CLK1, and a second terminal connected to the reset node NQB.

[0130] The synchronous driving control portion 760 can inactivate the first output portion 730 in response to a synchronous driving signal GCK. In an embodiment, the synchronous driving signal GCK can have a low level in a synchronous compensation interval and a high level in a remaining interval. In the synchronous compensation interval, the synchronous driving control portion 760 can transfer a high level of a gate cut-off voltage VGH to the set node NQ in response to the low level of the synchronous driving signal GCK. Through the gate cut-off voltage VGH of the set node NQ, the first output portion 730 can be inactivated. In an embodiment, the synchronous driving control portion 760 can include a synchronous driving control transistor T6 including a gate terminal receiving the synchronous driving signal GCK, a first terminal receiving the gate cut-off voltage VGH, and a second terminal connected to the set node NQ.

[0131] The stabilizing section 770 can stabilize the scan signal SCAN in response to the voltage of the reset node NQB and the third clock signal CLK3. For example, the stabilizing section 770 can stabilize the scan signal SCAN to a high level when the voltage of the reset node NQB and the third clock signal CLK3 have a low level. In an embodiment, the stabilizing section 770 can include a second stabilizing transistor T7_2 including a gate terminal receiving the third clock signal CLK3, a first terminal connected to the set node NQ, and a second terminal, and a first stabilizing transistor T7_1 including a gate terminal connected to the reset node NQB, a first terminal connected to the second terminal of the second stabilizing transistor T7_2, and a second terminal connected to an output node NO.

[0132] The first output section 730 can output the third clock signal CLK3 as the scan signal SCAN in response to the voltage of the set node NQ. For example, in the data programming interval, a low level of the input signal can be transferred to the set node NQ in response to a pulse of the second clock signal CLK2. Then, under a next pulse of the third clock signal CLK3, the voltage of the set node NQ can be changed from the low level to a lower level by a first output capacitor C730 of the first output section 730. A first output transistor T3 of the first output section 730 can output the third clock signal CLK3 of a low level as the scan signal SCAN in response to the changed voltage of the set node NQ. In an embodiment, the first output section 730 includes the first output transistor T3 including a gate terminal connected to the set node NQ, a first terminal receiving the third clock signal CLK3, and a second terminal connected to the output node NO, and the first output capacitor C730 including a first electrode connected to the set node NQ and a second electrode connected to the output node NO.

[0133] The second output portion 740 can output a synchronization driving signal GCK as a scan signal SCAN in response to a voltage of the reset node NQB. For example, in the synchronization compensation interval, when the synchronization driving signal GCK changes from a high level to a low level, the voltage of the reset node NQB can change from the low level to a lower level through the second output capacitor C740 of the second output portion 740. The second output transistor T4 of the second output portion 740 can output the synchronization driving signal GCK of the low level as the scan signal SCAN in response to the changed voltage of the reset node NQB. In an embodiment, the second output portion 740 can include the second output transistor T4 including a gate terminal connected to the reset node NQB, a first terminal receiving the synchronization driving signal GCK, and a second terminal connected to the output node NO, and the second output capacitor C740 including a first electrode connected to the reset node NBQ and a second electrode receiving the synchronization driving signal GCK.

[0134] The first output portion 730 and the second output portion 740 can be connected to a scan signal output portion of the scan circuit. The first output transistor T3 and the second output transistor T4 connected to the scan signal output portion can be defined as scan buffer transistors. The transistors T1, T2_1, T2_2, T5, T6, T7_1, T7_2 of the scan circuit except for the first output transistor T3 and the second output transistor T4 can be defined as scan circuit transistors.

[0135] Figure 6 is a circuit diagram illustrating an embodiment of a light emitting circuit configured in a light emitting driving portion of Figure 1 .

[0136] Referring to Figure 1 and Figure 6 , the light emitting driving portion 150 according to an embodiment of the present application can include a light emitting circuit. The light emitting circuit can include a plurality of transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13 and a plurality of capacitors C1, C2, C3. The light emitting circuit can be applied with a plurality of signals IN, CLK1, CLK2, VGL, VGH, ESR, and can output a light emitting control signal EM in response to the signals.

[0137] In an embodiment, the transistors M9, M10 connected to a light emitting control signal output portion outputting the light emitting control signal EM can be defined as light emitting buffer transistors, and the remaining transistors M1, M2, M3, M4, M5, M6, M7, M8, M11, M12, M13 except for the light emitting buffer transistors can be defined as light emitting circuit transistors.

[0138] The light emitting circuit can output the light emitting control signal EM to the display portion 110. The light emitting circuit can receive inputs of the first clock signal CLK1, the second clock signal CLK2, the protection signal ESR, the first gate power supply voltage VGH, the second gate power supply voltage VGL, and output the light emitting control signal EM.

[0139] The light emitting circuit can include a ninth transistor M9 connected between a first gate power supply voltage terminal to which the first gate power supply voltage VGH is applied and a light emitting control signal output terminal to output the light emitting control signal EM, and a tenth transistor M10 connected between a second gate power supply voltage terminal to which the second gate power supply voltage VGL is applied and the light emitting control signal output terminal.

[0140] The light emitting circuit can further include a thirteenth transistor M13 to apply the first gate power supply voltage VGH to a control electrode of the tenth transistor M10 in response to the protection signal ESR.

[0141] The light emitting circuit can include a pull-down portion involved in an operation to pull down the light emitting control signal EM to the second gate power supply voltage VGL. The pull-down portion can include a first transistor M1, a second transistor M2, a third transistor M3, the tenth transistor M10, and a twelfth transistor M12.

[0142] The first transistor M1 can output a gate signal to a fourth node X4 in response to the first clock signal CLK1. A control electrode of the first transistor M1 can be connected to the first clock terminal to which the first clock signal CLK1 is applied, an input electrode IN of the first transistor M1 can be connected to an input terminal to which the gate signal is applied, and an output electrode of the first transistor M1 can be connected to the fourth node X4.

[0143] The second transistor M2 can output the first gate power supply voltage VGH to a second node X2 in response to a voltage of a first node X1. A control electrode of the second transistor M2 can be connected to the first node X1, an input electrode of the second transistor M2 can be connected to the first gate power supply voltage terminal, and an output electrode of the second transistor M2 can be connected to the second node X2.

[0144] The third transistor M3 can output the second clock signal CLK2 to the second node X2 in response to a voltage of the third node X3. A control electrode of the third transistor M3 can be connected to the third node X3, an input electrode of the third transistor M3 can be connected to the second clock terminal to which the second clock signal CLK2 is applied, and an output electrode of the third transistor M3 can be connected to the second node X2.

[0145] The tenth transistor M10 can output the second gate power supply voltage VGL to an output terminal outputting the emission control signal EM in response to a voltage of the eighth node X8. A control electrode of the tenth transistor M10 can be connected to the eighth node X8, an input electrode of the tenth transistor M10 can be connected to the second gate power supply voltage terminal, and an output electrode of the tenth transistor M10 can be connected to the output terminal.

[0146] The twelfth transistor M12 can output a voltage of the fourth node X4 to the eighth node X8 in response to the second gate power supply voltage VGL. A control electrode of the twelfth transistor M12 can be connected to the second gate power supply voltage terminal, an input electrode of the twelfth transistor M12 can be connected to the fourth node X4, and an output electrode of the twelfth transistor M12 can be connected to the eighth node X8.

[0147] The emission circuit can include a pull-up portion involved in an operation of pulling up the emission control signal EM to the first gate power supply voltage VGH. The pull-up portion can include a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and an eleventh transistor M11.

[0148] The fourth transistor M4 can output the first clock signal CLK1 to the first node X1 in response to a voltage of the fourth node X4. The fourth transistor M4 can include a control electrode connected to the fourth node X4, an input electrode connected to the first clock terminal, and an output electrode connected to the first node X1.

[0149] The fifth transistor M5 can output the second gate power supply voltage VGL to the first node X1 in response to the first clock signal CLK1. The fifth transistor M5 includes a control electrode connected to the first clock terminal, an input electrode connected to the second gate power supply voltage terminal, and an output electrode connected to the first node X1.

[0150] The sixth transistor M6 can connect the fifth node X5 and the seventh node X7 in response to the second clock signal CLK2. The sixth transistor M6 can include a control electrode connected to the second clock terminal, an input electrode connected to the fifth node X5, and an output electrode connected to the seventh node X7.

[0151] The seventh transistor M7 can output the second clock signal CLK2 to the fifth node X5 in response to a voltage of the sixth node X6. The seventh transistor M7 can include a control electrode connected to the sixth node X6, an input electrode connected to the second clock terminal, and an output electrode connected to the fifth node X5.

[0152] The eighth transistor M8 can output the first gate power supply voltage VGH to the seventh node X7 in response to a voltage of the fourth node X4. The eighth transistor M8 can include a control electrode connected to the fourth node X4, an input electrode connected to the first gate power supply voltage terminal, and an output electrode connected to the seventh node X7.

[0153] The ninth transistor M9 can output the first gate power supply voltage VGH to the output terminal in response to a voltage of the seventh node X7. The ninth transistor M9 can include a control electrode connected to the seventh node X7, an input electrode connected to the first gate power supply voltage terminal, and an output electrode connected to the output terminal.

[0154] The eleventh transistor M11 can connect the first node X1 to the sixth node X6 in response to the second gate power supply voltage VGL. The eleventh transistor M11 can include a control electrode connected to the second gate power supply voltage terminal, an input electrode connected to the first node X1, and an output electrode connected to the sixth node X6.

[0155] The light emitting circuit can further include a first capacitor C1 including a first electrode connected to the first gate power supply voltage terminal and a second electrode connected to the seventh node X7, a second capacitor C2 including a first electrode connected to the fifth node X5 and a second electrode connected to the sixth node X6, and a third capacitor C3 including a first electrode connected to the second node X2 and a second electrode connected to the third node X3.

[0156] The first capacitor C1 can be a stabilizing capacitor that stabilizes the voltage of the seventh node X7. The second capacitor C2 can be a variable voltage capacitor that performs an operation of sufficiently pulling down the voltage of the seventh node X7 to a low level. The third capacitor C3 can be a variable voltage capacitor that performs an operation of sufficiently pulling down the voltage of the eighth node X8 to a low level.

[0157] In an embodiment, the thirteenth transistor M13 can be connected to the fourth node X4.

[0158] Figure 7 FIG. 1 is a diagram illustrating an embodiment of a buffer transistor and a circuit transistor.

[0159] Referring to Figure 5 and Figure 7 , the display device 100 can include a substrate 810, a buffer layer 820, a first interlayer insulating layer 860, a second interlayer insulating layer 880, a third interlayer insulating layer 920, a via insulating layer 940, a buffer transistor BUF_TFT, and a circuit transistor CIRCUIT_TFT.

[0160] In an embodiment, the buffer transistor BUF_TFT can be the scan buffer transistor. In this case, the buffer transistor BUF_TFT can be the first output transistor T3 and the second output transistor T4. The structure of the buffer transistor BUF_TFT can be substantially the same as that of the first pixel switch transistor SW_TFT1 of Figure 3 . The circuit transistor CIRCUIT_TFT can be the scan circuit transistor. In this case, the circuit transistor CIRCUIT_TFT can be the transistors T1, T2_1, T2_2, T5, T6, T7_1, T7_2. The structure of the circuit transistor CIRCUIT_TFT can be substantially the same as that of the first pixel drive transistor DR_TFT1 of Figure 3 .

[0161] Referring to Figure 6 and Figure 7 , in an embodiment, the buffer transistor BUF_TFT can be the emission buffer transistor. In this case, the buffer transistor BUF_TFT can be the transistors M9, M10 connected to the emission control signal output portion. The circuit transistor CIRCUIT_TFT can be the emission circuit transistor. In this case, the circuit transistor CIRCUIT_TFT can be the transistors M1, M2, M3, M4, M5, M6, M7, M8, M11, M12, M13.

[0162] Referring to Figure 7The buffer transistor BUF_TFT can include a first active layer 850, a first gate insulating layer 840, a first gate electrode 870, a first source electrode 890a, and a first drain electrode 890b. The first gate insulating layer 840 can be a multi-layer including a 1-1 gate insulating layer 830 and a 1-2 gate insulating layer 835. The circuit transistor CIRCUIT_TFT can include a second active layer 910, a second gate insulating layer 900, a second gate electrode 930, a second source electrode 950a, and a second drain electrode 950b.

[0163] In an embodiment, the 1-1 gate insulating layer 830 can include silicon oxide (SiO x ). The 1-2 gate insulating layer 835 can include silicon nitride (SiN x ). The second gate insulating layer 900 can be a single layer including silicon oxide (SiO x ).

[0164] The second channel region 915 of the second active layer 910 can have the first length a, and the first channel region 855 of the first active layer 850 can have the second length b shorter than the first length a. The buffer transistor BUF_TFT includes the first channel region 855 having the relatively short second length b, thereby being able to reduce a useless space of the display device. In addition, the buffer transistor BUF_TFT includes the first channel region 855 having the relatively short second length b, thereby being able to effectively transmit a signal to the display portion 110 as the amount of current flowing in the first active layer 850 becomes greater. In addition, the second active layer 910 includes the second channel region 915 having a relatively long length, thereby being able to stably drive the scan driving portion 140 and the light emitting driving portion 150. Figure 1

[0165] In the above-described embodiment, the exemplary embodiments of the present application are described with reference to the drawings, but it will be understood by those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the present application as recited in the following claims.

[0166] (Industrial applicability)

[0167] The present application can be applied to a display device. For example, the present application can be applied to a high-resolution smart phone, a portable phone, a smart pad, a smart watch, a tablet computer, a navigation system for a vehicle, a television, a computer monitor, a notebook computer, etc.​

Claims

1. A display device, characterized by comprising: The display device includes a pixel including a pixel drive transistor and a pixel switch transistor, The pixel drive transistor includes: a first active layer doped with a third group element and including a first channel region having a first length; a first gate insulating layer disposed on the first active layer; a first gate electrode disposed on the first gate insulating layer; a first source electrode disposed on the first gate electrode and connected to a source region of the first active layer; and a first drain electrode disposed on the first gate electrode and connected to a drain region of the first active layer, The pixel switch transistor includes: a second active layer doped with a fifth group element and including a second channel region having a second length shorter than the first length; a second gate insulating layer disposed on the second active layer; a second gate electrode disposed on the second gate insulating layer; a second source electrode disposed on the second gate electrode and connected to a source region of the second active layer; and a second drain electrode disposed on the second gate electrode and connected to a drain region of the second active layer, The pixel drive transistor and the pixel switch transistor are PMOS transistors.

2. The display device according to claim 1, wherein the first gate insulating layer and the second gate insulating layer are disposed on the same layer, the first gate insulating layer is a single layer including a silicon oxide-based substance, the second gate insulating layer is a multi-layer including a 2-1 gate insulating layer and a 2-2 gate insulating layer, the 2-1 gate insulating layer includes the silicon oxide-based substance, the 2-2 gate insulating layer is disposed on the 2-1 gate insulating layer and includes a silicon nitride-based substance.

3. The display device according to claim 1, wherein the first length is 10 um to 30 um, the second length is 1 um to 5 um.

4. The display device according to claim 1, wherein the pixel further includes: a capacitor electrode disposed on the first gate electrode and disposed below the first source electrode and the first drain electrode.

5. The display device according to claim 4, wherein the pixel further includes: an organic light emitting diode connected to the pixel drive transistor, the organic light emitting diode includes: a lower electrode connected to the first drain electrode; an intermediate layer disposed on the lower electrode; and an upper electrode disposed on the intermediate layer.

6. The display device according to claim 1, wherein the display device further includes: a scan drive portion that supplies a scan signal to the pixel and includes a scan buffer transistor and a scan circuit transistor, the scan circuit transistor includes: a third active layer doped with the third group element and including a third channel region having the first length; a third gate insulating layer disposed on the third active layer; a third gate electrode disposed on the third gate insulating layer; a third source electrode disposed on the third gate electrode and connected to a source region of the third active layer, and a third drain electrode disposed on the third gate electrode and connected to a drain region of the third active layer, the scan buffer transistor includes: a fourth active layer doped with the fifth group element and including a fourth channel region having the second length; a fourth gate insulating layer disposed on the fourth active layer; a fourth gate electrode disposed on the fourth gate insulating layer; a fourth source electrode disposed on the fourth gate electrode and connected to a source region of the fourth active layer, and a fourth drain electrode disposed on the fourth gate electrode and connected to a drain region of the fourth active layer.

7. The display device according to claim 6, wherein the third gate insulating layer is a single layer including a silicon oxide-based substance, the fourth gate insulating layer is a multilayer including a 4-1 gate insulating layer and a 4-2 gate insulating layer, the 4-1 gate insulating layer includes the silicon oxide-based substance, the 4-2 gate insulating layer is disposed on the 4-1 gate insulating layer and includes a silicon nitride-based substance.

8. The display device according to claim 6, wherein the scan buffer transistor is connected to a scan signal output portion of the scan driving portion.

9. The display device according to claim 6, wherein the scan circuit transistor is disposed on the scan buffer transistor.

10. The display device according to claim 1, wherein the display device further includes: a light emission driving portion that supplies a light emission control signal to the pixel and includes a light emission buffer transistor and a light emission circuit transistor, the light emission circuit transistor includes: a fifth active layer doped with the third group element and including a fifth channel region having the first length; a fifth gate insulating layer disposed on the fifth active layer; a fifth gate electrode disposed on the fifth gate insulating layer; a fifth source electrode disposed on the fifth gate electrode and connected to a source region of the fifth active layer, and a fifth drain electrode disposed on the fifth gate electrode and connected to a drain region of the fifth active layer, the light emission buffer transistor includes: a sixth active layer doped with the fifth group element and including a sixth channel region having the second length; a sixth gate insulating layer disposed on the sixth active layer; a sixth gate electrode disposed on the sixth gate insulating layer; a sixth source electrode disposed on the sixth gate electrode and connected to a source region of the sixth active layer, and a sixth drain electrode disposed on the sixth gate electrode and connected to a drain region of the sixth active layer.

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