Homomorphic encryption apparatus and ciphertext arithmetic method thereof
By generating re-encryption parameters and optimizing ciphertext levels using arithmetic circuits in the homomorphic encryption device, the problems of high computational load and slow speed in homomorphic encryption technology are solved, achieving more efficient and secure communication.
CN113810169BActive Publication Date: 2026-03-31SAMSUNG ELECTRONICS CO LTD
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Patent Information
- Application Number
- CN202110143171.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-05-29
- Filing Date
- 2021-02-02
- Publication Date
- 2026-03-31
- Estimated Expiration
- 2041-02-02
AI Technical Summary
Technical Problem
Existing homomorphic encryption technology requires frequent re-encryption of ciphertext when performing arithmetic operations, resulting in high computational load, slow operation speed, and the risk of hacker attacks.
Method used
By employing the re-encryption parameter generation circuit and arithmetic circuit in the homomorphic encryption device, the ciphertext level is optimized, unnecessary re-encryption operations are reduced, and operational efficiency is improved by generating and applying re-encryption parameters.
Benefits of technology
It reduces the computational cost of re-encryption, increases the operating speed of homomorphic encryption devices, reduces the risk of hacker attacks, and enhances communication security.
✦ Generated by Eureka AI based on patent content.
Abstract
A homomorphic encryption apparatus and a ciphertext arithmetic method thereof are disclosed. The homomorphic encryption apparatus includes a re-encryption parameter generation circuit, a re-encryption circuit, and an arithmetic circuit. The re-encryption parameter generation circuit is configured to generate re-encryption parameters including a plurality of re-encryption levels for a plurality of ciphertexts, respectively, based on an arithmetic scenario including information on an arithmetic schedule between the plurality of ciphertexts. The re-encryption circuit is configured to generate a plurality of re-encrypted ciphertexts by re-encrypting each of the plurality of ciphertexts to a corresponding re-encryption level based on the re-encryption parameters. The arithmetic circuit is configured to output an arithmetic result by performing an operation using the plurality of re-encrypted ciphertexts according to the arithmetic scenario.
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