Full alignment elimination process and electronics derived therefrom

Abstract

A method of forming a fully aligned via connecting two metal lines extending in two directions is described. The fully aligned via is aligned with a first metal line and a second metal line along two directions. A third metal layer is patterned on top of a second metal layer that is in electrical contact with the first metal layer. The patterned third metal layer is not aligned with the top of the second metal layer. The second metal layer is recessed to expose a side of the second metal layer and a portion of the side that is not aligned with the third metal layer is removed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to the fields of electronic devices and electronic device manufacturing. More specifically, embodiments of the present disclosure provide methods for producing electronic devices with perfectly aligned vias and / or contacts using a subtractive process. Background Art

[0002] Electronic devices (such as personal computers, workstations, computer servers, mainframes) and other computer-related equipment (such as printers, scanners, and hard drives) use memory devices that provide large amounts of data storage capabilities while reducing power consumption. There are two main types of random access memory cells (dynamic and static) that are well suited for use in electronic devices. Dynamic random access memory (DRAM) can be programmed to store a voltage representing one of two binary values, but needs to be reprogrammed or "refreshed" periodically to maintain this voltage for a very short period of time. Static random access memory (SRAM) is so called because they do not require regular refreshing.

[0003] Previously, "dual damascene" manufacturing techniques have been used to produce on-chip electrical interconnects, in which apertures are created through various layers of a device structure and filled with a conductive material to form interconnects between layers and between device features located on the various layers. However, for chips based on the 10nm node and smaller feature sizes, there are gap fill and resistivity limitations that make the use of the previously relied upon "dual damascene" manufacturing techniques impractical.

[0004] Current processes often encounter via alignment issues during interconnect fabrication. At advanced technology nodes, there is little or no margin for via alignment errors. Elimination schemes have been developed to allow the formation of vias (Vx) that are self-aligned with the underlying metal lines (Mx). However, the top metal lines (Mx+1) are not self-aligned, which can lead to alignment errors.

[0005] Therefore, a need exists for a method of forming an electronic device that reduces or eliminates via alignment errors. Summary of the invention

[0006] Embodiments of the present disclosure relate to a method of forming a fully aligned via. A third metal layer is patterned on top of a second metal layer. The second metal layer is in electrical contact with a first metal layer. The patterned third metal layer is misaligned with the second metal layer so that a portion of the top of the second metal layer is exposed. The top of the second metal layer is recessed to expose a side of the second metal layer aligned with the patterned third metal layer. The top of the second metal layer is recessed a distance from the bottom of the third metal layer.

[0007] Another embodiment of the present disclosure is directed to a method of forming a fully aligned via. A patterned third metal layer is formed on top of a patterned metal pad on a second metal layer. The second metal layer is in electrical contact with the first metal layer. The patterned third metal layer and the patterned metal pad are not aligned with the second metal layer so that a portion of the top of the second metal layer is exposed through an opening in the patterned third metal layer and the patterned metal pad. The second metal layer is recessed through the opening in the patterned third metal layer and the patterned metal pad to lower the top of the second metal layer and expose the sides of the second metal layer aligned with the sides of the patterned third metal layer and the top surface of the second metal layer spaced a distance from the bottom surface of the metal pad. The surface of the second metal layer is spaced about 100 mm from the bottom surface of the metal pad. to about distance within the range.

[0008] Other embodiments of the present disclosure relate to an electronic device. The electronic device includes a second metal layer, which contacts the first metal layer via a first etch stop layer. The second metal layer has a top portion, the top portion having an exposed side and a recessed top surface. The exposed side has a length. A dielectric layer is around the portion of the second metal layer. The dielectric layer has a top surface, which is substantially flush with the recessed top surface of the second metal layer. A patterned metal pad is located on the second metal layer and the dielectric layer. The patterned metal pad has an opening that exposes the top surface of the dielectric layer and the recessed top surface of the second metal layer. The patterned metal pad is spaced a distance from the recessed top surface of the second metal layer and the top surface of the dielectric layer, thereby forming a gap. The gap is substantially equal to the length of the exposed side of the second metal layer. The length of the gap is about to about The patterned third metal layer is on the patterned metal pad. The patterned third metal layer has an opening exposing a top surface of the dielectric layer and a top surface of the recess of the second metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to understand in detail the manner in which the above-mentioned features of the present disclosure may be understood, a more specific description of the present disclosure briefly summarized above may be obtained by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that only typical embodiments of the present disclosure are shown in the accompanying drawings, and therefore should not be considered as limiting the scope thereof, as the present disclosure may allow other equivalent embodiments. The embodiments described herein are shown by way of example and are not limited to the figures of the accompanying drawings, in which like reference numerals indicate like elements.

[0010] Figure 1 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0011] Figure 2 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0012] Figure 3 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0013] Figure 4 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0014] Figure 5 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0015] Figure 6 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0016] Figure 7 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0017] Figure 8 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0018] Fig. 9 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0019] Fig.10 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0020] Fig.11 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0021] Fig.12shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0022] Fig.13 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0023] Fig.14 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0024] Fig.15 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0025] Fig.16 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0026] Fig.17 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0027] Fig.18 shows an isometric view of an electronic device according to one or more embodiments of the present disclosure;

[0028] Fig.19 An isometric view showing an electronic device according to one or more embodiments of the present disclosure; and

[0029] Fig. 20 An isometric view of an electronic device according to one or more embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0030] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configuration or processing steps set forth in the following description. The present disclosure is capable of other embodiments and can be implemented or carried out in various ways.

[0031] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactant gas," and the like are used interchangeably to refer to any gaseous species that can react with a substrate surface.

[0032] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during the manufacturing process. For example, depending on the application, the substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys and other conductive materials. Substrates include (but are not limited to) semiconductor wafers. The substrate can be exposed to pre-treatment (pretreament) treatment to polish, etch, reduce, oxidize, hydroxylate, anneal and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any film processing step disclosed can also be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such an underlayer as indicated by the context. Thus, for example, in the case where a film / layer or a portion of a film / layer has been deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0033] One or more embodiments of the present disclosure advantageously provide a method that enables full alignment of vias (with respect to bottom and top wires) based on an elimination scheme. Embodiments of a fully aligned elimination scheme allow for the formation of electronic devices with or without metal barriers / pads. Some embodiments advantageously provide full alignment of vias in two orthogonal wire directions.

[0034] The present method provides a self-aligned interconnect structure for use in conjunction with a semiconductor device without the use of vias filled with contact material. Instead, all contact material is deposited in a conformal layer, so that no microconduits need to be filled with conductive material. Subsequently, a pattern is dry-etched through the stack of layers including the contact material layer so that pillars of contact material extend upward to provide interconnects extending from an underlying substrate layer, which contains contacts that mate with a surface on the semiconductor device. The pillars of contact material are typically metal, but may be doped ceramic compositions or conductive polymer materials capable of passing electrical current. It should also be understood that the resulting interconnect structure need not be in the form of vertical pillars, but may be in other shapes that can be processed from the stack of conformal layers using subtractive techniques.

[0035] The following description is about the generation of metal pillars, as this is likely to be a frequently used form of self-aligned interconnect structure; however, it is not intended to limit the embodiments to a form of conductive path, which includes metal, doped ceramic composition, or conductive polymer material that may be doped or undoped to provide the interconnect path. It is intended that when "metal" is mentioned in the description of the following structure, it should be understood that other conductive materials that can be applied in the form of a conformal layer are also intended to be included.

[0036] In recent years, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or electroplated copper have been used as the interconnect material of choice. However, when the feature size is at the 10nm node (16nm HPCD), the effective resistivity is in the range of about 6 μΩ-cm due to the eMFP (electron mean free path) of copper, which is about 39nm. When the feature size is at the 7nm node (11nm HPCD), the effective resistivity is in the range of about 6.5 μΩ-cm due to the eMFP of copper; and when the feature size is at the 5nm node (7nm HPCD), the effective resistivity of copper is in the range of about 11.5 μΩ-cm. At the 7nm node, and especially at the 5nm node, metals such as cobalt (eMFP is about 9.5nm, while copper has an eMFP of 39) or tungsten (eMFP is about 19nm)) and silicides (by way of example and not by way of limitation) become competitive with copper in terms of effective resistivity. For example, copper and cobalt both have an effective resistivity of about 12 μΩ-cm at the 5nm node, and tungsten has an effective resistivity of about 13.5 μΩ-cm. Effective resistivity is the resistivity of a metal at nanometer size. Due to the increased electron scattering at nanometer size, the effective resistance of a metal is higher than the intrinsic resistance ("bulk resistivity" or "large-scale resistivity").

[0037] Embodiments of the present disclosure produce an interconnect structure that includes depositing multiple layers of material followed by the use of a subtractive technique such as dry etching or atomic layer etching (ALE). If necessary, the resulting conductive interconnect is surrounded by a dielectric material.

[0038] By using a stack of different layers including line metals; etching a termination material layer (in the form of a metal or doped ceramic or polymer material) with a relatively high conductivity component; and patterning a transfer layer (usually including a hard mask material) that makes up the lithographic stack; and by applying subtractive techniques to form the desired structures within the stack, for example, interconnect conduits in the form of pillars may be formed without the need to fill tiny capillaries with a fluid conductive material. The method of forming the interconnect structure described above makes it possible to proceed to devices at the 16nm node and below.

[0039] Figure 1 A three-dimensional view of an exemplary starting "stack" of layers is shown that will be used to form the kind of interconnect structure useful for next generation semiconductor devices. Those skilled in the art will recognize that the exemplary stack 100 is only one possible configuration and should not be considered to limit the scope of the present disclosure. In the illustrated embodiment, a substrate 101 has an oxide layer 102 formed thereon. The substrate can be any suitable material described herein. For descriptive purposes only, the substrate 101 will be discussed as a silicon substrate. The oxide layer 102 can be grown from a substrate surface or can be deposited on a substrate surface. For example, a silicon substrate can be oxidized to form the oxide layer 102, or a silicon oxide film can be deposited (e.g., by a vapor deposition process) on the substrate 101.

[0040] The illustrated embodiment includes an optional metal liner 103. This liner may also be omitted from the stack 100. For example, if the first metal layer 104 has good adhesion to the oxide layer 102, the optional metal liner 103 may be redundant and omitted. The optional metal liner 103 may be any suitable material capable of increasing the adhesion of the first metal layer 104 to the oxide layer 102. The optional metal liner 103 may be deposited by any suitable technique known to those skilled in the art, including, but not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), evaporation, or electroplating.

[0041] The first metal layer 104 (also referred to as the first conductive layer) is on the optional metal liner 103; or if the optional metal liner 103 is omitted, on the oxide layer 102. The first metal layer 104 can be any suitable layer deposited by any suitable technique known to those skilled in the art. In some embodiments, the first metal layer 104 is a conformal layer. Suitable materials for the first metal layer 104 include (but are not limited to) tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), silicide, graphene, or a combination thereof. In some embodiments, the first metal layer 104 includes one or more of tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), silicide, or graphene. In some embodiments, the first metal layer 104 is substantially composed of one or more of tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), silicide, or graphene. As used in this specification and the appended claims, the term "consisting essentially of" means that the subject film, species, etc. is greater than or equal to about 95%, 98%, 99%, or 99.5% of the claimed material. If more than one component is claimed for a material (e.g., a film consisting essentially of tungsten and cobalt), the sum of the claimed components is greater than or equal to about 95%, 98%, 99%, or 99.5%. In some embodiments, the first metal layer 104 includes a pure metal doped with a small amount of other metals. For example, copper, tungsten, ruthenium, or molybdenum is doped with up to 5% of a dopant (e.g., aluminum, manganese, etc.). A first metal layer 104 consisting essentially of a doped metal means that the first metal layer 104 includes up to 5 atomic % of a dopant. In some embodiments, the dopant includes one or more of aluminum, manganese, phosphorus, astatine, or boron.

[0042] A first etch stop layer 106 having a low resistivity overlies the first metal layer 104. The first etch stop layer 106 may be a conformal layer of any suitable material, including but not limited to tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), W, Co, Ru, niobium (Nb), niobium nitride (NbN), and combinations thereof, deposited using a technique selected from CVD, PVD, ALD, deposited from an evaporated metal source, metal plating, or may be an oxide of Ti doped with a dopant such as silicide. In some embodiments, the first etch stop layer 106 includes or consists essentially of one or more of titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or tungsten silicon nitride (WSiN).

[0043] A second metal layer 108 is formed on the first etch stop layer 106. The second metal layer 108 may (but need not be) the same as the first metal layer 104 described above. In some embodiments, the second metal layer 108 includes the same composition as the first metal layer 104. In some embodiments, the second metal layer 108 includes a different composition than the first metal layer 104. As used herein, different compositions include (but are not limited to) compositions of the same material with different physical properties, or compositions of the same material formed by different techniques. In some embodiments, the first metal layer 104 and the second metal layer 108 include one or more of ruthenium, molybdenum, or tungsten. In some embodiments, the first metal layer 104 includes one or more of ruthenium, molybdenum, or tungsten or consists essentially of one or more of the above materials. In some embodiments, the second metal layer 108 includes one or more of ruthenium, molybdenum, or tungsten or consists essentially of one or more of the above materials. In some embodiments, the first metal layer 104 and the second metal layer 108 include the same metal or consist essentially of the same metal.

[0044] A second etch stop layer 110 overlies the second metal layer 108. The composition of the second etch stop layer 110 may (but need not be) the same as the first etch stop layer 106. Making the first etch stop layer 106 and the second etch stop layer 110 the same material can simplify processing. In some embodiments, the second etch stop layer 110 includes the same composition as the first etch stop layer 106. In some embodiments, the second etch stop layer 110 includes a different composition than the first etch stop layer 106. In some embodiments, the first etch stop layer 106 and the second etch stop layer 110 include the same material or consist essentially of the same material. In some embodiments, the first etch stop layer 106 and the second etch stop layer 110 include different materials. Suitable etch stop layer materials include (but are not limited to) titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). In some embodiments, the second etch stop layer 110 is omitted, and the subsequent hard mask layer 112 serves as both the etch stop layer 110 and the hard mask layer 112.

[0045] A hard mask layer 112 overlies the second etch stop layer 110. The hard mask layer is used in conjunction with the above "lithography stack" to transfer the device pattern through the lower layers 110, 108, 106, and 104 described above. The hard mask layer 112 can be a single layer or a combination of multiple layers. The hard mask layer 112 is not described herein, but can be manufactured using materials and patterning techniques known in the art that are capable of providing patterns at the 10nm node (16nm HPCD) or lower. In some embodiments, the hard mask layer 112 includes a metal or dielectric mask material. Suitable dielectric materials include (but are not limited to) silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx ), aluminum nitride (AlN), and combinations thereof. Those skilled in the art will recognize that the use of a chemical formula like SiO to represent silicon oxide does not imply any particular stoichiometric relationship between the elements. The chemical formula only identifies the major elements of the film.

[0046] Figure 2 Shows something like Figure 1 2 , wherein a bottom anti-reflective coating (BARC) 214 and a photoresist 216 are formed thereon. The photoresist 216 is shown patterned with trenches 218; however, one skilled in the art will recognize that the pattern may be any suitable shape or combination of shapes.

[0047] Figure 3 Shows something like Figure 2 Electronic device 300 after an M1 line etch process. The M1 line etch process creates openings corresponding to trenches 218 in photoresist 216. In the illustrated embodiment, trenches 315 are formed through BARC 214, hard mask layer 112, second etch stop layer 110, and second metal layer 108 to form patterned BARC 314, patterned hard mask layer 312, patterned second etch stop layer 310, and patterned second metal layer 308, respectively. The illustrated M1 line etch process terminates at first etch stop layer 106. In some embodiments, first etch stop layer 106 is also patterned. Forming the patterned layers may be performed in a single process or in multiple processes.

[0048] Figure 4 Shows something like Figure 3 The electronic device 400 after removing the photoresist 216 and the patterned BARC 314, leaving the patterned hard mask layer 312. The removal of the photoresist 216 and the patterned BARC 314 may be accomplished by any suitable technique known to those skilled in the art, including but not limited to anisotropic etching and chemical-mechanical planarization (CMP).

[0049] Figure 5 Shows something like Figure 4The electronic device 500 after forming a second bottom anti-reflective coating (BARC) 520 and a second patterned photoresist 522. The second patterned photoresist 522 is shown aligned at an angle relative to the trench 315. The illustrated embodiment shows the second patterned photoresist 522 having an opening 523 aligned at about 90° relative to the trench 315; however, one skilled in the art will recognize that the angle between the second patterned photoresist 522 and the trench 315 can be in the range of about 10° to about 90°. The deposition of the second BARC 520 and the second patterned photoresist 522 can be accomplished by any suitable technique known to one skilled in the art.

[0050] Figure 6 Shows something like Figure 5 The electronic device 600 after anisotropic etching through the openings 523 in the patterned second photoresist 522. The etching process is shown to have removed the second BARC 520 and the portions of the patterned hard mask layer 312 that were not covered by the photoresist material, leaving the patterned second BARC 620 and the patterned hard mask layer 612, respectively. The etching process is shown to terminate at the patterned second etch stop layer 310 and the first etch stop layer 106. Portions of the device are left below the second patterned BARC 522 and the patterned second etch stop layer 310 (relative to the etching direction).

[0051] Figure 7 Shows something like Figure 6 The electronic device 700 after removing the patterned second photoresist 522 and the patterned second BARC 620. The patterned second photoresist 522 and the patterned second BARC 620 may be removed separately or in the same process.

[0052] Figure 8 Shows something like Figure 7 Electronic device 800 after an etching process to remove portions of second etch stop layer 310 not covered by patterned hard mask layer 612. This process exposes top portion 309 of patterned second metal layer 308 in space 811 between patterned hard mask layer 612 and patterned second etch stop layer 810.

[0053] Fig. 9 Shows something like Figure 8 Electronic device 900 after etching to remove portions of second metal layer 308 and first etch stop layer 106 to form pillars of second metal (vias 908) on pads of first etch stop layer 906. Etching also transfers the pattern to first metal layer 104 via trenches 315 to form patterned first metal layer 904.

[0054] Fig.10 Shows something like Fig. 9 Electronic device 1000 after etching exposed portions of optional metal liner 103 to leave patterned optional metal liner 1003. In embodiments without optional metal liner 103, this etching process may be skipped.

[0055] Fig.11 Shows something like Fig.10 Electronic device 1100 after deposition of dielectric layer 1124. Dielectric layer 1124 can be deposited by any suitable technique known to those skilled in the art. In some embodiments, dielectric layer 1124 includes a low-k dielectric. In some embodiments, the low-k dielectric is deposited by a flowable CVD process.

[0056] Fig.12 Shows something like Fig.11 Electronic device 1200 after chemical mechanical planarization (CMP) of dielectric layer 1124. The CMP process removes material from dielectric layer 1124 to lower dielectric layer 1124, patterned hard mask layer 612, and top portion 1125 of patterned second etch stop layer 810 to expose patterned second metal layer (via 908). Patterned second metal layer (via 908) is also referred to as first via (V1 or Vx). First metal layer is also referred to as M1 or Mx. First via connects patterned first metal layer 904 to a layer above the first via that has not yet been formed by a combination also referred to as M1-V1 or Mx-Vx.

[0057] Fig.13 Shows something like Fig.12 The electronic device 1300 after forming a layer stack thereon. The layer stack is similar to a Figure 1 The layer stack includes an optional second metal liner 1330, which may be omitted as described above. A third metal layer 1332, a third etch stop layer 1334, a fourth metal layer 1336, a fourth etch stop layer 1338, a second hard mask layer 1340, a second BARC 1342, and a third patterned photoresist 1344. For illustrative purposes, the pattern of the trench 1346 of the third patterned photoresist 1344 is different from the pattern of the first via. The patterns shown should not be considered to limit the scope of the present disclosure.

[0058] Fig.14 Shows something like Fig.13 After executing something like Figure 3The electronic device 1400 after processing is shown. In short, the second BARC 1342, the second hard mask layer 1340, and the fourth etch stop layer 1338 are etched through the trenches 1346 in the third patterned photoresist 1344 to transfer the pattern to the fourth etch stop layer 1338 to form a patterned second BARC 1442, a patterned second hard mask layer 1440, and a patterned fourth etch stop layer 1438, respectively.

[0059] Fig.15 Shows something like Fig.14 After executing something like Figure 4 Electronic device 1500 after processing is shown. In short, third patterned photoresist 1344 and patterned second BARC 1442 have been etched, and patterns 1346 , 1446 are etched into fourth metal layer 1336 to produce patterned fourth metal layer 1536 having pattern 1546 .

[0060] Fig.16 Shows something like Fig.15 Before depositing the fourth BARC 1646 and the fourth patterned photoresist 1648 (similar to Figure 5 ) after the electronic device 1600. The fourth BARC 1646 can be the same as or different from the dielectric layer 1124. A fourth patterned photoresist 1648 is deposited and formed into a pattern 1650 by any suitable technique known to those skilled in the art (eg, photolithography).

[0061] Fig.17 Shows something like Fig.16 Electronic component 1700 after transferring pattern 1650 into patterned second hard mask layer 1440 to form patterned hard mask layer 1740 having pattern 1750 similar to pattern 1650. Fourth photoresist 1648 and fourth BARC 1646 are also removed.

[0062] Fig.18 Shows something like Fig.17 Electronic device 1800 after pattern 1750 is transferred into third metal layer 1332 to form patterned third metal layer 1332. Patterned fourth metal layer 1436 and patterned fourth etch stop layer 1438 are modified to become patterned fourth metal layer 1836 and patterned fourth etch stop layer 1838, respectively. Third metal layer 1332 serves as a second metal line (M2 or Mx+1) that is electrically in contact with the first metal line (M1 or Mx) via via 908. In some embodiments, dielectric layer 1124 and second dielectric 2024 prevent electrical leakage / short circuits at wire locations designed to be insulated.

[0063] The illustrated embodiment shows a misalignment 1855 of the patterned third metal layer 1832 relative to the vias 908. Misalignment 1855 of these features may result in electrical shorts between adjacent vias. Fig.19 Shows something like Fig.18 The electronic device 1900 after recessing the top 1125 of the dielectric layer 1124 and the top 909 of the second metal layer (via 908). The recessed dielectric layer 1124 exposes a length Lv of the second metal layer (via 908). The length Lv of the exposed second metal layer (via 908) is proportional to the amount by which the dielectric layer 1124 is recessed and the amount by which the top 909 of the second metal layer 908 is recessed. In some embodiments, the length of the exposed second metal layer (via 908) is about To date within the range of, or about To date within the range of, or about To date within the range of, or about To date within the range of, or about To date In some embodiments, the length Lv of the exposed second metal layer is greater than or equal to about or The length Lv is the same as the distance between the top of the second metal layer to the bottom of the optional metal pad or third metal layer. The third etch stop layer 1334 is used as a mask for the recess process to maintain the alignment of the via 908.

[0064] Recessing the dielectric layer lowers the top 909 of the second metal layer (via 908) to expose the side 911 of the second metal layer (via 908). Because the third etch stop layer 1334 is used as a mask, the side 911 of the second metal layer is aligned with the side 1833 of the patterned third metal layer 1832. The recessing process lowers the top 909 of the second metal layer (via 908) and creates or increases the distance from the bottom 1831 of the third metal layer 1830 to the top 909.

[0065] In the embodiment shown, there is an optional second metal liner 1330 that separates the bottom 1831 of the third metal layer 1830 from the top 909 of the second metal layer (via 908). In this case, recessing the top 909 increases the distance between the top 909 and the bottom 1831 of the third metal line and creates a distance between the top 909 and the bottom 1331 of the optional second metal liner 1330.

[0066] Fig. 20 Shows something like Fig.19Electronic device 2000 after depositing second dielectric 2024 and planarizing top 2025 to expose fourth metal layer 1836 as a second via. In some embodiments, second via (V2) can connect second metal line (third metal layer 1832) to subsequent metal line deposited by similar or different methods.

[0067] The use of the terms "a" and "an" and "the" and similar references in the context of describing the materials and methods discussed herein (particularly in the context of the following claims) should be interpreted as covering both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, the enumeration of ranges of values ​​herein is intended only to be used as a shorthand method of referring to each individual value falling within the range, respectively, and each individual value is incorporated into the specification as if it were individually listed herein. Unless otherwise indicated herein or clearly contradicted by the context, all methods described herein can be performed in any suitable order. Unless otherwise claimed, the use of any and all examples or exemplary language (such as "such as") provided herein is intended only to better illustrate the materials and methods and does not limit the scope. No language in the specification should be interpreted as indicating that any unclaimed element is necessary for implementing the disclosed materials and methods.

[0068] Throughout the specification, references to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that the specific features, structures, materials, or characteristics described in conjunction with that embodiment are included in at least one embodiment of the present disclosure. Thus, phrases such as "in one or more embodiments," "certain embodiments," "in an embodiment," or "in an embodiment" that appear in various places throughout the specification do not necessarily refer to the same embodiment of the present disclosure. In one or more embodiments, the specific features, structures, materials, or characteristics are combined in any suitable manner.

[0069] Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a plurality of fully aligned vias, the method comprising the following steps: a third metal layer patterned on top of the second metal layer, the second metal layer being in electrical contact with the first metal layer, the patterned third metal layer being misaligned with the second metal layer such that a portion of the top of the second metal layer is exposed, a patterned fourth metal layer and a patterned fourth etch stop layer being used as a mask for patterning the third metal layer, wherein forming the patterned fourth metal layer and the patterned fourth etch stop layer comprises depositing the fourth metal layer and the fourth etch stop layer on the third metal layer, patterning the fourth metal layer and the fourth etch stop layer using a hard mask layer and a patterned photoresist; and The top of the second metal layer is recessed to expose sides of the second metal layer aligned with the patterned third metal layer and to recess the top of the second metal layer a distance from a bottom of the third metal layer.

2. The method of claim 1 , wherein an optional metal pad is located between the top of the second metal layer and the bottom of the third metal layer, and recessing the top of the second metal layer creates a distance between the top of the second metal layer and the bottom of the optional metal pad.

3. The method of claim 1, further comprising the steps of: A dielectric layer is deposited on top of the recess of the second metal layer and on the third metal layer. The method of claim 3 , wherein the dielectric layer comprises a low-k dielectric material.

5. The method of claim 4, wherein the low-k dielectric material is deposited by a flowable chemical vapor deposition process. The method of claim 3 , wherein the dielectric layer covers a top portion of the fourth metal layer on the third metal layer.

7. The method of claim 6, further comprising the steps of: The dielectric layer is planarized to expose the top of the fourth metal layer.

8. The method of claim 1, wherein a contact between the second metal layer and the third metal layer has an effective resistivity less than or equal to 20 μΩ-cm.

9. The method of claim 1, wherein the contact between the second metal layer and the third metal layer has an electron mean free path less than or equal to 20 nm.

10. A method for forming a plurality of fully aligned vias, the method comprising the steps of: forming a patterned fourth metal layer and a patterned fourth etch stop layer on the third metal layer using a hard mask layer and a patterned photoresist; forming a patterned third metal layer on top of a patterned metal pad on a second metal layer using the patterned fourth metal layer and the patterned fourth etch stop layer as a mask, the second metal layer being in electrical contact with the first metal layer, the patterned third metal layer and the patterned metal pad being misaligned with the second metal layer such that a portion of a top of the second metal layer is exposed through openings in the patterned third metal layer and the patterned metal pad; and The second metal layer is recessed through the openings in the patterned third metal layer and the patterned metal pad to lower the top of the second metal layer and expose multiple sides of the second metal layer aligned with multiple sides of the patterned third metal layer and a top surface of the second metal layer spaced a distance from a bottom surface of the metal pad, the top surface of the second metal layer being spaced a distance from the bottom surface of the metal pad. to distance within the range.

11. The method of claim 10, further comprising the steps of: A dielectric layer is deposited on top of the recess of the second metal layer, the patterned metal liner, and the patterned third metal layer.

12. The method of claim 11, wherein the dielectric layer comprises a low-k dielectric material.

13. The method of claim 12, wherein the low-k dielectric material is deposited by a flowable chemical vapor deposition process.

14. The method of claim 10, wherein a contact between the second metal layer and the third metal layer has an effective resistivity less than or equal to 20 μΩ-cm.

15. The method of claim 10, wherein the contact between the second metal layer and the third metal layer has an electron mean free path less than or equal to 20 nm.

16. An electronic device comprising: a second metal layer, the second metal layer contacting the first metal layer via the first etch stop layer, the second metal layer having a top portion, the top portion having a plurality of exposed side surfaces and a recessed top surface, the exposed side surfaces having a length; a dielectric layer having a top surface that is substantially flush with a top surface of the recess of the second metal layer; a patterned metal liner, the patterned metal liner being located on the second metal layer and the dielectric layer, the patterned metal liner having a plurality of openings exposing a top surface of the dielectric layer and a top surface of the recess of the second metal layer, the patterned metal liner being spaced a certain distance from the top surface of the recess of the second metal layer and the top surface of the dielectric layer, thereby forming a gap, the gap being substantially equal to the length of the exposed side surface of the second metal layer, the length of the gap being between to within the scope of a patterned third metal layer on the patterned metal pad, the patterned third metal layer having a plurality of openings exposing the top surface of the dielectric layer and the recessed top surface of the second metal layer; and A patterned fourth metal layer and a patterned fourth etch stop layer.

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