Circuits and methods for transmitting signals in integrated circuit devices

Abstract

A circuit for transmitting signals in an integrated circuit device is described. The circuit comprises a first die (501), a second die (502) stacked on the first die (501), and a buffer (513) for transmitting data between the first die (501) and the second die (502), wherein a first inverter (512) of the buffer (513) is on the first die (501) and a second inverter (514) of the buffer (513) is on the second die (513). A method for transmitting signals in an integrated circuit device is also described.

Description

Technical Field

[0001] This invention relates generally to integrated circuit devices, and more specifically, to circuits and methods for transmitting signals in integrated circuit devices. Background Technology

[0002] The implementation of integrated circuit devices is constantly evolving, with efforts to reduce device size, lower power consumption, and improve performance. For any product, there is always a pursuit of increasing the yield of integrated circuit devices during manufacturing. Recently, integrated circuit devices with multiple dies have been developed, where these dies can be placed on internal modules enabling signal communication between them. Other implementations of integrated circuit devices include multiple dies stacked on top of each other, where circuitry on the stacked dies can transmit signals through interconnect units between the dies, such as through-silicon vias (TSVs).

[0003] However, defects may exist at the die or the connection between dies during the manufacturing process of stacked integrated circuit devices, which may reduce yield and affect performance.

[0004] Therefore, there is a need for a circuit and method for transmitting signals in an integrated circuit device with multiple dies, in order to reduce the problems associated with conventional devices. Summary of the Invention

[0005] A circuit for transmitting signals in an integrated circuit device is described. The circuit may include a first die, a second die stacked on the first die, and a buffer for transmitting data between the first die and the second die, wherein a first inverter of the buffer is on the first die and a second inverter of the buffer is on the second die.

[0006] In some implementations, the first inverter can be configured to receive a reference voltage, and the second inverter can be configured to receive a gated reference voltage based on the reference voltage.

[0007] In some embodiments, the circuit may further include a third inverter on the second die, wherein the third inverter is configured to receive the output of the first inverter and a reference voltage.

[0008] In some embodiments, the circuit may further include a third die stacked on the second die, wherein a third inverter is configured to transfer data from the first die to the third die.

[0009] In some implementations, the second die may include interconnect units configured to receive a second gated reference voltage.

[0010] In some implementations, the interconnect unit may include a selection circuit having a selection input configured to receive a control signal from a memory unit configured to receive a second gating reference voltage.

[0011] In some implementations, the first inverter may include a tri-state inverter and may be configured to receive a tri-state signal, and the second inverter may be configured to receive a gated reference voltage.

[0012] In some implementations, the first inverter and the second inverter may be coupled to a pillar connection extending between the first die and the second die.

[0013] In some implementations, the circuit may further include a power gating circuit coupled to a second inverter of the buffer, wherein the power gating circuit is configured to apply a gating reference voltage to the second inverter.

[0014] In some implementations, the first inverter may be associated with the input / output block of the first die, and the second inverter may be associated with the input / output block of the second die.

[0015] A method for transmitting signals in an integrated circuit device is also described. The method may include providing a first die, stacking a second die onto the first die, and transmitting data between the first and second dies via a buffer, wherein a first inverter of the buffer is on the first die, and a second inverter of the buffer is on the second die.

[0016] In some embodiments, the method may further include configuring a first inverter to receive a reference voltage and configuring a second inverter to receive a gated reference voltage based on the reference voltage.

[0017] In some embodiments, the method may further include implementing a third inverter on a second die, wherein the third inverter is configured to receive a reference voltage.

[0018] In some embodiments, the method may further include stacking a third die on the second die, wherein a third inverter is configured to transfer data from the first die to the third die.

[0019] In some embodiments, the method may further include configuring interconnect units of the second die to receive a second gated reference voltage.

[0020] In some implementations, configuring the interconnect unit may include configuring a selection circuit with a selection input, wherein the selection input is coupled to receive a control signal from a memory unit configured to receive a second gated reference voltage.

[0021] In some implementations, the first inverter may include a tri-state inverter and may be configured to receive a tri-state signal.

[0022] In some embodiments, the method may further include coupling the first inverter and the second inverter to a post connection extending between the first die and the second die.

[0023] In some embodiments, the method may further include coupling a power gating circuit to a second inverter of a buffer, wherein the power gating circuit is configured to apply a gating reference signal to the second inverter.

[0024] In some implementations, the first inverter may be associated with the input / output block of the first die, and the second inverter may be associated with the input / output block of the second die. Brief description of the attached diagram

[0026] Figure 1 This is a block diagram of an exemplary stacked integrated circuit device;

[0027] Figure 2 It is an exemplary stacked integrated circuit device (e.g.) Figure 1 A cross-sectional view of a portion of an integrated circuit device;

[0028] Figure 3 It is a block diagram of a portion of an integrated circuit, wherein the integrated circuit has a region that receives a power-gated reference voltage;

[0029] Figure 4 It is a block diagram of a portion of an integrated circuit, wherein the integrated circuit has a circuit block that receives a power-gated reference voltage;

[0030] Figure 5 It is a block diagram of a portion of a circuit used to transmit signals between dies of an integrated circuit device;

[0031] Figure 6 It is another block diagram of a part of a circuit used to transmit signals between dies of an integrated circuit device;

[0032] Figure 7 It is possible Figure 5 and 6 A block diagram of an exemplary gated circuit implemented in the circuit;

[0033] Figure 8 It is a display Figure 7 Timing diagram of the gated circuit operation;

[0034] Figure 9 It is a flowchart showing the method of transmitting signals in an integrated circuit device.

[0035] Figure 10This is a block diagram of a programmable logic device, which implements circuits and methods for transmitting signals in integrated circuit devices; and

[0036] Figure 11 yes Figure 10 A block diagram of the configurable logic units of a programmable logic device. Detailed Implementation

[0037] Implementing multiple integrated circuit dies in an integrated circuit package can increase density and improve performance. However, some dies in a packaged integrated circuit device may be defective or unused. For example, in active-on-active (AOA) devices, stacking dies can bring the circuitry within the integrated circuit (IC) package closer together, thereby improving performance. Stacked dies used in integrated circuit packaging can be formed by stacking wafers (a process known as wafer-to-wafer bonding) and then dicing the stacked wafers to form individual stacked dies implemented in the integrated circuit package. However, during manufacturing, because wafer-to-wafer stacking is performed before dicing the stacked wafers, it is impossible to stack “known good dies” in a stacked die architecture. That is, defects may exist between dies in the die stack or within the dies themselves, and these defects may not be identified until after the stacked wafers have been diced. Therefore, defect tolerance and redundancy are beneficial. The circuitry and methods described below for transmitting data in integrated circuit devices are advantageous for redundancy schemes implemented in a stacked die architecture.

[0038] The circuits and methods described below enable power gating to shut off current on defective or partially defective dies in multi-die integrated circuit devices (e.g., stacked field-programmable gate array (FPGA) subsystems formed using wafer-to-wafer bonding). According to some embodiments, the circuits and methods provide 3D stacked dies with dual power-gated power supplies (e.g., a higher voltage (e.g., VGG) for memory devices and a lower voltage (e.g., VCCINT) for circuits such as logic circuits that do not require the higher voltage). Power supply gating reduces static leakage of unused chips. However, because in some embodiments, power-gated and non-power-gated regions can coexist on the same die, parasitic current paths may exist between the non-gated and gated regions. Using isolation cells between the non-gated and gated regions can block these parasitic current paths. Circuits and methods for separating the inverters of the buffer provide isolation, wherein a first inverter is on the non-gated power supply region of the circuit, and a second inverter is on the gated power supply that shares power with the gated region.

[0039] According to some implementations, the inverters of the driver can be separated across two dies, where one of the inverters (e.g., the second inverter of a buffer) can be provided with a gated reference voltage. Therefore, the power-gated inverter acts as an isolation unit between gated and ungated power supplies and isolates the driver in the valid die from the source / drain load in the defective die. The circuit arrangement has no impact on area but improves the die-to-die connection implementation. That is, because two inverters for the buffer are required on the same die in a conventional device, separating the inverters of the buffer between two dies means that the second inverter of the die in the conventional buffer arrangement would occupy the area of ​​the inverter that would be moved to the next die. Therefore, there is no area impact because the inverter used has actually been moved to another die.

[0040] While the specification includes claims that define one or more features of what are considered novel embodiments of the invention, it is believed that the circuits and methods will be better understood by considering the following description in conjunction with the accompanying drawings. Although various circuits and methods are disclosed, it should be understood that these are merely examples of arrangements of the invention, which may be embodied in various forms. Therefore, the specific structural and functional details disclosed in this specification should not be construed as limiting, but only as the basis for the claims and as a representative basis for teaching those skilled in the art to use the arrangements of the invention differently in virtually any appropriately detailed manner. Furthermore, the terminology and phrases used herein are not intended to be limiting, but rather to provide an understandable description of the circuits and methods.

[0041] First turn Figure 1 A block diagram of an exemplary stacked integrated circuit device 100 is shown. More specifically, a substrate 102 (shown here as a package substrate for example) is configured to receive a plurality of bare dies electrically connected via interconnect units, as will be shown below. Figure 2 As described in more detail below. Alternatively, the substrate may include an interposer layer located on a package substrate, or any other unit for receiving a bare die of an integrated circuit device. Figure 1 As shown, the first die stack includes a first substrate 106 having a corresponding interconnect layer 108, wherein the interconnect layer 108 includes interconnect cells capable of routing signals to the package substrate. The interconnect cells may include pads, hybrid interconnect technologies, or any other conductive cells for routing signals to and from the die. A second substrate 110 has a corresponding interconnect layer 112, which includes interconnect cells capable of routing signals. A third substrate 114 has a corresponding interconnect layer 116, which also includes interconnect cells capable of routing signals. A package cover 118 may be included to cover the substrate 114 or package multiple dies. The substrate and interconnect layer pairs (106 and 108, 110 and 112, and 114 and 116) shown form three dies and are configured to route signals between the dies, as will be referenced below. Figure 2 A more detailed description. It should be understood that... Figure 1 The arrangement is intended to illustrate, by way of example, a general arrangement of stacked dies, where specific die arrangements can have different configurations such as face-to-face dies (also known as work-to-work-face dies) and back-to-back dies (where the face represents the metal layer side of the back-to-work order (BEOL) process, and the back represents the substrate). Depending on the die configuration, interconnect units may include TSVs or BEOL metal layers of the die. For face-to-back bonding, the interconnects between dies are implemented in the substrate (i.e., where the TSV is located). According to one example, interconnect layer 112 may include a metal layer of substrate 110 (i.e., the back side) (i.e., on one face), where interconnect layer 112 and die 110 together constitute a die layer. Interconnects from one die to another or between the substrate package and the die may include metal layers or TSVs, depending on the die orientation. It should be noted that stacked IC devices can include different types of vias (TSVs): for example, through-hole TSVs fabricated before devices (such as transistors, capacitors, or resistors) formed during the front-end process; intermediate via TSVs fabricated after the transistor, capacitor, or resistor devices are patterned but before the metal layers formed in the back-end process; and final via TSVs fabricated during or after the back-end process. Intermediate via TSVs are currently a common option for advanced 3D integrated circuits and interposer stacking.

[0042] The integrated circuit device may include additional die groups, including a second set of dies 120, which may be implemented in a manner similar to die group 104, wherein substrate 102 enables signal communication between the first and second sets of dies. While the exemplary stacked integrated circuit device 100 is shown by way of example, it should be understood that other arrangements of dies may also be incorporated, including dies placed adjacent to each other on the horizontal plane of the package substrate. Furthermore, while examples of circuits and methods have been described with reference to stacked dies of an integrated circuit device, it should be understood that circuits and methods may be implemented in dies adjacent to each other on the horizontal plane of the package substrate, wherein the dies of the first set of dies 104 may communicate with the dies of the second set of dies 120. According to one embodiment, the inverters of a buffer capable of transmitting signals between dies are separated between the dies, wherein a first inverter of the buffer is located on a first side of the boundary between the first and second dies, and a second inverter of the buffer is located on a second side of the boundary between the first and second dies. The boundary may be, for example, the top and bottom surfaces of the two stacked dies. Alternatively, for non-stacked die arrangements (e.g., dies on a horizontal plane of a substrate or interposer, or dies stacked in different groups on a horizontal plane), the boundary may include, for example, the top or bottom of one of the dies. For instance, circuitry and methods for separating a buffer inverter between two dies may include an inverter for a buffer in one die stack and another inverter for a buffer in another die stack, wherein the boundary includes the top or bottom of at least one of the dies.

[0043] Turn now Figure 2 A cross-sectional view of a portion of an exemplary stacked integrated circuit device 200 is shown, which may be Figure 1 The cross-section of the integrated circuit device is shown, but it has five dies. The stacked integrated circuit device 200 includes multiple dies, with dies 1 to 5 as examples here. Each die typically includes the same type of cells, such as active elements, metal traces, and vias formed in silicon, indicated by the same reference numerals in each die. For example, each die may include a substrate 202 with active cells 204, shown here as a transistor, including a source 206 and a drain 208 in a well region 209, and a gate region 210.

[0044] Active cells of the substrate of a die are interconnected or connected to cells of other dies via interconnect cells, wherein the active cells may include metal traces and vias in a metal layer separated by a non-conductive layer, wherein the vias connect portions of the metal layer through the non-conductive layer. More specifically, as shown, interconnect cells 212 are coupled together via vias 214. A via 216, commonly referred to as a through-silicon via (TSV), extending through the substrate, extends from a contact cell 218 on the back side of the substrate. This contact cell 218 may be coupled to a contact cell 220, which can be connected to a contact pad 222 extending through an insulating layer 224 to provide external connectivity. Other contact cells may also be implemented to provide electrical connections between dies. For example, a first contact cell 226 of a first die may be electrically coupled to a second contact cell 228 of a second die, wherein contact cells 226 and 228 may be part of a hybrid contact cell 230. Figure 2 Examples are provided to illustrate where this can be achieved, as described in more detail below. Figure 3 and 4 Examples of circuit components.

[0045] Figure 2 The circuit is shown by way of example and can include any number of dies, which can be implemented in any orientation. Although a face-to-face arrangement of dies is shown between die 1 and die 2 and a face-to-back arrangement is shown in the connection of another die, it should be understood that other orientations of the dies can be implemented. Some or all of the dies can be the same type of device, such as a programmable logic device (PLD), or they can have specific functions, such as memory or logic, in different dies.

[0046] Turn now Figure 3 A block diagram of a portion 300 of an integrated circuit is shown, including a region that receives a power-gated reference voltage. The circuitry and methods for transmitting signals can be implemented in any type of integrated circuit device. However, this circuitry and methods are advantageous in integrated circuit devices with repetitive circuit cells dedicated to certain functions, such as those in the following... Figure 10 and 11 The examples and descriptions of PLDs are helpful.

[0047] according to Figure 3For example, the circuit can be divided into four regions, including a first circuit region 302 with a corresponding power gate circuit 303, a second circuit region 304 with a corresponding power gate circuit 305, a third circuit region 306 with a corresponding power gate circuit 307, and a second circuit region 308 with a corresponding power gate circuit 309. For each circuit region, a first reference voltage (first Vref) is coupled to the first input 310 and input 312 of the corresponding power gate circuit, and its gated output is coupled to the second input 314 of the circuit region. As will be described in more detail below, the gated reference voltage corresponding to the first reference voltage responds to the corresponding control signal (in Figure 3 The control (1-4) is designated as the control area and coupled to the circuit region. The second reference voltage (second Vref) is coupled to input 316.

[0048] Although the second reference voltage is not coupled to a corresponding power gating circuit, the second power gating circuit can be implemented between the second reference voltage and input 316. According to one embodiment, the first reference voltage can be a lower voltage (e.g., VCCINT), and the second reference voltage can be a higher voltage (e.g., VGG). Although four regions are shown as an example, it should be understood that any number of regions can be implemented, and any number of gated and ungated reference voltages can be used. Furthermore, a single reference voltage or more than two reference voltages can be implemented.

[0049] Turn now Figure 4 The diagram shows a block diagram of a portion 400 of an integrated circuit arrangement, which includes a circuit block that receives a power-gated reference voltage. Figure 4 The circuit layout includes a configurable logic unit (CLE) 402 with a corresponding power gate circuit 403, an interconnect unit block 404 with a corresponding power gate circuit 405, and a configuration random access memory (CRAM) 406 with a corresponding power gate circuit 407. Details of the CLE, interconnect unit block, and CRAM will be provided in [reference]. Figure 10 and 11 To describe in more detail.

[0050] according to Figure 4In some implementations, some CLEs 402 are configured to receive a first reference voltage (e.g., VCCINT) at input 410, while other CLEs may be configured to receive a gated first reference voltage at input 410. More specifically, for the gated first reference voltage, the first reference voltage is coupled to input 412 of the power gate circuit 403, which is also coupled to receive CLE gate control signals (e.g., CC1...CCn) at control input 414. Although a CLE 402 receives only one gated or non-gated reference voltage, it should be understood that CLEs may be configured to each receive both gated and non-gated voltages, as well as more than one gated and non-gated voltage.

[0051] Figure 4 The circuit arrangement also includes multiple interconnect unit blocks 404, each shown by way of example to receive a first reference voltage and gate the first reference voltage. More specifically, the first reference voltage is provided to input 420 of interconnect unit block 404. Corresponding power gating circuitry is also configured for each of the interconnect unit blocks 404 to receive the reference voltage at input 422 and generate a gated reference voltage coupled to input 424 of interconnect unit block 404 in response to a corresponding control interconnect signal (CI1-CIn) coupled to control input 426.

[0052] Figure 4 The circuit arrangement also includes multiple CRAM blocks 406, shown as an example, each receiving a second reference voltage (VGG) and a gated second reference voltage (gated VGG). More specifically, a corresponding power gating circuit 407 is configured for each CRAM block 406 to receive the second reference voltage (e.g., VGG) at input 432 and generate a gated second reference voltage coupled to input 430 of the CRAM 406 in response to corresponding CRAM control signals (CC1-CCn) at control input 434. Although Figure 4 The circuit layout includes three types of circuit blocks with different power-gated layouts, but it should be understood that... Figure 4 The arrangement is provided as an example; different types of circuit blocks can be implemented with different power gating configurations.

[0053] In integrated circuit devices such as programmable logic devices with dual voltage supplies (e.g., a higher voltage supply (VGG) can be provided for the memory cell while a nominal voltage (VCCINT) can be provided for the core), power gating of VCCINT can be beneficial. Power gating of the higher voltage VGG can also be beneficial because some circuitry (e.g., configuration random access memory (CRAM) cells receiving higher voltages) may leak in 7nm technology, potentially accounting for up to 15% of the total power of the integrated circuit device. Therefore, as will be described in more detail below, gating both voltages on a bad die can be beneficial, not only in terms of saving static power but also in terms of increasing yield.

[0054] It should be noted that while gated power supplies are beneficial, some circuits require non-gated power supplies to power normally open modules. For example, in 3D integrated circuits, such as... Figure 1 and Figure 2 In integrated circuit devices, when the power supply of one of the defective chips is power-gated, an active signal still needs to propagate through the defective power-gated die. This may result in a power-gated load on the defective die (where the signal between dies is typically referred to as a z-signal (i.e., extending along the z-direction between stacked dies)). Transmitting the signal to the defective die can create parasitic leakage paths from the ungated power supply to the gated power supply, and also introduce indeterminate floating capacitances on the power-gated die due to parasitic leakage along the paths, which can significantly impact performance. Therefore, isolation circuitry is essential in conventional devices, but it is typically expensive and undesirable in area-constrained FPGA interconnect blocks. Figure 5 and 6 The isolation circuit arrangement overcomes the shortcomings of traditional isolation circuits by separating the inverter of the buffer between the two dies, thus eliminating the need for additional circuitry.

[0055] An active z-signal (i.e., a signal in the vertical direction between two stacked dies) can be coupled to different types of loads, including loads on adjacent dies and loads spanning multiple dies. Figure 5 and Figure 6 The circuitry and method described herein overcomes the problems of conventional devices by splitting the bi-inverter of the buffer (i.e., driver) of the die interconnect unit into two inverting stages. The first inverter is located on one die including the signal driver, and the second inverter is located on a second die serving as the load die. The first inverter can be implemented using a non-power-gated supply to enable signal transmission across multiple dies, while the second inverter can be on a power-gated supply. The second inverter receiving the power-gated supply serves as an isolation unit. Unlike conventional isolation units that require unnecessary circuitry, the circuitry and method of the decoupled driver provides limited load capacitance and improves the performance of shared connections between dies, such as z-connections shared between dies.

[0056] In other words, this circuit and method provide an inverter connected to a power-gated power supply. Due to the splitting technique, the circuit and method can be implemented without additional circuitry space and improves the performance of non-power-gated solutions. While also achieving full-power gating of VGG (which helps increase product yield and saves additional power), the circuit and method also allow for a strategy of splitting the inverter across the die regardless of power gating, thereby improving interconnect performance on 3D integrated circuits.

[0057] Turn now Figure 5 This shows a block diagram of a portion of a circuit 500 used to transmit signals between stacked dies of an integrated circuit device. Figure 5 The circuitry includes units that are part of two dies, and more specifically, units that include buffers associated with drivers on the first die 501 and the second die 502. Circuitry 500 may include a first selection circuitry 503, shown here as an example as a multiplexer adapted to receive input signals (input_1 and input_2) at a first input 504 and a second input 506, wherein a control signal provided at the inputs and generated in response to a memory cell 509 is capable of generating a selected value (of the input_1 and input_2 signals) at an output 510. It should be noted that memory cell 509 may be part of a CRAM and receives a reference voltage (e.g., VGG), as referenced above. Figure 4 As described. It should be noted that although selection circuit 503 is configured to receive a selection signal at input 508 for selecting the input of the selection circuit, and selection circuit 530 is configured to receive a selection signal at input 537 via a memory cell that receives a VGG reference voltage, it should be understood that the memory cell can receive different, non-gated reference voltages. That is, selection circuits 503 and 530 are controlled by a selection input signal that is always on to enable signal transmission between dies, such as between die 1 and die 3, even if, for example, die 2 or a portion of die 2 is defective. Although the control signal is provided to the selection circuit via the memory cell as a control input, it should be understood that the control signal can be provided by other circuit units that enable selection circuits 503 and 530 to be always on.

[0058] The output signal generated at output 510 is coupled to a first inverter 512 in buffer 513, and the output of the first inverter 512 is coupled to a second inverter 514 via interconnect unit 516. The first inverter 512 and the second inverter 514 are part of a buffer separated between a first die and a second die. Interconnect unit 516 can be any type of contact unit capable of transmitting signals between the first inverter on the first die and the second inverter on the second die. For example, interconnect unit 516 can include units of two dies, such as contact pads, TSVs, metal traces, or hybrid bonding units.

[0059] The second inverter 514 can be coupled to the selection circuit 518 at the first input 520 of the multiple inputs. In response to an input at the selection input 523, an output signal of the selection circuit 518 is generated at output 522. According to some embodiments, the selection input 523 receives the outputs of memory cells 524 and 526. Memory cells 524 and 526 may be part of a CRAM that receives a gated reference voltage (e.g., a gated VGG voltage). By providing gating for the second inverter 514, leakage current / parasitic current from the ungated to the gated circuit region can be reduced. Many leakage paths exist in the circuitry of an integrated circuit device. For example, leakage paths may exist in the drive paths of die 2, such as in the transistors coupled to the selection circuit 518 at input 520. More specifically, leakage current may exist in the transmission gates including the P-channel transistor coupled to input 520, where current may leak from the source of the P-channel transistor to the body of the transistor. Leakage may also exist in the path between inputs 520 and 521 that includes the P-channel transistor. By using a gated reference voltage to inverter 514 to provide isolation between interconnect units 516 that transmit signals to inverter 514, current leakage in die 2, such as current leakage in selection circuit 518, can be reduced. It should be noted that current leakage generally occurs between the non-gated and gated regions. In addition to current leakage, actively enabled paths can create current paths from the non-gated to the gated regions, where the isolation provided by the gated power supply will shut down these current paths.

[0060] To enable the transmission of signals from inverter 512 to other parts of the integrated circuit device (including other parts of die 2) or to die 3 of the stacked die arrangement of the integrated circuit device via interconnect unit 516, additional units are provided in die 2. For example, an inverter 528 that receives a reference voltage (e.g., VCCINT) instead of a gated reference voltage (e.g., gated VCCINT) is provided to ensure that signals provided to die 2 via interconnect unit 516 can be provided to other parts of die 2 and die 3. Inverter 528 receives the signal generated at interconnect unit 516 and provides the signal to other circuit units for signal routing. For example, other circuit units may include a multiplexer 530 having inputs 532 and 534 configured to receive a signal that can be selected to be provided to output 536 in response to a signal received at selection input 537, which can be received from a memory unit, which may be a CRAM memory unit 538 that receives the reference signal. Output 536 is coupled to inverter 540, which receives a reference voltage Vref and provides its output to other parts of the integrated circuit device, such as die 2 or die 3, via interconnect unit 542 (which enables signal transmission to die 3). By providing inverter 528 and other units that enable signal transmission from interconnect unit 516 to other parts of the integrated circuit, signals from die 1 can be transmitted to other parts of the integrated circuit. This allows inverter 514 to be controlled by a gated reference voltage to avoid defective parts of the integrated circuit and to prevent current leakage in potentially unused devices, such as selection circuit 518.

[0061] The benefit provided by the described circuitry and method is the presence of short circuits, such as a VCCINT-GND short circuit on a die. Without power gating, the die must be discarded. However, with power gating, the short circuit is transformed into a virtual VCCINT-GND short circuit, thus avoiding the VCCINT-GND short circuit. VCCINT is a global power supply that may be common to all dies in the stack, while the virtual VCCINT is a local power supply for that specific die. Any short circuit to this local power supply can be isolated from the global external power supply. This improves yield by avoiding the use of defective dies. For example, if there is a stack of 3 dies and a VCCINT-GND short circuit on one die, it is necessary to discard the device with multiple dies, one of which is defective and lacks power gating. With power gating, a stack of 2 dies can still function normally.

[0062] Turn now Figure 6 This shows another block diagram of a portion of a circuit 600 used to transmit signals between stacked dies of an integrated circuit device. Figure 6 The circuit is similar to Figure 5The circuit, except that post connection 603 extends between die 601 and 602, includes a tri-state inverter adapted to provide and receive tri-state signals to and from the post connection. For example... Figure 6 As shown, the inverter 604 of buffer 605 is configured to receive an input signal and be controlled by a tri-state signal, such that the output of the tri-state inverter can float if no signal is sent to the pin connection. The output of tri-state inverter 604 is coupled to pin connection 603, which is also coupled to inverter 606 to receive a signal from pin connection 603. Inverter 606 is controlled by a gated reference voltage and, together with inverter 604, forms a buffer separated between die 1 and die 2. The output of inverter 606 is coupled to selection circuit 608 at input 610. In response to a signal received at control signal input 613, a selection input for selection circuit 608 is generated at output 612. According to some embodiments, the signal provided to the control signal input may come from memory cells 614 and 616, which may be CRAM cells that receive a gated voltage (e.g., gated VGG). Other tri-state inverters (such as tri-state inverter 618) can be coupled to pillar connection 603 to allow data to be transferred from inverter 604 to other parts of the die or to die 3. In the case of pillar connection, using a split inverter with a defined inverter load can also provide better control over latency and offer lower latency than a non-split solution.

[0063] Turn now Figure 7 It shows that it can be used Figure 5 and 6 A block diagram of an exemplary gated circuit 700 implemented in the circuit is shown below. A gated reference voltage can be generated using a series of transistors coupled between a reference voltage Vref and ground. A p-channel transistor 702 has a source and a drain, wherein the source is configured to receive the reference voltage, and the drain is coupled to the drain of an n-channel transistor 704. A first control signal (control_1) is coupled to the gate 706 of transistor 702, and a second control signal (control_2) is coupled to the gate 708 of transistor 704. The gated reference voltage (gated Vref) can be generated at a node between the drains of transistors 702 and 704 in response to the control signals. A specific example of generating a gated VGG signal will be referenced below. Figure 8 Describe it.

[0064] Turn now Figure 8 The timing diagram shows Figure 7The gating circuit generates the gated VGG signal. For a defect-free die, control signal _1 remains low to keep transistor 702 on. Control signal _2 remains high until VGG is on, then goes low, allowing the gated VGG signal to follow VGG. For a defective die, control signal _2 remains high, keeping transistor 704 on, while the gated VGG signal remains low. Control signal _1 follows the VGG signal.

[0065] In the presence of a defective die, both Control_1 and Control_2 are pulled low. Control_2 remains on Vccint, and Control_1 rises with Vgg. A pull-down circuit is provided on the gated Vref signal (e.g., the gated VGG signal) during startup to ensure wake-up in a known state. This is achieved using an N-channel transistor 704 controlled by Vccint. During the startup sequence, transistor 704 initially remains on. Then, depending on whether the device is defective, the Vgg transmission gate switch (transistor 704) will either remain off or turn on.

[0066] like Figure 5 and 6 The described full VGG gate with isolation is advantageous, as VGG power gating would be impossible without these isolation inverters, since the PMOS transistors in the select multiplexer would be turned on, and a current path would exist without the isolation inverters. Furthermore, better yield can be achieved if the short circuit between the gated VGG and ground is overcome.

[0067] Turn now Figure 9 The flowchart illustrates a method for transferring circuitry in an integrated circuit device; at block 902, a first die is provided, for example... Figure 5 and 6 Die 1. At block 904, the second die is coupled to the first die, for example... Figure 5 and 6 Die 2. At block 906, as described above, a first inverter with a buffer is provided on a first side of the boundary between the first die and the second die. At block 908, a second inverter with a buffer is provided on a second side of the boundary between the first die and the second die. For example, the first and second inverters could be... Figure 5 Inverters 512 and 514 or Figure 6 Inverters 604 and 606. At block 910, data is transferred between the first and second dies via a buffer. At block 912, power gating is provided for the inverters, such as the second inverter with a buffer.

[0068] According to some embodiments, the second inverter can be configured to receive a gated reference voltage based on a reference voltage, wherein the first inverter is configured to receive the reference voltage. A third inverter can be implemented on the second die, wherein the third inverter is configured to receive the reference voltage. According to some embodiments, the first inverter may include a tri-state inverter and be configured to receive a tri-state signal. For example, as... Figure 6 As shown, the use of a tri-state inverter may be advantageous for use with post connections. The power gating circuit can be implemented in various ways, wherein the power gating circuit can be coupled to the first inverter of the buffer, and wherein the power gating circuit is configured to apply a gating reference signal to the first inverter. The second die may also include an interconnect unit configured to receive a second gating reference voltage. The interconnect unit may include a selection circuit with a selection input configured to receive a control signal from a memory cell configured to receive the second gating reference voltage. The first inverter may be associated with the input / output block of the first die, and the second inverter may be associated with the input / output block of the second die.

[0069] Figure 9 The method can be used Figure 1-8 The circuit described in 10-11, or some other suitable circuit, can be used to implement it. Although specific features of the method have been described, it should be understood that additional features of the method or additional details related to those features can be implemented according to... Figure 1-9 It will be implemented based on publicly available information.

[0070] Turn now Figure 10The diagram shows a block diagram of a programmable logic device. While devices with programmable resources can be implemented in any type of integrated circuit device, such as application-specific integrated circuits (ASICs) with programmable resources, other devices include application-specific programmable logic devices (PLDs). One type of PLD is a complex programmable logic device (CPLD). A CPLD consists of two or more "functional blocks" connected together by an interconnect switch matrix and linked to input / output (I / O) resources. Each functional block of a CPLD contains a two-level and / or structure similar to that used in programmable logic arrays (PLAs) or programmable array logic (PAL) devices. Another type of PLD is a field-programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input / output blocks (IOBs). CLBs and IOBs are interconnected through a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream (typically from off-chip memory) into the FPGA's configuration memory cells. For both types of programmable logic devices, the function of the device is controlled by configuration data bits (or configuration data bits sent during partial reconfiguration) provided to the configuration bit stream for this purpose. Configuration data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), non-volatile memory (e.g., flash memory, as in some CPLDs), or any other type of memory cell.

[0071] Figure 10 The devices include an FPGA architecture 1000 with a large number of different programmable blocks, including a multi-gigabit transceiver (MGT) 1001, a CLB 1002, a block of random access memory (BRAM) 1003, an input / output block (IOB) 1004, configuration and clock logic (CONFIG / CLOCKS) 1005, a digital signal processing block (DSP) 1006, dedicated input / output blocks (I / O) 1007 (e.g., configuration ports and clock ports), and other programmable logic 1008, such as a digital clock manager, analog-to-digital converter, system monitoring logic, etc. For example, some FPGAs also include a dedicated processor block (PROC) 1010, which can be used to implement software applications.

[0072] In some FPGAs, each programmable block includes a programmable interconnect unit (INT) 1011 with standardized connections to corresponding interconnect units in each adjacent block. Thus, the programmable interconnect units together implement the programmable interconnect structure of the FPGA shown. The programmable interconnect unit 1011 also includes connections to and from programmable logic units within the same block, such as in... Figure 10 The examples included at the top are shown.

[0073] For example, CLB 1002 may include configurable logic units (CLEs) 1012, which can be programmed to implement user logic plus a single programmable interconnect unit 1011. In addition to including one or more programmable interconnect units, BRAM 1003 may also include BRAM logic units (BRLs) 1013. BRAM includes dedicated memory separate from the distributed RAM of the configuration logic blocks. Typically, the number of interconnect units contained in a tile depends on the height of the tile. In the illustrated embodiment, a BRAM tile has the same height as five CLBs, but other numbers may also be used. In addition to an appropriate number of programmable interconnect units, DSP block 1006 may also include DSP logic units (DSPLs) 1014. In addition to one instance of programmable interconnect unit 1011, IOB 1004 may also include, for example, two instances of input / output logic units (IOLs) 1015. IOLs 1015 can be used to implement circuits and methods. The location of device connections is controlled by configuration data bits in a configuration bitstream provided to the device for this purpose. In response to the bits configuring the bit stream, programmable interconnects enable connections including interconnects to be used to couple various signals to circuits implemented in programmable logic or other circuits such as BRAM or processors.

[0074] In the illustrated embodiment, the column region near the center of the die is used for configuration, clock, and other control logic. A configuration / clock distribution area 1009 extending from this column is used to distribute clock and configuration signals across the width of the FPGA. Some utilize... Figure 10 The FPGA architecture shown includes additional logic blocks that disrupt the conventional columnar structure that makes up the majority of the FPGA. These additional logic blocks can be programmable blocks and / or dedicated logic. For example, Figure 10 The processor block PROC1010 shown spans several columns of CLB and BRAM.

[0075] It should be pointed out that, Figure 10 This is for illustrative purposes only, representing an exemplary FPGA architecture. The number of logic blocks in a column, the relative width of the column, the number and order of columns, the types of logic blocks contained in the column, the relative size of the logic blocks, and the contents contained within the columns are all specified. Figure 10 The interconnect / logic implementation at the top is purely exemplary. For example, in a real FPGA, more than one column of adjacent CLBs is typically included wherever a CLB appears, to facilitate efficient implementation of user logic. While Figure 10 The implementations relate to integrated circuits with programmable resources; however, it should be understood that the circuits and methods described above can be implemented in any type of device with a combination of programmable resources and hardware.

[0076] Turn now Figure 11 , showed Figure 10 A block diagram of the configurable logic units of a programmable logic device. Specifically, Figure 11 The diagram is presented in a simplified form. Figure 10 The configuration logic block 1002 is a configurable logic unit as an example of programmable logic. Figure 11 In this implementation, slice M 1101 includes four lookup tables (LUTMs) 1101A-1101D, each driven by six LUT data inputs A1-A6, B1-B6, C1-C6, and D1-D6, and each lookup table provides two LUT output signals O5 and O6. The O6 output from LUTs 1101A-1101D drives the slice outputs AD, respectively. The LUT data input signals are provided by the FPGA interconnect structure via an input multiplexer, which can be implemented by a programmable interconnect unit 1111, and the LUT output signals are also provided to the interconnect structure. Slice M also includes: output selection multiplexers 1111A-1111D driving the AMUX-DMUX output; multiplexers 1112A-1112D driving the data inputs of memory cells 1102A-1102D; combination multiplexers 1116, 1118, and 1119; bounce multiplexer circuits 1122-1123; circuitry represented by inverter 1105 and multiplexer 1106 (which together provide optional inversion on the input clock path); and carry logic with multiplexers 1114A-1114D, 1115A-1115D, 1120-1121, and XOR gates 1113A-1113D. All these units are as follows: Figure 11 They are coupled together as shown. For in Figure 11 The multiplexer shown does not include a selection input; the selection input is controlled by a configuration memory unit. That is, the configuration bits of the configuration bitstream stored in the configuration memory unit are coupled to the selection input of the multiplexer to select the correct input. These well-known configuration memory units are shown for clarity from... Figure 11 Figures from other selections in this article are omitted.

[0077] In the illustrated embodiment, each memory cell 1102A-1102D can be programmed to function as a synchronous or asynchronous trigger or latch. The selection between synchronous and asynchronous functions for all four memory cells in the slice is made by programming the synchronous / asynchronous selection circuit 1103. When a memory cell is programmed such that the S / R (set / reset) input signal provides a set function, the REV input provides a reset function. When a memory cell is programmed such that the S / R input signal provides a reset function, the REV input provides a set function. Memory cells 1102A-1102D are timed by a clock signal CK, which can be provided, for example, by a global clock network or interconnect structure. Such programmable memory cells are well-known in the FPGA design field. Each memory cell 1102A-1102D provides registered output signals AQ-DQ to the interconnect structure. Since each LUT 1101A-1101D provides two output signals O5 and O6, the LUT can be configured as two 5-input LUTs with five shared input signals (IN1-IN5), or a 6-input LUT with input signals IN1-IN6.

[0078] exist Figure 11In this implementation, each LUTM 1101A-1101D can operate in any of several modes. In lookup table mode, each LUT has six data input signals IN1-IN6, which are provided by the FPGA interconnect structure via input multiplexers. Based on the values ​​of signals IN1-IN6, one of 64 data values ​​is programmably selected from the configuration memory cell. In RAM mode, each LUT functions as a single 64-bit RAM or two 32-bit RAMs with shared addressing. RAM write data is provided to the 64-bit RAM via input terminal DI1 (via multiplexers 1117A-1117C for LUTs 1101A-1101C), or to the two 32-bit RAMs via inputs DI1 and DI2. RAM write operations in the LUT RAM are controlled by the clock signal CK from multiplexer 1106 and the write enable signal WEN from multiplexer 1107, which can selectively provide either the clock enable signal CE or the write enable signal WE. In shift register mode, each LUT serves as two 16-bit shift registers, or two 16-bit shift registers are cascaded to create a single 32-bit shift register. The shift-in signal is provided through one or both of inputs DI1 and DI2. The 16-bit and 32-bit shift-out signals can be provided through the LUT outputs, with the 32-bit shift-out signal also provided more directly through LUT output MC31. The 32-bit shift-out signal MC31 of the LUT1101A can also be provided to a general interconnect structure for shift register chains via the output selector multiplexer 1111D and the CLE output DMUX. Therefore, the circuits and methods described above can be applied to, for example... Figure 10 and 11 It can be implemented in devices such as those or in any other suitable device.

[0079] Therefore, it can be understood that novel circuits and methods for transmitting signals in integrated circuit devices have been described. Those skilled in the art will understand that many alternatives and equivalents exist in conjunction with the disclosed invention. Therefore, the invention is not limited to the foregoing embodiments, but only to the following claims.

Claims

1. A circuit for transmitting signals in an integrated circuit device, characterized in that, The circuit includes: The first nude film; The second die stacked on the first die; and A buffer for transmitting data between the first die and the second die; The first inverter of the buffer is on the first die, and the second inverter of the buffer is on the second die. The first inverter is configured to receive a reference voltage, and the second inverter is configured to receive a gated reference voltage. The first inverter is implemented in the non-gated region, and the second inverter is implemented in the gated region. The second inverter acts as an isolation unit to reduce current leakage between the gated region and the non-gated region, and The circuit also includes a third inverter on the second die, wherein the third inverter is configured to receive the output of the first inverter and the reference voltage.

2. The circuit according to claim 1, characterized in that, The gating reference voltage is based on the reference voltage.

3. The circuit according to claim 1, characterized in that, The circuit also includes a third die stacked on the second die, wherein the third inverter is configured to transfer the data from the first die to the third die.

4. The circuit according to claim 2, characterized in that, The second die includes interconnect elements configured to receive a second gated reference voltage.

5. The circuit according to claim 4, characterized in that, The interconnect element includes a selection circuit with a selection input configured to receive a control signal from a memory element configured to receive the second gated reference voltage.

6. The circuit according to claim 1, characterized in that, The first inverter includes a tri-state inverter and is configured to receive a tri-state signal, and the second inverter is configured to receive a gated reference voltage.

7. The circuit according to claim 6, characterized in that, The first inverter and the second inverter are coupled to a post connection extending between the first die and the second die.

8. The circuit according to claim 1, characterized in that, The circuit also includes a power gating circuit coupled to a second inverter of the buffer, wherein the power gating circuit is configured to apply a gating reference voltage to the second inverter.

9. The circuit according to claim 1, characterized in that, The first inverter is associated with the input / output block of the first die, and the second inverter is associated with the input / output block of the second die.

10. A method for transmitting signals in an integrated circuit device, characterized in that, The method includes: Provide the first nude film; Stack a second die on the first die; and Data is transferred between the first die and the second die via a buffer; The first inverter of the buffer is on the first die, and the second inverter of the buffer is on the second die. The first inverter is configured to receive a reference voltage, and the second inverter is configured to receive a gated reference voltage. The first inverter is implemented in the non-gated region, and the second inverter is implemented in the gated region. The second inverter acts as an isolation unit to reduce current leakage between the gated region and the non-gated region, and The method further includes implementing a third inverter on the second die, wherein the third inverter is configured to receive the output of the first inverter and the reference voltage.

11. The method according to claim 10, characterized in that, The method further includes configuring the first inverter to receive a reference voltage, and configuring the second inverter to receive a gated reference voltage based on the reference voltage.

12. The method according to claim 10, characterized in that, The method further includes stacking a third die on the second die, wherein the third inverter is configured to transfer the data from the first die to the third die.

13. The method according to claim 11, characterized in that, The method further includes configuring interconnect elements of the second die to receive a second gated reference voltage, wherein configuring the interconnect elements includes configuring a selection circuit having a selection input coupled to receive a control signal from a memory element configured to receive the second gated reference voltage.

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