Display driving apparatus

Abstract

A display driving apparatus that is not sensitive to external noise is disclosed. The display driving apparatus can include a first data line and a second data line configured to connect a transmitter of a timing controller and a receiver of a source driver, a first termination resistance and a second termination resistance configured to connect the first data line and the second data line, and a noise reduction circuit configured to detect a lock fault, generate a common voltage when the lock fault is detected, and provide the common voltage to a node between the first termination resistance and the second termination resistance. The display driving apparatus can prevent image failure by minimizing the effect of external noise.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display apparatus, and more particularly, to a display driving apparatus capable of preventing image failure by minimizing the influence of external noise. BACKGROUND

[0002] In general, a display apparatus can include a display panel, a gate driver, a source driver, a timing controller, etc. The timing controller can provide image data to the source driver. The source driver can provide a source signal corresponding to the image data to the display panel.

[0003] The timing controller and the source driver can be connected through a pair of data lines. In order to match impedance, a termination resistance can be provided at an end of the data line.

[0004] The timing controller can transmit input data having a packet form and including a clock, image data, and control data to the source driver through the data line. The source driver can recover the clock, the image data, and the control data from the input data.

[0005] However, if external noise acts on the pair of data lines together, a level of a common voltage formed in the termination resistance can be changed. If the level of the common voltage is changed due to the external noise, a level of the input data can deviate from an input range of a receiver of the source driver. Accordingly, a problem that the source driver cannot normally recover the clock, the image data, and the control data from the input data will occur.

[0006] Therefore, there is a need for a technology capable of minimizing the influence of external noise on the common voltage. SUMMARY

[0007] Various embodiments relate to providing a display driving apparatus capable of preventing image failure by minimizing the influence of external noise.

[0008] In one embodiment, the display driving apparatus can include a first data line and a second data line configured to connect a transmitter of a timing controller and a receiver of a source driver, a first termination resistance and a second termination resistance configured to connect the first data line and the second data line, and a noise reduction circuit configured to detect a lock failure in response to a clock signal, generate a common voltage when the lock failure is detected, and provide the common voltage to a node between the first termination resistance and the second termination resistance.

[0009] A display driving apparatus can include a first data line and a second data line configured to connect a transmitter of a timing controller and a receiver of a source driver, a first termination resistance and a second termination resistance configured to connect the first data line and the second data line, and a noise reduction circuit configured to detect a lock fault in response to a clock signal, determine whether the detected lock fault satisfies a preset condition, generate a common voltage when the detected lock fault satisfies the preset condition, and provide the common voltage to a node between the first termination resistance and the second termination resistance.

[0010] A display driving apparatus can include a first data line and a second data line configured to connect a transmitter of a timing controller and a receiver of a source driver, a first termination resistance and a second termination resistance configured to connect the first data line and the second data line, and a voltage source configured to have one end connected to a node between the first termination resistance and the second termination resistance.

[0011] According to an embodiment, when a lock fault attributable to external noise is detected, a common voltage having a fixed level is provided to a node between the first termination resistance and the second termination resistance disposed between the first data line and the second data line. Accordingly, a level change of input data attributable to external noise can be minimized.

[0012] Further, an embodiment can prevent an image fault by minimizing an influence of external noise on a common voltage.

[0013] Further, an embodiment can prevent an image fault by minimizing a change in a voltage level of a node attributable to external noise by connecting a capacitor to the node between the first termination resistance and the second termination resistance. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a block diagram of a display apparatus according to an embodiment.

[0015] Figure 2 is a block diagram of a display apparatus including a source driver according to a first embodiment.

[0016] Figure 3 is a waveform diagram of input data transmitted through a pair of data lines of Figure 1 .

[0017] Figure 4 is a waveform diagram illustrating that a level of input data is changed due to external noise.

[0018] Figure 5 is a block diagram of a noise reduction circuit of a source driver according to another embodiment.

[0019] Figure 6is a block diagram of a display apparatus including a source driver according to a second embodiment.

[0020] Figure 7 is a block diagram of a display apparatus including a source driver according to a third embodiment.

[0021] Figure 8 is a block diagram of a display apparatus including a source driver according to a fourth embodiment.

[0022] Figure 9 is a block diagram of a display apparatus including a source driver according to a fifth embodiment. DETAILED DESCRIPTION

[0023] Embodiments disclose a display driving apparatus capable of preventing image failure by minimizing the influence of external noise.

[0024] In embodiments, a transmitter TX can be defined as a transmitter of a timing controller that transmits input data, image data, and control data having a packet form and including a clock to a source driver.

[0025] In embodiments, a receiver RX can be defined as a receiver of a source driver that receives input data, image data, and control data having a packet form and including a clock from a timing controller.

[0026] In embodiments, a protocol for transmitting input data, image data, and control data having a packet form and including a clock through a pair of first and second data lines can be established in a timing controller. A protocol for recovering a clock, image data, and control data from input data received through a pair of first and second data lines can be established in a source driver.

[0027] Figure 1 is a block diagram of a display apparatus 100 according to embodiments.

[0028] Referring to Figure 1 , the display apparatus 100 can include a display driving apparatus and a display panel. The display driving apparatus can include a timing controller TCON and a plurality of first to fifth source drivers SDIC1 to SDIC5. The number of source drivers of the display driving apparatus can be determined by the resolution of the display panel.

[0029] The timing controller TCON can be connected to the plurality of first to fifth source drivers SDIC1 to SDIC5 in a point-to-point manner through a pair of data lines L1 and L2. "L1" is designated as a first data line, and "L2" is designated as a second data line.

[0030] The timing controller TCON can provide input data CED to each of the source drivers SDIC1 to SDIC5 through each pair of data lines L1 and L2.

[0031] The first source driver SDIC1 to the fifth source driver SDIC5 are configured to transmit a lock signal LOCK through a lock link. The lock link means that the first source driver SDIC1 to the fifth source driver SDIC5 are sequentially cascaded to transmit the lock signal LOCK.

[0032] For example, each of the first source driver SDIC1 to the fifth source driver SDIC5 includes a lock signal input stage and a lock signal output stage. The first lock signal input stage of the first source driver SDIC1 can be connected to a power terminal VCC. In addition, the lock signal output stage of the first source driver SDIC1 and the lock signal input stage of the second source driver SDIC2, the lock signal output stage of the second source driver SDIC2 and the lock signal input stage of the third source driver SDIC3, the lock signal output stage of the third source driver SDIC3 and the lock signal input stage of the fourth source driver SDIC4, and the lock signal output stage of the fourth source driver SDIC4 and the lock signal input stage of the fifth source driver SDIC5 can be interconnected. In addition, the last lock signal output stage of the fifth source driver SDIC5 can be connected to the timing controller TCON through a feedback link.

[0033] When a lock failure occurs in at least one of the first source driver SDIC1 to the fifth source driver SDIC5, the fifth source driver SDIC5 can provide the timing controller TCON with the lock signal LOCK having a logic level indicating the lock failure.

[0034] For example, when the clock signal is stabilized by clock training, the first source driver SDIC1 to the fifth source driver SDIC5 can output the lock signal LOCK having a high logic level indicating a normal lock state. In addition, when a lock failure is detected due to an unstable timing signal attributable to external noise or other causes, the first source driver SDIC1 to the fifth source driver SDIC5 can output the lock signal LOCK having a low logic level indicating the lock failure.

[0035] For example, when the lock signal LOCK having a high logic level is received from the fifth source driver SDIC5, the timing controller TCON can provide the first source driver SDIC1 to the fifth source driver SDIC5 with input data CED including a clock, image data, and control data.

[0036] Further, when receiving the lock signal LOCK having a low logic level from the fifth source driver SDIC5, the timing controller TCON can provide the first source driver SDIC1 to the fifth source driver SDIC5 with input data CED including a clock training mode for setting a clock.

[0037] Figure 2 is a block diagram of a display apparatus 100 including the source driver SDIC according to the first embodiment.

[0038] Referring to Figure 2 , the display apparatus 100 can include a transmitter TX of the timing controller TCON and the source driver SDIC.

[0039] The source driver SDIC can include a receiver RX and a noise reduction circuit 10.

[0040] The transmitter TX of the timing controller TCON and the receiver RX of the source driver SDIC can be connected through a pair of first and second data lines L1 and L2.

[0041] Further, a first termination resistor R1 can be configured at an end portion of the first data line L1. A second termination resistor R2 can be configured at an end portion of the second data line L2. The first termination resistor R1 and the second termination resistor R2 are connected through a node N1. That is, the first termination resistor R1 and the second termination resistor R2 can be connected in series between the first data line L1 and the second data line L2.

[0042] In this case, for impedance matching, the first termination resistor R1 can be configured to have the same resistance value as the first data line L1. The second termination resistor R2 can be configured to have the same resistance value as the second data line L2. In Figure 2 , the PCB means a printed circuit board on which the first termination resistor R1 and the second termination resistor R2 are printed.

[0043] The transmitter TX of the timing controller TCON can provide the receiver RX of the source driver SDIC with input data CED through the first and second data lines L1 and L2. In this case, the input data CED can include a clock, image data, and control data in a packet form.

[0044] The receiver RX of the source driver SDIC can receive the input data CED through the first and second data lines L1 and L2. The source driver SDIC can provide the input data CED to a clock recovery circuit (not shown) and a data recovery circuit (not shown).

[0045] For example, the clock recovery circuit can generate a sampling clock signal by recovering a clock from the input data CED based on a preset protocol, and can provide the sampling clock signal to the data recovery circuit.

[0046] The data recovery circuit can recover image data and control data from the input data CED by using the sampling clock signal.

[0047] The noise reduction circuit 10 can detect a lock failure by using the lock signal LOCK, can generate a common voltage VCM when the lock failure is detected, and can provide the common voltage VCM to a node N1 between the first termination resistance R1 and the second termination resistance R2.

[0048] The noise reduction circuit 10 can include a lock failure detector 12 and a VCM generator 14.

[0049] The lock failure detector 12 can receive the lock signal LOCK, can detect a lock failure in response to the lock signal LOCK, and can output an enable signal EN to the VCM generator 14 when the lock failure is detected.

[0050] For example, the lock signal LOCK can be received from another source driver through a lock link, or can be generated in an internal circuit. In this case, when an abnormal communication state occurs due to external noise, the lock signal LOCK can be generated as a signal having a low logic level.

[0051] The VCM generator 14 can generate a common voltage VCM having a fixed level in response to the enable signal EN, and can provide the common voltage VCM to the node N1 between the first termination resistance R1 and the second termination resistance R2.

[0052] Further, after providing the common voltage VCM to the node N1 between the first termination resistance R1 and the second termination resistance R2, the VCM generator 14 can be disabled when a given time elapses.

[0053] The VCM generator 14 can be configured to include a buffer acting as a current source. The VCM generator 14 fixes a potential of the node N1 to the common voltage VCM and acts as a current source for the first termination resistance R1 and the second termination resistance R2. Therefore, although external noise affects the first termination resistance R1 and the second termination resistance R2, a change in voltage applied to the first termination resistance R1 and the second termination resistance R2 can be suppressed by the VCM generator 14, which fixes the potential of the node N1 to the common voltage VCM and acts as a current source to provide a current path for the external noise.

[0054] When a lock-up failure attributable to external noise occurs, the noise reduction circuit 10 configured as described above can minimize the influence of external noise on the common voltage VCM by supplying the common voltage VCM, which is internally generated and has a fixed level, to the node N1 between the first termination resistor R1 and the second termination resistor R2.

[0055] Figure 2 The first embodiment of the first termination resistor R1 and the second termination resistor R2 is shown as being disposed in the printed circuit board PCB, but the present disclosure is not limited thereto. The first termination resistor R1 and the second termination resistor R2 can be disposed within a chip of the source driver SDIC.

[0056] Figure 3 is a waveform diagram illustrating input data CED transmitted through a pair of a first data line L1 and a second data line L2 of Figure 1

[0057] The input data CED can be applied to the first termination resistor R1 and the second termination resistor R2, and can be expressed as a differential voltage that swings based on the common voltage VCM.

[0058] The receiver RX can be set to have a fixed input range.

[0059] When a lock-up failure attributable to external noise occurs, the noise reduction circuit 10 can minimize the influence of external noise on the common voltage VCM by generating the common voltage VCM having a fixed level and supplying the common voltage VCM to the node N1 between the first termination resistor R1 and the second termination resistor R2.

[0060] As described above, the noise reduction circuit 10 can minimize the influence of external noise on the common voltage VCM. The input data CED can swing through the first termination resistor R1 and the second termination resistor R2 based on the common voltage VCM having a fixed level.

[0061] The source driver SDIC can normally recover a clock, image data, and control data from the input data CED received as described above.

[0062] Figure 4 is a waveform diagram illustrating that a level of input data CED is changed due to external noise.

[0063] For example, if there is no element of the noise reduction circuit 10, and common noise occurs in a positive node P_NODE of the first data line L1 and a negative node N_NODE of the second data line L2, a level of the common voltage VCM can be changed due to the common noise, and a swing range of the input data CED can deviate from an input range of the receiver RX of the source driver SDIC.

[0064] ​In this case, the source driver SDIC cannot recover the clock, the image data, and the control data from the input data CED deviated from the input range.

[0065] However, the source driver SDIC according to the present embodiment includes the noise reduction circuit 10. Therefore, when the common noise occurs in the positive node P_NODE of the first data line L1 and the negative node N_NODE of the second data line L2, the common voltage VCM having a fixed level is provided to the node N1 between the first termination resistance R1 and the second termination resistance R2, and the influence of the external noise on the common voltage VCM can be minimized.

[0066] Figure 5 is a block diagram of the noise reduction circuit 10 of the source driver SDIC according to another embodiment.

[0067] Reference Figure 5 , the noise reduction circuit 10 can include a lock fault detector 12, a control logic circuit 16, and a VCM generator 14.

[0068] The lock fault detector 12 can receive a lock signal LOCK, can detect a lock fault in response to the lock signal LOCK, and can output a first enable signal EN1 corresponding to the lock fault to the control logic circuit 16.

[0069] For example, the lock signal LOCK can be provided by another source driver through a lock link, or can be generated in an internal circuit. In this case, when an abnormal communication state occurs due to external noise, the lock signal LOCK can be generated as a signal having a low logic level.

[0070] The control logic circuit 16 can output a second enable signal EN2 to the VCM generator 14 in response to the first enable signal EN1 when a reference number or more of the lock faults are detected.

[0071] The VCM generator 14 can generate the common voltage VCM in response to the second enable signal EN2, and can provide the common voltage VCM to the node N1 between the first termination resistance R1 and the second termination resistance R2.

[0072] Further, after providing the common voltage VCM to the node N1 between the first termination resistance R1 and the second termination resistance R2, the VCM generator 14 can be disabled when a given time elapses.

[0073] When a reference number or more number of lock failures attributable to external noise are detected, the noise reduction circuit 10 configured as described above can minimize the influence of external noise on the common voltage VCM by generating the common voltage VCM and supplying the common voltage VCM to the node N1 between the first termination resistor R1 and the second termination resistor R2.

[0074] If the lock failure is maintained for a reference time or more after the lock failure attributable to external noise is detected, the noise reduction circuit 10 according to another embodiment can generate the common voltage VCM and supply the common voltage VCM to the node N1 between the first termination resistor R1 and the second termination resistor R2.

[0075] The noise reduction circuit 10 can include a lock failure detector 12, a control logic circuit 16, and a VCM generator 14.

[0076] The lock failure detector 12 can receive a lock signal LOCK, can detect a lock failure in response to the lock signal LOCK, and can output a first enable signal EN1 to the control logic circuit 16 upon detecting the lock failure.

[0077] If the lock failure is maintained for a reference time or more after the lock failure is detected, the control logic circuit 16 can output a second enable signal EN2 to the VCM generator 14 in response to the first enable signal EN1.

[0078] The VCM generator 14 can generate the common voltage VCM in response to the second enable signal EN2, and can supply the common voltage VCM to the node N1 between the first termination resistor R1 and the second termination resistor R2.

[0079] As described above, the noise reduction circuit 10 can detect a lock failure, can determine whether the detected lock failure satisfies a preset condition, can generate the common voltage VCM when the detected lock failure satisfies the preset condition, and can supply the common voltage VCM to the node N1 between the first termination resistor R1 and the second termination resistor R2.

[0080] In this case, the preset condition can be set as a condition in which a reference number or more number of lock failures are detected, or a condition in which the lock failure is maintained for a reference time or more.

[0081] As described above, when a lock failure is detected due to external noise and the detected lock failure satisfies a preset condition, the display driving apparatus according to an embodiment can minimize a change in the level of input data CED by supplying a common voltage VCM to a node N1 between first and second termination resistors R1 and R2 formed between a first data line L1 and a second data line L2.

[0082] Further, the embodiment can prevent image failure by minimizing the influence of external noise on the common voltage VCM.

[0083] Figure 6 is a block diagram of a display device 100 including a source driver SDIC according to a second embodiment.

[0084] Referring to Figure 6 , the source driver SDIC according to the second embodiment can include a receiver RX, a first termination resistance R1, a second termination resistance R2, and a capacitor C.

[0085] The receiver RX can be connected to a transmitter TX of a timing controller through a first data line L1 and a second data line L2.

[0086] The first termination resistance R1 and the second termination resistance R2 can be disposed within a chip of the source driver SDIC. The first termination resistance R1 and the second termination resistance R2 can be connected in series between the first data line L1 and the second data line L2.

[0087] The capacitor C can have one end connected to a node N1 between the first termination resistance R1 and the second termination resistance R2, and can have the other end connected to a terminal to which an external voltage Vx is applied. The external voltage Vx can have a fixed level.

[0088] The transmitter TX of the timing controller TCON can provide input data CED to the receiver RX of the source driver SDIC through the first data line L1 and the second data line L2.

[0089] Figure 7 is a block diagram of a display device 100 including a source driver SDIC according to a third embodiment.

[0090] Referring to Figure 7 , the source driver SDIC according to the third embodiment can include a receiver RX and a capacitor C.

[0091] The receiver RX can be connected to a transmitter TX of a timing controller through a first data line L1 and a second data line L2.

[0092] In this case, the first termination resistance R1 and the second termination resistance R2 connected in series can be connected between the first data line L1 and the second data line L2. The first termination resistance R1 and the second termination resistance R2 can be disposed in a printed circuit board PCB.

[0093] The capacitor C can have one end connected to a node N1 between the first termination resistance R1 and the second termination resistance R2 disposed in the printed circuit board PCB, and can have the other end connected to a terminal to which an external voltage Vx is applied.

[0094] The capacitor C can function as a voltage source for the first termination resistor R1 and the second termination resistor R2. Thus, although external noise affects the first termination resistor R1 and the second termination resistor R2, a change in the voltage applied to the first termination resistor R1 and the second termination resistor R2 can be suppressed by the buffering action of the capacitor C.

[0095] Figure 6 And The embodiment of Figure 7 can minimize the influence of external noise on the common voltage VCM through the capacitor C and the external voltage Vx.

[0096] Figure 8 is a block diagram of a display device 100 including a source driver SDIC according to the fourth embodiment.

[0097] Referring to Figure 8 , the source driver SDIC according to the fourth embodiment can include a receiver RX, a first termination resistor R1, a second termination resistor R2, a capacitor C, and a VCM generator 14.

[0098] The receiver RX can be connected to a transmitter TX of a timing controller through a first data line L1 and a second data line L2.

[0099] The first termination resistor R1 and the second termination resistor R2 can be disposed within a chip of the source driver SDIC and can be connected in series between the first data line L1 and the second data line L2.

[0100] The capacitor C can have one end connected to a node N1 between the first termination resistor R1 and the second termination resistor R2 and can have the other end connected to the VCM generator 14. The VCM generator 14 can generate a common voltage VCM having a fixed level and can supply the common voltage VCM to the other end of the capacitor C.

[0101] Figure 8 The embodiment of can minimize the influence of external noise on the common voltage VCM through the capacitor C and the common voltage VCM.

[0102] Figure 9 is a block diagram of a display device 100 including a source driver SDIC according to the fifth embodiment.

[0103] Referring to Figure 9 , the source driver SDIC according to the fifth embodiment can include a receiver RX and a capacitor C.

[0104] The receiver RX can be connected to a transmitter TX of a timing controller through a first data line L1 and a second data line L2.

[0105] In this case, the first termination resistor R1 and the second termination resistor R2 connected in series can be connected between the first data line L1 and the second data line L2. The first termination resistor R1 and the second termination resistor R2 can be provided in the printed circuit board PCB.

[0106] The capacitor C can have one end connected to the node N1 between the first termination resistor R1 and the second termination resistor R2 provided in the printed circuit board PCB, and can have the other end connected to the terminal to which the ground voltage is applied.

[0107] Figure 9 The embodiment can minimize the influence of external noise on the common voltage through the capacitor C to which the ground voltage is applied.

[0108] As described above, the second embodiment to the fifth embodiment can minimize the change in the voltage level of the node N1 attributable to external noise by connecting the capacitor to the node N1 between the first termination resistor R1 and the second termination resistor R2, and thus can prevent image failure.

Claims

1. A display driving apparatus comprising: first and second data lines configured to connect a transmitter of a timing controller and a receiver of a source driver; first and second termination resistors configured to connect the first and second data lines; and a noise reduction circuit configured to detect a lock fault in response to a clock signal, generate a common voltage when the lock fault is detected, and provide the common voltage to a node between the first and second termination resistors, wherein the noise reduction circuit comprises: a lock fault detector configured to receive a lock signal corresponding to the clock signal, detect the lock fault in response to the lock signal, and output an activation signal when the lock fault is detected; and a common voltage generator configured to generate the common voltage in response to the activation signal and provide the common voltage to the node between the first and second termination resistors. The common voltage generator is disabled when a given time elapses after the common voltage is provided to the node between the first and second termination resistors.

2. The display driving device according to claim 1, wherein The first and second termination resistors have resistance values identical to those of the first and second data lines, respectively.

3. The display driving device according to claim 1, wherein The first and second termination resistors are disposed between end portions of the first and second data lines and connected in series.

4. The display driving apparatus according to claim 1, wherein The common voltage has a fixed level.

5. The display driving apparatus according to claim 1, wherein 6.A display driving apparatus comprising: first and second data lines configured to connect a transmitter of a timing controller and a receiver of a source driver; first and second termination resistors configured to connect the first and second data lines; and a noise reduction circuit configured to detect a lock fault in response to a clock signal, determine whether the detected lock fault satisfies a preset condition, generate a common voltage when the detected lock fault satisfies the preset condition, and provide the common voltage to a node between the first and second termination resistors, wherein the noise reduction circuit generates the common voltage and provides the common voltage to the node between the first and second termination resistors when a reference number or more of the lock faults are detected. The noise reduction circuit comprises: a lock fault detector configured to receive a lock signal, detect the lock fault in response to the lock signal, and output a first activation signal when the lock fault is detected; a control logic circuit configured to output a second activation signal in response to the first activation signal when the lock fault is maintained for a reference time or more; and 7. The display driving device according to claim 6, wherein a common voltage generator configured to generate the common voltage in response to the second activation signal and provide the common voltage to the node between the first and second termination resistors. The common voltage generator is disabled when a given time elapses after the common voltage is provided to the node between the first and second termination resistors. ​ 8. The display driving device according to claim 7, wherein ​ 9. The display driving device according to claim 6, wherein The common voltage has a fixed level.

10. A display driving apparatus, comprising: a first data line and a second data line configured to connect a transmitter of a timing controller and a receiver of a source driver; a first termination resistor and a second termination resistor configured to connect the first data line and the second data line; and a noise reduction circuit configured to detect a lock fault in response to a clock signal, determine whether the detected lock fault satisfies a preset condition, generate a common voltage when the detected lock fault satisfies the preset condition, and provide the common voltage to a node between the first termination resistor and the second termination resistor.

11. A display driving apparatus, comprising: a first data line and a second data line configured to connect a transmitter of a timing controller and a receiver of a source driver; a first termination resistor and a second termination resistor configured to connect the first data line and the second data line; and a noise reduction circuit configured to detect a lock fault in response to a clock signal, determine whether the detected lock fault satisfies a preset condition, generate a common voltage when the detected lock fault satisfies the preset condition, and provide the common voltage to a node between the first termination resistor and the second termination resistor. The noise reduction circuit comprises: a lock fault detector configured to receive a lock signal corresponding to the clock signal, detect the lock fault in response to the lock signal, and output a first enable signal when the lock fault is detected; a control logic circuit configured to output a second enable signal in response to the first enable signal when a reference number or more of the lock faults are detected; and a common voltage generator configured to generate the common voltage in response to the second enable signal, and provide the common voltage to the node between the first termination resistor and the second termination resistor. ​ ​ ​

Images