Semiconductor structure and method for forming the same

Abstract

The present application provides a semiconductor structure and a method for forming the same, the semiconductor structure comprising: a semiconductor substrate, a fin formed on the semiconductor substrate, the fin comprising a first fin portion; a gate structure, the gate structure spanning the first fin portion and covering the top and sidewalls of the first fin portion, grooves formed in the first fin portions on both sides of the gate structure, and the width of the bottom surface of the groove is less than the width of the fin portion. The semiconductor structure and the method for forming the same provided by the present application increase the average distance between the epitaxial layer and the channel, thereby reducing parasitic capacitance and leakage current, thereby improving the reliability of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Fin field effect transistor (FinFET) includes fins and gate structures. The gate structure covers part of the sidewalls and top of the fins. The sidewall surface and top surface of the fins covered by the gate structure are the channels of the FinFET. The distance between the source and drain and the channel has a great influence on the performance of the device. In order to improve the performance of the device, the distance from the source and drain to the channel is required to be as small as possible.

[0003] Usually, the fins on both sides of the gate structure are etched to form grooves, and the grooves are extended to the bottom of the gate structure. The bottom of the groove contacts the channel. After the epitaxial layer is grown in the groove as the source or drain, the source or drain can achieve zero distance from the channel. Since dry etching does not have crystal orientation selectivity, the bottom of the formed groove is flat or tends to be flat, and the width of the bottom of the groove is equal to the width of the fin. Growing the source or drain in such a groove will cause a series of problems, such as parasitic capacitance, causing RC delay in the device, affecting the operating frequency, and may also cause leakage. At the same time, the breakdown voltage between the gate and the source and drain will also become smaller, making the reliability of the device worse. Summary of the invention

[0004] The technical problem solved by the present application is to increase the distance between the source, drain and channel, reduce parasitic capacitance and leakage current, and improve the reliability of the device without affecting the performance of the device as much as possible.

[0005] To solve the above technical problems, the present application provides a semiconductor structure, including: a semiconductor substrate, a fin is formed on the semiconductor substrate, and the fin includes a first fin part; a gate structure, the gate structure spans the first fin part and covers the top and side walls of the first fin part, grooves are formed in the first fin part on both sides of the gate structure, and the width of the bottom surface of the groove is smaller than the width of the fin.

[0006] In an embodiment of the present application, a connection surface between the groove and the first portion of the fin is V-shaped, U-shaped or trapezoidal.

[0007] In an embodiment of the present application, the gate structure includes a sidewall spacer, and the depth of the groove extending to the gate structure is greater than 0 and less than or equal to the thickness of the sidewall spacer.

[0008] In an embodiment of the present application, the fin further includes a fin second portion, and the groove extends to the fin second portion along a direction perpendicular to the semiconductor substrate.

[0009] In an embodiment of the present application, a connection surface between the groove and the second portion of the fin is V-shaped, U-shaped or trapezoidal.

[0010] In an embodiment of the present application, the semiconductor structure further includes an epitaxial layer, and the epitaxial layer fills the groove.

[0011] The present application also provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, on which a fin and a gate structure are formed, the fin comprising a first fin portion, the gate structure spanning the first fin portion and covering a portion of the top and side walls of the first fin portion; etching the first fin portion on both sides of the gate structure to form a groove, and the width of the bottom surface of the groove is smaller than the width of the fin.

[0012] In an embodiment of the present application, the gate structure includes a sidewall spacer, and the depth of the groove extending to the gate structure is greater than 0 and less than or equal to the thickness of the sidewall spacer.

[0013] In an embodiment of the present application, the fin further includes a fin second portion, and the groove extends to the fin second portion along a direction perpendicular to the semiconductor substrate.

[0014] In an embodiment of the present application, the process of forming the groove includes: using a dry etching process to etch the first part of the fin on both sides of the gate structure to expose the second part of the fin on both sides of the gate structure; using an anisotropic wet etching process or an anisotropic dry etching process to continue etching part of the second part of the fin and the first part of the fin covered by the gate structure to form a groove, wherein the groove extends to the second part of the fin in a direction perpendicular to the semiconductor substrate, and the groove extends along the extension direction of the fin to below the gate structure.

[0015] In an embodiment of the present application, the method further includes growing an epitaxial layer in the groove, wherein the epitaxial layer fills the groove.

[0016] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0017] By making the bottom width of the groove smaller than the width of the fin, the average distance between the epitaxial layer and the channel is reduced, and the parasitic capacitance and leakage current are reduced without reducing the device performance, thereby improving the reliability of the device.

[0018] A two-step etching method is used to form the grooves. In the first step, a dry etching process is used to etch the first part of the fin on both sides of the gate structure to expose the second part of the fin on both sides of the gate structure; in the second step, an anisotropic wet etching process or a milder anisotropic dry etching process is used to continue etching. Compared with the dry etching process in the first step, the anisotropic wet etching or the milder anisotropic dry etching process in the second step causes less damage to the silicon surface and has a better interface state, which is beneficial to the subsequent epitaxial growth process, such as significantly reducing growth defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only used for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0020] Figure 1 is a schematic structural diagram of a semiconductor structure;

[0021] Figures 2 to 9 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0023] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0024] refer to Figure 1 A semiconductor structure includes a semiconductor substrate 100, on which a fin 110 and an isolation structure 120 are formed, wherein a portion of the fin 110 higher than the isolation structure 120 is a first fin portion 111, and a portion of the fin 110 located in the isolation structure 120 is a second fin portion 112.

[0025] The gate structure 130 spans across the first fin portion 111 and covers the top and sidewalls of the first fin portion 111. The gate structure 130 includes a gate layer 131 and a sidewall 132 located on the sidewall of the gate layer 131. The top surface and sidewall surface of the first fin portion 111 covered by the gate layer 131 are the channel 113 of the device. Grooves 140 are formed in the first fin portion 111 on both sides of the gate structure 130.

[0026] refer to Figure 1 The cross section obtained along plane P Figure 1 a. The bottom of the groove 140 formed by the dry etching process is flat or tends to be flat, and the width of the bottom of the groove 140 is the same as the width of the fin 110, that is, the width of the bottom of the groove 140 is the same as the width of the channel 113, that is, the distance between each position of the bottom of the groove 140 and the channel 113 is equal. If the bottom of the groove 140 contacts the channel 113, then after the epitaxial layer is grown in the groove 140 as the source or drain, it also contacts the channel 113. Although this semiconductor structure reduces the distance between the source or drain and the channel 113 and can improve the device performance, it is also very easy to generate parasitic capacitance, causing the device to generate RC delay, affecting the operating frequency, and may also cause leakage. At the same time, the breakdown voltage between the source or drain and the gate will also become smaller, making the reliability of the device worse.

[0027] In view of this, the technical solution of the present application reduces the contact portion of the epitaxial layer with the channel and increases the average distance between the epitaxial layer and the channel by making the bottom width of the groove smaller than the width of the fin, that is, the bottom width of the groove is smaller than the width of the channel, thereby reducing parasitic capacitance and leakage current without affecting the device performance as much as possible, thereby improving the reliability of the device.

[0028] Figures 2 to 9 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application.

[0029] refer to Figure 2 , providing a semiconductor substrate 200, wherein the material of the semiconductor substrate 200 includes (i) an element semiconductor, such as silicon or germanium, etc.; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or indium gallium phosphide, etc.; or (iv) a combination of the above. In addition, the semiconductor substrate 200 may be doped (for example, a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 200 may be doped with a P-type dopant (for example, boron, indium, aluminum or gallium) or an N-type dopant (for example, phosphorus or arsenic).

[0030] The semiconductor substrate 200 is provided with a fin 210. The fin 210 may include an alloy semiconductor, the alloy semiconductor including silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, gallium indium arsenide phosphide, aluminum indium arsenide and / or aluminum gallium arsenide, and the fin 210 may include an elemental semiconductor, such as silicon or germanium. In some embodiments, the fin 210 and the semiconductor substrate 200 may be integrated, for example, the fin 210 is a protruding structure formed by etching the semiconductor substrate 200. The fin 210 includes a first fin portion 211 and a second fin portion 212.

[0031] An isolation structure 230 is also formed on the semiconductor substrate 200, the fin 210 higher than the isolation structure 230 is the fin first part 211, and the fin 210 located in the isolation structure 230 is the fin second part 212. The isolation structure 230 is used to isolate adjacent active areas. The isolation structure 230 can be made of a dielectric material. In some embodiments of the present application, the material of the isolation structure 230 may include silicon oxide, silicon nitride, silicon oxynitride and / or other suitable insulating materials. In some embodiments of the present application, the isolation structure 230 may include a multilayer structure.

[0032] A gate structure 220 is also formed on the semiconductor substrate 200. The gate structure 220 spans the first fin portion 211 and covers a portion of the top and sidewalls of the first fin portion 211. The surface of the portion of the top and sidewalls of the first fin portion 211 covered by the gate structure 220 is a channel 213 of the device (see Figure 6 Cross-section Figure 6 a) The gate structure 220 includes a gate dielectric layer 221 covering the sidewalls and the top of the first fin portion 211 and a gate layer 222 located on a portion of the gate dielectric layer 221 .

[0033] In some embodiments, the material of the gate dielectric layer 221 includes silicon oxide, and the method for forming the gate dielectric layer 221 may be a thermal oxidation process. The material of the gate layer 222 includes polysilicon. The method for forming the gate layer 222 may be: forming a gate material layer on the isolation structure 230 and the gate dielectric layer 221; forming a patterned hard mask layer 240 on the gate material layer; etching the gate material layer using the patterned hard mask layer 240 as a mask to form the gate layer 222. For example, etching may be performed using a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the material of the hard mask layer 240 includes silicon nitride. The hard mask layer 240 may protect the gate layer 222 from being affected when the fin 210 is subsequently etched.

[0034] refer to Figure 3 and Figure 4 In some embodiments, the gate structure 220 further includes a sidewall 223, and the sidewall 223 is located on the sidewalls of the gate layer 222 and the hard mask layer 240. The method for forming the sidewall 223 may include: forming a sidewall material layer 223a on the sidewalls of the gate layer 222 and the hard mask layer 240, the top surface of the hard mask layer 240, and the surface of the gate dielectric layer 221. In some embodiments of the present application, the method for forming the sidewall material layer 223a includes a chemical vapor deposition process or a physical vapor deposition process. Then, the sidewall material layer 223a is etched to leave only the sidewall material layer 223a on the sidewalls of the gate layer 222 and the hard mask layer 240 to form the sidewall 223.

[0035] refer to Figure 5 The first fin portion 211 on both sides of the gate structure 220 is etched to form a groove 250. Before etching the first fin portion 211, the gate dielectric layer 221 on the top surface and sidewall of the first fin portion 211 is first etched away. Then, the first fin portion 211 on both sides of the gate structure 220 is etched by a dry etching process to expose the second fin portion 212 on both sides of the gate structure 220. In some embodiments, the etching gas of the dry etching process may include HBr, NF3, etc.

[0036] refer to Figure 6 , and then an anisotropic wet etching process or an anisotropic dry process (such as low bias voltage / high temperature plasma) is used to continue etching part of the second fin part 212 and the first fin part 211 covered by the gate structure 220 to form a groove 250. Since the wet etching process used in the embodiment of the present application is anisotropic, the etching rate of the silicon <111> crystal plane is much lower than the etching rate of the <100> crystal plane. Therefore, the width of the bottom surface of the groove 250 can be controlled by controlling the temperature and time during etching, and the shape of the connection surface 250a between the groove 250 and the first fin part 211 can be controlled. In some embodiments, the etching solvent may include HCL, HF, TMAH, HNO3, etc., which can make the shape of the connection surface 250a between the groove 250 and the first fin part 211 V-shaped.

[0037] In the embodiment of the present application, the groove 250 is formed to extend along the fin 210 in the direction A in the figure, and the depth of the groove 250 extending to the gate structure 220 is greater than 0 and less than or equal to the thickness of the sidewall 223. The deeper the groove 250 extends to the gate structure 220, the closer the source or drain formed is to the channel 213, which improves the device performance and is more likely to generate parasitic capacitance and leakage current. In some embodiments, the depth of the groove 250 extending to the gate structure 220 can be 2nm to 10nm.

[0038] refer to Figure 1 , the top surface width of the groove 140 formed in the semiconductor structure is equal to the bottom surface width and equal to the width of the fin 110, and the connection surface between the groove 140 and the first part 111 of the fin is similar to a rectangle. However, the bottom surface width of the groove 250 in the embodiment of the present application is less than the width of the fin 210, and the top surface width of the groove 250 is equal to the width of the fin 210. For example, the connection surface 250a between the groove 250 and the first part 211 of the fin can be V-shaped, U-shaped or trapezoidal, etc. Obviously, the average distance between the source or drain formed in the V-shaped, U-shaped or trapezoidal groove and the channel 213 is greater than the average distance between the source or drain formed in the rectangular groove and the channel. Therefore, the groove 250 in the embodiment of the present application can reduce parasitic capacitance and leakage current without affecting the device performance as much as possible, thereby improving the reliability of the device.

[0039] refer to Figure 6 The cross section obtained along plane P1 Figure 6 a, the depth of the groove 250 extending to the gate structure 220 is equal to the thickness of the side wall 223, and the connection surface 250a of the groove 250 and the first part 211 of the fin is V-shaped, then the source or drain formed by growing an epitaxial layer in the groove 250 in the subsequent process is also V-shaped, the source or drain located at the vertex of the V-shape contacts the channel 213, and there is a certain distance t between the source or drain in the remaining part of the V-shape and the channel 213, so the V-shaped groove can increase the average distance between the source or drain and the channel 213, and can reduce parasitic capacitance and leakage current without affecting the device performance as much as possible, thereby improving the reliability of the device.

[0040] refer to Figure 7In some embodiments, the depth of the groove 250 extending to the gate structure 220 is equal to the thickness of the sidewall 223, and the connection surface 250a between the groove 250 and the first fin portion 211 is U-shaped. The U-shaped groove is similar to the V-shaped groove. The source or drain at the apex of the U-shape contacts the channel 213, which can ensure that the device has good performance. There is a certain distance t between the source or drain of the remaining part and the channel 213. Therefore, the U-shaped groove can also increase the average distance between the source or drain and the channel 213 without affecting the device performance as much as possible, reduce parasitic capacitance and leakage current, and improve the reliability of the device.

[0041] refer to Figure 8 In some embodiments, the depth of the groove 250 extending to the gate structure is equal to the thickness of the sidewall 223, and the connection surface 250a between the groove 250 and the first fin portion 211 is trapezoidal. Unlike the V-shaped groove and the U-shaped groove, the bottom surface of the trapezoidal groove contacts the channel 213. Compared with the V-shaped groove and the U-shaped groove, the contact area of ​​the trapezoidal groove with the channel 213 is larger. Therefore, the ability of the trapezoidal groove to reduce parasitic capacitance and leakage current is slightly weaker than that of the V-shaped groove and the U-shaped groove, but the ability of the trapezoidal groove to reduce parasitic capacitance and leakage current is stronger than that of the rectangular groove in the prior art.

[0042] Figures 6 to 8 The depth of the groove 250 shown extending to the gate structure 220 is equal to the thickness of the side wall 223. In other embodiments, the depth of the groove 250 extending to the gate structure 220 may also be less than the thickness of the side wall 223. The specific extension depth can be designed according to actual conditions.

[0043] refer to Figure 6 The cross section along plane Q Figure 6 b, the groove 250 extends to the second fin portion 212 along a direction perpendicular to the semiconductor substrate 200, and the depth of the groove 250 extending to the second fin portion 212 along a direction perpendicular to the semiconductor substrate 200 can be set according to actual conditions, for example, the depth of the groove 250 extending to the second fin portion 212 along a direction perpendicular to the semiconductor substrate 200 can be 2nm to 10nm. The shape of the connection surface 250b between the groove 250 and the second fin portion 212 can be the same as the shape of the connection surface 250a between the groove 250 and the first fin portion, for example, it can be v-shaped, U-shaped or trapezoidal.

[0044] The following takes the connection surfaces 250 a and 250 b being both V-shaped as an example to illustrate the formation process of the epitaxial layer.

[0045] refer to Fig. 9An epitaxial layer 260 is grown in the trench 250 . The epitaxial layer 260 fills the groove 250 . The epitaxial layer 260 is used as a source or a drain in the semiconductor structure.

[0046] The epitaxial layer 260 may include an epitaxially grown semiconductor material. In some embodiments of the present application, the epitaxially grown semiconductor material is the same material as the material of the semiconductor substrate 200. In other embodiments of the present application, the epitaxially grown semiconductor material may include a material different from the material of the semiconductor substrate 200. The epitaxially grown semiconductor material may include: (i) a semiconductor material, such as germanium or silicon; (ii) a compound semiconductor material, such as silicon phosphide or silicon carbon phosphide; or (iii) a semiconductor alloy, such as silicon germanium or gallium arsenic phosphide.

[0047] In some embodiments of the present application, for example, the epitaxial layer 260 can be grown by (i) chemical vapor deposition (CVD), such as low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD) or any suitable CVD; (ii) molecular beam epitaxy (MBE) process; (iii) any suitable epitaxial process; or (iv) a combination of the above.

[0048] In some embodiments of the present application, the epitaxial layer 260 may be P-type or N-type. In some embodiments of the present application, for example, the P-type epitaxial layer 260 may include SiGe and may be in-situ doped using a P-type dopant (e.g., boron, indium, or gallium) during the epitaxial growth process. For P-type in-situ doping, a P-type doping precursor may be used, including but not limited to diborane (B2H6), boron trifluoride (BF3), and / or other P-type doping precursors. In some embodiments of the present application, for example, the N-type epitaxial layer 260 may include Si and may be in-situ doped using an N-type dopant (e.g., phosphorus or arsenic) during the epitaxial growth process. For N-type in-situ doping, an N-type doping precursor may be used, including but not limited to phosphine (PH3), arsine (AsH3), and / or other N-type doping precursors.

[0049] The semiconductor formation method of the embodiment of the present application forms a groove 250 in the first part 211 of the fin on both sides of the gate structure 220 through two-step etching. The width of the bottom surface of the groove 250 is smaller than the width of the fin. While ensuring that the device performance is not affected as much as possible, the average distance between the source or drain and the channel is increased, the parasitic capacitance and leakage current are reduced, and the reliability of the device is improved.

[0050] Reference Figure 6The embodiment of the present application also provides a semiconductor structure, which includes: a semiconductor substrate 200, on which a fin 210 is formed, and the fin 210 includes a first fin portion 211; a gate structure 220, wherein the gate structure 220 spans the first fin portion 211 and covers the top and side walls of the first fin portion 211, and grooves 250 are formed in the first fin portion 211 on both sides of the gate structure 220, and the width of the bottom surface of the groove 250 is smaller than the width of the fin 210.

[0051] In some embodiments, the material of the semiconductor substrate 200 includes (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, etc.; or (iv) a combination of the above. In addition, the semiconductor substrate 200 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 200 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0052] In some embodiments, a connection surface 250 a between the groove 250 and the first fin portion 211 is V-shaped, U-shaped, or trapezoidal.

[0053] In some embodiments, the gate structure 220 includes a gate dielectric layer 221 covering the sidewalls and top of the first portion 211 of the fin and a gate layer 222 located on a portion of the gate dielectric layer 221, wherein the material of the gate dielectric layer 221 includes silicon oxide, the material of the gate layer 222 includes polycrystalline silicon, and a hard mask layer 240 is also formed on the gate layer 222, wherein the material of the hard mask layer 240 includes silicon nitride.

[0054] In some embodiments, the gate structure 220 further includes a sidewall spacer 223 , and the sidewall spacer 223 is located on the sidewalls of the gate layer 222 and the hard mask layer 240 . The depth of the groove 250 extending to the gate structure 220 is greater than 0 and less than or equal to the thickness of the sidewall spacer 223 .

[0055] In some embodiments, the fin 210 further includes a fin second portion 212 , and the groove 250 extends to the fin second portion 212 along a direction perpendicular to the semiconductor substrate.

[0056] In some embodiments, the connection surface 250 b and the connection surface 250 a of the groove 250 and the second fin portion 212 have the same shape, for example, may be V-shaped, U-shaped, or trapezoidal.

[0057] In some embodiments, the semiconductor further includes an isolation structure 230, the isolation structure 230 being located on the sidewall of the second fin portion 212, and the isolation structure 230 being used to isolate adjacent active regions. The isolation structure 230 may be made of a dielectric material. In some embodiments of the present application, the material of the isolation structure 230 may include silicon oxide, silicon nitride, silicon oxynitride, and / or other suitable insulating materials. In some embodiments of the present application, the isolation structure 230 may include a multilayer structure.

[0058] refer to Fig. 9 In some embodiments, the semiconductor structure further includes an epitaxial layer 260, and the epitaxial layer 260 fills the groove 250. The epitaxial layer 260 may include an epitaxially grown semiconductor material. The epitaxially grown semiconductor material may be the same material as the semiconductor substrate 200, or may include a material different from the material of the semiconductor substrate 200. For example, the epitaxially grown semiconductor material may include: (i) a semiconductor material, such as germanium or silicon; (ii) a compound semiconductor material, such as silicon phosphide or silicon carbon phosphide; or (iii) a semiconductor alloy, such as silicon germanium or gallium arsenic phosphide.

[0059] In some embodiments, the epitaxial layer 260 may be P-type or N-type. In some embodiments, for example, the P-type epitaxial layer 260 may include SiGe and may be in-situ doped using a P-type dopant (e.g., boron, indium, or gallium) during the epitaxial growth process. For P-type in-situ doping, a P-type doping precursor may be used, including but not limited to diborane (B2H6), boron trifluoride (BF3), and / or other P-type doping precursors. In some embodiments, for example, the N-type epitaxial layer 260 may include Si and may be in-situ doped using an N-type dopant (e.g., phosphorus or arsenic) during the epitaxial growth process. For N-type in-situ doping, an N-type doping precursor may be used, including but not limited to phosphine (PH3), arsine (AsH3), and / or other N-type doping precursors.

[0060] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0061] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements.

[0062] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0063] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0064] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, characterized in that: include: A semiconductor substrate, on which a fin and an isolation structure are formed, wherein the fin comprises a first fin portion and a second fin portion, wherein the second fin portion is located in the isolation structure, and the second fin portion is flush with a top surface of the isolation structure; A gate structure, the gate structure spans the first part of the fin and covers a portion of the top and side walls of the first part of the fin, grooves are formed in the first part of the fin on both sides of the gate structure, the grooves extend to the second part of the fin along a direction perpendicular to the semiconductor substrate, the grooves extend toward the gate structure along the extension direction of the fin, along the extension direction of the grooves, the width of the top surface of the grooves is equal to the width of the fin, and the width of the bottom surface of the grooves is less than the width of the fin.

2. The semiconductor structure according to claim 1, characterized in that: The connection surface between the groove and the first part of the fin is V-shaped, U-shaped or trapezoidal.

3. The semiconductor structure according to claim 1, characterized in that: The gate structure includes a sidewall spacer, and the depth of the groove extending to the gate structure is greater than 0 and less than or equal to the thickness of the sidewall spacer.

4. The semiconductor structure according to claim 1, characterized in that The connection surface between the groove and the second portion of the fin is V-shaped, U-shaped or trapezoidal.

5. The semiconductor structure according to claim 4, characterized in that: An epitaxial layer is also included, and the epitaxial layer fills the groove.

6. A method for forming a semiconductor structure, characterized in that: include: A semiconductor substrate is provided, on which a fin, a gate structure and an isolation structure are formed, wherein the fin comprises a first fin portion, the gate structure spans the first fin portion and covers a portion of the top and sidewalls of the first fin portion; the second fin portion is located in the isolation structure, and the second fin portion is flush with a top surface of the isolation structure; The first part of the fin on both sides of the gate structure is etched to form a groove, wherein the groove extends to the second part of the fin in a direction perpendicular to the semiconductor substrate, and the groove extends toward the gate structure along the extension direction of the fin. Along the extension direction of the groove, the width of the top surface of the groove is equal to the width of the fin, and the width of the bottom surface of the groove is less than the width of the fin.

7. The method for forming a semiconductor structure according to claim 6, wherein: The gate structure includes a sidewall spacer, and the depth of the groove extending to the gate structure is greater than 0 and less than or equal to the thickness of the sidewall spacer.

8. The method for forming a semiconductor structure according to claim 7, characterized in that: The process of forming the groove includes: Etching the first part of the fin on both sides of the gate structure by a dry etching process to expose the second part of the fin on both sides of the gate structure; An anisotropic wet etching process or an anisotropic dry etching process is used to continue etching part of the second part of the fin and the first part of the fin covered by the gate structure to form a groove, which extends to the second part of the fin in a direction perpendicular to the semiconductor substrate, and the groove extends to under the gate structure along the extension direction of the fin.

9. The method for forming a semiconductor structure according to claim 8, characterized in that: The method further includes growing an epitaxial layer in the groove, wherein the epitaxial layer fills the groove.

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