Display device and image display system including the same

Abstract

A display device and an image display system including the same are provided. The image display system includes: a graphics processor that supplies image signals, control signals, and variable frequency signals to the display device; and the display device that displays an image at a frame rate corresponding to the variable frequency signals. The display device includes: a plurality of pixels connected to each light emission control line, each data line, and each scan line; a control unit that provides the graphics processor with reference data including information of a plurality of reference periods as the period of an output light emission control start signal, outputs a light emission control start signal based on the control signals, and adjusts the output timing of a scan start signal based on the variable frequency signals; a light emission driving unit that supplies light emission control signals to the light emission control lines based on the light emission control start signal; and a scan driving unit that supplies scan signals to the scan lines based on the scan start signal.

Description

Technical Field

[0001] This invention relates to image display systems and electronic devices, and more specifically to display devices and image display systems including the same. Background Technology

[0002] The display device includes a pixel unit having multiple pixels and a driving unit for driving the pixel unit. The driving unit displays an image on the display unit using an image signal applied from an external graphics processor.

[0003] The graphics processor (GPU) renders the raw data to generate an image signal. The rendering time for generating the image signal corresponding to one frame is variable depending on the type or characteristics of the image. The driver unit can change the frame rate in accordance with the rendering time.

[0004] However, if the output of the illumination control signal based on the drawing time and frame rate is inconsistent, flickering may be detected when the frame rate changes. To prevent the detection of such flickering, the number of applicable frame rates is reduced when the drawing time is synchronized with the output of the illumination control signal. Summary of the Invention

[0005] One object of the present invention is to provide a display device that outputs light emission control signals and scanning signals at various frame rates synchronized with the input frequency of the image signal.

[0006] Another object of the present invention is to provide a graphics processor that outputs an image signal at a drawing speed corresponding to the available frame rate of the display device, and an image display system for the display device.

[0007] However, the purpose of this invention is not limited to the above-described purpose, and various extensions can be made without departing from the spirit and scope of this invention.

[0008] To achieve an objective of the present invention, the image display system according to various embodiments of the present invention may include: a graphics processor that supplies image signals, control signals, and variable frequency signals to a display device; and the display device that displays an image at a frame rate corresponding to the variable frequency signals. The display device may include: a plurality of pixels connected to each light emission control line, each data line, and each scan line; a control unit that provides the graphics processor with reference data including information on a plurality of reference periods as the period for outputting a light emission control start signal, outputs the light emission control start signal based on the control signals, and adjusts the output timing of the scan start signal based on the variable frequency signals; a light emission driving unit that supplies light emission control signals to the light emission control lines based on the light emission control start signal; and a scan driving unit that supplies scan signals to the scan lines based on the scan start signal.

[0009] According to one embodiment, the control signal may include a data gating signal that divides the active period and the blank period of the supplied image signal within a frame.

[0010] According to one embodiment, the blank period may be an integer multiple of a selected reference period among a plurality of reference periods. Alternatively, the control signal may be determined based on a selected reference period among the plurality of reference periods.

[0011] According to one embodiment, the length of a frame may be an integer multiple of a selected reference period among a plurality of reference periods.

[0012] According to one embodiment, the control unit may include: a receiving unit for restoring a vertical synchronization signal based on the variable frequency signal; a memory for storing the reference data; and a control signal generation unit for selecting an effective period that conforms to the frame frequency from a plurality of reference periods based on the data gating signal, and outputting the light emission control start signal with the effective period.

[0013] According to one embodiment, the effective period may be p times the length of the effective period (where p is a positive integer), and the blank period may be q times the length of the effective period (where q is an integer greater than or equal to 0).

[0014] According to one embodiment, the control signal generation unit may output the scan start signal in correspondence with the vertical synchronization signal.

[0015] According to one embodiment, the vertical synchronization signal and the scan start signal may be output in accordance with the frame rate.

[0016] According to one embodiment, the graphics processor may control the rendering speed of the image signal based on the reference data.

[0017] According to one embodiment, the graphics processor may select one of a plurality of reference periods and generate the control signal and the variable frequency signal based on the selected reference period. Alternatively, the output frequency of the emission control signal may be an integer multiple of the frame rate determined by the variable frequency signal.

[0018] According to one embodiment, the control signal may include information about the effective period and the blank period.

[0019] According to one embodiment, the control signal generation unit may detect the blank period and determine the reference period corresponding to 1 / r of the detected blank period (where r is a positive integer) as the effective period.

[0020] According to one embodiment, the control signal generation unit may change the effective period of the light emission control start signal based on the change in the variable frequency signal and the frame frequency.

[0021] According to one embodiment, if there is no blank period in the current frame, the control signal generation unit outputs the light emission control start signal with the effective period of the light emission control start signal output in the previous frame.

[0022] According to one embodiment, when the frame rate is the same, the number of light emission control start signals supplied within one frame may vary depending on the reference period.

[0023] According to one embodiment, the control unit may further include an image data generation unit, which rearranges the image signal and outputs image data corresponding to the frame rate.

[0024] According to one embodiment, the display device may further include: a data driving unit that converts the image data into an analog data signal and supplies the data signal to the data line.

[0025] To achieve an objective of the present invention, the display device according to various embodiments of the present invention may include: a plurality of pixels connected to each light emission control line, each data line and each scan line, and displaying an image at a frame rate corresponding to a variable frequency signal based on a data gating signal; a control unit that selects an effective period from a plurality of reference periods that serve as the period for outputting a light emission control start signal based on the data gating signal, outputs the light emission control start signal at the effective period, and adjusts the output timing of the scan start signal based on the variable frequency signal; a light emission driving unit that supplies a light emission control signal to the light emission control line based on the light emission control start signal; and a scan driving unit that supplies a scan signal to the scan line based on the scan start signal.

[0026] According to one embodiment, the data strobe signal may include an effective period for supplying the image signal and a blank period within a frame, wherein the effective period is p times the length of the effective period (where p is a positive integer) and the blank period is q times the length of the effective period (where q is an integer greater than or equal to 0).

[0027] (Invention Effects)

[0028] In the display device and image display system including the present invention, according to various embodiments, the display device includes information on multiple reference cycles, and the input frequency of the image signal supplied from the graphics processor to the display device can be limited to be selected from values ​​corresponding to each reference cycle. Therefore, the input frequency supplied to the display device (i.e., the rendering speed of the graphics processor) can be completely synchronized with the output cycle (i.e., the frame rate) of the light emission control signal (light emission control start signal) and the scan signal, which can reduce and / or prevent flickering caused by changes in light emission time during frame rate switching from being detected.

[0029] Furthermore, by pre-setting various reference cycles, the frame rate that the control unit of the display device can respond to when flicker-free operation is detected can be further increased, thus expanding the versatility of the control unit applicable to the display device.

[0030] However, the effects of the present invention are not limited to those described above, and various extensions can be made without departing from the spirit and scope of the present invention. Attached Figure Description

[0031] Figure 1 This is a block diagram illustrating the image display system involved in various embodiments of the present invention.

[0032] Figure 2 It means Figure 1 A circuit diagram of an example of pixels included in the display device of an image display system.

[0033] Figure 3 It means to Figure 2 A timing diagram of an example of the signal supplied by the pixels.

[0034] Figure 4 It means Figure 1 A block diagram of an example of the control unit included in the display device of a graphics processor and image display system.

[0035] Figure 5 It means Figure 4 A timing diagram illustrating an example of the operation of the control unit.

[0036] Figure 6 It means Figure 4 A timing diagram of another example of the operation of the control unit.

[0037] Figure 7 It means Figure 4 A timing diagram illustrating another example of the operation of the control unit.

[0038] Figure 8 It is used for explanation Figure 1 The image display system is illustrated in the figure, which shows an example of a frame rate applicable to the display device.

[0039] Figure 9 It means Figure 1 The image shows a timing diagram of an example of the system's operation. Detailed Implementation

[0040] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and repeated descriptions of the same constituent elements are omitted.

[0041] Figure 1 This is a block diagram illustrating the image display system involved in various embodiments of the present invention.

[0042] Reference Figure 1 The image display system 1 may include a display device 1000 and a graphics processor 2000.

[0043] The graphics processor 2000 can supply the display device 1000 with image signals RGB, control signals CTL, and frequency-modulated signals Fsync. The graphics processor 2000 can process raw data through methods such as rendering to generate image signals RGB and control signals CTL that control the display of image signals RGB.

[0044] The image signal RGB may include grayscale information having brightness information for each pixel PX. Furthermore, the image signal RGB may be supplied from the graphics processor 2000 to the control unit 500 of the display device 1000 at a predetermined input frequency.

[0045] The control signal CTL can include a data strobe signal. The data strobe signal can be divided within a frame into an active period and a blank period for supplying the image signal RGB or image data DAT. Additionally, the control signal CTL can include information about the vertical synchronization signal and the horizontal synchronization signal. The timing of the vertical and horizontal synchronization signals can vary correspondingly to the variable frequency signal Fsync. The vertical synchronization signal divides the image signal RGB in frames, and the horizontal synchronization signal divides the image signal RGB in horizontal lines (pixel rows).

[0046] In one embodiment, the control signal CTL may also include information related to the length of the blank period.

[0047] The variable frequency signal Fsync is a signal indicating that the frame rate of the image signal RGB and the control signal CTL provided from the graphics processor 2000 to the display device 1000 can be changed every other frame. The frame rate of the image signal RGB and the control signal CTL can vary depending on the rendering speed of the graphics processor 2000. For example, the time required to process the raw data corresponding to one frame to generate and supply the image signal RGB is variable.

[0048] In one embodiment, the graphics processor 2000 can control the rendering speed of the RGB image signal based on reference data RD supplied from the display device 1000. The reference data RD can include information on multiple reference periods, where the reference period is the period at which the emission control start signal EFLM is output. For example, the reference period of the emission control start signal EFLM can be set to 480Hz (output approximately every 2.08ms), 600Hz (output approximately every 1.67ms), etc. However, this is just an example; the reference data RD can also include reference periods suitable for various spectra applicable to the display device 1000.

[0049] The graphics processor 2000 can select one of a plurality of reference periods and generate the control signal CTL and the variable frequency signal Fsync based on the selected reference period. For example, when a reference period of 480 Hz (or 2.08 ms) is selected, the duration of the data strobe signal supplied to the control signal CTL and the duration of a frame can be determined to be an integer multiple of 2.08 ms.

[0050] The display device 1000 may include a pixel unit 100, a scan driving unit 200, a light-emitting driving unit 300, a data driving unit 400, and a control unit 500.

[0051] The pixel unit 100 may include scan lines S11 to S1n, S21 to S2n, S31 to S3n, light emission control lines E1 to En, and data lines D1 to Dm, and includes a plurality of pixels PX (where m and n are integers greater than 1) connected to the scan lines S11 to S1n, S21 to S2n, S31 to S3n, light emission control lines E1 to En, and data lines D1 to Dm. Each pixel PX may include a driving transistor and a plurality of switching transistors.

[0052] The control unit 500 can generate a data drive control signal DCS, a light emission control start signal EFLM, a first scan start signal SFLM1, and a second scan start signal SFLM2 based on the control signal CTL and the variable frequency signal Fsync. The light emission control start signal EFLM can be supplied to the light emission drive unit 300, the first scan start signal SFLM1 and the second scan start signal SFLM2 can be supplied to the scan drive unit 200, and the data drive control signal DCS can be supplied to the data drive unit 400.

[0053] In one embodiment, the first scan start signal SFLM1 can control the first scan signal supplied to the first scan lines S11 to S1n and the second scan signal supplied to the second scan lines S21 to S2n, and the second scan start signal SFLM2 can control the third scan signal supplied to the third scan lines S31 to S3n. However, this is an example, and the second scan signal can be controlled by a control signal different from the first scan start signal SFLM1.

[0054] In one embodiment, the control unit 500 can provide the graphics processor 2000 with reference data RD including information about a reference period, and can output an illumination control start signal EFLM based on the data strobe signal included in the control signal CTL. That is, the control unit 500 can adjust the output timing of the illumination control start signal EFLM based on the data strobe signal.

[0055] In one embodiment, the control unit 500 may supply a second scan start signal SFLM2 to the scan drive unit 200 at the same period as the light emission control start signal EFLM.

[0056] The control unit 500 can adjust the output timing of the first scan start signal SFLM1 based on the variable frequency signal Fsync and the vertical synchronization signal. For example, the first scan start signal SFLM1 can control the first scan signal that controls the data writing time of pixel PX, and can be supplied once per frame. In addition, the first scan start signal SFLM1 can control the second scan signal so that the second scan signal is output with the same period as the first scan signal.

[0057] The control unit 500 can convert the image signal RGB into a form suitable for driving the display device 1000, and rearrange it to generate image data DAT. The image data DAT can be supplied to the data driving unit 400.

[0058] The scan drive unit 200 can receive a first scan start signal SFLM1 from the control unit 500, and based on the first scan start signal SFLM1, supply a first scan signal and a second scan signal to the first scan lines S11 to S1n and the second scan lines S21 to S2n, respectively. In addition, the scan drive unit 200 can supply a third scan signal to the third scan lines S31 to S3n based on the second scan start signal SFLM2.

[0059] The first to third scan signals can be set to a gate on-state voltage (e.g., a low voltage). The transistor receiving the scan signal can be set to the on state when the scan signal is supplied.

[0060] The scanning drive unit 200 can be mounted onto the substrate through a thin film process. Figure 1The illustration shows a case where a scan drive unit supplies a first scan signal to a third scan signal, but the invention is not limited thereto. As an example, the scan drive unit 200 may include a plurality of scan drive units that respectively supply at least one of the first scan signal to the third scan signal.

[0061] The light-emitting driving unit 300 can supply light-emitting control signals to the light-emitting control lines E1 to En based on the light-emitting control start signal EFLM. For example, the light-emitting control signals can be supplied to the light-emitting control lines E1 to En in sequence.

[0062] The light emission control signal can be set to a gate cutoff voltage (e.g., a high voltage). The transistor receiving the light emission control signal can be set to the cutoff state when the light emission control signal is supplied, and to the on state under other conditions.

[0063] The data drive unit 400 can receive a data drive control signal DCS and image data DAT from the control unit 500. The data drive unit 400 can convert the digital image data DAT into an analog data signal. The data drive unit 400 can supply data signals (data voltages) to the data lines D1 to Dm in accordance with the data drive control signal DCS.

[0064] The image display system 1 according to various embodiments of the present invention can generate a variable frequency signal Fsync and a control signal CTL by a graphics processor 2000 based on reference data RD generated by a control unit 500. Furthermore, the control unit 500 can control the output cycles of the light emission control start signal EFLM, the first scan start signal SFLM1, and the second scan start signal SFLM2 based on the variable frequency signal Fsync and the control signal CTL. Therefore, the frequency supplied to the image signal RGB can be completely synchronized with the output cycles of the light emission control signal and the scan signal, thus preventing and / or reducing flicker during frame rate changes.

[0065] Figure 2 It means Figure 1 A circuit diagram of an example of pixels included in the display device of an image display system.

[0066] exist Figure 2 For ease of explanation, pixel 10, located on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj, is shown (where i and j are natural numbers).

[0067] Reference Figure 1 and Figure 2 Pixel 10 may include a light-emitting element LD, a first transistor T1 to a seventh transistor T7, and an energy storage capacitor Cst.

[0068] The first electrode (anode or cathode) of the light-emitting element LD is connected to the sixth transistor T6, and the second electrode (cathode or anode) is connected to the second power supply VSS. The light-emitting element LD generates light of a predetermined brightness in accordance with the amount of current supplied from the first transistor T1.

[0069] In one embodiment, the light-emitting element LD can be an organic light-emitting diode including an organic light-emitting layer. In other embodiments, the light-emitting element LD can be an inorganic light-emitting element formed of inorganic materials. In other embodiments, the light-emitting element LD can also be a light-emitting element composed of a composite of inorganic and organic materials. Alternatively, the light-emitting element LD can also have a configuration in which multiple inorganic light-emitting elements are connected in parallel and / or in series between the second power supply VSS and the sixth transistor T6.

[0070] The first transistor T1 (or driving transistor) can be connected between the second node N2 and the third node N3. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of current (driving current) flowing from the first power supply VDD through the light-emitting element LD to the second power supply VSS based on the voltage of the first node N1. For this purpose, the first power supply VDD can be set to a higher voltage than the second power supply VSS.

[0071] The second transistor T2 can be connected between the j-th data line Dj (hereinafter referred to as the data line) and the second node N2. The gate electrode of the second transistor T2 can be connected to the i-th first scan line S1i (hereinafter referred to as the first scan line). The second transistor T2 can be turned on when a first scan signal is supplied to the first scan line S1i, thereby electrically connecting the data line Dj and the second node N2.

[0072] The third transistor T3 can be connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 can be connected to the first scan line S1i. The third transistor T3 can be turned on together with the second transistor T2.

[0073] The fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 can be connected to the i-th second scan line S2i (hereinafter referred to as the second scan line). The fourth transistor T4 can be turned on when the second scan signal is supplied to the second scan line S2i, thereby supplying the voltage of the initialization power supply Vint to the first node N1.

[0074] The fifth transistor T5 can be connected between the first power supply VDD and the second node N2. The gate electrode of the fifth transistor T5 can be connected to the light-emitting control line Ei. The sixth transistor T6 can be connected between the third node N3 and the light-emitting element LD. The gate electrode of the sixth transistor T6 can be connected to the light-emitting control line Ei. The fifth transistor T5 and the sixth transistor T6 can be turned off when a light-emitting control signal is supplied to the light-emitting control line Ei, and can be turned on under other conditions.

[0075] The seventh transistor T7 can be connected between the first electrode of the light-emitting element LD and the initialization power supply Vint. The gate electrode of the seventh transistor T7 can be connected to the i-th third scan line S3i (hereinafter referred to as the third scan line). The seventh transistor T7 can be turned on by the third scan signal supplied to the third scan line S3i, and can supply the voltage of the initialization power supply Vint to the first electrode of the light-emitting element LD.

[0076] The energy storage capacitor Cst can be connected between the first power supply VDD and the first node N1.

[0077] Figure 3 It means to Figure 2 A timing diagram of an example of the signal supplied by the pixels.

[0078] Reference Figures 1 to 3 The display device 1000 can supply multiple light emission control signals to the light emission control line Ei connected to the pixel 10 within one frame 1F.

[0079] In one embodiment, with a frame rate of 120Hz, one frame 1F can be approximately 8.33ms, and four emission control signals can be supplied during one frame 1F. For example, one emission control signal can be supplied during the first period P1, and three emission control signals can be supplied during the second period P2. The third scan signal supplied to the third scan line S3i can be supplied to pixel 10 with the same period as the emission control signal. Therefore, the emission control signal and the third scan signal can be supplied to pixel 10 at 480Hz. That is, Figure 3 The effective period C1 (or the first reference period) of the supply cycle for the light emission control signal can be approximately 2.08 ms, which corresponds to 1 / 4 of 8.33 ms.

[0080] The first scan signal supplied to the first scan line S1i and the second scan signal supplied to the second scan line S2i can be supplied only during the first period P1. The first scan signal and the second scan signal can be supplied to the pixel 10 at 120Hz.

[0081] The period during which the light emission control signal is low (the period during which the light emission control signal is not supplied) can be a light emission period, and the period outside the light emission period can be a non-light emission period.

[0082] During the first period P1, during the non-light-emitting period when the light-emitting control signal is supplied, the second scan signal, the first scan signal, and the third scan signal can be sequentially supplied to the second scan line S2i, the first scan line S1i, and the third scan line S3i, respectively.

[0083] First, in response to the second scan signal, the fourth transistor T4 can be turned on. With the fourth transistor T4 turned on, the voltage of the first node N1 is initialized.

[0084] Then, in response to the first scan signal, the second transistor T2 and the third transistor T3 can be turned on. With the second transistor T2 and the third transistor T3 turned on, a data signal is written to pixel 10, and the first transistor T1 can be connected in a diode configuration. Thus, data writing and threshold voltage compensation can be performed.

[0085] Then, in response to the third scan signal, the seventh transistor T7 can be turned on. By turning on the seventh transistor T7, the voltage of the first electrode of the light-emitting element LD can be initialized.

[0086] Then, the supply of the light emission control signal can be interrupted, and the fifth transistor T5 and the sixth transistor T6 are turned on, so that pixel 10 emits light.

[0087] During the second period P2, a light emission control signal and a third scan signal can be periodically supplied to pixel 10. Pixel 10 can display an image corresponding to the data signal supplied during the first period P1 within one frame 1F.

[0088] based on Figure 3 The driving method of the pixels in the timing diagram can correspond to various frame rates. That is, by adjusting the number of light emission control signals supplied within a frame 1F, synchronization of the frame rate, light emission control signals, and scan signals corresponding to integer multiples of the effective period C1 can be achieved. For example, according to Figure 3 In the timing diagram, when the rendering speed of the graphics processor 2000 corresponds to frame rates such as 30Hz, 40Hz, 60Hz, and 120Hz, the input time of the image signal RGB input to the control unit 500 and the output period of the light emission control signal (and scan signal) of the driving pixel unit 100 can be consistent.

[0089] However, if the rendering time and frame rate of the graphics processor 2000 are not integer multiples of the effective period C1, inconsistencies may occur between the input time of the RGB image signal and the output period of the illumination control signal. For example, when the frame rate changes from 120Hz to 51Hz according to the variable frequency signal Fsync, brightness changes may occur due to the difference in the length of the illumination period before and after the frame rate change (i.e., the length of the period during which the illumination control signal is not supplied), which may result in flickering.

[0090] In the display device 1000 and image display system 1 including the present invention, according to various embodiments, the control unit 500 includes information on multiple reference periods. The input frequency of the image signal RGB supplied from the graphics processor 2000 to the display device 1000 can be limited to a value corresponding to the reference period. Therefore, the input frequency of the image signal RGB received from the graphics processor 2000 (e.g., the period of the data strobe signal or the drawing speed of the graphics processor 2000) can be completely synchronized with the output periods of the light emission control signal (light emission control start signal EFLM) and the scan signal, thereby reducing and preventing flickering during frame rate changes from being detected.

[0091] Figure 4 It means Figure 1 A block diagram of an example of the control unit included in the display device of a graphics processor and image display system.

[0092] Reference Figure 1 and Figure 4 The control unit 500 may include a receiving unit 520, a memory 540, a control signal generating unit 560, and an image data generating unit 580.

[0093] The receiver 520 can recover the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync from the control signal CTL based on the variable frequency signal Fsync. It can output the vertical synchronization signal Vsync at a period corresponding to the frame frequency.

[0094] Additionally, the receiving unit 520 can recover the data strobe signal DE from the control signal CTL. The receiving unit 520 can receive the image signal RGB and transmit it to the image data generation unit 580.

[0095] The memory 540 can store reference data RD. The reference data RD can include information about multiple reference cycles, where the reference cycle is the cycle of the output illumination control start signal EFLM. The memory 540 can provide the reference data RD to the graphics processor 2000. Additionally, in response to a selection signal SS supplied from the control signal generation unit 560, the valid cycle VP can be read from the memory 540.

[0096] In one embodiment, the memory 540 may be a non-volatile memory in which the stored information will not be lost even if the power supply is interrupted. For example, the memory may be implemented by EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), and flash memory.

[0097] The control signal generation unit 560 can select an effective period VP that conforms to the frame rate and the input frequency from multiple reference periods from the reference data RD based on the data strobe signal DE. The control signal generation unit 560 can supply a selection signal SS corresponding to the effective period VP to the memory 540, thereby reading out the data corresponding to the effective period VP.

[0098] The effective period VP can be determined based on the length of the data strobe signal DE and the length of the blank period of the data strobe signal DE. For example, the effective period of the data strobe signal DE can be p times the length of the effective period VP (where p is a positive integer), and the blank period of the data strobe signal DE can be q times the length of the effective period VP (where q is an integer greater than or equal to 0).

[0099] In one embodiment, the control signal CTL may further include metadata containing information about the blank period and the effective period VP. Thus, the control signal generation unit 560 can use this metadata to directly read the effective period VP from the memory 540.

[0100] In one embodiment, the control signal generation unit 560 can detect a blank period from the data strobe signal DE. The control signal generation unit 560 can determine the effective period VP as a reference period corresponding to 1 / r (where r is a positive integer) of the detected blank period. In this case, the control signal generation unit 560 may also include hardware and / or software configurations for detecting the blank period.

[0101] The control signal generation unit 560 can output a light emission control start signal EFLM with an effective period VP. The control signal generation unit 560 can also output a second scan start signal SFLM2 with an effective period VP. In addition, the control signal generation unit 560 can generate a first scan start signal SFLM1 corresponding to the period of the vertical synchronization signal Vsync.

[0102] In one embodiment, the control signal generation unit 560 can generate a data-driven control signal DCS based on the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync to generate the output timing of the control data signal.

[0103] The image data generation unit 580 can rearrange the image signal RGB' transmitted from the receiving unit 520 to output image data DAT corresponding to the frame rate.

[0104] Figure 5 It means Figure 4 A timing diagram illustrating an example of the operation of the control unit.

[0105] Reference Figures 2 to 5 The control unit 500 can output a light emission control start signal EFLM based on the data gating signal DE. Additionally, the control unit 500 can output a first scan start signal SFLM1 based on the vertical synchronization signal Vsync, which is restored from the variable frequency signal Fsync and the control signal CTL.

[0106] The data strobe signal DE may include an active period ACTIVE and blank periods BK1 and BK2. The active period ACTIVE may be the period during which the image signal RGB is supplied to the control unit 500 within a frame. During the blank periods BK1 and BK2, the image signal RGB is not supplied.

[0107] In one embodiment, the graphics processor 2000 can determine the first reference period C1 (approximately 2.08 ms, or 480 Hz) among a plurality of reference periods as the effective period VP. The graphics processor 2000 can determine the frequency corresponding to a time that is an integer multiple of the effective period VP as the frame rate, and depict the image signal RGB corresponding to the corresponding frame rate. For example, as... Figure 5 As shown, the frame rate can be freely selected from approximately 120Hz, approximately 96Hz, approximately 80Hz, etc., depending on the operation of the graphics processor 2000. The graphics processor 2000 can output a variable frequency signal Fsync and a data strobe signal DE, which include information about the vertical synchronization signal Vsync corresponding to the corresponding frame rate.

[0108] On the other hand, the values ​​recorded as reference periods, etc., in the accompanying drawings and detailed descriptions can be understood as approximate values ​​rounded to three decimal places.

[0109] In one embodiment, the control unit 500 may output a light emission control start signal EFLM based on the data gating signal DE and the variable frequency signal Fsync with an effective period VP. For example, the first reference period C1 may be selected as the effective period VP.

[0110] With a frame rate of approximately 120Hz, four emission control start signals EFLM (four-cycle drive) can be output within one frame.

[0111] At a frame rate of approximately 96Hz, five emission control start signals EFLM (five-cycle drive) can be output within one frame. At this time, the first blank period BK1 can be substantially the same as the first reference period C1.

[0112] With a frame rate of approximately 80Hz, six emission control start signals EFLM (six-cycle drive) can be output within one frame. At this time, the second blank period BK2 can be substantially the same as twice the first reference period C1.

[0113] On the other hand, when the effective period VP is the same, the effective period ACTIVE of the data strobe signal DE can all be the same. For example, when the first reference period C1 is the effective period VP, the effective period ACTIVE can be the same as the period of the output four-times emission control start signal EFLM.

[0114] As described above, when the effective period VP is determined to be the first reference period C1, the rendering time of the graphics processor 2000 (e.g., the effective period ACTIVE) is fixed to a predetermined time, and the blank periods BK1 and BK2 can be determined to be integer multiples of the first reference period C1. Therefore, the length of a frame can be consistent with an integer multiple of the first reference period C1.

[0115] As a result, during frame rate conversion based on the first reference period C1, the inputs of the data strobe signal DE and the image signal RGB can be fully synchronized with the output period of the light emission control start signal EFLM, thus preventing and / or reducing flicker during frame rate conversion.

[0116] Figure 6 It means Figure 4 A timing diagram of another example of the operation of the control unit. Figure 7 It means Figure 4 A timing diagram illustrating another example of the operation of the control unit.

[0117] Reference Figures 4 to 7 The control unit 500 can output a light emission control start signal EFLM based on the data strobe signal DE.

[0118] In one embodiment, such as Figure 6As shown, the effective period VP can be determined as the second period C2 (approximately 1.67 ms, or 600 Hz). The graphics processor 2000 can determine the frame rate as the frequency corresponding to a time that is an integer multiple of the effective period VP, and depict the image signal RGB accordingly. For example, the frame rate can be freely selected from approximately 120 Hz, approximately 100 Hz, approximately 85.71 Hz, etc., depending on the operation of the graphics processor 2000. The graphics processor 2000 can output a variable frequency signal Fsync and a data strobe signal DE that include information about the vertical synchronization signal Vsync corresponding to the corresponding frame rate.

[0119] In one embodiment, the control unit 500 may output a light emission control start signal EFLM with an effective period VP based on the data gating signal DE and the variable frequency signal Fsync.

[0120] With a frame rate of approximately 120Hz, five emission control start signals (EFLM) can be output within one frame (5 cycles of drive).

[0121] At a frame rate of approximately 100Hz, six emission control start signals EFLM (six-cycle drive) can be output within one frame. At this time, the first blank period BK1 can be substantially the same as the second reference period C2.

[0122] At a frame rate of approximately 85.71 Hz, the emission control start signal EFLM (7-cycle drive) can be output seven times within one frame. At this time, the second blank period BK2 can be substantially the same as twice the second reference period C2.

[0123] In one embodiment, such as Figure 7 As shown, the effective period VP can be determined as the third period C3 (approximately 1.39ms, or 700Hz). At a frame rate of approximately 120Hz, six emission control start signals EFLM (6 cycle drives) can be output within one frame. At a frame rate of approximately 102.86Hz, seven emission control start signals EFLM (7 cycle drives) can be output within one frame. In this case, the first blank period BK1 can be substantially the same as the third reference period C3. At a frame rate of approximately 90Hz, eight emission control start signals EFLM (eight cycle drives) can be output within one frame. In this case, the second blank period BK2 can be substantially the same as twice the time of the third reference period C3.

[0124] As described above, during frame rate conversion based on a predetermined reference period, the inputs of the data strobe signal DE and the image signal RGB can be fully synchronized with the output period of the light emission control start signal EFLM, thus preventing and / or reducing flickering during frame rate conversion.

[0125] Furthermore, for the same frame rate (e.g., 120Hz), the range of corresponding frame rates can differ depending on the number of times the emission control start signal EFLM is output.

[0126] Figure 8 It is used to illustrate what is applicable Figure 1 A diagram illustrating an example of the frame rate of a display device in an image display system.

[0127] Reference Figures 5 to 8 Based on the reference period RC and the number of times the light emission control start signal EFLM is supplied during one frame, various frame rates applicable to the display device 1000 can be determined.

[0128] Figure 8 This refers to a frame rate that varies discontinuously within the frequency range of 48Hz to 120Hz. That is, the frame rate of the display device according to the embodiments of the present invention can be transformed into discontinuous values ​​on a frame-by-frame basis. This frequency transformation drive can be defined as a discontinuous variable frame rate drive.

[0129] In one embodiment, the emission control start signal EFLM can be supplied more than twice within one frame. For example, such as... Figure 8 As shown, the number of times the EFLM (Emitting Light Control Start Signal) is supplied can be determined within the range of 4 to 17 times. Furthermore, the duration of a frame and the frame rate can be determined based on the number of times the EFLM is supplied and the reference period RC.

[0130] The duration of one frame can be determined as the product of the number of times the emission control start signal EFLM is supplied and the reference period RC. Therefore, the duration of one frame can be an integer multiple of the reference period RC.

[0131] The graphics processor 2000 can set the active period of the data strobe signal DE and the blank periods BK1 and BK2 to integer multiples of the reference period RC, respectively, and depict the image signal RGB accordingly.

[0132] In addition, display devices ( Figure 1 The control unit 500 of the 1000 can display images with various frame rates based on multiple reference periods RC.

[0133] For example, with a reference period RC of approximately 2.08 ms, the frame rate can be varied at more than seven frequencies. Furthermore, with a reference period RC of approximately 1.67 ms, the frame rate can be varied at more than eight frequencies. With a reference period of approximately 1.39 ms, the frame rate can be varied at more than ten frequencies. With a reference period of approximately 1.19 ms, the frame rate can be varied at more than eleven frequencies.

[0134] As described above, even excluding the frame rates that repeat between multiple reference cycles RC, the input frequency (rendering speed) of the image signal RGB can be adjusted within a frequency range of 48Hz to 120Hz to match the display device's ( Figure 1 The frame rate synchronization (or consistency) frequency of 1000 is extended to 28 or more. Therefore, in display devices that are suitable for discontinuous variable frame rate driving ( Figure 1 In the 1000), the frame rate that the control unit 500 can correspond to when flicker-free operation is detected can be further increased, which can expand its applicability to display devices. Figure 1 The versatility of the control unit 500 (of the 1000).

[0135] On the other hand, such as Figure 8 As shown, the predetermined frame rate can be achieved by multiple reference periods RC that are different from each other. For example, when driving a display device at a frame rate of 120Hz, four light emission control start signals EFLM can be supplied with a reference period RC of approximately 2.08ms, or five light emission control start signals EFLM can be supplied with a reference period RC of approximately 1.67ms, or six light emission control start signals EFLM can be supplied with a reference period RC of approximately 1.39ms, or seven light emission control start signals EFLM can be supplied with a reference period RC of approximately 1.19ms.

[0136] Figure 9 It means Figure 1 The image shows a timing diagram of an example of the system's operation.

[0137] Reference Figures 4 to 9 The control signal generation unit 560 included in the control unit 500 can change the effective period VP of the light emission control start signal EFLM according to the changes in the variable frequency signal Fsync and the frame frequency.

[0138] In one embodiment, the graphics processor 2000 can supply the image signal RGB to the control unit 500 at an input frequency based on a selected reference period RC. For example, in Figure 6 When the second reference period C2 is selected as the effective period VP, the length of the data strobe signal DE can be an integer multiple of the second reference period C2, and the frame frequency can freely change among frequencies corresponding to integer multiples of the effective period VP.

[0139] like Figure 9 As shown, the effective period VP can be changed at the first moment A. For example, the effective period VP can be changed from the second reference period C2 to the third reference period C3. The control signal generation unit 560 can output the light emission control start signal EFLM and the first scan start signal SFLM1 based on the changed effective period VP and the data strobe signal DE. Although not in Figure 9As shown, however, the first scan start signal SFLM1 for data writing can be output synchronously with the start time of the effective period of the data strobe signal DE.

[0140] The frame rate can be changed if the effective period VP is changed. For example, as Figure 9 As shown, a 90Hz frame rate that cannot be synchronized with the second reference period C2 can be implemented based on the third reference period C3.

[0141] Similarly, a 96Hz frame rate that cannot be synchronized with the second reference period C2 and the third reference period C3 can be implemented based on the first reference period C1. Therefore, the effective period VP of the second time point B can be determined as the first reference period C1, and the frame rate can be changed.

[0142] In one embodiment, when there is no blank period in the current frame (e.g., Figure 9 In the 120Hz range, the control signal generation unit 560 can output the light emission control start signal EFLM with the effective period VP (e.g., the third reference period C3) of the light emission control start signal EFLM output in the previous frame.

[0143] That is, such as Figure 8 As shown, various reference periods RC can be applied when implementing a 120Hz frame rate without a blank period. However, the control signal generation unit 560 may produce errors in driving when selecting the effective period VP. However, as... Figure 9 As shown, when the effective period VP of the previous frame is the third reference period C3, the control signal generation unit 560 can output the light emission control start signal EFLM of the current frame with the third reference period C3. Therefore, driving errors in the control unit 500 can be prevented using a relatively simple driving algorithm.

[0144] As described above, in the display device and image display system including the present invention, the display device may include information on multiple reference cycles, and the input frequency of the image signal supplied from the graphics processor to the display device may be limited to a value selected from the multiple reference cycles. Therefore, the input frequency to the display device (i.e., the rendering speed of the graphics processor) can be fully synchronized with the output cycles of the light emission control signal (light emission control start signal) and the scan signal (i.e., the frame rate), which can reduce and / or prevent flickering caused by variations in light emission time during frame rate changes from being detected.

[0145] Furthermore, by presetting various reference cycles, the frame rate that the control unit of the display device can respond to when no flicker is detected can be further increased, thus expanding the versatility of the control unit applicable to the display device.

[0146] The above description refers to various embodiments of the present invention. However, those skilled in the art should understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention.

Claims

1. An image display system comprising: a graphic processor that supplies an image signal, a control signal, and a variable frequency signal to a display device; and the display device that displays an image at a frame frequency corresponding to the variable frequency signal, the display device including: a plurality of pixels connected to each light emission control line, each data line, and each scanning line; a control section that provides reference data including information of a plurality of reference periods as a period of an output light emission control start signal to the graphic processor, outputs the light emission control start signal based on the control signal, and adjusts an output timing of a scanning start signal based on the variable frequency signal; a light emission drive section that supplies a light emission control signal to the light emission control line based on the light emission control start signal; and a scanning drive section that supplies a scanning signal to the scanning line based on the scanning start signal, wherein the graphic processor selects one reference period among the plurality of reference periods, and generates the control signal and the variable frequency signal based on the selected one reference period.

2. The image display system according to claim 1, wherein the control signal includes a data strobe signal that divides an active period and a blank period in which the image signal is supplied within one frame.

3. The image display system according to claim 2, wherein the blank period is an integer multiple of the selected one reference period among the plurality of reference periods.

4. The image display system according to claim 2, wherein a length of the one frame is an integer multiple of the selected one reference period among the plurality of reference periods.

5. The image display system according to claim 2, wherein the control section includes: a reception section that restores a vertical synchronization signal based on the variable frequency signal; a memory that stores the reference data; and a control signal generation section that selects an active period that corresponds to the frame frequency among the plurality of reference periods from the reference data based on the data strobe signal, and outputs the light emission control start signal with the active period.

6. The image display system according to claim 5, wherein the active period is p times a length of the active period, where p is a positive integer, the blank period is q times the length of the active period, where q is an integer of 0 or more.

7. The image display system according to claim 5, wherein the control signal generation section outputs the scanning start signal corresponding to the vertical synchronization signal.

8. The image display system according to claim 5, wherein the vertical synchronization signal and the scanning start signal are output corresponding to the frame frequency.

9. The image display system according to claim 5, wherein the graphic processor controls a drawing speed of processing the image signal based on the reference data.

10. The image display system according to claim 9, wherein an output frequency of the light emission control signal is an integer multiple of the frame frequency determined according to the variable frequency signal.

11. The image display system according to claim 10, wherein the control signal includes information of the active period and the blank period.

12. The image display system according to claim 5, wherein the control signal generating section detects the blank period, and determines a reference period corresponding to 1 / r of the detected blank period as the effective period, where r is a positive integer.

13. The image display system according to claim 5, wherein the control signal generating section changes the effective period of the light emission control start signal in accordance with a change in the variable frequency signal and the frame frequency.

14. The image display system according to claim 2, wherein in a case where there is no blank period in a current frame, the control signal generating section outputs the light emission control start signal with the effective period of the light emission control start signal output in a previous frame.

15. The image display system according to claim 2, wherein in a case where the frame frequencies are the same, the number of the light emission control start signals supplied within one frame differs in accordance with the reference period.

16. The image display system according to claim 1, wherein the control section further includes an image data generating section that rearranges the image signal and outputs image data corresponding to the frame frequency.

17. The image display system according to claim 16, wherein the display device further includes a data driving section that converts the image data into an analog form data signal and supplies the data signal to the data line.

18. A display device comprising: a plurality of pixels connected to each light emission control line, each data line, and each scanning line, and displaying an image at a frame frequency corresponding to a variable frequency signal based on a data strobe signal; a control section that selects an effective period from a plurality of reference periods that are periods in which a light emission control start signal is output based on the data strobe signal, outputs the light emission control start signal with the effective period, and adjusts an output timing of a scanning start signal based on the variable frequency signal; a light emission driving section that supplies a light emission control signal to the light emission control line based on the light emission control start signal; and a scanning driving section that supplies a scanning signal to the scanning line based on the scanning start signal, wherein one of the plurality of reference periods is selected, and the variable frequency signal is generated based on the selected one of the reference periods.

19. The display device according to claim 18, wherein the data strobe signal includes an effective period in which an image signal is supplied and a blank period within one frame, the effective period is p times the length of the effective period, where p is a positive integer, the blank period is q times the length of the effective period, where q is an integer of 0 or more. ​

Images