Scan driving circuit and display device including the same

Abstract

Disclosed are a scan driving circuit and a display device including the same. The scan driving circuit includes a driving circuit, a first masking circuit, and a second masking circuit, the driving circuit outputs a first node signal, a second node signal, a third node signal, and a second scan signal in response to a clock signal and a carry signal, the first masking circuit outputs a first scan signal in response to a first masking signal, the second node signal, and the third node signal, and the second masking circuit discharges the first node signal to a first voltage in response to a second masking signal and the second scan signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0077281, filed on June 24, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] This disclosure relates to display devices, and more specifically, to display devices including scan driving circuitry. Background Technology

[0004] Organic light-emitting diodes (OLEDs) in display devices use organic light-emitting diodes (OLEDs) to emit light through the recombination of electrons and holes to display images. OLEDs offer advantages such as fast response time and low power consumption.

[0005] The organic light-emitting display device includes pixels connected to data lines and scan lines. Each pixel includes an organic light-emitting diode (OLED) and a circuit unit for controlling the amount of current flowing through the OLED. In response to a data signal, the circuit unit controls the amount of current flowing through the OLED from a first driving voltage to a second driving voltage. Here, in response to the amount of current flowing through the OLED, light of a predetermined brightness is generated.

[0006] The transistors included in the circuit cells are typically formed from transistors with a low-temperature polycrystalline silicon (“LTPS”) semiconductor layer. LTPS transistors are advantageous in terms of high mobility and stability, but leakage current is generated when the voltage level of the second drive voltage decreases or the operating frequency decreases. When leakage current is generated in the circuit cells of a pixel, the amount of current flowing through the organic light-emitting diode changes, and thus the display quality may deteriorate.

[0007] To reduce leakage current in transistors within the circuit units of a pixel, transistors using oxide semiconductors as the semiconductor layer are being investigated. Furthermore, the use of both LTPS semiconductor transistors and oxide semiconductor transistors in the circuit units of a pixel is also being explored.

[0008] In addition, technologies are needed to reduce power consumption in display devices. Summary of the Invention

[0009] This disclosure provides a scan drive circuit capable of reducing power consumption and a display device including the scan drive circuit.

[0010] An embodiment of the present invention provides a scanning drive circuit, which includes a drive circuit, a first masking circuit, and a second masking circuit. The drive circuit outputs a first node signal, a second node signal, and a second scan signal in response to a clock signal and a carry signal. The first masking circuit outputs a first scan signal in response to the first masking signal, the first node signal, and the second node signal. The second masking circuit discharges the first node signal to a first voltage in response to the second masking signal and the second scan signal.

[0011] In an implementation, the driving circuit may include a first transistor and a second transistor, wherein the first transistor, in response to a first clock signal in the clock signal, transmits a carry signal as a first node signal, and the second transistor, in response to a second node signal, transmits a second voltage as a second scan signal.

[0012] In an embodiment, the scan driving circuit may further include a first output terminal connected to the first scan line and outputting a first scan signal, and a second output terminal connected to the second scan line and outputting a second scan signal.

[0013] In an embodiment, the first masking circuit may include a first masking transistor, a second masking transistor, and a third masking transistor, wherein the first masking transistor is connected between a second voltage terminal receiving a second voltage and a first masking node and includes a gate electrode for receiving a second node signal, the second masking transistor is connected between the first masking node and a first output terminal and includes a gate electrode for receiving a first masking signal, and the third masking transistor is connected between the first output terminal and a first voltage terminal receiving a first voltage and includes a gate electrode for receiving a first node signal.

[0014] In an implementation, the driving circuit may output a third node signal to a third node in response to a clock signal, a carry signal, and a first node signal, and the first masking circuit may further include a fourth masking transistor and a fifth masking transistor connected in series between the first output terminal and the first voltage terminal, wherein the fourth masking transistor may include a gate electrode connected to the third node, and the fifth masking transistor may include a gate electrode connected to the first output terminal.

[0015] In an implementation, the second masking circuit may include a first masking transistor and a second masking transistor, wherein the first masking transistor is connected between the first transistor and the second masking node and includes a gate electrode for receiving a second masking signal, and the second masking transistor is connected between the second masking node and a first voltage terminal for receiving a first voltage and includes a gate electrode connected to a second output terminal.

[0016] In this implementation, the first masking circuit may also receive a third masking signal.

[0017] In an embodiment, the first masking circuit may include a first masking transistor, a second masking transistor, a third masking transistor, and a fourth masking transistor, wherein the first masking transistor is connected between a second voltage terminal receiving a second voltage and a first masking node and includes a gate electrode for receiving a third masking signal; the second masking transistor is connected between a second node transmitting a second node signal and the first masking node and includes a gate electrode for receiving a first masking signal; the third masking transistor is connected between a second voltage terminal and a first output terminal and includes a gate electrode connected to the first masking node; and the fourth masking transistor is connected between the first output terminal and a first voltage terminal receiving a first voltage and includes a gate electrode connected to the first node for transmitting the first node signal.

[0018] In an implementation, the third masking signal may be complementary to the first masking signal.

[0019] In an implementation, the driving circuit may output a third node signal to a third node in response to a clock signal, a carry signal, and a first node signal, and the first masking circuit may further include a fifth masking transistor and a sixth masking transistor connected in series between the first output terminal and the first voltage terminal, wherein the fifth masking transistor may include a gate electrode connected to the third node, and the sixth masking transistor may include a gate electrode connected to the first output terminal.

[0020] In an embodiment of the present invention, a display device includes: a display panel including a plurality of pixels respectively connected to a plurality of data lines, a plurality of first scan lines, and a plurality of second scan lines, wherein the display panel is divided into a first display area and a second display area; a data driving circuit for driving the plurality of data lines; a scan driving circuit for driving the plurality of first scan lines and the plurality of second scan lines; and a driving controller for receiving an image signal and a control signal, and controlling the data driving circuit and the scan driving circuit such that an image corresponding to the image signal is displayed on the display panel. The driving controller outputs a first masking signal and a second masking signal indicating the start point of the second display area, and the scan driving circuit includes a plurality of driving stages, each of which outputs a first scan signal to a corresponding first scan line among the plurality of first scan lines, and outputs a second scan signal to a corresponding second scan line among the plurality of second scan lines. Each of the plurality of drive stages includes: a drive circuit that outputs a first node signal, a second node signal, and a second scan signal in response to a clock signal and a carry signal; a first masking circuit that outputs a first scan signal in response to the first masking signal, the first node signal, and the second node signal; and a second masking circuit that discharges the first node signal to a first voltage in response to the second masking signal and the second scan signal.

[0021] In one embodiment, in response to a first masking signal and a second masking signal, the scan driving circuit can drive a first scan line and a second scan line corresponding to the first display area among a plurality of first scan lines and a plurality of second scan lines at a first driving frequency, and drive a first scan line and a second scan line corresponding to the second display area among a plurality of first scan lines and a plurality of second scan lines at a second driving frequency, wherein the second driving frequency is lower than the first driving frequency.

[0022] In an implementation, the second scan signal output from the j-th drive stage among a plurality of drive stages can be provided as the carry signal of the (j+1)-th drive stage, where j is a natural number.

[0023] In an implementation, the driving circuit may include: a first transistor that transmits a carry signal as a first node signal in response to a first clock signal in a clock signal, and a second transistor that transmits a second voltage as a second scan signal in response to a second node signal.

[0024] In an implementation, each of the plurality of drive stages may further include: a first output terminal connected to a first scan line and outputting a first scan signal, and a second output terminal connected to a second scan line and outputting a second scan signal.

[0025] In an implementation, the first masking circuit may include: a first masking transistor connected between a second voltage terminal receiving a second voltage and a first masking node and including a gate electrode for receiving a second node signal; a second masking transistor connected between the first masking node and a first output terminal and including a gate electrode for receiving a first masking signal; and a third masking transistor connected between the first output terminal and the first voltage terminal receiving a first voltage and including a gate electrode for receiving a first node signal.

[0026] In an implementation, the driving circuit may output a third node signal to a third node in response to a clock signal, a carry signal, and a first node signal, and the first masking circuit may further include a fourth masking transistor and a fifth masking transistor connected in series between the first output terminal and the first voltage terminal, wherein the fourth masking transistor may include a gate electrode connected to the third node, and the fifth masking transistor may include a gate electrode connected to the first output terminal.

[0027] In an implementation, the second masking circuit may include: a first masking transistor connected between the first transistor and the second masking node and including a gate electrode for receiving a second masking signal, and a second masking transistor connected between the second masking node and a first voltage terminal for receiving a first voltage and including a gate electrode connected to a second output terminal.

[0028] In an embodiment, the first masking circuit may include: a first masking transistor connected between a second voltage terminal receiving a second voltage and a first masking node and including a gate electrode for receiving a third masking signal; a second masking transistor connected between a second node transmitting a second node signal and the first masking node and including a gate electrode for receiving a first masking signal; a third masking transistor connected between a second voltage terminal and a first output terminal and including a gate electrode connected to the first masking node; and a fourth masking transistor connected between the first output terminal and the first voltage terminal receiving the first voltage and including a gate electrode connected to the first node for transmitting the first node signal.

[0029] In an implementation, the driving circuit may output a third node signal to a third node in response to a clock signal, a carry signal, and a first node signal, and the first masking circuit may further include a fifth masking transistor and a sixth masking transistor connected in series between the first output terminal and the first voltage terminal, wherein the fifth masking transistor may include a gate electrode connected to the third node, and the sixth masking transistor may include a gate electrode connected to the first output terminal. Attached Figure Description

[0030] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0031] Figure 1 A display device according to an embodiment of the concept of the present invention is shown;

[0032] Figure 2 This is a block diagram of a display device according to an embodiment of the concept of the present invention;

[0033] Figure 3 This is an equivalent circuit diagram of a pixel according to an embodiment of the concept of the present invention;

[0034] Figure 4 It is shown Figure 3 A timing diagram of the operation of pixels in a display device;

[0035] Figure 5 This is a block diagram of a first scan drive circuit according to an embodiment of the concept of the present invention;

[0036] Figure 6 This shows the difference between normal mode and low power mode. Figure 5 An exemplary first scan signal output by the first scan drive circuit (“SD1”) shown in the figure;

[0037] Figure 7 An exemplary second scan signal in low-power mode is shown;

[0038] Figure 8 This is a circuit diagram illustrating the j-th drive stage in a first scan drive circuit according to an embodiment of the concept of the present invention;

[0039] Figure 9 This is an example shown Figure 8 The timing diagram shows the operation of the j-th drive stage in the normal mode of the first scan drive circuit shown.

[0040] Figure 10 This is an example shown Figure 8 Timing diagram of the operation of the j-th drive stage in the low-power mode of the first scan drive circuit shown;

[0041] Figure 11 This is a circuit diagram illustrating the j-th drive stage in a first scan drive circuit according to another embodiment of the concept of the present invention;

[0042] Figure 12 Exemplary examples illustrate the first to third masking signals in normal mode and low power mode, as well as the signals from... Figure 5 The first scan signal output by the first scan drive circuit shown in the figure;

[0043] Figure 13 This is a circuit diagram illustrating the j-th drive stage in a first scan drive circuit according to yet another embodiment of the concept of the present invention; and

[0044] Figure 14 This is a circuit diagram illustrating the j-th drive stage in a first scan drive circuit according to yet another embodiment of the concept of the present invention. Detailed Implementation

[0045] It should be understood that when an element or layer is referred to as being “on,” “connected to,” or “linked to” another element or layer, that element or layer may be directly on, directly connected to, or linked to the other element, or there may be an intermediary third element. It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or sections, these elements, components, areas, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or section from another element, component, area, layer, or section. Therefore, the first element, component, area, layer, or section discussed below may be referred to as the second element, component, area, layer, or section without departing from the teachings herein.

[0046] In the accompanying drawings, the same reference numerals denote the same elements. Furthermore, in the drawings, the thickness, scale, and dimensions of the elements are exaggerated for the sake of effective description of the technical content. The term "and / or" includes any and all combinations of one or more of the related items.

[0047] Terms such as first, second, etc., may be used to describe various components, but these components should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component. As used herein, the singular forms “a,” “an,” and “the” may also be intended to include the plural forms, unless the context clearly indicates otherwise.

[0048] Furthermore, terms such as “under,” “lower,” “on,” and “upper” are used to explain the association of items shown in the accompanying drawings. It should be understood that spatial relative terms are intended to include different orientations of the apparatus in use or operation other than those depicted in the figures.

[0049] It should also be understood that the terms “include” and / or “including” as used in this specification indicate the presence of the stated features, integers, steps, operations, elements, components or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or combinations thereof.

[0050] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. Furthermore, it should be understood that terms, such as those defined in common dictionaries, shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0051] In the following description, embodiments of the concept of the present invention will be described with reference to the accompanying drawings.

[0052] Figure 1 A display device according to an embodiment of the concept of the present invention is shown.

[0053] Reference Figure 1A mobile terminal is shown as an example of a display device DD according to an embodiment of the concept of the present invention. The mobile terminal may include a tablet PC, smartphone, personal digital assistant (“PDA”), portable multimedia player (“PMP”), game console, watch-type electronic device, etc. However, embodiments of the concept of the present invention are not limited thereto. The concept of the present invention can be applied not only to large electronic devices such as televisions or outdoor billboards, but also to medium or small electronic devices such as personal computers, laptop computers, kiosks, vehicle navigation units, or cameras. These are merely examples, and the display device DD may also be employed in other electronic devices without departing from the concept of the present invention.

[0054] like Figure 1 As shown, the display surface displaying the first image IM1 and the second image IM2 is parallel to the surface defined by the first direction DR1 and the second direction DR2. The display device DD includes a plurality of regions divided on the display surface. The display surface includes a display area DA displaying the first image IM1 and the second image IM2, and a non-display area NDA adjacent to the display area DA. The non-display area NDA may be referred to as a border area. In one embodiment, for example, the display area DA may be quadrilateral in shape. The non-display area NDA may surround the display area DA. Furthermore, although not shown in the figures, the display device DD may partially include, for example, a curved shape. As a result, a region of the display area DA may have a curved shape.

[0055] The display area DA of the display device DD includes a first display area DA1 and a second display area DA2. In a specific application, a first image IM1 may be displayed in the first display area DA1, and a second image IM2 may be displayed in the second display area DA2. In one embodiment, for example, the first image IM1 may be a moving image, and the second image IM2 may be a still image or text information that does not change over a long period of time.

[0056] According to the embodiment, the display device DD can drive the first display area DA1, which displays moving images, at a normal frequency (e.g., 120 Hz), and drive the second display area DA2 at a lower frequency (e.g., 1 Hz). The display device DD can reduce power consumption by reducing the driving frequency of the second display area DA2.

[0057] The size of each of the first display area DA1 and the second display area DA2 can be preset and changed by the application. In an implementation, when a still image is displayed in the first display area DA1 and a moving image is displayed in the second display area DA2, the first display area DA1 can be driven at a low frequency (e.g., 1 Hz), and the second display area DA2 can be driven at a normal frequency (e.g., 120 Hz). Furthermore, the display area DA can be divided into three or more display areas, and the driving frequency of each display area can be determined according to the type of image to be displayed in each display area (e.g., whether it is a still image or a moving image).

[0058] Figure 2 This is a block diagram of a display device according to an embodiment of the concept of the present invention.

[0059] Reference Figure 2 The display device DD includes a display panel DP, a drive controller 100, a data drive circuit 200, and a voltage generator 300.

[0060] The drive controller 100 receives the image signal RGB and the control signal CTRL. The drive controller 100 generates the image data signal DATA by converting the data format of the image signal RGB to meet the interface specifications with the data drive circuit 200. The drive controller 100 outputs a first scan control signal SCS1, a second scan control signal SCS2, a data control signal DCS, and a light emission control signal ECS.

[0061] The data drive circuit 200 receives the data control signal DCS and the image data signal DATA from the drive controller 100. The data drive circuit 200 converts the image data signal DATA into a data signal and outputs the data signal to multiple data lines DL1 to DLm (described later). The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0062] Voltage generator 300 generates voltages for the operation of display panel DP. In this embodiment, voltage generator 300 can generate a first drive voltage ELVDD, a second drive voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2.

[0063] The display panel DP may include first scan lines GIL1 to GILn, second scan lines GCL1 to GCLn, third scan lines GWL1 to GWLn+1, light emission control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX. Here, m and n are natural numbers. The display panel DP may also include a first scan driving circuit SD1, a second scan driving circuit SD2, and a light emission driving circuit EDC. In an embodiment, the first scan driving circuit SD1 and the second scan driving circuit SD2 may be arranged on a first side of the display panel DP, and the light emission driving circuit EDC may be arranged on a second side of the display panel DP. In other words, the first scan driving circuit SD1 and the second scan driving circuit SD2 may be arranged to face the light emission driving circuit EDC across the pixels PX in a first direction DR1.

[0064] The first scan lines GIL1 to GILn and the second scan lines GCL1 to GCLn extend from the first scan drive circuit SD1 in the first direction DR1. The third scan lines GWL1 to GWLn+1 extend from the second scan drive circuit SD2 in the first direction DR1. The light emission control lines EML1 to EMLn extend from the light emission drive circuit EDC in the opposite direction to the first direction DR1 (i.e., Figure 2 It extends from right to left (in the direction of the middle).

[0065] The first scan lines GIL1 to GILn, the second scan lines GCL1 to GCLn, the third scan lines GWL1 to GWLn+1, and the light emission control lines EML1 to EMLn are arranged spaced apart from each other on the second direction DR2. Data lines DL1 to DLm start from the data drive circuit 200 in the opposite direction to the second direction DR2 (i.e., Figure 2 Extending from the top to the bottom, and arranged spaced apart from each other in the first direction DR1.

[0066] Each of the plurality of pixels PX is electrically connected to one corresponding of the first scan lines GIL1 to GILn, one corresponding of the second scan lines GCL1 to GCLn, two corresponding of the third scan lines GWL1 to GWLn+1, and one corresponding of the light emission control lines EML1 to EMLn. That is, each of the plurality of pixels PX can be electrically connected to four scan lines. In one embodiment, for example, as... Figure 2 As shown, pixels in the first row can be connected to scan lines GIL1, GCL1, GWL1, and GWL2. Furthermore, pixels in the second row can be connected to scan lines GIL2, GCL2, GWL2, and GWL3. Pixels in the nth row can be connected to scan lines GILn, GCLn, GWLn, and GWLn+1.

[0067] Each of the multiple pixels PX may include a light-emitting diode (ED) (see Figure 3 ) and the pixel circuit unit PXC used to control the light emission of the light-emitting diode ED (see Figure 3 The pixel circuit unit (PXC) may include multiple transistors and capacitors. At least one of the first scan drive circuit (SD1), the second scan drive circuit (SD2), and the light emission drive circuit (EDC) may include transistors provided using the same process as the transistors in the pixel circuit unit (PXC).

[0068] Each of the multiple pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2.

[0069] The first scan drive circuit SD1 receives a first scan control signal SCS1 from the drive controller 100. In response to the first scan control signal SCS1, the first scan drive circuit SD1 can output a first scan signal to the first scan lines GIL1 to GILn, and output a second scan signal to the second scan lines GCL1 to GCLn.

[0070] The second scan drive circuit SD2 receives the second scan control signal SCS2 from the drive controller 100. In response to the second scan control signal SCS2, the second scan drive circuit SD2 can output the third scan signal to the third scan lines GWL1 to GWLn+1.

[0071] The circuit configuration and operation of the first scan drive circuit SD1 will be described in detail later.

[0072] The optical emission driver circuit EDC receives the optical emission control signal ECS from the driver controller 100. In response to the optical emission control signal ECS, the optical emission driver circuit EDC can output the emission control signal to the optical emission control lines EML1 to EMLn.

[0073] exist Figure 2 In the diagram, the first scan driving circuit SD1 and the second scan driving circuit SD2 are shown arranged only on the first side of the display panel DP, but the embodiments of the present invention are not limited thereto. In another embodiment, one of the first scan driving circuit SD1 and the second scan driving circuit SD2 may be arranged on the first side of the display panel DP, and the other may be arranged on the second side of the display panel DP.

[0074] According to the embodiment, the drive controller 100 divides the display panel DP into a first display area DA1 based on the control signal CTRL and / or the image signal RGB (see...). Figure 1 ) and the second display area DA2 (see Figure 1The system outputs at least one masking signal to indicate the starting point of the second display area DA2. The at least one masking signal may be included in each of the first scan control signal SCS1 and the second scan control signal SCS2.

[0075] In response to the first scan control signal SCS1, the first scan drive circuit SD1 according to the embodiment can drive the first scan line and the second scan line corresponding to the first display area DA1 among the first scan lines GIL1 to GILn and the second scan lines GCL1 to GCLn at a first drive frequency, and drive the first scan line and the second scan line corresponding to the second display area DA2 at a second drive frequency different from the first drive frequency.

[0076] Similarly, in response to the second scan control signal SCS2, the second scan drive circuit SD2 can drive the third scan line GWL1 to GWLn+1 corresponding to the first display area DA1 at the first drive frequency, and drive the third scan line corresponding to the second display area DA2 at the second drive frequency, which is different from the first drive frequency.

[0077] Figure 3 This is an equivalent circuit diagram of a pixel according to an embodiment of the concept of the present invention.

[0078] Figure 3 It shows the relationship with Figure 2 The diagram shows an exemplary equivalent circuit diagram of pixel PXij connected to the i-th data line DL1 to DLm, the j-th first scan line GILj among the first scan lines GIL1 to GILn, the j-th second scan line GCLj among the second scan lines GCL1 to GCLn, the j-th third scan line GWLj and the (j+1)-th third scan line GWLj+1 among the third scan lines GWL1 to GWLn+1, and the j-th light emission control line EMLj among the light emission control lines EML1 to EMLn. Here, i is a natural number equal to or less than m, and j is a natural number equal to or less than n.

[0079] Figure 2 Each of the plurality of pixels PX shown may have the same as Figure 3The equivalent circuit diagram of pixel PXij shown has the same circuit configuration. In an embodiment, the pixel circuit unit PXC of pixel PXij may include a first transistor T1 to a seventh transistor T7 and a capacitor Cst. Furthermore, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a P-type transistor with an LTPS semiconductor layer, and each of the third transistor T3 and the fourth transistor T4 may be an N-type transistor with an oxide semiconductor layer. However, embodiments of the present invention are not limited to this, and in another embodiment, at least one of the first transistor T1 to the seventh transistor T7 may be an N-type transistor, and the remaining transistors may be P-type transistors. Moreover, the circuit configuration of the pixel according to embodiments of the present invention is not limited to... Figure 3 . Figure 3 The pixel circuit unit PXC shown is merely exemplary, and the configuration of the pixel circuit unit PXC can be modified and implemented.

[0080] Reference Figure 3 According to an embodiment, the pixel PXij of the display device DD includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a capacitor Cst, and at least one light-emitting diode ED. This embodiment describes an example where a pixel PXij includes one light-emitting diode ED.

[0081] For ease of description, in the following text, the j-th first scan line GILj, the j-th second scan line GCLj, the j-th third scan line GWLj, the (j+1)-th third scan line GWLj+1 and the j-th light emission control line EMLj will be referred to as the first scan line GILj, the second scan line GCLj, the third scan line GWLj, the fourth scan line GWLj+1 and the light emission control line EMLj, respectively.

[0082] The first scan line GILj, the second scan line GCLj, the third scan line GWLj, and the fourth scan line GWLj+1 can respectively transmit the first scan signal GIj, the second scan signal GCj, the third scan signal GWj, and the fourth scan signal GWj+1. The first scan signal GIj can turn on / off the fourth transistor T4, which is an N-type transistor. The second scan signal GCj can turn on / off the third transistor T3, which is an N-type transistor. The third scan signal GWj can turn on / off the second transistor T2, which is a P-type transistor. The fourth scan signal GWj+1 can turn on / off the seventh transistor T7, which is a P-type transistor.

[0083] The light emission control line EMLj transmits an emission control signal EMj that controls the emission of the light-emitting diode ED included in pixel PXij. The emission control signal EMj transmitted by the light emission control line EMLj may have a different waveform than the first scan signal GIj, second scan signal GCj, third scan signal GWj, and fourth scan signal GWj+1 transmitted by the first scan line GILj, second scan line GCLj, third scan line GWLj, and fourth scan line GWLj+1, respectively. The data line DLi transmits a data signal Di. The data signal Di may have a waveform different from the one input to the display device DD (see...). Figure 2 The image signal RGB corresponds to the voltage level. The first driving voltage line VL1, the second driving voltage line VL2, the third driving voltage line VL3, and the fourth driving voltage line VL4 can respectively transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT1, and the second initialization voltage VINT2. The first initialization voltage VINT1 and the second initialization voltage VINT2 can have different voltage levels. In another embodiment, the first initialization voltage VINT1 and the second initialization voltage VINT2 can have the same voltage level.

[0084] The first transistor T1 includes a first electrode connected to the first drive voltage line VL1 via a fifth transistor T5, a second electrode electrically connected to the anode of the light-emitting diode ED via a sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 receives the data signal Di transmitted by the data line DLi according to the switching operation of the second transistor T2, and provides the drive current Id to the light-emitting diode ED.

[0085] The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the third scan line GWLj. The second transistor T2 can be turned on according to the third scan signal GWj transmitted through the third scan line GWLj, and then transmit the data signal Di that has been transmitted from the data line DLi to the first electrode of the first transistor T1.

[0086] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the second scan line GCLj. The third transistor T3 can be turned on according to the second scan signal GCj transmitted through the second scan line GCLj, and then the first transistor T1 is connected in a diode form by connecting the gate electrode of the first transistor T1 to the second electrode.

[0087] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to a third drive voltage line VL3 for transmitting a first initialization voltage VINT1, and a gate electrode connected to a first scan line GILj. The fourth transistor T4 can be turned on according to a first scan signal GIj transmitted via the first scan line GILj, and then transmits the first initialization voltage VINT1 to the gate electrode of the first transistor T1, thus performing an initialization operation to initialize the voltage at the gate electrode of the first transistor T1.

[0088] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the light emission control line EMLj.

[0089] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting diode ED, and a gate electrode connected to the light emission control line EMLj.

[0090] The fifth transistor T5 and the sixth transistor T6 can be turned on substantially simultaneously according to the emission control signal EMj transmitted through the light emission control line EMLj, and through this conduction, the first driving voltage ELVDD compensated by the first transistor T1 connected in the form of a diode can be transmitted to the light-emitting diode ED.

[0091] The seventh transistor T7 includes a first electrode connected to the fourth drive voltage line VL4, a second electrode connected to the second electrode of the sixth transistor T6, and a gate electrode connected to the fourth scan line GWLj+1. In an alternative embodiment, the first electrode of the seventh transistor T7 may be connected to the third drive voltage line VL3 instead of the fourth drive voltage line VL4.

[0092] As described above, one end of capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end is connected to the first driving voltage line VL1. The cathode of the light-emitting diode ED can be connected to the second driving voltage line VL2 for transmitting the second driving voltage ELVSS. The structure of pixel PXij according to the embodiment is not limited to... Figure 3 The structure shown can be modified in various ways, including the number of transistors and capacitors in a pixel and their interconnections.

[0093] Figure 4 It is shown Figure 3 The timing diagram shows the operation of the pixels of the display device DD. (Refer to...) Figure 3 and Figure 4 Describe the operation of the display device DD according to an embodiment.

[0094] Reference Figure 3 and Figure 4 During the initialization period within a frame F, a high-level first scan signal GIj is supplied through the first scan line GILj. The fourth transistor T4 is turned on in response to the high-level first scan signal GIj, and the first initialization voltage VINT1 is transmitted to the gate electrode of the first transistor T1 through the fourth transistor T4, thereby initializing the first transistor T1.

[0095] Then, during the data programming and compensation period, when the high-level second scan signal GCj is provided through the second scan line GCLj, the third transistor T3 is turned on. The first transistor T1 is connected as a diode through the turned-on third transistor T3 and is forward biased. The pulse width of each of the first scan signal GIj and the second scan signal GCj can be four horizontal time intervals 4H. The horizontal time interval H indicates the driving display panel DP (see...). Figure 2 The time of pixel PX in a row on the first direction DR1.

[0096] When a low-level third scan signal GWj is supplied through the third scan line GWLj, the second transistor T2 is turned on. Then, a compensation voltage is applied to the gate electrode of the first transistor T1. Here, the compensation voltage is equivalent to the voltage value of the data signal Di minus the threshold voltage of the first transistor T1. In other words, the gate voltage applied to the gate electrode of the first transistor T1 can be the compensation voltage.

[0097] The first driving voltage ELVDD and the compensation voltage are applied to the two ends of the capacitor Cst, and the charge corresponding to the voltage difference between the two ends can be stored in the capacitor Cst.

[0098] On the other hand, the seventh transistor T7 is turned on by receiving the low-level fourth scan signal GWj+1 through the fourth scan line GWLj+1. A portion of the drive current Id can be led out as a bypass current Ibp through the seventh transistor T7.

[0099] Even when the minimum current of the first transistor T1, used to display a black image, flows as the drive current Id, the black image may not be displayed correctly when the light-emitting diode ED emits light. Therefore, the seventh transistor T7 in the pixel PXij according to an embodiment of the present invention can divert a portion of the minimum current of the first transistor T1 to a current path other than the current path on the OLED side, as a bypass current Ibp. Here, the minimum current of the first transistor T1 means the current under the condition that the gate-source voltage of the first transistor T1 is less than the threshold voltage to turn off the first transistor T1. Under this condition of turning off the first transistor T1, the minimum drive current (e.g., 10 picoamperes (pA) or less) is transferred to the light-emitting diode ED so that the black image is rendered. When the minimum drive current used to display a black image flows, the bypass current Ibp has a large effect on bypassing and transfer. However, when a large drive current Id used to display an image such as a typical image or a white image flows, the effect of the bypass current Ibp is small. Therefore, when displaying a black image, the emission current Ied of the light-emitting diode ED, which is the difference between the driving current Id and the bypass current Ibp drawn through the seventh transistor T7, has the minimum current required to reliably render a black image. Thus, contrast can be improved by using the seventh transistor T7 to achieve an accurate black image. In this embodiment, the bypass signal is the fourth scan signal GWj+1, but it is not always limited to this.

[0100] Then, during the light emission period, the emission control signal EMj supplied from the light emission control line EMLj changes from a high level to a low level. During the light emission period, the fifth transistor T5 and the sixth transistor T6 are turned on by the emission control signal EMj. Then, a drive current Id is generated based on the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD. The drive current Id is supplied to the light-emitting diode ED through the sixth transistor T6, and the emission current Ied flows to the light-emitting diode ED. During the light emission period, the gate-source voltage of the first transistor T1 is maintained by the capacitor Cst as "compensation voltage minus the first drive voltage ELVDD". According to the current-voltage relationship of the first transistor T1, the drive current Id can be expressed as the square of the value obtained by subtracting the threshold voltage from the gate-source voltage of the first transistor T1, i.e., "(voltage value of data signal Di minus the first drive voltage ELVDD)". 2 "Proportional. Therefore, the drive current Id can be determined independently of the threshold voltage of the first transistor T1."

[0101] Figure 5 This is a block diagram of the first scan drive circuit SD1 according to an embodiment of the concept of the present invention.

[0102] Reference Figure 5The first scan drive circuit SD1 includes drive stages ST1 to STn+4.

[0103] Each of the drive levels ST1 to STn+4 from Figure 2 The drive controller 100 shown receives a first scan control signal SCS1. The first scan control signal SCS1 includes a start signal FLM, a first clock signal CLK1, a second clock signal CLK2, a first masking signal MS1, and a second masking signal MS2. Each of the drive stages ST1 to STn+4 receives a first voltage VGL and a second voltage VGH. The first voltage VGL and the second voltage VGH can be obtained from... Figure 2 The voltage generator 300 shown is provided.

[0104] The first masking signal MS1 and the second masking signal MS2 are signals used to drive a portion of the drive stages ST1 to STn+4 at a normal frequency (e.g., 120 Hz) and the remainder of the drive stages ST1 to STn+4 at a low frequency (e.g., 1 Hz).

[0105] In the implementation, driver stages ST1 to STn+4 output first scan signals GI1 to GIn and second scan signals GC1 to GCn. The first scan signals GI1 to GIn can be provided to... Figure 2 The first scan lines GI1 to GILn shown are illustrated, and the second scan signals GC1 to GCn can be provided to... Figure 2 The second scan lines GCL1 to GCLn are shown in the diagram.

[0106] Driver stage ST1 can receive a start signal FLM as a carry signal. Each of driver stages ST1 to STn+4 has a subordinate coupling relationship in which a second scan signal output from the previous driver stage is received as a carry signal. In one embodiment, for example, driver stage ST2 receives the second scan signal output from the previous driver stage ST1 as a carry signal, and driver stage ST3 receives the second scan signal output from the previous driver stage ST2 as a carry signal.

[0107] Figure 6 An example is shown showing the difference between normal mode and low power mode. Figure 5 The first scan signal GI1 to GIn is output by the first scan drive circuit SD1 shown in the figure.

[0108] Reference Figure 5 and Figure 6 During normal mode N-MODE, the first masking signal MS1 may be maintained at a first level (e.g., low level), and the second masking signal MS2 may be maintained at a second level (e.g., high level).

[0109] In normal N-MODE, driver stages ST1 to STn+4 output the first scan signals GI1 to GIn sequentially at high level in each of frames F1, F2, and F3. Figure 6 and Figure 7 In the example, an instance with n = 3840 is used.

[0110] In low-power mode (L-MODE), the first masking signal MS1 is used in the second display area DA2 driven at a low frequency (e.g., 1 Hz). Figure 1 The first masking signal changes from a low level to a high level at the start of the second display area DA2, and then changes back to a low level at the start of the next frame (e.g., F5).

[0111] In other words, the first masking signal MS1 is maintained at a first level (e.g., low level) in normal mode N-MODE, and periodically changes between a second level (e.g., high level) and the first level in low power mode L-MODE. The second masking signal MS2 is maintained at a second level in normal mode N-MODE, and periodically changes between the second level and the first level in low power mode L-MODE.

[0112] In one implementation, for example, when the low-power mode (L-MODE) starts from the fourth frame (F4), such as Figure 1 The first image IM1 shown can be displayed in the first display area DA1, and the second image IM2 can be displayed in the second display area DA2. Although the first masking signal MS1 is held low and the second masking signal MS2 is held high in the fourth frame F4, the first scan signals GI1 to GI1920 can be driven sequentially at high levels. In the fourth frame F4, when the first masking signal MS1 changes to a high level and the second masking signal MS2 changes to a low level, the first scan signals GI1921 to GI3840 can be held low. When the fourth frame F4 ends and the fifth frame F5 begins, the first masking signal MS1 can change to a low level again, and the second masking signal MS2 can change to a high level again.

[0113] Similar to the fourth frame F4, in the fifth frame F5, although the first masking signal MS1 is at a low level and the second masking signal MS2 is at a high level, the first scan signals GI1 to GI1920 can be driven sequentially at a high level. Although in the middle of the fifth frame F5, the first masking signal MS1 changes to a high level and the second masking signal MS2 changes to a low level, the first scan signals GI1921 to GI3840 remain at a low level.

[0114] Figure 7 An exemplary second scan signal GC1 to GCn is shown in low-power mode.

[0115] Reference Figure 7 In low-power mode, the frequency of the second scan signals GC1 to GC1920 is 120Hz, and the frequency of the second scan signals GC1921 to GC3840 is 1Hz. Although not shown in the figures, in low-power mode, the first scan signals GI1 to GI3840 may have the same waveform as the second scan signals GC1921 to GC3840.

[0116] In one implementation, for example, the second scan signals GC1 to GC1920 correspond to Figure 1 The display device DD shown has a first display area DA1, and second scan signals GC1921 to GC3840 corresponding to a second display area DA2. The first display area DA1, displaying moving images, is driven by the second scan signals GC1 to GC1920 at a normal frequency (e.g., 120 Hz). In other words, the first display area DA1 can be refreshed with a new image signal every 8.33 milliseconds (ms). The second display area DA2, displaying still images, is driven by the second scan signals GC1921 to GC3840 at a low frequency (e.g., 1 Hz). In other words, the second display area DA2 can be refreshed with a new image signal every 1 second.

[0117] In this way, since the second display area DA2, which only displays still images, is driven at a low frequency (e.g., 1 Hz), power consumption can be reduced without degrading display quality. In the low-power mode L-MODE, a portion of the second scan signals GC1 to GC3840 is driven at a normal frequency (e.g., 120 Hz), and the remainder of the second scan signals GC1 to GC3840 is driven at a frequency lower than the normal frequency (e.g., 1 Hz). Therefore, the low-power mode can be referred to as a multi-frequency mode.

[0118] Figure 8 This is a circuit diagram illustrating the j-th drive stage STj in the first scan drive circuit SD1 according to an embodiment of the concept of the present invention.

[0119] Figure 8 An example is shown Figure 5 The j-th driver STj is shown among the driver levels ST1 to STn+4 (where j is a positive integer and less than or equal to n+4). Figure 5 Each of the plurality of driver stages ST1 to STn+4 shown may include the same circuitry as the j-th driver stage STj. Hereinafter, the j-th driver stage STj is referred to as driver stage STj.

[0120] Reference Figure 8 The driver stage STj includes a driver circuit DC, a first masking circuit MSC11, a second masking circuit MSC12, first input terminals IN1 to fifth input terminals IN5, and a first output terminal OUT1 and a second output terminal OUT2.

[0121] The DC drive circuit includes transistors NT1 to NT12 and capacitors C1 to C3.

[0122] The DC drive circuit receives the first clock signal CLK1, the second clock signal CLK2, and the carry signal CRj through the first input terminal IN1 to the third input terminal IN3, respectively. The DC drive circuit receives the first voltage VGL and the second voltage VGH through the first voltage terminal V1 and the second voltage terminal V2, respectively. The DC drive circuit outputs the first scan signal GIj through the first output terminal OUT1 and the second scan signal GCj-4 through the second output terminal OUT2. The j-th drive stage STj can receive the second scan signal GCj-5 output through the second output terminal OUT2 of the (j-1)-th drive stage STj-1 as the carry signal CRj. The (j+1)-th drive stage STj+1 can receive the second scan signal GCj-4 output through the second output terminal OUT2 of the j-th drive stage STj as the carry signal CRj.

[0123] Figure 5 The carry signal CR1 of the drive stage ST1 shown can be the start signal FLM.

[0124] Figure 5 In the driver stages ST1 to STn+4 shown, each of the driver stages (e.g., odd-numbered driver stages) receives a first clock signal CLK1 at its first input terminal IN1 and a second clock signal CLK2 at its second input terminal IN2. Furthermore, in the driver stages ST1 to STn+4, each of the driver stages (e.g., even-numbered driver stages) receives the first clock signal CLK1 at its second input terminal IN2 and the second clock signal CLK2 at its first input terminal IN1.

[0125] Transistor NT1 is connected between the third input terminal IN3 and the first node N1, and includes a gate electrode connected to the first input terminal IN1. Transistor NT2 is connected between the second voltage terminal V2 and the sixth node N6, and includes a gate electrode connected to the fourth node N4. Transistor NT3 is connected between the sixth node N6 and the second input terminal IN2, and includes a gate electrode connected to the second node N2.

[0126] Transistors NT4-1 and NT4-2 are connected in series between the fourth node N4 and the first input terminal IN1. Each of transistors NT4-1 and NT4-2 includes a gate electrode connected to the first node N1. Transistor NT5 is connected between the fourth node N4 and the first voltage terminal V1, and includes a gate electrode connected to the first input terminal IN1. Transistor NT6 is connected between the third node N3 and the seventh node N7, and includes a gate electrode connected to the second input terminal IN2. Transistor NT7 is connected between the seventh node N7 and the second input terminal IN2, and includes a gate electrode connected to the fifth node N5.

[0127] Transistor NT8 is connected between the second voltage terminal V2 and the third node N3, and includes a gate electrode connected to the first node N1. Transistor NT9 is connected between the second voltage terminal V2 and the second output terminal OUT2, and includes a gate electrode connected to the third node N3. Transistor NT10 is connected between the second output terminal OUT2 and the first voltage terminal V1, and includes a gate electrode connected to the second node N2. Transistor NT11 is connected between the fourth node N4 and the fifth node N5, and includes a gate electrode connected to the first voltage terminal V1. Transistor NT12 is connected between the first node N1 and the second node N2, and includes a gate electrode connected to the first voltage terminal V1.

[0128] Capacitor C1 is connected between the second voltage terminal V2 and the third node N3. Capacitor C2 is connected between the fifth node N5 and the seventh node N7. Capacitor C3 is connected between the sixth node N6 and the second node N2.

[0129] The first masking circuit MSC11 includes masking transistors MT11, MT12, and MT13. In response to the first masking signal MS1 received through the fourth input terminal IN4, the first masking circuit MSC11 stops (or masks) the output of the first scan signal GIj.

[0130] Masking transistor MT11 is connected between the second voltage terminal V2 and the ninth node N9 (in other words, the "first masking node"), and includes a gate electrode connected to the third node N3. Masking transistor MT12 is connected between the ninth node N9 and the first output terminal OUT1, and includes a gate electrode connected to the fourth input terminal IN4. Masking transistor MT13 is connected between the first output terminal OUT1 and the first voltage terminal V1, and includes a gate electrode connected to the second node N2.

[0131] The second masking circuit MSC12 includes masking transistors MT1 and MT2. In response to the second masking signal MS2 received through the fifth input terminal IN5, the second masking circuit MSC12 stops (or masks) the output of the second scan signal GCj-4 by discharging the first node N1.

[0132] Masking transistor MT1 is connected between the first node N1 and the eighth node N8 (in other words, the "second masking node"), and includes a gate electrode connected to the fifth input terminal IN5. Masking transistor MT2 is connected between the eighth node N8 and the first voltage terminal V1, and includes a gate electrode connected to the second output terminal OUT2.

[0133] Typically, when the DC drive circuit is designed to output a first scan signal GIj and a second scan signal GCj, it can be designed so that switching between either the first scan signal GIj or the second scan signal GCj (e.g., the first scan signal GIj) is based on the other to be output (e.g., the second scan signal GCj). In this case, the second scan signal GCj can be output at its normal voltage level, but the voltage level of the first scan signal GIj can be reduced. When the voltage level of the first scan signal GIj is reduced, Figure 3 The fourth transistor T4 shown may not be fully turned on, and therefore may not guarantee the proper operation of pixel PXij.

[0134] Conversely, in an embodiment of the present invention, when the first masking signal MS1 is at a low level, Figure 8 The first masking circuit MSC11 shown can output a second voltage VGH as the first scan signal GIj through masking transistors MT11 and MT12. Therefore, the voltage level of the first scan signal GIj in the embodiment can be kept constant.

[0135] Figure 9 This is an example shown Figure 8 The timing diagram shows the operation of the j-th drive level STj in the normal mode of the first scan drive circuit SD1 shown.

[0136] Reference Figure 8 and Figure 9 The first clock signal CLK1 and the second clock signal CLK2 have the same frequency and transition to an active level (e.g., low level) during different horizontal periods.

[0137] During normal N-MODE, the first masking signal MS1 may be held at a first level (e.g., low level), and the second masking signal MS2 may be held at a second level (e.g., high level).

[0138] During normal N-MODE, since the masking transistor MT12 in the first masking circuit MSC11 is kept on by the low-level first masking signal MS1, the first scan signal GIj output from the first output terminal OUT1 can be determined based on the signal levels of the second node N2 and the third node N3. The signal at the second node N2 can be the "first node signal", and the signal at the third node N3 can be the "second node signal".

[0139] During normal mode N-MODE, the first node N1 and the eighth node N8 remain electrically isolated because the masking transistor MT1 in the second masking circuit MSC12 is kept off by the high-level second masking signal MS2.

[0140] When the first clock signal CLK1 is low during the (j-5)th level period Hj-5, transistor NT1 is turned on. As transistor NT1 is turned on, the first node N1 and the second node N2 increase to a high level according to the voltage level of the carry signal CRj (e.g., 8 volts (V)). When the first clock signal CLK1 is low, transistor NT5 is turned on to discharge the fourth node N4 and the fifth node N5 to a low level of the first voltage VGL (e.g., -6V). On the other hand, as the voltage level at the first node N1 increases, transistor NT8 is turned off.

[0141] When the second clock signal CLK2 transitions to a low level during the (j-4)th horizontal period Hj-4, transistor NT6 turns on, discharging the charge at the third node N3 to the second input terminal IN2 through transistors NT6 and NT7. Consequently, the signal at the third node N3 (the second node signal) transitions to a low level. As the signal at the third node N3 transitions to a low level, transistor NT9 turns on, and thus the high-level second scan signal GCj-4 can be output through the second output terminal OUT2. Here, since the signal at the first node N1 is high, the masking transistor MT13 is off. Since the signal at the third node N3 is low, the masking transistor MT11 turns on, and the high-level first scan signal GIj can be output through the first output terminal OUT1.

[0142] When the carry signal CRj transitions from high to low during the j-th level time period Hj, and the first clock signal CLK1 is low during the (j+1)-th level time period Hj+1, transistor NT1 is turned on, and the voltage levels of the first node N1 and the second node N2 decrease to the voltage level of the carry signal CRj (e.g., -6V). As transistor NT10 turns on in response to the low-level signal of the second node N2, a low-level (e.g., -6V) second scan signal GCj-4 can be output. Additionally, when the masking transistor MT13 turns on in response to the low-level signal of the second node N2, a low-level (e.g., -6V) first scan signal GIj can be output.

[0143] As the second clock signal CLK2 goes low during the (j+2)th level period Hj+2, transistor NT3 turns on, and the voltage levels of the first node N1 and the second node N2 decrease to a lower level (e.g., -15V). Consequently, the voltage levels of the first scan signal GIj and the second scan signal GCj-4 can decrease to the level of the first voltage VGL (e.g., -8V).

[0144] Figure 10 This is an example shown Figure 8 The timing diagram shows the low-power mode operation of the j-th drive stage STj in the first scan drive circuit SD1 shown.

[0145] Reference Figure 8 and Figure 10 In low-power mode, the first masking signal MS1 is applied to the second display area DA2, which is to be driven at a low frequency (e.g., 1 Hz). Figure 1 The first masking signal MS1 changes from a low level to a high level at the starting point of the first masking signal MS1, and the second masking signal MS2 changes from a high level to a low level. In an embodiment, the first masking signal MS1 first changes from a low level to a high level, and then the second masking signal MS2 may change from a high level to a low level after four horizontal time periods 4H.

[0146] When the first masking signal MS1 changes to a high level, the masking transistor MT12 in the first masking circuit MSC11 is turned off. Even when the masking transistor MT12 is turned off, the first scan signals GIj-2 and GIj-1, which have already changed to a high level, can remain at a high level due to the capacitive components on the first scan lines GILj-2 and GILj-1. Regardless of the voltage level of the third node N3, the first scan signal GIj, which has not yet changed to a high level, cannot change to a high level and remains at a low level.

[0147] When the second masking signal MS2 goes low, the masking transistor MT1 in the second masking circuit MSC12 turns on, electrically connecting the first node N1 and the eighth node N8. Since the masking transistor MT2 in the second masking circuit MSC12 operates in response to the second scan signal GCj-4 output to the second output terminal OUT2, even when the second masking signal MS2 goes low, the second scan signals GCj-6, GCj-5, and GCj-4, which have already gone high, can remain at a high level.

[0148] When the second masking signal MS2 goes low, the driver stage STj+4 receives the low-level second scan signal GCj-1 as the carry signal CRj, and therefore the driver stage STj+4 can output the low-level second scan signal GCj.

[0149] Refer again Figure 3 The pixel PXij in the j-th row is connected to the j-th first scan line GILj and the j-th second scan line GCLj. When attempting to drive the pixel in the (j-1)-th row at a normal frequency (e.g., 120 Hz) and the pixel in the j-th row at a low frequency (e.g., 1 Hz), the (j-1)-th first scan signal GIj-1 and the (j-1)-th second scan signal GCj-1 will be output at the normal frequency.

[0150] Figure 8 The j-th drive stage STj shown outputs the j-th first scan signal GIj to the first output terminal OUT1, and outputs the (j-4)-th second scan signal GCj-4 to the second output terminal OUT2.

[0151] therefore, Figure 2 The drive controller 100 shown changes the first masking signal MS1 from low to high during the (j-4)th horizontal time period Hj-4, and then changes the second masking signal MS2 from high to low during the j-th horizontal time period Hj. In this way, the drive controller 100 can set the signal levels of the first masking signal MS1 and the second masking signal MS2 according to the connection relationship between pixel PXij and the scan line.

[0152] Figure 11 This is a circuit diagram illustrating the j-th drive level STaj in the first scan drive circuit SD1 according to another embodiment of the concept of the present invention. Hereinafter, the j-th drive level STaj is referred to as drive level STaj.

[0153] Reference Figure 11 The driver stage STaj includes a driver circuit DC, a first masking circuit MSC21, and a second masking circuit MSC22. Figure 11 The driving circuit DC and the second masking circuit MSC22 shown may include, with Figure 8 The driving circuit DC of the driving stage STj shown has the same circuit configuration as the second masking circuit MSC12. The first masking circuit MSC21 of the driving stage STj is different. Figure 8 The first masking circuit MSC11 of the driver stage STj is included. The driver stage STj also includes a sixth input terminal IN6 for receiving the third masking signal MS1B. The third masking signal MS1B can be a signal complementary to the first masking signal MS1. That is, the first masking signal MS1 and the third masking signal MS1B have opposite signal modes, such as... Figure 12 As shown in the image.

[0154] The first masking circuit MSC21 includes masking transistors MT21, MT22, MT23, and MT24. In response to the first masking signal MS1 received through the fourth input terminal IN4 and the third masking signal MS1B received through the sixth input terminal IN6, the first masking circuit MSC21 stops (or masks) the output of the first scan signal GIj.

[0155] The masking transistor MT21 is connected to the second voltage terminal V2 and the tenth node N10 (this can be Figure 11 The masking transistor MT21 is connected between the "first masking node" and the "third masking node" (N2), and includes a gate electrode connected to the sixth input terminal IN6. The masking transistor MT22 is connected between the third node N3 and the tenth node N10, and includes a gate electrode connected to the fourth input terminal IN4. The masking transistor MT23 is connected between the second voltage terminal V2 and the first output terminal OUT1, and includes a gate electrode connected to the tenth node N10. The masking transistor MT24 is connected between the first output terminal OUT1 and the first voltage terminal V1, and includes a gate electrode connected to the second node N2.

[0156] Figure 12 Exemplary examples illustrate the first to third masking signals in normal mode and low power mode, as well as the signals from... Figure 5 The first scan signal GI1 to GIn is output by the first scan drive circuit SD1 shown in the figure.

[0157] Reference Figure 5 , Figure 11 and Figure 12 During normal mode N-MODE, the first masking signal MS1 may be maintained at a first level (e.g., low level), and the second masking signal MS2 and the third masking signal MS1B may be maintained at a second level (e.g., high level).

[0158] During normal N-MODE, the driver stage STaj operates in response to a low-level first masking signal MS1 and a high-level second masking signal MS2 and a high-level third masking signal MS1B.

[0159] When the first masking signal MS1 is low and the third masking signal MS1B is high, the masking transistor MT22 in the first masking circuit MSC21 remains on, and the masking transistor MT21 remains off. Therefore, the first scan signal GIj output from the first output terminal OUT1 can be determined based on the signal levels of the third node N3 and the second node N2.

[0160] During normal mode N-MODE, the first node N1 and the eighth node N8 remain electrically isolated because the masking transistor MT1 in the second masking circuit MSC22 is kept off by the high-level second masking signal MS2.

[0161] Therefore, during normal mode N-MODE, the first scan signals GI1 to GI3840 can be driven sequentially at high levels.

[0162] During low-power mode (L-MODE), when the first masking signal MS1 goes high and the third masking signal MS1B goes low, masking transistor MT22 in the first masking circuit MSC21 is turned off, and masking transistor MT21 is turned on. Through the turned-on masking transistor MT21, the second voltage VGH is transmitted to the tenth node N10, thus turning off masking transistor MT23. When the signal at the second node N2 is low, masking transistor MT24 is turned on to output a low-level (e.g., -6V) first scan signal GIj.

[0163] Therefore, when the first masking signal MS1 changes to a high level and the third masking signal MS1B changes to a low level in the low power mode L-MODE, the first scan signals GI1 to GI1920 can be not driven at a high level and remain at a low level.

[0164] When the first masking signal MS1 is at a low level Figure 8 The first masking circuit MSC11 shown can output a second voltage VGH as the first scan signal GIj through masking transistors MT11 and MT12. Therefore, the voltage level of the first scan signal GIj can remain constant. However, the size of the masking transistor MT12 needs to be large enough so that the masking transistor MT12 can be fully turned on / off in response to the signal at the third node N3.

[0165] On the contrary, Figure 11In the first masking circuit MSC21 shown, the signal at the third node N3 can be provided to the gate electrode of the masking transistor MT23 through the masking transistor MT22, and the second voltage VGH can be provided to the gate electrode of the masking transistor MT23 through the masking transistor MT21. Therefore, the size of the masking transistor MT23 can be smaller than that of the first node N3. Figure 8 The dimensions of the masking transistor MT12 are shown.

[0166] Figure 13 This is a circuit diagram illustrating the j-th drive stage STbj in a first scan drive circuit SD1 according to yet another embodiment of the concept of the present invention. Hereinafter, the j-th drive stage STbj is referred to as drive stage STbj.

[0167] Reference Figure 13 The drive stage STbj includes a drive circuit DC, a first masking circuit MSC31, and a second masking circuit MSC32. Figure 13 The driving circuit DC of the driving stage STbj shown and the second masking circuit MSC32 may include, with Figure 8 The driving circuit DC of the driving stage STj shown has the same circuit configuration as the second masking circuit MSC12. The first masking circuit MSC31 of the driving stage STbj is different. Figure 8 The first masking circuit MSC11 of the intermediate drive stage STj.

[0168] The first masking circuit MSC31 includes masking transistors MT31, MT32, MT33, MT34, and MT35. In response to the first masking signal MS1 received through the fourth input terminal IN4, the first masking circuit MSC31 stops (or masks) the output of the first scan signal GIj.

[0169] The masking transistor MT31 is connected between the second voltage terminal V2 and the ninth node N9, and includes a gate electrode connected to the third node N3. The masking transistor MT32 is connected between the ninth node N9 and the first output terminal OUT1, and includes a gate electrode connected to the fourth input terminal IN4.

[0170] Masking transistors MT33 and MT34 are connected in series between the first output terminal OUT1 and the first voltage terminal V1. Masking transistor MT33 includes a gate electrode connected to the fifth node N5, and masking transistor MT34 includes a gate electrode connected to the first output terminal OUT1. Masking transistor MT35 is connected between the first output terminal OUT1 and the first voltage terminal V1, and includes a gate electrode connected to the second node N2.

[0171] In low-power mode (L-MODE), when the first scan signal GIj is low, the masking transistor MT35 is turned off when the signal at the second node N2 is in a floating state. Masking transistors MT33 and MT34 can discharge the first output terminal OUT1 to the first voltage VGL in response to the signal at the fifth node N5 (here, the signal at the fifth node N5 can be the "third node signal") and the first scan signal GIj. Therefore, in low-power mode (L-MODE), the first scan signal GIj can be stably maintained at a low level.

[0172] Figure 14 This is a circuit diagram illustrating the j-th drive stage STcj in a first scan drive circuit SD1 according to yet another embodiment of the concept of the present invention. Hereinafter, the j-th drive stage STcj is referred to as drive stage STcj.

[0173] Reference Figure 14 The driver stage STcj includes a driver circuit DC, a first masking circuit MSC41, and a second masking circuit MSC42. Figure 14 The driving circuit DC of the driving stage STcj and the second masking circuit MSC42 shown may include, with Figure 8 The driving circuit DC and the second masking circuit MSC12 of the driving stage STj shown have the same circuit configuration. The first masking circuit MSC41 of the driving stage STj is different. Figure 8 The first masking circuit MSC11 of the drive stage STj. The drive stage STj also includes a sixth input terminal IN6 for receiving a third masking signal MS1B. The third masking signal MS1B can be a signal complementary to the first masking signal MS1.

[0174] The first masking circuit MSC41 includes masking transistors MT41, MT42, MT43, MT44, MT45, and MT46. In response to a first masking signal MS1 received via the fourth input terminal IN4 and a third masking signal MS1B received via the sixth input terminal IN6, the first masking circuit MSC41 stops (or masks) the output of the first scan signal GIj.

[0175] Masking transistor MT41 is connected between the second voltage terminal V2 and the tenth node N10, and includes a gate electrode connected to the sixth input terminal IN6. Masking transistor MT42 is connected between the third node N3 and the tenth node N10, and includes a gate electrode connected to the fourth input terminal IN4. Masking transistor MT43 is connected between the second voltage terminal V2 and the first output terminal OUT1, and includes a gate electrode connected to the tenth node N10.

[0176] Masking transistors MT44 and MT45 are connected in series between the first output terminal OUT1 and the first voltage terminal V1. Masking transistor MT44 includes a gate electrode connected to the fifth node N5, and masking transistor MT45 includes a gate electrode connected to the first output terminal OUT1. Masking transistor MT46 is connected between the first output terminal OUT1 and the first voltage terminal V1, and includes a gate electrode connected to the second node N2.

[0177] The size of the masking transistor MT43 in the first masking circuit MSC41 can be smaller than that of the masking transistor MT43. Figure 8 The dimensions of the masking transistor MT12 are shown.

[0178] In low-power mode (L-MODE), when the first scan signal GIj is low, the masking transistor MT46 is turned off when the signal at the second node N2 is in a floating state. Masking transistors MT44 and MT45 can discharge the first output terminal OUT1 to the first voltage VGL in response to the signal at the fifth node N5 and the first scan signal GIj. Therefore, in low-power mode (L-MODE), the first scan signal GIj can be stably maintained at a low level.

[0179] In this implementation, the display device can drive a first display area displaying moving images and a second display area displaying still images at different frequencies. Specifically, the driving frequency of the second display area displaying still images can be lower than the driving frequency of the first display area displaying moving images, thus reducing power consumption. Furthermore, even when a masking circuit for masking the scan signal output is included, a stable level scan signal can be output.

[0180] Although exemplary embodiments of the invention have been described, it should be understood that the invention is not limited to these exemplary embodiments, but rather various changes and modifications can be made by those skilled in the art within the spirit and scope of the invention as claimed below. Furthermore, the embodiments disclosed in this invention concept are not intended to limit the technical spirit of the invention concept, and the scope of protection of the invention should be interpreted based on the appended claims, and it should be understood that all technical spirit included within its equivalent scope is included within the scope of protection of the invention.

Claims

1. A scan driving circuit comprising: a driving circuit that outputs a first node signal, a second node signal, a third node signal, and a second scan signal in response to a clock signal and a carry signal; a first masking circuit that outputs a first scan signal in response to a first masking signal, the second node signal, and the third node signal; and a second masking circuit that discharges the first node signal to a first voltage in response to a second masking signal and the second scan signal, wherein the driving circuit comprises: a first transistor that transfers the carry signal as the first node signal in response to a first clock signal among the clock signal; and a second transistor that transfers a second voltage as the second scan signal in response to the third node signal.

2. The scan driving circuit according to claim 1, further comprising: a first output terminal connected to a first scan line and outputting the first scan signal; and a second output terminal connected to a second scan line and outputting the second scan signal. the first masking circuit comprises:

3. The scan driving circuit according to claim 2, wherein a first masking transistor connected between a second voltage terminal that receives the second voltage and a first masking node, and including a gate electrode that receives the third node signal; a second masking transistor connected between the first masking node and the first output terminal, and including a gate electrode that receives the first masking signal; and a third masking transistor connected between the first output terminal and a first voltage terminal that receives the first voltage, and including a gate electrode that receives the second node signal. the driving circuit outputs a fifth node signal to a fifth node in response to the clock signal, the carry signal, and the first node signal, and 4. The scan driving circuit according to claim 3, wherein the first masking circuit further comprises a fourth masking transistor and a fifth masking transistor connected in series between the first output terminal and the first voltage terminal, wherein the fourth masking transistor includes a gate electrode connected to the fifth node, and the fifth masking transistor includes a gate electrode connected to the first output terminal. the second masking circuit comprises:

5. The scan driving circuit according to claim 2, wherein a first masking transistor connected between the first transistor and a second masking node, and including a gate electrode that receives the second masking signal; and a second masking transistor connected between the second masking node and a first voltage terminal that receives the first voltage, and including a gate electrode connected to the second output terminal. the first masking circuit further receives a third masking signal.

6. The scan driving circuit according to claim 2, wherein the first masking circuit comprises:

7. The scan driving circuit according to claim 6, wherein a first masking transistor connected between a second voltage terminal that receives the second voltage and a first masking node, and including a gate electrode that receives the third masking signal; ​ a second masking transistor connected between a third node transmitting the third node signal and the first masking node, and including a gate electrode receiving the first masking signal; a third masking transistor connected between the second voltage terminal and the first output terminal, and including a gate electrode connected to the first masking node; and a fourth masking transistor connected between the first output terminal and a first voltage terminal receiving the first voltage, and including a gate electrode connected to a second node for transmitting the second node signal.

8. The scan driving circuit according to claim 7, wherein the third masking signal is complementary to the first masking signal.

9. The scan driving circuit according to claim 7, wherein the drive circuit outputs a fifth node signal to a fifth node in response to the clock signal, the carry signal, and the first node signal, and the first masking circuit further includes a fifth masking transistor and a sixth masking transistor connected in series between the first output terminal and the first voltage terminal, wherein the fifth masking transistor includes a gate electrode connected to the fifth node, and the sixth masking transistor includes a gate electrode connected to the first output terminal.

10. A display device, comprising: a display panel including a plurality of pixels connected to a plurality of data lines, a plurality of first scan lines, and a plurality of second scan lines, respectively, the display panel being divided into a first display area and a second display area; a data drive circuit driving the plurality of data lines; a scan drive circuit driving the plurality of first scan lines and the plurality of second scan lines; and a drive controller receiving an image signal and a control signal, and controlling the data drive circuit and the scan drive circuit such that an image corresponding to the image signal is displayed on the display panel, wherein the drive controller outputs a first masking signal and a second masking signal indicating a start point of the second display area, wherein the scan drive circuit includes a plurality of drive stages, wherein each of the plurality of drive stages outputs a first scan signal to a corresponding first scan line among the plurality of first scan lines, and outputs a second scan signal to a corresponding second scan line among the plurality of second scan lines, wherein the each of the plurality of drive stages includes: a drive circuit outputting a first node signal, a second node signal, a third node signal, and the second scan signal in response to a clock signal and a carry signal; a first masking circuit outputting the first scan signal in response to the first masking signal, the second node signal, and the third node signal; and a second masking circuit discharging the first node signal to a first voltage in response to the second masking signal and the second scan signal, wherein the drive circuit includes: a first transistor transmitting the carry signal as the first node signal in response to a first clock signal among the clock signal; and a second transistor outputting the second node signal in response to a second clock signal among the clock signal. a second transistor that, in response to the third node signal, transfers a second voltage as the second scan signal.

11. The display device of claim 10, wherein, In response to the first mask signal and the second mask signal, the scan driving circuit drives first scan lines and second scan lines corresponding to the first display region among the plurality of first scan lines and the plurality of second scan lines at a first driving frequency, and drives first scan lines and second scan lines corresponding to the second display region among the plurality of first scan lines and the plurality of second scan lines at a second driving frequency, and the second driving frequency is lower than the first driving frequency.

12. The display device of claim 10, wherein, The second scan signal output from a jth driving stage among the plurality of driving stages is provided as the carry signal of a (j+1)th driving stage, where j is a natural number.

13. The display device of claim 10, wherein, Each of the plurality of driving stages further includes: a first output terminal connected to the first scan line and outputting the first scan signal; and a second output terminal connected to the second scan line and outputting the second scan signal.

14. The display device of claim 13, wherein, The first mask circuit includes: a first mask transistor connected between a second voltage terminal receiving the second voltage and a first mask node, and including a gate electrode receiving the third node signal; a second mask transistor connected between the first mask node and the first output terminal, and including a gate electrode receiving the first mask signal; and a third mask transistor connected between the first output terminal and a first voltage terminal receiving the first voltage, and including a gate electrode receiving the first node signal.

15. The display device of claim 14, wherein, The driving circuit outputs a fifth node signal to a fifth node in response to the clock signal, the carry signal, and the first node signal, and The first mask circuit further includes a fourth mask transistor and a fifth mask transistor connected in series between the first output terminal and the first voltage terminal, wherein the fourth mask transistor includes a gate electrode connected to the fifth node, and the fifth mask transistor includes a gate electrode connected to the first output terminal.

16. The display device of claim 13, wherein, The second mask circuit includes: a first mask transistor connected between the first transistor and a second mask node, and including a gate electrode receiving the second mask signal; and a second mask transistor connected between the second mask node and a first voltage terminal receiving the first voltage, and including a gate electrode connected to the second output terminal.

17. The display device of claim 13, wherein, The first mask circuit includes: a first mask transistor connected between a second voltage terminal receiving the second voltage and a first mask node, and including a gate electrode receiving a third mask signal; a second mask transistor connected between a third node transferring the third node signal and the first mask node, and including a gate electrode receiving the first mask signal; a third masking transistor connected between the second voltage terminal and the first output terminal and including a gate electrode connected to the first masking node; and a fourth masking transistor connected between the first output terminal and a first voltage terminal receiving the first voltage and including a gate electrode connected to a first node for passing the first node signal.

18. The display device of claim 17, wherein, the drive circuit outputs a fifth node signal to a fifth node in response to the clock signal, the carry signal, and the first node signal, and the first masking circuit further includes a fifth masking transistor and a sixth masking transistor connected in series between the first output terminal and the first voltage terminal, wherein the fifth masking transistor includes a gate electrode connected to the fifth node, and the sixth masking transistor includes a gate electrode connected to the first output terminal.

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