Modular, frequency-flexible superconducting quantum processor architecture

Abstract

A modular superconducting quantum processor includes: a first superconducting chip including a first plurality of qubits and a second plurality of qubits, the first plurality of qubits each substantially having a first resonant frequency, the second plurality of qubits each substantially having a second resonant frequency, the first resonant frequency being different from the second resonant frequency; and a second superconducting chip including a third plurality of qubits and a fourth plurality of qubits, the third plurality of qubits each substantially having the first resonant frequency, the fourth plurality of qubits each substantially having the second resonant frequency. The quantum processor further includes an interposer chip connected to the first superconducting chip and the second superconducting chip. The interposer chip has an interposer coupler element configured to couple the second plurality of qubits to the fourth plurality of qubits.

Description

Background Art

[0001] The present invention relates to a superconducting quantum processor, and more particularly to a modular superconducting quantum processor, a quantum computer using the modular superconducting quantum processor, and a method for manufacturing the modular superconducting quantum processor.

[0002] Quantum computing is based on the reliable control of quantum bits (referred to as qubits throughout this article). The basic operations required to implement quantum algorithms are a set of single-qubit operations and two-qubit operations that establish a correlation between two separated qubits. In order to reach the error threshold of quantum computing and realize reliable quantum simulation, it may be necessary to realize high-fidelity two-qubit operations.

[0003] A superconducting quantum processor (or superconducting qubit) comprises a superconducting metal (e.g., Al, Nb, etc.) on an insulating substrate (e.g., Si or high resistivity Si, Al2O3, etc.). A quantum processor is typically a planar two-dimensional lattice structure of individual qubits connected by couplers with different lattice symmetries (e.g., square, hexagonal, etc.), and a readout structure located on a flip chip. The coupler can be composed of a capacitor, a resonator, a coil, or any microwave component that provides coupling between qubits.

[0004] In order to connect input / output signal cables or lines, the quantum processor is packaged in a substrate, such as a printed circuit board (PCB). The material used for the PCB can be, for example, FR4 laminate, ceramic, etc. FR4 is a multi-purpose glass reinforced epoxy laminate material. FR4 is a composite material with woven fiberglass cloth and epoxy resin adhesive. The name FR4 was created by the National Electrical Manufacturers Association (NEMA).

[0005] As quantum processes scale up, since future quantum computers may use large numbers of qubits (hundreds to thousands or more), there are a number of issues that may need to be addressed that may arise due to the scaling factor. The various issues that may arise include spurious resonant modes that may be related to chip size, frequency arrangements between qubits that cause crosstalk, and limited manufacturing technology to handle large and growing chip sizes.

[0006] Conventional flip-chip technology can be used with qubit chips. However, conventional flip-chip methods do not provide frequency flexibility when connecting qubits. Therefore, there remains a need for improved quantum processors and methods of producing or assembling quantum processors. Summary of the invention

[0007] One aspect of the present invention is to provide a modular superconducting quantum processor. The modular superconducting quantum processor includes: a first superconducting chip, which includes a first plurality of qubits each substantially having a first resonant frequency and a second plurality of qubits each substantially having a second resonant frequency, the first resonant frequency being different from the second resonant frequency; a second superconducting chip, which includes a third plurality of qubits each substantially having the first resonant frequency and a fourth plurality of qubits each substantially having the second resonant frequency; and an interposer chip connected to the first superconducting chip and the second superconducting chip, wherein the interposer chip includes an interposer coupler element configured to couple the second plurality of qubits substantially having the second resonant frequency to the fourth plurality of qubits substantially having the second resonant frequency.

[0008] Another aspect of the present invention is to provide a method for manufacturing a modular superconducting quantum processor. The method includes: providing a first superconducting chip, the first superconducting chip including a first plurality of qubits each having a substantially first resonant frequency and a second plurality of qubits each having a substantially second resonant frequency, the first resonant frequency being different from the second resonant frequency; providing a second superconducting chip, the second superconducting chip including a third plurality of qubits each having a substantially first resonant frequency and a fourth plurality of qubits each having a substantially second resonant frequency; providing an interposer chip including an interposer coupler element configured to couple the second plurality of qubits having a substantially second resonant frequency to the fourth plurality of qubits having a substantially second resonant frequency; mounting the first superconducting chip and the second superconducting chip on a substrate; and mounting the interposer chip on at least a portion of the first superconducting chip, on at least a portion of the second superconducting chip, and on at least a portion of the substrate, such that the first plurality of qubits, the second plurality of qubits, the third plurality of qubits, and the fourth plurality of qubits are accessible from a side opposite to a side facing the substrate.

[0009] Another aspect of the present invention is to provide a quantum computer including a modular superconducting quantum processor. The modular superconducting quantum processor includes: a first superconducting chip including a first plurality of qubits each substantially having a first resonant frequency and a second plurality of qubits each substantially having a second resonant frequency, the first resonant frequency being different from the second resonant frequency; a second superconducting chip including a third plurality of qubits each substantially having the first resonant frequency and a fourth plurality of qubits each substantially having the second resonant frequency; and an interposer chip connected to the first superconducting chip and the second superconducting chip, wherein the interposer chip includes an interposer coupler element configured to couple the second plurality of qubits substantially having the second resonant frequency to the fourth plurality of qubits substantially having the second resonant frequency.

[0010] BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present disclosure, as well as the methods of operation and function of the related elements of the structure and the economy of combination and manufacture of the parts, will become more apparent upon consideration of the following description and appended claims with reference to the accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate corresponding parts throughout the several figures. It is to be expressly understood, however, that the drawings are for illustration and description purposes only and are not intended as a definition of the limits of the invention.

[0012] Figure 1 is a schematic top view of a modular superconducting quantum processor according to an embodiment of the present invention;

[0013] Figure 2 is a schematic top view of a modular superconducting quantum processor 200 according to another embodiment of the present invention;

[0014] Figure 3A According to an embodiment of the present invention Figure 1 A schematic cross-sectional view of a modular superconducting quantum processor shown in FIG.

[0015] Figure 3B According to another embodiment of the present invention, Figure 1 A schematic cross-sectional view of a modular superconducting quantum processor shown in FIG.

[0016] Figure 4A According to an embodiment of the present invention Figure 3A and 3B A detailed schematic side view of the first or second superconducting chip shown in ;

[0017] Figure 4B is a top view of a first or second superconducting chip according to an embodiment of the present invention;

[0018] Figure 5A According to an embodiment of the present invention Figure 3A and Figure 3B Detailed schematic side view of the interposer chip shown in ;

[0019] Figure 5B is a top view of an interposer chip according to an embodiment of the present invention;

[0020] Figure 6 is a schematic diagram of a quantum computer according to an embodiment of the present invention; and

[0021] Figure 7 is a flow chart of a method for manufacturing a quantum processor according to an embodiment of the present invention. Specific embodiments

[0022] Figure 11 is a schematic top view of a modular superconducting quantum processor 100 according to an embodiment of the present invention. The modular superconducting quantum processor 100 includes a first superconducting chip 102 and a second superconducting chip 104. The first superconducting chip 102 includes a first plurality of qubits 102A and a second plurality of qubits 102B, each of the first plurality of qubits substantially having a first resonant frequency, and each of the second plurality of qubits substantially having a second resonant frequency. The first resonant frequency is different from the second resonant frequency. The terms "first resonant frequency" and "second resonant frequency" should be understood to broadly represent the first resonant frequency range and the second resonant frequency range, respectively. In an embodiment, for example, the second resonant frequency may be in the range of 4.8-5.0 GHz, and the first resonant frequency may be in the range of 5.6-5.8 GHz, or vice versa. The second superconducting chip 104 includes a third plurality of qubits 104A and a fourth plurality of qubits 104B, each of the third plurality of qubits 104A substantially having a first resonant frequency, and each of the fourth plurality of qubits 104B substantially having a second resonant frequency.

[0023] In an embodiment, first plurality of qubits 102A and third plurality of qubits 104A are arranged to have frequencies to implement a cross-resonance (CR) gate. In an embodiment, second plurality of qubits 102B and fourth plurality of qubits 104B include tunable gates or resonant induced phase (RIP) gates, or both. In another embodiment, second plurality of qubits 102B and fourth plurality of qubits 104B include tunable qubits (e.g., asymon, WTQ, etc.). However, in addition to having different frequencies, the qubits may also be made of different materials and / or have different structures, or both.

[0024] In an embodiment, second plurality of qubits 102B is arranged at a periphery of first superconducting chip 102 and fourth plurality of qubits 104B is arranged at a periphery of second superconducting chip 104 to enable coupling between second plurality of qubits 102B and fourth plurality of qubits 104B.

[0025] Modular superconducting quantum processor 100 also includes an interposer chip 106 connected to first superconducting chip 102 and to second superconducting chip 104. Interposer chip 106 has an interposer coupler element 106A, which is configured to couple a second plurality of qubits 102B having substantially a second resonant frequency to a fourth plurality of qubits 104B having substantially a second resonant frequency. In an embodiment, interposer coupler element 106A includes microwave lines 106B configured to couple the second plurality of qubits 102B to the fourth plurality of qubits 104B. In an embodiment, interposer coupler element 106A further includes drive lines 106C. Drive lines 106C can also be used to further couple the second plurality of qubits 102B to the fourth plurality of qubits 104B.

[0026] In an embodiment, first superconducting chip 102 further includes a first plurality of coupling elements 102C configured to couple first plurality of qubits 102A with second plurality of qubits 102B. In an embodiment, second superconducting chip 104 further includes a second plurality of coupling elements 104C configured to couple third plurality of qubits 104A with fourth plurality of qubits 104B. In an embodiment, first plurality of coupling elements 102C and / or second plurality of coupling elements 104C include resonators, direct capacitive couplers, or tunable frequency elements (e.g., superconducting quantum interference devices (SQUIDs) etc.), or any combination thereof.

[0027] In an embodiment, first superconducting chip 102 and second superconducting chip 104 include a plurality of readout elements 108A, 108B for reading out each of first plurality of qubits 102A, each of second plurality of qubits 102B, each of third plurality of qubits 104A, or each of fourth plurality of qubits 104B, or for reading out any combination thereof. In an embodiment, first superconducting chip 102 and second superconducting chip 104 may further include grounding elements 110A, 110B, which are configured to connect ground planes of first superconducting chip 102 and second superconducting chip 104.

[0028] In an embodiment, the interposer chip 106 may further include a ground element 106D configured to connect a ground plane on the interposer chip 106 .

[0029] Figure 2 1 is a schematic top view of a modular superconducting quantum processor 200 according to another embodiment of the present invention. In this embodiment, the modular superconducting quantum processor 200 includes a plurality of first superconducting chips 102h and a plurality of second superconducting chips 104, wherein the first superconducting chip includes a first plurality of qubits 102A and a second plurality of qubits 102B (in Figure 1), the second superconducting chip includes a third plurality of qubits 104A and a fourth plurality of qubits 104B (shown in Figure 1 ). The modular superconducting quantum processor 200 further includes an interposer chip 106, which is configured to be connected to the plurality of first superconducting chips 102 and the plurality of second superconducting chips 104. Therefore, the interposer chip 106 can connect more than two chips 102, 104 or more than two chips.

[0030] Figure 3A is a schematic cross-sectional view of a modular superconducting quantum processor 100 according to an embodiment of the present invention. Figure 2 In, use Figure 1 The same reference numerals in the drawings represent the same components of the modular superconducting quantum processor 100. Figure 2 As shown, modular superconducting quantum processor 100 further includes substrate 120. First and second superconducting chips 102 and 104 are mounted on substrate 120. In an embodiment, first plurality of qubits 102A, second plurality of qubits 102B, third plurality of qubits 104A, and fourth plurality of qubits 104B are connected to substrate 120 through a plurality of through-holes 122 and solder bumps 124. In an embodiment, plurality of through-holes 122 are configured to input and output signals to first plurality of qubits 102A, second plurality of qubits 102B, third plurality of qubits 104A, and fourth plurality of qubits 104B through substrate 120.

[0031] In an embodiment, the first superconducting chip 102 and the second superconducting chip 104 are mounted on the substrate 120 so as to allow free access to the first plurality of qubits 102A, the second plurality of qubits 102B, the third plurality of qubits 104A, and the fourth plurality of qubits 104B from a side 126 of the first and second superconducting chips 102, 104 opposite to a side 128 of the first and second superconducting chips 102, 104 facing the substrate 120. As a result, unlike a flip chip, this structure has the benefit of providing access to the top of the superconducting chips 102, 104. This is possible because the first superconducting chip 102 and the second superconducting chip 104 are connected by through-holes 122 or bump-bonded to the substrate 120 using solder bumps 124. As a result, by providing access to the qubits from the top of the superconducting chip, modification of the qubits is allowed, for example, by frequency tuning these qubit devices (for example, by using LASIQ and / or magnetic techniques).

[0032] In an embodiment, input and output signals come from a side 128 (back side) facing the substrate 120 through a via 122. In an embodiment, a first plurality of qubits 102A, a second plurality of qubits 102B of a first superconducting chip 102, and a third plurality of qubits 14A and a fourth plurality of qubits 104B of a second superconducting chip 104 are provided on insulating (non-conductor) substrates 102S, 104S, respectively. The insulating substrate may be made of, for example, high resistivity Si, Al2O3, etc. In an embodiment, the via 122 is formed in an insulating substrate (e.g., high resistivity Si, Al2O3). When the via 122 is formed in a Si substrate, the via is referred to as a through silicon via (TSV).

[0033] In an embodiment, first superconducting chip 102, second superconducting chip 104, and interposer chip 106 are configured and arranged to provide a modular system that enables direct access to each of first plurality of qubits 102A, second plurality of qubits 102B, third plurality of qubits 104A, and fourth plurality of qubits 104B. In an embodiment, interposer chip 106 is connected to first and second superconducting chips 102, 104 using solder bumps 130 and to substrate 120 using solder bumps 132.

[0034] Figure 3B is a schematic cross-sectional view of a modular superconducting quantum processor 100 according to another embodiment of the present invention. Figure 3B The superconducting quantum processor 100 shown in FIG. 1 is similar in many respects to the Figure 3A Therefore, the description of the common features will not be repeated here. Figure 3A and Figure 3B One difference between the illustrated embodiments is the addition of support features 140 to provide additional support to the first and second superconducting chips 102 and 104. These support features 140 provide additional mechanical support to the first and second superconducting chips 102 and 104 to enhance robustness and stability.

[0035] Figure 4A is a detailed schematic side view of a first or second superconducting chip 102, 104 according to an embodiment of the present invention. Figure 5A is a detailed schematic side view of the interposer chip 106 according to an embodiment of the present invention. Figure 3A and 3B In addition to the different features described, Figure 4AThe through holes 122 formed in the insulating substrates 102S, 104S of the first and second superconducting chips 102, 104 are shown in more detail. The through holes 122 may be filled or coated with a conductor (e.g., metal). In addition, under-bump metallurgy (UBM) 150 is also shown. The UBM 150 is provided to bond the first and second superconducting chips 102, 104 to the interposer 106 via solder bumps 130, as shown in FIG. Figure 5A In addition, Figure 3A As shown, another UBM 152 is provided at the end of the through hole 122 to be bonded to the solder bump 124 on the substrate 120. Figure 5A As shown, the interposer chip 106 also includes a Figure 3A The interposer chip 106 is shown bonded to pads 160 of a substrate 120 (eg, a PCB) via solder bumps 132 .

[0036] Figure 4B FIG. 1 is a top view of the first or second superconducting chip 102 or 104 according to an embodiment of the present invention. Figure 5B is a top view of the interposer chip 106 according to an embodiment of the present invention. Figure 4B The arrangement of the qubits 102A, 102B, 104A, 104B is shown in more detail. For example, the qubits are shown arranged in a matrix arrangement. However, it should be appreciated that the qubits may also be arranged in a different arrangement or configuration, such as another polygonal structure. In an embodiment, the UBM 150 provided for connecting the first and second superconducting chips 102, 104 to the interposer chip 106 via solder bumps 130 is arranged at the periphery of the first and second superconducting chips 102, 104. In an embodiment, the first and second superconducting chips 102, 104 are rectangular in shape, such as Figure 4B As shown. Therefore, the interposer chip 106 can be connected to each side of the rectangular-shaped first and second superconducting chips 102, 104 using the UBM 150 on the superconducting chips 102, 104 and the solder bumps 130 on the interposer chip 106. Each first superconducting chip 102 and each second superconducting chip 104, together with the interposer chip connecting them, form a module attached to a substrate 120 (e.g., PCB). It is also considered to provide first and second superconducting chips 102, 104 with different polygonal shapes (e.g., triangles, pentagons, hexagons, etc.). In this case, each side of the polygonal first and second superconducting chips 102, 104 can be connected to the interposer chip 106 by the UBM 150 on the superconducting chips 102, 104 and the solder bumps 130 on the interposer chip 106.

[0037] like Figure 5BAs shown, the interposer chip 120 has a plurality of solder bumps 130 configured to connect to the corresponding UBMs 150 on the first and second superconducting chips 102, 104. In addition, the interposer chip 106 also includes a Figure 3A The interposer chip 106 is shown bonded to pads 160 of a substrate 120 (eg, a PCB) via solder bumps 132 .

[0038] According to an embodiment of the present invention, the quantum computer processor architecture of the present invention has a modular architecture because, for example, superconducting qubits 102A, 104A, 102B, and 104B are configured to optimize frequency arrangement conditions using, for example, inter-chip and intra-chip hybrid gate schemes within the processor. In addition, in an embodiment, the modular architecture of the quantum computer processor of the present invention is able to repair, service, or modify the processor only by repairing, servicing, or modifying the target chip without damaging the entire quantum computer processor device. In addition, the use of through holes (e.g., TSVs) enables access to the qubits from the top, which enables post-processing of the qubits and testing of the qubits. For example, this can be performed for room temperature measurements, annealing, and / or further qubit tuning. According to an embodiment of the present invention, the modular architecture of the quantum computer processor of the present invention also reduces the probability of chip modes coupling to qubits through through holes (e.g., TSVs).

[0039] As can be understood from the above paragraphs, in an embodiment, a quantum computer having a modular superconducting quantum processor is also provided. Figure 6 6 is a schematic diagram of a quantum computer 600 according to an embodiment of the present invention. The quantum computer 600 includes a refrigeration system under vacuum, including a sealed container 602. The quantum computer 600 includes a modular superconducting quantum processor 100. The modular superconducting quantum processor 100 is arranged inside the sealed container 602. The modular superconducting quantum processor 100 includes a first superconducting chip 102, the first superconducting chip includes a first plurality of qubits 102A each having substantially a first resonant frequency and a second plurality of qubits 102B each having substantially a second resonant frequency, the first resonant frequency being different from the second resonant frequency. The modular superconducting quantum processor 100 also includes a second superconducting chip 104, the second superconducting chip includes a third plurality of qubits 104A each having substantially a first resonant frequency and a fourth plurality of qubits 104B each having substantially a second resonant frequency. The modular superconducting quantum processor 100 further includes an interposer chip 106 connected to the first superconducting chip 102 and to the second superconducting chip 104. Interposer chip 106 includes an interposer coupler element configured to couple second plurality of qubits 102B having substantially the second resonant frequency to fourth plurality of qubits 104B having substantially the second resonant frequency.

[0040] As can be understood from the above paragraphs, a method for making a quantum processor is also provided. Figure 7 1 is a flow chart of a method for manufacturing a quantum processor 100 according to an embodiment of the present invention. The method includes: at S300, providing a first superconducting chip 102, the first superconducting chip 102 having a first plurality of qubits 102A each having substantially a first resonant frequency and a second plurality of qubits 102B each having substantially a second resonant frequency, the first resonant frequency being different from the second resonant frequency. The method also includes: at S302, providing a second superconducting chip 104, the second superconducting chip 104 having a third plurality of qubits 104A each having substantially a first resonant frequency and a fourth plurality of qubits 104B each having substantially a second resonant frequency. The method also includes: at S304, providing an interposer chip 106 including an interposer coupler element configured to couple the second plurality of qubits 102B having substantially a second resonant frequency to the fourth plurality of qubits 104B having substantially a second resonant frequency.

[0041] The method further includes: at S306, mounting first superconducting chip 102 and second superconducting chip 104 on substrate 120. The method further includes: at S308, mounting interposer chip 106 on at least a portion of first superconducting chip 102, on at least a portion of second superconducting chip 104, and on at least a portion of substrate 120, such that first plurality of qubits 102A, second plurality of qubits 102B, third plurality of qubits 104A, and fourth plurality of qubits 104B are accessible from a side opposite to a side facing substrate 120.

[0042] In an embodiment, the method further includes conductively connecting first plurality of qubits 102A, second plurality of qubits 102B, third plurality of qubits 104A, and fourth plurality of qubits 104B to substrate 120 , and conductively connecting interposer chip 106 to substrate 120 and to first superconducting chip 102 and to second superconducting chip 104 .

[0043] In an embodiment, mounting first superconducting chip 102 and second superconducting chip 104 on substrate 120 includes connecting first, second, third, and fourth pluralities of qubits 102A, 102B, 104A, and 104B to substrate 120 using a plurality of vias 122 in first and second superconducting chips 102 and 104 and solder bumps 124. In an embodiment, plurality of vias 122 are configured to input and output signals to first, second, third, and fourth pluralities of qubits 102A, 102B, 104A, and 104B through substrate 120.

[0044] In an embodiment, the method further includes producing first plurality of qubits 102A and second plurality of qubits 102B on first substrate 102S to form first superconducting chip 102 , and producing third plurality of qubits 104A and fourth plurality of qubits 104B on second substrate 104S to form second superconducting chip 104 .

[0045] In an embodiment, producing first plurality of qubits 102A and second plurality of qubits 102B on first substrate 102S includes producing first plurality of qubits 102A and second plurality of qubits 102B on first non-conductive (insulating) substrate 102S, and producing third plurality of qubits 104A and fourth plurality of qubits 104B on second substrate 104S includes producing third plurality of qubits 104A and fourth plurality of qubits 104B on second non-conductive (insulating) substrate 104S.

[0046] In an embodiment, generating first plurality of qubits 102A and second plurality of qubits 102B on first substrate 102S includes generating second plurality of qubits 102B at a perimeter of first substrate 102S, and generating third plurality of qubits 104A and fourth plurality of qubits 104B on second substrate 104S includes generating fourth plurality of qubits 104B at a perimeter of second substrate 104S, such that conductive coupling is enabled between second plurality of qubits 102B and fourth plurality of qubits 104B.

[0047] The description of various embodiments of the present invention has been presented for illustrative purposes, but the description is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A modular superconducting quantum processor, comprising: a first superconducting chip comprising a plurality of first qubits each having substantially a first resonant frequency and a plurality of second qubits each having substantially a second resonant frequency, the first resonant frequency being different from the second resonant frequency; a second superconducting chip comprising a third plurality of qubits each having substantially the first resonant frequency and a fourth plurality of qubits each having substantially the second resonant frequency; and An interposer chip connected to the first superconducting chip and to a second superconducting chip, wherein the interposer chip includes an interposer coupler element configured to couple a second plurality of qubits having substantially the second resonant frequency to a fourth plurality of qubits having substantially the second resonant frequency.

2. The modular superconducting quantum processor according to claim 1, wherein: The second plurality of qubits are arranged at a periphery of the first superconducting chip, and the fourth plurality of qubits are arranged at a periphery of the second superconducting chip to enable coupling between the second plurality of qubits and the fourth plurality of qubits.

3. The modular superconducting quantum processor according to claim 1, wherein: The first superconducting chip further includes a first plurality of coupling elements configured to couple the first plurality of qubits with the second plurality of qubits.

4. The modular superconducting quantum processor according to claim 1, wherein: The second superconducting chip further includes a second plurality of coupling elements configured to couple the third plurality of qubits with the fourth plurality of qubits.

5. The modular superconducting quantum processor according to claim 1, wherein: The first superconducting chip and the second superconducting chip include a readout element for reading out each of the first plurality of qubits, each of the second plurality of qubits, each of the third plurality of qubits, or each of the fourth plurality of qubits, or for reading out any combination thereof.

6. The modular superconducting quantum processor according to claim 1, wherein: The first superconducting chip and the second superconducting chip include a ground element configured to connect ground planes of the first superconducting chip and the second superconducting chip.

7. The modular superconducting quantum processor according to claim 1, wherein: The interposer chip includes a ground element configured to connect a ground plane on the interposer chip.

8. The modular superconducting quantum processor according to claim 1, wherein: The interposer coupler element is selected from the group consisting of a resonator, a direct capacitive coupler, and a frequency tunable element.

9. The modular superconducting quantum processor according to claim 1, wherein: The first plurality of qubits and the third plurality of qubits are arranged to have frequencies to implement a cross-resonance (CR) gate.

10. The modular superconducting quantum processor according to claim 1, wherein: The second plurality of qubits and the fourth plurality of qubits include tunable gates or resonant induced phase (RIP) gates.

11. The modular superconducting quantum processor according to claim 1, further comprising a substrate, wherein The first and second superconducting chips are mounted to a substrate and the first, second, third, and fourth pluralities of qubits are connected to the substrate through a plurality of vias and solder bumps, wherein the plurality of vias are configured to input and output signals to the first, second, third, and fourth pluralities of qubits through the substrate.

12. The modular superconducting quantum processor according to claim 11, wherein: The first and second superconducting chips are mounted to the substrate so as to allow free access to the first, second, third and fourth pluralities of qubits from a side of the first and second superconducting chips opposite a side of the first and second superconducting chips facing the substrate.

13. The modular superconducting quantum processor according to claim 11, wherein: The interposer chip is connected to the first and second superconducting chips and the substrate using solder bumps.

14. The modular superconducting quantum processor according to claim 1, wherein: The first superconducting chip, the second superconducting chip, and the interposer chip are configured and arranged to provide a modular system to enable direct access to each of the first, second, third, and fourth qubits.

15. The modular superconducting quantum processor according to claim 1, further comprising: a plurality of first superconducting chips including a first plurality of qubits and a second plurality of qubits; a plurality of second superconducting chips including a third plurality of qubits and a fourth plurality of qubits, The interposer chip is configured to be connected to the plurality of first superconducting chips and the plurality of second superconducting chips.

16. A method for manufacturing a modular superconducting quantum processor, comprising: Providing a first superconducting chip including a plurality of first qubits each substantially having a first resonant frequency and a plurality of second qubits each substantially having a second resonant frequency, the first resonant frequency being different from the second resonant frequency; providing a second superconducting chip, the second superconducting chip comprising a third plurality of qubits each having substantially the first resonant frequency and a fourth plurality of qubits each having substantially the second resonant frequency; providing an interposer chip including an interposer coupler element configured to couple a second plurality of qubits having substantially the second resonant frequency to a fourth plurality of qubits having substantially the second resonant frequency; mounting a first superconducting chip and a second superconducting chip on a substrate; and An interposer chip is mounted on at least a portion of the first superconducting chip, on at least a portion of the second superconducting chip, and on at least a portion of the substrate such that the first plurality of qubits, the second plurality of qubits, the third plurality of qubits, and the fourth plurality of qubits are accessible from a side opposite to a side facing the substrate.

17. The method of claim 16, further comprising conductively connecting the first, second, third, and fourth pluralities of qubits to a substrate and conductively connecting an interposer chip to the substrate and to the first and second superconducting chips.

18. The method according to claim 16, wherein: Mounting the first superconducting chip and the second superconducting chip on the substrate includes connecting the first, second, third, and fourth pluralities of qubits to the substrate using a plurality of vias in the first superconducting chip and the second superconducting chip and solder bumps, wherein the plurality of vias are configured to input and output signals to the first, second, third, and fourth pluralities of qubits through the substrate.

19. The method of claim 16, further comprising producing the first plurality of qubits and the second plurality of qubits on a first substrate to form a first superconducting chip; and A third plurality of qubits and a fourth plurality of qubits are produced on a second substrate to form a second superconducting chip.

20. The method according to claim 19, wherein: Generating the first plurality of qubits and the second plurality of qubits on the first substrate includes generating the first plurality of qubits and the second plurality of qubits on the first non-conductive substrate, Wherein generating a third plurality of qubits and a fourth plurality of qubits on the second substrate includes generating a third plurality of qubits and a fourth plurality of qubits on a second non-conductive substrate.

21. The method according to claim 19, wherein: Generating the first plurality of qubits and the second plurality of qubits on the first substrate includes generating the second plurality of qubits at a perimeter of the first substrate, and Wherein generating the third plurality of qubits and the fourth plurality of qubits on the second substrate includes generating the fourth plurality of qubits at a perimeter of the second substrate to enable conductive coupling between the second plurality of qubits and the fourth plurality of qubits.

22. A quantum computer comprising the modular superconducting quantum processor according to any one of claims 1 to 15.

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