Display device

Abstract

A display device is provided. The display device includes a pixel configured to display an image based on image data and a reference voltage, a controller configured to generate reference voltage data corresponding to the reference voltage for suppressing a leakage current in the pixel based on a frame frequency, and a power supply configured to generate the reference voltage based on the reference voltage data and to supply the reference voltage to the pixel.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0078690, filed on June 26, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to display devices, and more specifically, to display devices capable of changing driving frequencies and methods for driving display devices. Background Technology

[0004] The display device uses control signals applied from an external device to display images.

[0005] The display device may include multiple pixels. Each of the multiple pixels may include multiple transistors, a light-emitting element electrically connected to the transistors, and a capacitor. The transistors may generate a drive current based on a signal provided through a signal line. The light-emitting element may emit light according to the drive current.

[0006] To enhance the driving efficiency of a display device, various methods can be used to reduce its power consumption. For example, the power consumption of a display device can be reduced by lowering the driving frequency (or data writing frequency) used to display still images. However, when the display device displays images at a low driving frequency, leakage of driving current may occur in the pixels, and flickering or similar issues may become noticeable. Summary of the Invention

[0007] Various embodiments of this disclosure relate to a display device that adjusts the value of a reference voltage to be supplied to a pixel based on changes in the driving frequency and the representative grayscale of the frame.

[0008] Various embodiments of this disclosure relate to a method for driving a display device by adjusting the value of a reference voltage to be supplied to a pixel based on changes in the driving frequency and the representative grayscale of the frame.

[0009] However, this disclosure is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit and scope of this disclosure.

[0010] According to embodiments of the present disclosure, the display device includes a pixel, a controller, and a power supply, wherein the pixel is configured to display an image based on image data and a reference voltage, the controller is configured to generate reference voltage data corresponding to a reference voltage used to suppress leakage current in the pixel based on a frame frequency, and the power supply is configured to generate a reference voltage based on the reference voltage data and supply the reference voltage to the pixel.

[0011] In an embodiment, the controller can further determine the reference voltage data with reference to a representative value of the gray scale of the image data.

[0012] In an embodiment, the representative value can be an average value of the gray scale included in the image data of one frame.

[0013] In an embodiment, in case that the representative value is the same, the reference voltage can vary as the frame frequency varies from a first frequency to a second frequency.

[0014] In an embodiment, in case that the frame frequency is the same, the reference voltage can vary as the representative value varies from a first value to a second value.

[0015] In an embodiment, the controller can include a frequency analyzer configured to determine a frame frequency based on at least one of a vertical synchronization signal and a data enable signal supplied from an external device, a representative value determiner configured to determine a representative value based on a gray scale included in the image data, and a voltage data generator configured to generate reference voltage data with reference to a look-up table in which a plurality of values of the reference voltage corresponding to the frame frequency and the gray scale are stored.

[0016] In an embodiment, the voltage data generator can include a comparator configured to compare the frame frequency with a reference frequency, and a data determiner configured to determine the reference voltage data based on a comparison result of the comparator.

[0017] In an embodiment, in case that the frame frequency is equal to or greater than the reference frequency, the data determiner can output a default value of the reference voltage data corresponding to a default value among the plurality of values of the reference voltage. In case that the frame frequency is lower than the reference frequency, the data determiner can determine the reference voltage data with reference to the look-up table.

[0018] In an embodiment, the data determiner can extract a plurality of reference values from the look-up table based on the frame frequency and the representative value, and calculate the reference voltage data by interpolating the plurality of reference values.

[0019] In an embodiment, the controller can further include a register configured to output a compensation factor reflecting a distribution of threshold voltages of driving transistors of pixels. The power supply can output the reference voltage based on the reference voltage data and the compensation factor.

[0020] In an embodiment, the power supply can include a variable resistor circuit configured to adjust a resistance value based on the reference voltage data and vary an input power supply voltage based on the resistance value.

[0021] In an embodiment, the display device can further include a data driver configured to supply a data voltage to the pixels through a data line based on image data, a scan driver configured to supply a first scan signal to the pixels through a first scan line and a second scan signal to the pixels through a second scan line, and an emission driver configured to supply a first emission control signal to the pixels through a first emission control line. The pixel can include a light emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein the first transistor is configured to control a driving current based on a voltage of a first node and is coupled between a second node and a third node, the second transistor is coupled between the data line and the second node and is configured to be turned on by the first scan signal supplied to the first scan line, the third transistor and the fourth transistor are coupled in series between the first node and the third node and are configured to be turned on by the second scan signal supplied to the second scan line, the fifth transistor is configured to supply a reference voltage to a fourth node between the third transistor and the fourth transistor and is turned off by the first emission control signal supplied to the first emission control line, and the sixth transistor is coupled between a first power voltage and the second node and is configured to be turned off by the first emission control signal.

[0022] In an embodiment, the scan driver can be further configured to supply a third scan signal to the pixels through a third scan line and a fourth scan signal to the pixels through a fourth scan line, and wherein the pixel can further include a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor, wherein the seventh transistor is coupled between the third node and the light emitting element and is configured to be turned off by the first emission control signal, the eighth transistor is configured to supply an initialization voltage to the light emitting element and is turned on by the third scan signal supplied to the third scan line, the ninth transistor and the tenth transistor are coupled in series between the first node and a power line for supplying the initialization voltage and are configured to be turned on by the fourth scan signal supplied to the fourth scan line, and the eleventh transistor is configured to supply a reference voltage to a fifth node between the ninth transistor and the tenth transistor and is turned off by the first emission control signal.

[0023] In an embodiment, the first scan line and the second scan line can be supplied with the same scan signal.

[0024] In an embodiment, the scan driver is further configured to supply a third scan signal to the pixel through a third scan line, the emission driver can be further configured to supply a second emission control signal to the pixel through a second emission control line, and the pixel can further include a seventh transistor and an eighth transistor, wherein the seventh transistor is coupled between a third node and the light emitting element and configured to be turned off by the second emission control signal supplied to the second emission control line, and the eighth transistor is configured to supply an initialization voltage to the third node and to be turned on by the third scan signal supplied to the third scan line.

[0025] In an embodiment, the second emission control signal can be supplied later than the first emission control signal.

[0026] In an embodiment, a first frequency at which the first scan signal is supplied to the first scan line can be equal to a frame frequency. A second frequency at which the first emission control signal is supplied to the first emission control line can be greater than the frame frequency.

[0027] According to an embodiment of the present disclosure, a method of driving a display apparatus includes determining a frame frequency based on at least one of a data enable signal and a vertical synchronization signal, determining a representative value of a gray scale of a frame based on a gray scale included in image data of the frame, generating reference voltage data corresponding to a reference voltage based on the frame frequency and the representative value, and supplying a reference voltage for suppressing a leakage current in a pixel to the pixel based on the reference voltage.

[0028] In an embodiment, in case that the representative value of the image data is the same, the reference voltage can vary as the frame frequency varies from a first frequency to a second frequency.

[0029] In an embodiment, generating the reference voltage data can include comparing the frame frequency with a reference frequency, outputting a default value of the reference voltage data regardless of the frame frequency and the representative value in case that the frame frequency is equal to or greater than the reference frequency, and calculating the reference voltage data corresponding to the frame frequency and the representative value with reference to a lookup table in case that the frame frequency is less than the reference frequency.

[0030] Since the value of the reference voltage can be controlled based on the frame frequency and the representative value of the gray scale of the corresponding frame, the display apparatus can minimize the leakage current in the pixel and alleviate image flicker by controlling the reference voltage in response to a change in the frame frequency.

[0031] Further, since the leakage current can be minimized depending on the frame frequency, the display apparatus can display a static image at a very low frequency. Accordingly, the display apparatus can implement a reliable low-power driving operation while reducing power consumption.

[0032] However, the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0034] Figure 2 is a circuit diagram illustrating an example of a pixel included in the display device of Figure 1 .

[0035] Figure 3 is a timing chart illustrating an example of a signal supplied to the pixel of Figure 2 .

[0036] Figure 4 is a block diagram illustrating an example of a controller included in the display device of Figure 1 .

[0037] Figure 5 is a block diagram illustrating an example of a voltage data generator included in the controller of Figure 4 .

[0038] Figure 6 is a diagram illustrating an example of a lookup table included in the controller of Figure 4 .

[0039] Figure 7 is a block diagram illustrating an example of a controller and a power supply included in the display device of Figure 1 .

[0040] Figure 8 is a circuit diagram illustrating another example of a pixel included in the display device of Figure 1 .

[0041] Figure 9 is a timing chart illustrating an example of a signal supplied to the pixel of Figure 8 .

[0042] Figure 10 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0043] Figure 11 is a flowchart illustrating an example of a method of generating reference voltage data according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Like reference numerals are used to refer to like elements throughout the drawings and repetitive descriptions of the same components will be omitted.

[0045] Figure 1 is a block diagram illustrating a display device 1000 according to an embodiment of the present disclosure.

[0046] Referring to Figure 1 , the display device 1000 can include a pixel unit 100, a scan driver 200, an emission driver 300, a data driver 400, a controller 500, and a power supply 600.

[0047] The pixel unit 100 can include a plurality of scan lines S11 to S1n, S21 to S2n, and S31 to S3n, a plurality of emission control lines E1 to En, a plurality of data lines D1 to Dm, and a plurality of pixels PX coupled with the plurality of scan lines S11 to S1n, S21 to S2n, and S31 to S3n, the plurality of emission control lines E1 to En, and the plurality of data lines D1 to Dm (here, m and n are each an integer of 1 or more). Each of the plurality of pixels PX can include a driving transistor and a plurality of switching transistors. To prevent current leakage from occurring in the pixel PX during a low-frequency driving operation, the power supply 600 can supply a reference voltage Vref to the pixel PX.

[0048] The display device 1000 can display an image at various frame frequencies (also referred to herein as refresh rates or driving frequencies) depending on an operation mode and / or a driving condition. A frame frequency FF (see Figure 4 ) can be a frequency at which a data voltage is substantially applied to a driving transistor of a pixel PX per unit time (e.g., per second). For example, the frame frequency FF can also be referred to as a "scan rate" or a "refresh frequency," and indicates the number of images displayed per unit time.

[0049] In an embodiment, the frame frequency FF can be an output frequency of a first scan signal supplied to the data driver 400 and / or the first scan line S1i of the i-th pixel row. For example, the frame frequency FF for driving a video can be about 60 Hz or more (e.g., 120 Hz). In this case, the first scan signal can be supplied to each horizontal line (pixel row) sixty times per second.

[0050] In an embodiment, the display device 1000 can adjust the output frequencies of the scan driver 200 and the emission driver 300 and the output frequency of the data driver 400 corresponding thereto depending on an operation mode and / or a driving condition. For example, the display device 1000 can display an image or a video in response to various frame frequencies in a range of 1 Hz to 120 Hz. However, this is for illustrative purposes only. For example, the display device 1000 can display an image at a frame frequency FF (e.g., 240 Hz or 480 Hz) greater than 120 Hz.

[0051] The controller 500 can generate the first control signal SCS, the second control signal ECS, the third control signal DCS, and the fourth control signal PCS based on a data enable signal DE, a vertical synchronization signal Vsync, and a horizontal synchronization signal Hsync supplied from an external device. The vertical synchronization signal Vsync can divide the image signal RGB on a frame basis. The horizontal synchronization signal Hsync can divide the image signal RGB on a horizontal line (pixel row) basis. The data enable signal DE can distinguish an active period from a blanking period, and the controller 500 can receive the image signal RGB or the image data DAT per frame during the active period. For example, the controller 500 can receive the image signal RGB substantially during the active period.

[0052] The controller 500 can supply the first control signal SCS to the scan driver 200, can supply the second control signal ECS to the emission driver 300, can supply the third control signal DCS to the data driver 400, and can supply the fourth control signal PCS to the power supply 600. In one embodiment, the controller 500 can receive the image signal RGB from an external device, change a format of the image signal RGB or rearrange the image signal RGB into the image data DAT suitable for the display device 1000, and supply the image data DAT to the data driver 400.

[0053] In an embodiment, the first control signal SCS can include one or more control signals, and the scan driver 200 can control transmission of the first scan signal to the plurality of first scan lines S11 to S1n, transmission of the second scan signal to the plurality of second scan lines S21 to S2n, and transmission of the third scan signal to the plurality of third scan lines S31 to S3n, respectively.

[0054] In an embodiment, the controller 500 can generate the reference voltage data RVD corresponding to the reference voltage Vref based on a frame frequency FF for driving the pixel unit 100, and supply the reference voltage data RVD to the power supply 600. In this case, a value of the reference voltage Vref can be adjusted depending on the frame frequency FF of the pixel unit 100.

[0055] In an embodiment, the controller 500 can generate the reference voltage data RVD with reference to a representative value of a gray scale of the image signal RGB (or the image data DAT) and the frame frequency FF. For example, in a case where the frame frequency FF for the representative value of the gray scale of the same image data DAT is changed from a first frequency to a second frequency, the reference voltage Vref can vary. Also, in a case where the representative value of the gray scale of the image data DAT for the same frame frequency FF is changed from a first value to a second value, the reference voltage Vref can vary.

[0056] The scan driver 200 can receive a first control signal SCS from the controller 500, and supply first, second, and third scan signals to the plurality of first scan lines S11 to S1n, the plurality of second scan lines S21 to S2n, and the plurality of third scan lines S31 to S3n, respectively, based on the first control signal SCS.

[0057] Each of the first to third scan signals can be set to a gate-on voltage (e.g., a low voltage). The transistor of the pixel PX that receives the scan signal can be set to an on state when the scan signal of the gate-on voltage is supplied thereto.

[0058] The emission driver 300 can supply emission control signals to the plurality of emission control lines E1 to En based on a second control signal ECS. For example, the emission control signals can be supplied to the plurality of emission control lines E1 to En consecutively.

[0059] The plurality of emission control signals can each be set to a gate-off level (e.g., a high voltage). The transistor of the pixel PX that receives the emission control signal can be turned off during an emission period (e.g., when the emission control signal is supplied thereto), and can be turned on during other periods.

[0060] Although Figure 1 Although each of the scan driver 200 and the emission driver 300 is illustrated as a single component, the present disclosure is not limited thereto. Depending on the design of the display apparatus 1000, the scan driver 200 can include a plurality of scan drivers, and each of the plurality of scan drivers supplies at least one of the first to third scan signals. Also, at least a portion of the scan driver 200 and / or the emission driver 300 can be integrated into a single driving circuit, module, or the like.

[0061] The data driver 400 can receive a third control signal DCS and image data DAT from the controller 500. The data driver 400 can convert the digital image data DAT into an analog data signal (data voltage). The data driver 400 can supply the data signal (or data voltage) to the plurality of data lines D1 to Dm in response to the third control signal DCS.

[0062] The power supply 600 can supply a first power voltage VDD, a second power voltage VSS, and a reference voltage Vref for driving the pixels PX to the pixel unit 100. The power supply 600 can also generate an initialization voltage Vint for initializing the pixels PX (see Figure 2 ). In an embodiment, the power supply 600 can generate the reference voltage Vref based on reference voltage data RVD received from the controller 500. The reference voltage Vref can be adjusted based on a frame frequency FF of the pixel unit 100 and a representative value of an image signal RGB (or a representative value of the image data DAT).

[0063] The display device 1000 can operate in one of a first mode (or normal mode) in which a data voltage is applied at a nominal frequency (e.g., 60 Hz) or higher to display a video or the like and a second mode (or low power mode) in which a data voltage is applied at a frequency lower than the nominal frequency to display, for example, a static image.

[0064] During the low frequency driving operation in the second mode, leakage of a driving current of the light emitting element of the pixel PX can occur, and image flicker can be visible due to the current leakage. As will be explained in further detail below, the pixel PX having a circuit structure as shown in Figure 2 or Figure 8 The pixel PX having a circuit structure as shown in

[0065] However, the leakage current of the pixel PX can vary depending on the data voltage. Also, if the frame frequency FF is changed even at the same data voltage, the leakage current can vary. By adjusting the reference voltage Vref based on the frame frequency FF and the data voltage (gray scale), the pixel PX can optimally control the leakage current.

[0066] Figure 2 is a circuit diagram showing an example of a pixel 10 included in the display device 1000 of Figure 1 .

[0067] For illustrative purposes, Figure 2 a pixel 10 coupled with an i-th horizontal line (or i-th pixel row) and a j-th data line Dj (here, i is a natural number less than or equal to n, and j is a natural number less than or equal to m) is shown.

[0068] The pixel 10 can include a light emitting element LD, first to eleventh transistors T1 to T11, and a storage capacitor Cst.

[0069] The light emitting element LD can include a first electrode (anode or cathode) coupled with the seventh transistor T7 and a second electrode (the other of the cathode and the anode) coupled with a second power supply voltage VSS. The light emitting element LD can generate light having a predetermined brightness corresponding to an amount of current supplied from the first transistor T1 (or driving transistor).

[0070] In an embodiment, the light emitting element LD can be an organic light emitting diode including an organic light emitting layer. In an embodiment, the light emitting element LD can be an inorganic light emitting element formed of an inorganic material. In an embodiment, the light emitting element LD can be a light emitting element formed of a combination of an inorganic material and an organic material. The light emitting element LD can include a plurality of inorganic light emitting elements coupled in parallel and / or in series between the second power supply voltage VSS and the seventh transistor T7.

[0071] The first transistor T1 can be coupled between the second node N2 and the third node N3. A gate electrode of the first transistor T1 can be coupled to the first node N1. The first transistor T1 can control an amount of current (a driving current) flowing from the first power supply voltage VDD to the second power supply voltage VSS via the light emitting element LD in response to a voltage supplied to the first node N1. To this end, the first power supply voltage VDD can be higher than the second power supply voltage VSS.

[0072] The second transistor T2 can be coupled between the jth data line Dj (hereinafter referred to as a data line) and the second node N2. A gate electrode of the second transistor T2 can be coupled to the ith first scan line S1i (hereinafter referred to as a first scan line). When a first scan signal is supplied to the first scan line S1i, the second transistor T2 can be turned on to electrically couple the data line Dj with the second node N2.

[0073] The third transistor T3 and the fourth transistor T4 can be coupled in series between the first node N1 and the third node N3. A gate electrode of the third transistor T3 and a gate electrode of the fourth transistor T4 can be coupled to the first scan line S1i. When a first scan signal is supplied to the first scan line S1i, the third transistor T3 and the fourth transistor T4 can be turned on in synchronization with the second transistor T2.

[0074] Here, due to the stacked structure of the transistors, a parasitic capacitance component can exist in the fourth node N4 and the first scan line S1i. To prevent current from being undesirably leaked due to the parasitic capacitance, the fifth transistor T5 can be added to directly control a voltage of the fourth node N4.

[0075] The fifth transistor T5 can be coupled to the fourth node N4 between the third transistor T3 and the fourth transistor T4. The fifth transistor T5 can supply a reference voltage Vref to the fourth node N4. A gate electrode of the fifth transistor T5 can be coupled to the ith emission control line Ei (hereinafter referred to as an emission control line). The fifth transistor T5 can be turned off by an emission control signal (e.g., a high level) supplied to the emission control line Ei. The fifth transistor T5 can be turned on during an emission period based on the emission control signal, and can supply the reference voltage Vref to the fourth node N4.

[0076] In an embodiment, the reference voltage Vref can be a value within a range of data voltages determined by the gray scale range. For example, the reference voltage Vref can be a middle value of the range of data voltages. Since the reference voltage Vref has a value between the black gray scale voltage and the white gray scale voltage, the source-drain voltage of the third transistor T3 can be controlled to have a low level during the emission period. Accordingly, a path of a current flowing to the third transistor T3 and the fourth transistor T4 during the emission period can be limited, thereby reducing leakage of a driving current.

[0077] The sixth transistor T6 can be coupled between the first power voltage VDD and the second node N2. A gate electrode of the sixth transistor T6 can be coupled to the emission control line Ei. The seventh transistor T7 is coupled between the third node N3 and the light emitting element LD. A gate electrode of the seventh transistor T7 can be coupled to the emission control line Ei. The sixth transistor T6 and the seventh transistor T7 can be turned off during an emission period when an emission control signal is supplied to the emission control line Ei, and can be turned on during other periods.

[0078] The eighth transistor T8 can be coupled between the power line PL and the first electrode of the light emitting element LD. A gate electrode of the eighth transistor T8 can be coupled to the i-th second scan line S2i (hereinafter referred to as a second scan line). When a second scan signal is supplied to the second scan line S2i, the eighth transistor T8 can be turned on, and can transmit the initialization voltage Vint to the first electrode of the light emitting element LD.

[0079] The ninth transistor T9 and the tenth transistor T10 can be coupled in series between the first node N1 and the power line PL for transmitting the initialization voltage Vint. A gate electrode of the ninth transistor T9 and a gate electrode of the tenth transistor T10 can be coupled to the i-th third scan line S3i (hereinafter referred to as a third scan line). When a third scan signal is supplied to the third scan line S3i, the ninth transistor T9 and the tenth transistor T10 can be turned on, and transmit the initialization voltage Vint to the first node N1 or the gate electrode of the first transistor T1.

[0080] A parasitic capacitance component can exist between the fifth node N5 and the third scan line S3i between the ninth transistor T9 and the tenth transistor T10. In order to prevent a current from being undesirably leaked due to the parasitic capacitance, the eleventh transistor T11 can directly control a voltage of the fifth node N5.

[0081] The eleventh transistor T11 can be coupled between the fifth node N5 and a reference voltage Vref. A gate electrode of the eleventh transistor T11 can be coupled to the emission control line Ei. The eleventh transistor T11 can be turned off by an emission control signal (e.g., a high level) supplied to the emission control line Ei. The eleventh transistor T11 can be turned on during an emission period and supply the reference voltage Vref to the fifth node N5.

[0082] The storage capacitor Cst can be coupled between the first power supply voltage VDD and the first node N1.

[0083] Figure 3 is an example of a timing chart showing signals of the pixel 10 to which the Figure 2 is an example of a timing chart showing signals of the pixel 10 to which the

[0084] Referring to Figures 1 to 3 , the frame frequency FF at which the pixels 10 of the display apparatus 1000 are driven can vary depending on the operation mode and / or the driving conditions.

[0085] In an embodiment, during the variable-frequency driving operation for controlling the frame frequency FF, each frame period FP can include a first period P1 and a second period P2. The first period P1 and the second period P2 can respectively include a first non-emission period NEP1 and a second non-emission period NEP2 and a first emission period EP1 and a second emission period EP2. During the first non-emission period NEP1, a data voltage can be applied to the pixel 10. During the second non-emission period NEP2, the data voltage can not be applied to the pixel 10. Accordingly, during the second emission period EP2, the pixel 10 can emit light based on the data voltage supplied during the first non-emission period NEP1.

[0086] As shown in Figure 3 , the emission control signal and the second scan signal can be supplied to the emission control line Ei and the second scan line S2i, respectively, at a first frequency, and the first scan signal and the third scan signal can be supplied to the first scan line S1i and the third scan line S3i, respectively, at a second frequency lower than the first frequency. For example, the first frequency can be 120 Hz, and the second frequency can be 60 Hz. The frequency of the first scan signal can be substantially the same as the frame frequency FF.

[0087] However, this is for illustrative purposes only, and the second frequency can be 60 Hz or less. As the second frequency decreases or the difference between the first frequency and the second frequency increases, the iteration count of the second period P2 in the frame period FP can increase. For example, depending on the frame frequency FF, the frame period FP can include one first period P1 and a plurality of consecutive second periods P2.

[0088] The emission control signal having a low level can be supplied to the emission control line Ei in the first emission period EP1 and the second emission period EP2. A period other than the first emission period EP1 and the second emission period EP2 can correspond to the first non-emission period NEP1 and the second non-emission period NEP2.

[0089] During the first non-emission period NEP1, the third scan signal, the first scan signal, and the second scan signal can be continuously supplied to the third scan line S3i, the first scan line S1i, and the second scan line S2i, respectively.

[0090] When the third scan signal is supplied to the third scan line S3i, the ninth transistor T9 and the tenth transistor T10 can be turned on, and the initialization voltage Vint can be supplied to the first node N1. Accordingly, the gate voltage of the first transistor T1 can be initialized.

[0091] Thereafter, when the first scan signal is supplied, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be turned on, and the first transistor T1 can be diode-connected. Accordingly, data voltage application and threshold voltage compensation can be performed on the pixel 10.

[0092] Subsequently, when the second scan signal is supplied, the eighth transistor T8 can be turned on, and the initialization voltage Vint can be supplied to the first electrode of the light emitting element LD, and the voltage of the first electrode of the light emitting element LD can be initialized.

[0093] Thereafter, during the first emission period EP1, when the supply of the emission control signal to the emission control line Ei is interrupted (e.g., a low-level emission control signal is supplied), the sixth transistor T6 and the seventh transistor T7 can be turned on, and the light emitting element LD can emit light. Further, the fifth transistor T5 and the eleventh transistor T11 can be turned on, and the reference voltage Vref can be supplied to the fourth node N4 and the fifth node N5. Accordingly, during the first emission period EP1, leakage of the current flowing from the third node N3 to the first node N1 can be reduced or minimized.

[0094] Thereafter, only the second scan signal and the emission control signal can be supplied during the second non-emission period NEP2. In other words, during the second non-emission period NEP2, the voltage of the first electrode of the light emitting element LD can be initialized.

[0095] Subsequently, during the second emission period EP2, the light emitting element LD can emit light based on the data voltage supplied during the first non-emission period NEP1.

[0096] Since the iteration count of the second period P2 varies depending on the frame frequency FF, the leakage current can vary. For example, as the frame frequency FF decreases, the leakage current can increase, and the reduction width of the luminance can increase. To mitigate the variation in luminance due to the leakage current in the second period P2 and reduce image flicker due to the luminance variation, the reference voltage Vref can be controlled based on the frame frequency FF.

[0097] Figure 4 is a block diagram illustrating an example of a controller 500 included in a display apparatus 1000 of Figure 1

[0098] Referring to Figure 1 and Figure 4 , the controller 500 can include a frequency analyzer 520, a representative value determiner 540, a voltage data generator 560, and a lookup table 580.

[0099] The controller 500 can generate reference voltage data RVD corresponding to the reference voltage Vref based on the frame frequency FF.

[0100] The frequency analyzer 520 can determine the frame frequency FF based on a control signal CON supplied from an external apparatus such as a graphic processor. The control signal CON can include a data enable signal DE, a vertical synchronization signal Vsync, a frequency variable signal, etc. The control signal CON can also include metadata including information about the frame frequency FF.

[0101] For example, the frequency analyzer 520 can calculate the frame frequency FF by detecting a time at which a data enable signal DE corresponding to one frame period is supplied. Alternatively, the frequency analyzer 520 can count the vertical synchronization signal Vsync and calculate the frame frequency FF based on the vertical synchronization signal Vsync.

[0102] However, this is for illustrative purposes only, and the frequency analyzer 520 can determine the frame frequency FF in various ways without departing from the scope of the present disclosure.

[0103] The representative value determiner 540 can determine a representative value RGV of the gray scale of the corresponding frame based on information about the gray scale included in the image signal RGB or the image data DAT. In an embodiment, the representative value RGV can be an average value of the gray scale included in the image signal RGB or the image data DAT.

[0104] Alternatively, the representative value determiner 540 can determine the representative value RGV based on the proportion of the turned-on pixels. In other words, the representative value determiner 540 can calculate the representative value RGV based on the proportion of the pixels emitting light among all the pixels or the proportion of the luminance of the current frame with respect to the maximum luminance.

[0105] ​However, this is for illustrative purposes only, and the representative value determiner 540 can determine the representative value RGV in various ways without departing from the scope of the present disclosure.

[0106] The voltage data generator 560 can generate the reference voltage data RVD based on the frame frequency FF and the representative value RGV. In an embodiment, the voltage data generator 560 can refer to the lookup table 580 to generate the reference voltage data RVD, and the lookup table 580 sets the value of the reference voltage Vref based on the frequency and the gray scale.

[0107] The lookup table 580 can include a predetermined frame frequency FF, a plurality of gray scales (i.e., representative values) corresponding to the predetermined frame frequency FF, the reference voltage Vref set to match each of the predetermined frame frequency FF and the plurality of gray scales (i.e., representative values), and the value of the reference voltage Vref. The lookup table 580 can include a plurality of tables set for the respective frame frequency FF, and can be set and stored in correspondence with the characteristics of the display apparatus 1000.

[0108] For example, in the case where the driving transistor of the pixel PX is a P-channel metal oxide semiconductor (PMOS) transistor, as the gray scale corresponding to the representative value RGV for the same frame frequency FF increases, the value of the reference voltage Vref stored in the lookup table 580 can decrease. Also, as the frame frequency FF for the same representative value RGV (or the same gray scale) decreases, the value of the reference voltage Vref stored in the lookup table 580 can increase. However, this is for illustrative purposes only, and the relationship between the frame frequency FF, the gray scale, and the reference voltage Vref set in the lookup table 580 is not limited thereto. The relationship between the frame frequency FF, the gray scale, and the reference voltage Vref in the lookup table 580 can be set to correspond to the characteristics of the display apparatus 1000 as determined through testing.

[0109] The voltage data generator 560 can supply the reference voltage data RVD to the power supply 600.

[0110] Figure 5 is a block diagram illustrating an example of the voltage data generator 560 included in the controller 500 of Figure 4 . Figure 6 is a diagram illustrating an example of the lookup table 580 included in the controller 500 of Figure 4 .

[0111] Referring to Figure 1 , Figure 4 , Figure 5 and Figure 6 , the voltage data generator 560 can include a comparator 562 and a data determiner 564.

[0112] The comparator 562 can receive the frame frequency FF and the reference frequency RF. The comparator 562 can compare the frame frequency FF with the reference frequency RF. The comparison result CV can have two result values. For example, the comparison result CV can be a first result value indicating that the frame frequency FF is equal to or greater than the reference frequency RF, or a second result value indicating that the frame frequency FF is less than the reference frequency RF.

[0113] In an embodiment, the reference frequency RF can be set to a normal frame frequency (e.g., 60 Hz) of the display apparatus 1000 for displaying an image, a video, or the like.

[0114] The data determiner 564 can determine the reference voltage data RVD based on the comparison result CV. For example, the data determiner 564 can receive the frame frequency FF, a default value D_RV of the reference voltage data RVD, and the comparison result CV.

[0115] In an embodiment, if the frame frequency FF is equal to or greater than the reference frequency RF, the data determiner 564 can output the default value D_RV of the reference voltage data RVD corresponding to the default value of the reference voltage Vref. In a case where the frame frequency FF is a high frequency equal to or greater than the reference frequency RF, it can be impossible to recognize image flicker due to current leakage. In this case, the reference voltage Vref can not be adjusted depending on the average gray scale of the frame and / or the frame frequency FF.

[0116] In other words, if the frame frequency FF is equal to or greater than the reference frequency RF, the data determiner 564 of the controller 500 can output the reference voltage data RVD having the default value D_RV, and the power supply 600 can supply the reference voltage Vref having the default value to the pixel unit 100, regardless of the frame frequency FF and the representative value RGV.

[0117] On the other hand, if the frame frequency FF is less than the reference frequency RF, the data determiner 564 can refer to the lookup table 580 to determine the reference voltage data RVD.

[0118] In other words, the data determiner 564 can directly output the reference voltage data RVD corresponding to the default value D_RV based on the comparison result CV, or output the reference voltage data RVD corresponding to the frame frequency FF by referring to the lookup table 580. For example, the comparison result CV provided to the data determiner 564 can be used to select the frame frequency FF or the default value D_RV.

[0119] If the default value D_RV is selected according to the comparison result CV, the data determiner 564 can directly output the reference voltage data RVD corresponding to the default value D_RV. If the frame frequency FF is selected according to the comparison result CV, the data determiner 564 can output the reference voltage data RVD corresponding to the frame frequency FF based on the lookup table 580.

[0120] Referring to Figure 6 The look-up table 580 can include a plurality of look-up tables including a first look-up table LUT1, a second look-up table LUT2, and a third look-up table LUT3. The first look-up table LUT1, the second look-up table LUT2, and the third look-up table LUT3 can be distinguished from each other based on the frame frequency FF. For example, the first look-up table LUT1 corresponds to a frame frequency FF of 30 Hz, the second look-up table LUT2 corresponds to a frame frequency FF of 20 Hz, and the third look-up table LUT3 corresponds to a frame frequency FF of 10 Hz. Further, each of the first look-up table LUT1, the second look-up table LUT2, and the third look-up table LUT3 can include values of reference voltage data RVD matching preset gray levels or gray level ranges. Each of the plurality of values of the reference voltage data RVD can be a code or a register value corresponding to the reference voltage Vref that the power supply 600 can output. The values of the reference voltage data RVD can also be represented in a digital form.

[0121] For example, in a case where the frame frequency FF is 30 Hz and the representative value RGV is a gray level 2, the data determiner 564 can extract a value of the reference voltage Vref as "4" from the first look-up table LUT1. The data determiner 564 can output the digital reference voltage data RVD corresponding to the value 4 as the reference voltage Vref.

[0122] In an embodiment, the data determiner 564 can extract a plurality of reference values from the look-up table 580 based on the frame frequency FF and the representative value RGV, and calculate the reference voltage data RVD by interpolating the extracted reference values. In a case where the frame frequency FF and / or the representative value RGV are not set in the look-up table 580, the data determiner 564 can interpolate a plurality of reference voltages Vref according to a predetermined algorithm, and calculate the reference voltage data RVD and a corresponding value of the reference voltage Vref based on the frame frequency FF and the representative value RGV. The data determiner 564 can include a circuit and / or a software algorithm for calculating a value of the reference voltage Vref. In this case, the size of the look-up table 580 can be reduced.

[0123] For example, in a case where the frame frequency FF is 25 Hz and the representative value RGV is a gray level 2, the data determiner 564 can extract a first reference value corresponding to a frame frequency FF of 30 Hz from the first look-up table LUT1, and extract a second reference value corresponding to a frame frequency FF of 20 Hz from the second look-up table LUT2. The data determiner 564 can determine the reference voltage data RVD by an operation such as interpolation using the first reference value and the second reference value.

[0124] Thus, the display device 1000 according to the embodiment of the disclosure can control the reference voltage Vref based on the frame frequency FF and the representative value RGV of the gray scale corresponding to the frame frequency FF. Accordingly, the display device 1000 can reduce or minimize the leakage current in the pixel PX and mitigate image flicker by controlling the reference voltage Vref in response to a change in the frame frequency FF.

[0125] Further, since the leakage current can be minimized depending on the frame frequency FF, the display device 1000 can display a static image at a very low frequency. Accordingly, the display device 1000 can provide a reliable low-power driving operation while reducing power consumption.

[0126] Figure 7 is a block diagram illustrating an example of another controller 500A and a power supply 600 included in the display device 1000 of Figure 1

[0127] In addition to the register 590, Figure 7 the configuration and operation of the controller 500A are substantially the same as those of the controller 500 described with reference to Figures 4 to 6 Thus, like reference numerals will be used to designate similar or identical components, and repeated explanations will be omitted.

[0128] With reference to Figure 1 and Figure 7 , the controller 500A can include a frequency analyzer 520, a representative value determiner 540, a voltage data generator 560, a lookup table 580, and a register 590. The power supply 600 can include a variable resistor circuit 620 and a voltage generator 640.

[0129] The register 590 can output a compensation factor CF reflecting a threshold voltage distribution P_Vth of a driving transistor (e.g., the first transistor T1) of the pixel PX. The threshold voltage distribution P_Vth can be determined through testing during a manufacturing process of the display device 1000. The threshold voltage distribution P_Vth can be an inherent characteristic of the display device 1000. For example, the threshold voltage distribution P_Vth can be an average value of threshold voltages of one or more driving transistors of the pixel PX included in the display device 1000, or a deviation between a reference value and the average value. The register 590 can output the compensation factor CF corresponding to the threshold voltage distribution P_Vth. The compensation factor CF can be digital data capable of adjusting the reference voltage Vref. Figure 2 The power supply 600 can output the reference voltage Vref based on the reference voltage data RVD and the compensation factor CF.

[0130]

[0131] ​​The variable resistor circuit 620 included in the power supply 600 can adjust a resistance value based on the reference voltage data RVD, and can change a voltage of the input power supply voltage Vin based on the resistance value. In an embodiment, the variable resistor circuit 620 can adjust the resistance value by further reflecting the compensation factor CF.

[0132] In an embodiment, the variable resistor circuit 620 can be implemented as a digital potentiometer. The digital potentiometer can store information about the reference voltage Vref corresponding to the reference voltage data RVD. Here, the information stored in the digital potentiometer can be updated or changed by the controller 500A, the power supply 600, or the like.

[0133] The reference voltage data RVD and the compensation factor CF can be used to adjust the input power supply voltage Vin by increasing or decreasing the resistance value of the variable resistor circuit 620. For example, the value of the reference voltage Vref can increase as the resistance value of the digital potentiometer increases. Here, the input power supply voltage Vin can be supplied from a battery or the like.

[0134] The variable resistor circuit 620 provides the input voltage Vin' adjusted by the variable resistor to the voltage generator 640. The voltage generator 640 can generate the reference voltage Vref based on the adjusted input voltage Vin'. For example, the voltage generator 640 can include a boost converter and / or a buck converter configured to adjust the level of the input voltage Vin'.

[0135] Thus, since the threshold voltage distribution P_Vth of the driving transistor of the pixel PX is additionally reflected in determining the reference voltage Vref, the reference voltage Vref can be controlled based on the characteristics of the display device 1000. Accordingly, the display device 1000 can alleviate image flicker of various frame frequencies FF.

[0136] Figure 8 is a circuit diagram illustrating another example of a pixel 11 included in the display device 1000 of Figure 1 .

[0137] For illustrative purposes, Figure 8 a pixel 11 coupled with an i-th horizontal line (or i-th pixel row) and a j-th data line Dj (here, i is a natural number less than or equal to n, and j is a natural number less than or equal to m) is illustrated.

[0138] Except for some transistors and signal lines, the pixel 11 is substantially the same as or similar to the pixel 10 described with reference to Figure 2 . Accordingly, like reference numerals will be used to designate similar or like components, and repeated explanations will be omitted.

[0139] With reference to Figure 8The pixel 11 can include a light emitting element LD, first to eighth transistors T1 to T8, and a storage capacitor Cst.

[0140] The first transistor T1 can control an amount of current flowing from the first power supply voltage VDD to the second power supply voltage VSS via the light emitting element LD in response to a voltage supplied to the first node N1. The second transistor T2 can electrically couple the data line Dj to the second node N2 in response to a first scan signal supplied to the first scan line S1i.

[0141] The third transistor T3 and the fourth transistor T4 can be coupled in series between the first node N1 and a third node N3. A gate electrode of the third transistor T3 and a gate electrode of the fourth transistor T4 can be coupled to a second scan line S2i.

[0142] The fifth transistor T5 can be coupled to a fourth node N4 between the third transistor T3 and the fourth transistor T4. The fifth transistor T5 can supply a reference voltage Vref to the fourth node N4. A gate electrode of the fifth transistor T5 can be coupled to an i-th first emission control line E1i (hereinafter referred to as a first emission control line). The fifth transistor T5 can be turned off by a first emission control signal (e.g., a high level) supplied to the first emission control line E1i.

[0143] The sixth transistor T6 can be coupled between the first power supply voltage VDD and the second node N2. A gate electrode of the sixth transistor T6 can be coupled to the first emission control line E1i.

[0144] The seventh transistor T7 is coupled between the third node N3 and the light emitting element LD. A gate electrode of the seventh transistor T7 can be coupled to an i-th second emission control line E2i (hereinafter referred to as a second emission control line). The seventh transistor T7 can be turned off by a second emission control signal (e.g., a high level) supplied to the second emission control line E2i.

[0145] In other words, the sixth transistor T6 and the seventh transistor T7 can be controlled by different emission control signals. In an embodiment, the second emission control signal can be supplied later than the first emission control signal. For example, the same emission control signal can be supplied to the second emission control line E2i and an (i+2)-th first emission control line (indicated as E1i+2 in Figure 9 ).

[0146] The eighth transistor T8 can supply an initialization voltage Vint to the third node N3. A gate electrode of the eighth transistor T8 can be coupled to a third scan line S3i. The eighth transistor T8 can be turned on by a third scan signal supplied to the third scan line S3i and can supply the initialization voltage Vint to the third node N3.

[0147] Figure 9 is a timing chart showing an example of a signal supplied to Figure 8 a pixel 11.

[0148] In the description of Figure 9 , repeated explanations described with reference to Figure 3 will be omitted.

[0149] With reference to Figure 1 , Figure 8 and Figure 9 , during a variable frequency driving operation for controlling the frame frequency FF, each frame period FP can include a first period P1 and a second period P2.

[0150] The first emission control signal, the second emission control signal, the first scan signal, and the third scan signal can be supplied to the first emission control line Ei, the second emission control line E2i, the first scan line S1i, and the third scan line S3i, respectively, at a first frequency. The second scan signal can be supplied to the second scan line S2i at a second frequency lower than the first frequency. For example, the second scan signal can be supplied only during the first period P1. The frequency of the second scan signal can be substantially the same as the frame frequency FF.

[0151] As the second frequency decreases or the difference between the first frequency and the second frequency increases, the iteration count of the second period P2 in the frame period FP can increase. For example, depending on the frame frequency FF, the frame period FP can include one first period P1 and a plurality of consecutive second periods P2.

[0152] During the first non-emission period NEP1, the first emission control signal (high level) and the second emission control signal (high level) can be supplied consecutively. For example, the second emission control signal can be the same as the first emission control signal supplied to the (i+2)th first emission control line E1i+2. In this case, the first emission control signal and the second emission control signal can have a time difference of two horizontal periods.

[0153] The first non-emission period NEP1 can include a first initialization period IP1, a second initialization period IP2, a write period WP, and a third initialization period IP3.

[0154] When the first emission control signal is supplied to the first emission control line E1i, the fifth transistor T5 and the sixth transistor T6 can be turned off.

[0155] Thereafter, the third scan signal can be supplied to the third scan line S3i during the first initialization period IP1. The eighth transistor T8 can be turned on in response to the third scan signal, and the initialization voltage Vint can be supplied to the first electrode of the light emitting element LD through the seventh transistor T7 in the on state. Thus, during the first initialization period IP1, the anode voltage of the light emitting element LD can be initialized.

[0156] During the second initialization period IP2, the second scan signal can be supplied to the second scan line S2i, and the third scan line can be supplied to the third scan line S3i. Thus, the third transistor T3, the fourth transistor T4, and the eighth transistor T8 can be turned on, and the initialization voltage Vint can be supplied to the first node N1 and the anode of the light emitting element LD again. Thus, the gate voltage of the first transistor T1 and the anode voltage of the light emitting element LD can be initialized.

[0157] Thereafter, during the write period WP, the first scan signal can be supplied to the first scan line S1i, and the second scan signal can be supplied to the second scan line S2i. During the write period WP, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be turned on, and the first transistor T1 can be diode-connected. Thus, data voltage application and threshold voltage compensation can be performed on the pixel 11.

[0158] Thereafter, the third scan signal can be supplied to the third scan line S3i during the third initialization period IP3. When the eighth transistor T8 is turned on, the initialization voltage Vint can be supplied to the third node N3. Thus, the drain voltage of the first transistor T1 (in the case where the first transistor T1 is a PMOS transistor) can be initialized. Since the voltage of the third node N3, which has been increased by threshold voltage compensation, is decreased by the initialization voltage Vint, an increase in the brightness of a black gray scale can be minimized.

[0159] Thereafter, during the first emission period EP1, the supply of the first emission control signal and the supply of the second emission control signal can be continuously interrupted (low level), and the sixth transistor T6 and the seventh transistor T7 can be continuously turned on. Thus, the light emitting element LD can emit light. In addition, the fifth transistor T5 can be turned on, and the reference voltage Vref can be supplied to the fourth node N4. Thus, during the first emission period EP1, leakage of a current flowing from the third node N3 to the first node N1 can be minimized.

[0160] During the second non-emission period NEP2, the first emission control signal, the second emission control signal, the first scan signal, and the third scan signal can be supplied to the first emission control line Ei, the second emission control line E2i, the first scan line S1i, and the third scan line S3i, respectively, and the second scan signal can not be supplied to the second scan line S2i. The second non-emission period NEP2 can include the first initialization period IP1, the bias period BP, and the third initialization period IP3. During the second non-emission period NEP2, the operations of the first initialization period IP1 and the third initialization period IP3 can be substantially the same as those of the first initialization period IP1 and the third initialization period IP3 during the first non-emission period NEP1.

[0161] During the second non-emission period NEP2, the light emitting element LD can emit light based on the voltage of the first node N1 supplied by the data voltage during the first non-emission period NEP1. Accordingly, the second initialization period IP2 can be omitted.

[0162] During the bias period BP, the first scan signal is supplied to the first scan line S1i, and the second transistor T2 can be turned on. The data voltage can be supplied to the second node N2 by turning on the second transistor T2. Accordingly, the first transistor T1 can be turned on and biased, and changes in the hysteresis characteristics of the first transistor T1 and changes in the emission brightness due to the low-frequency driving operation can be minimized.

[0163] Subsequently, during the third initialization period IP3, the initialization voltage Vint can be supplied to the third node N3.

[0164] During the second emission period EP2, the light emitting element LD can emit light based on the data voltage supplied during the first non-emission period NEP1.

[0165] However, this is for illustrative purposes only, and the structure of the pixel 11 for driving with a variable frame frequency FF and the timing of the scan signals and the emission control signals to be supplied to the pixel 11 are not limited thereto.

[0166] Since the iteration count of the second period P2 can vary depending on the frame frequency FF, the leakage current can change. In order to mitigate changes in brightness due to the leakage current and image flicker caused by changes in brightness during the second period P2, as described with reference to Figures 4 to 7 As described with reference to FIG. 6, the controller 500 (or the controller 500A) of the display apparatus 1000 can control the reference voltage Vref depending on the frame frequency FF.

[0167] Figure 10 is a flowchart illustrating a method of driving the display apparatus 1000 according to an embodiment of the present disclosure. Figure 11is a flowchart illustrating an example of a method of generating reference voltage data RVD according to an embodiment of the disclosure.

[0168] Referring to Figure 10 and Figure 11 , the method of driving the display apparatus 1000 can include a step S100 of determining a frame frequency FF, a step S200 of determining a representative value RGV of a gray scale of a frame, a step S300 of generating reference voltage data RVD corresponding to a reference voltage Vref based on the frame frequency FF and the representative value RGV, and a step S400 of supplying the reference voltage Vref to the pixels PX based on the reference voltage data RVD.

[0169] The frame frequency FF can be determined (at step S100) based on at least one of a data enable signal DE and a vertical synchronization signal Vsync.

[0170] The representative value RGV of the gray scale of the frame can be determined (at step S200) based on a gray scale included in image data DAT of the frame. For example, the representative value RGV can be an average value of the gray scale of the frame.

[0171] The reference voltage data RVD can be generated (at step S300) based on the detected frame frequency FF and the calculated representative value RGV.

[0172] Referring to Figure 11 , the frame frequency FF and the reference frequency RF can be compared with each other (at step S320). In a case where the frame frequency FF is equal to or greater than the reference frequency RF, a default value of the reference voltage data RVD can be output regardless of the frame frequency FF and the representative value RGV (at step S360). In a case where the frame frequency FF is less than the reference frequency RF, the reference voltage data RVD corresponding to the frame frequency FF and the representative value RGV can be calculated with reference to the look-up table 580 (at step S340).

[0173] Further, the reference voltage Vref can be supplied to the pixels PX based on the reference voltage data RVD (at step S400).

[0174] The method of driving the display apparatus 1000 has been described with reference to Figures 1 to 9 , and thus repetitive description thereof will be omitted.

[0175] As described above, in the display apparatus 1000 and the method of driving the display apparatus 1000 according to an embodiment of the disclosure, the reference voltage Vref can be controlled based on the frame frequency FF and the representative value RGV of the gray scale of the corresponding frame. Accordingly, in response to a change in the frame frequency FF, by controlling the reference voltage Vref, the display apparatus 1000 can minimize a leakage current in the pixels PX and alleviate image flicker.

[0176] Further, since the leakage current can be minimized depending on the frame frequency FF, the display device 1000 can display a static image at a very low frequency. Accordingly, the display device 1000 can implement a reliable low-power driving operation while reducing power consumption.

[0177] Although the embodiments of the present disclosure have been described above with reference to various embodiments, it will be apparent to those skilled in the art that various modifications, additions and substitutions can be made thereto without departing from the scope and spirit of the disclosure as included in the following claims.

Claims

1. A display device, comprising: Pixels, wherein the pixels are configured to display an image based on image data and a reference voltage; A controller configured to generate reference voltage data corresponding to the reference voltage based on the frame frequency, the reference voltage being used to suppress leakage current in the pixel; as well as A power supply configured to generate a reference voltage based on the reference voltage data and supply the reference voltage to the pixel. The controller further includes: A register configured to output a compensation factor reflecting the distribution of the threshold voltage of the driving transistor of the pixel, and The power supply outputs the reference voltage based on the reference voltage data and the compensation factor.

2. The display device according to claim 1, wherein, The controller also refers to the representative value of the grayscale of the image data to determine the reference voltage data.

3. The display device according to claim 2, wherein, The representative value is the average gray level included in the image data of a frame.

4. The display device according to claim 2, wherein, With the representative value remaining the same, the reference voltage changes as the frame frequency changes from a first frequency to a second frequency. Wherein, with the same frame frequency, the reference voltage changes as the representative value changes from a first value to a second value.

5. The display device according to claim 2, wherein, The controller includes: A frequency analyzer configured to determine the frame frequency based on at least one of a vertical synchronization signal and a data enable signal supplied from an external device; A representative value determiner, the representative value determiner being configured to determine the representative value based on grayscale values ​​included in the image data; and A voltage data generator is configured to generate the reference voltage data by referring to a lookup table, the lookup table storing multiple values ​​of the reference voltage corresponding to the frame frequency and the grayscale.

6. The display device according to claim 5, wherein, The voltage data generator includes: A comparator configured to compare the frame frequency with a reference frequency; and A data determiner configured to determine the reference voltage data based on the comparison result of the comparator.

7. The display device according to claim 6, wherein, When the frame frequency is equal to or greater than the reference frequency, the data determiner outputs a default value for the reference voltage data corresponding to a default value among the plurality of values ​​of the reference voltage, and Wherein, if the frame frequency is lower than the reference frequency, the data determiner refers to the lookup table to determine the reference voltage data.

8. The display device according to claim 6, wherein, The data determiner extracts multiple reference values ​​from the lookup table based on the frame frequency and the representative value, and calculates the reference voltage data by interpolating the multiple reference values.

9. The display device according to claim 1, wherein, The power source includes: A variable resistor circuit configured to adjust the resistance value based on the reference voltage data and to change the input power supply voltage based on the resistance value.

10. The display device according to claim 1, further comprising: A data driver configured to supply data voltage to the pixel via a data line based on the image data; A scan driver configured to supply a first scan signal to the pixel via a first scan line and a second scan signal to the pixel via a second scan line; as well as A transmit driver, configured to supply a first transmit control signal to the pixel via a first transmit control line. The pixels include: Light-emitting elements; The first transistor is configured to control the drive current based on the voltage of the first node and is connected between the second node and the third node. The second transistor is connected between the data line and the second node and is configured to be turned on by the first scan signal supplied to the first scan line; A third transistor and a fourth transistor are connected in series between the first node and the third node, and are configured to be turned on by the second scan signal supplied to the second scan line; A fifth transistor, configured to supply the reference voltage to a fourth node between the third and fourth transistors, and to be turned off by the first transmit control signal supplied to the first transmit control line; and A sixth transistor, which is connected between the first power supply voltage and the second node, and configured to be turned off by the first transmit control signal.

11. The display device according to claim 10, wherein, The scan driver is further configured to supply a third scan signal to the pixel via a third scan line and a fourth scan signal to the pixel via a fourth scan line; and The pixels further include: A seventh transistor, which is connected between the third node and the light-emitting element, and configured to be turned off by the first emission control signal; The eighth transistor is configured to supply an initialization voltage to the light-emitting element and to be turned on by the third scan signal supplied to the third scan line; A ninth transistor and a tenth transistor, the ninth transistor and the tenth transistor being connected in series between the first node and a power line for supplying the initialization voltage, and configured to be turned on by the fourth scan signal supplied to the fourth scan line; and The eleventh transistor is configured to supply the reference voltage to a fifth node between the ninth and tenth transistors and is turned off by the first transmit control signal.

12. The display device according to claim 11, wherein, The first scan line and the second scan line are supplied with the same scan signal.

13. The display device according to claim 10, wherein, The scan driver is further configured to supply a third scan signal to the pixel via a third scan line. The transmit driver is further configured to supply a second transmit control signal to the pixel via a second transmit control line. The pixels further include: A seventh transistor, connected between the third node and the light-emitting element, and configured to be turned off by a second emission control signal supplied to the second emission control line; and An eighth transistor, configured to supply an initialization voltage to the third node and to be turned on by the third scan signal supplied to the third scan line, and The second transmission control signal is supplied later than the first transmission control signal.

14. The display device according to claim 10, wherein, The first scan signal is supplied to the first scan line at a first frequency equal to the frame frequency, and Wherein, the second frequency at which the first transmit control signal is supplied to the first transmit control line is greater than the frame frequency.

Images