Fan-out substrates and methods of forming the same

Abstract

Embodiments of the present application provide a fan-out substrate, comprising: a substrate; a fan-out layer on the substrate; a via connecting to the substrate through the fan-out layer, the fan-out layer having a crack structure on an upper surface of the fan-out layer and a second surface of the fan-out layer in contact with the via. The purpose of the present application is to provide a fan-out substrate and a forming method thereof to optimize the performance of the fan-out substrate.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a fan-out substrate and a method of forming the same. BACKGROUND

[0002] In a fan-out substrate (FOSub) structure, a fan-out layer is first bonded to a substrate, then laser drilling is performed, and then a plating process of a connection via is performed to electrically connect the fan-out layer and the substrate. For the current fan-out layer, since the surface of the dielectric layer is relatively smooth, the adhesion with the metal is not good when the via is formed by electroplating, which easily causes peeling problems. If a plasma vapor deposition method (PVD) is used, the via hole will be too small, which will have the risk of subsequent electroplating being unable to fill. SUMMARY

[0003] In view of the problems in the related art, the purpose of the present application is to provide a fan-out substrate and a method of forming the same to optimize the performance of the fan-out substrate.

[0004] To achieve the above-mentioned purpose, an embodiment of the present application provides a fan-out substrate, comprising: a substrate; a fan-out layer located on the substrate; a via passing through the fan-out layer to connect to the substrate, the upper surface of the fan-out layer and the second surface of the fan-out layer in contact with the via having a crack structure.

[0005] In some embodiments, the via includes a first seed layer in contact with the fan-out layer, the first seed layer filling within the crack structure on the second surface of the dielectric layer of the fan-out layer.

[0006] In some embodiments, Pd particles are included between the first seed layer and the dielectric layer.

[0007] In some embodiments, the crack structure on the first surface of the dielectric layer has a residual seed layer within.

[0008] In some embodiments, the material of the first seed layer and the residual seed layer includes Ni.

[0009] In some embodiments, the Ni is bonded with the material of the dielectric layer.

[0010] In some embodiments, the thickness of the first seed layer is 0.1-0.5 μm.

[0011] In some embodiments, the diameter of the via is 10-50 μm.

[0012] In some embodiments, the via includes a first metal layer adhering to the first seed layer and a second metal layer surrounded by the first metal layer, the thickness of the first seed layer being less than the thickness of the first metal layer which is less than or equal to the thickness of the second metal layer.

[0013] In some embodiments, the first metal layer and the second metal layer include the same material.

[0014] Embodiments of the present application also provide a method for forming a fan-out substrate, comprising: forming a fan-out layer on a substrate; forming an opening through the fan-out layer to expose the substrate; performing a surface roughening treatment on the fan-out layer; and forming a via in the opening.

[0015] In some embodiments, the surface roughening treatment comprises soaking sodium hydroxide.

[0016] In some embodiments, forming the via comprises: using Ni to form a surface ion bond with the dielectric layer of the fan-out layer after the surface roughening treatment to form a first seed layer on the fan-out layer and in the opening.

[0017] In some embodiments, before the surface ion bonding, Pd is plated on the surface of the dielectric layer of the fan-out layer after the surface roughening treatment.

[0018] In some embodiments, forming the via further comprises: after the surface ion bonding, plating a first metal layer on the first seed layer.

[0019] In some embodiments, forming the via further comprises: covering a second metal layer on the first metal layer; and removing the first seed layer, the first metal layer and the second metal layer outside the opening.

[0020] In some embodiments, part of the first seed layer in the crack structure on the upper surface of the dielectric layer is not removed.

[0021] In some embodiments, the first metal layer and the second metal layer comprise the same material.

[0022] In some embodiments, the thickness of the first metal layer is 0.02 μm to 5 μm.

[0023] In some embodiments, the ratio of the thickness of the first metal layer to the second metal layer is 0.01 to 1. BRIEF DESCRIPTION OF DRAWINGS

[0024] Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings in which: It should be noted that, in accordance with standard practice, the various elements are not drawn to scale. In fact, the dimensions of the various elements can be arbitrarily increased or decreased for clarity of discussion.

[0025] Figures 1-6B A process for forming a fan-out substrate according to embodiments of the present application is shown.

[0026] Figures 7A-7D A process for forming another embodiment of a fan-out substrate of the present application is shown. DETAILED DESCRIPTION

[0027] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0028] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0029] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0030] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0031] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0032] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0033] The fan-out substrate and its formation method of this application will be described in detail below with reference to the accompanying drawings.

[0034] See Figure 1 A fan-out layer 12 is formed on the substrate 10, and an opening 14 is formed through the fan-out layer 12 to expose the substrate 10. The fan-out layer 12 includes a dielectric layer 16 and a circuit structure 18 located in the dielectric layer 16, and the opening 14 passes through the dielectric layer 16 and the circuit structure 18.

[0035] See Figure 2 The fan-out layer 12 is subjected to a surface roughening treatment, which includes immersion in sodium hydroxide. After the surface roughening treatment is performed, a crack structure 20 is formed on the upper surface of the dielectric layer 16 of the fan-out layer 12 and on the surface located in the opening 14.

[0036] See Figure 3A A first seed layer 30 is formed on the fan-out layer 12 and in the opening 14. In some embodiments, the first seed layer 30 comprises Ni and is formed by electroless plating, wherein the Ni is surface-ion bonded to the surface-roughened dielectric layer 16 of the fan-out layer 12. A first metal layer 32 is formed on the first seed layer 30. In some embodiments, the first metal layer 32 comprises Cu and is formed by electroless plating. In some embodiments, the thickness of the first metal layer 32 is greater than the thickness of the first seed layer 30, and the thickness of the first metal layer 32 is less than or equal to the thickness of the second metal layer 40. In some embodiments, the thickness of the first seed layer 30 is 0.02 μm to 5 μm, for example, 1.25 μm. In some embodiments, the depth of the crack structure 20 is 0.1 μm to 0.5 μm. In some embodiments, the thickness of the first seed layer 30 is in the range of 0.1 μm to 0.1 μm. In some embodiments, the ratio of the thickness of the first seed layer 30 to the thickness of the first metal layer 32 is 0.01 to 1, for example, 0.5.

[0037] Figure 3B It shows in Figure 2 The soaking sodium hydroxide solution shown and Figure 3AThe molecular formula of the material at the upper surface of the dielectric layer 16 (e.g., PI) changes during the Ni plating process shown. Without surface roughening treatment, the surface of the dielectric layer 16 is smooth and has no hydrophilic functional groups. After surface roughening treatment, the functional groups -COO- and -NH- make the surface of the dielectric layer 16 hydrophilic, and the improved hydrophobicity will increase the adhesion between Ni and PI.

[0038] In some embodiments, the first seed layer 30 is not formed, and the first metal layer 32 is formed directly on the surface of the dielectric layer 16 after surface roughening treatment.

[0039] See Figure 4 A second metal layer 40 is formed on the first metal layer 32. In some embodiments, the second metal layer 40 comprises Cu and is formed by electroplating. In some embodiments, the material of the second metal layer 40 is different from that of the first metal layer 32. In some embodiments, a mask layer is first formed on the first metal layer 32, the mask layer is patterned to expose the first metal layer 32 corresponding to the opening 14, and the mask layer is removed after the second metal layer 40 is formed on the exposed first metal layer 32.

[0040] See Figure 5 The first metal layer 32 and the first seed layer 30 are patterned to form a via 50 including the first seed layer 30, the first metal layer 32, and the second metal layer 40. In some embodiments, a residual seed layer 31 of the first seed layer 30 is also retained in the crack structure 20 at the upper surface of the dielectric layer 16. In some embodiments, no residual seed layer 31 is present on the portion of the upper surface of the dielectric layer 16 exposed by the via 50.

[0041] Figure 6A and Figure 6B It shows Figure 5 A magnified view of region 55 in the middle, where, for clarity, Figure 6A and Figure 6B Not with Figure 5 Shown to scale. Figure 6A In the illustrated embodiment, the residual seed layer 31 is located within the crack structure 20 on the upper surface of the dielectric layer 16. Figure 6B In the illustrated embodiment, there is no residual seed layer 31. In some embodiments, the first seed layer 30 is smaller than the size of the crack structure 20, such that the first metal layer 32 also extends into the crack structure 20. An embodiment of the present invention provides a fan-out substrate 65, comprising: a substrate 10; a fan-out layer 12 located on the substrate 10; a through-hole 50 passing through the fan-out layer 12 and connected to the substrate 10, wherein the upper surface 66 of the fan-out layer 12 and the second surface 68 of the fan-out layer 12 in contact with the through-hole 55 have crack structures 20.

[0042] Figures 7A-7DIt shows Figures 2-3A Conceptual diagrams of other embodiments of the intermediate steps. See also Figure 7A After Figure 2 After the roughening treatment shown, the surface of dielectric layer 16 is swelled. In some embodiments, the material of dielectric layer 16 is polyimide (PI). The surface of dielectric layer 16 is surface treated by immersing it in potassium manganate (KMnO4) to remove the overly loose structure 70 on the surface of dielectric layer 16 and to generate a negative charge 72 on the surface of dielectric layer 16.

[0043] See Figure 7B Pd is electroplated (E'less) on the surface of dielectric layer 16. Since Pd is positively charged, it will bond with the negatively charged 72 ions on the surface of dielectric layer 16 to form... Figure 7C The Pd seed layer 74 is shown.

[0044] See Figure 7C The process involves electroless Ni plating, where Ni contacts and forms a surface bond with the dielectric layer 16 exposed from the Pd seed layer 74. Since Pd will undergo ion substitution with Cu when Cu is directly electroless plated, Ni is electroless plated first to form the first seed layer 30 before Cu plating.

[0045] See Figure 7D Then, Cu is electroplated onto the first seed layer 30 to form the first metal layer 32.

[0046] In embodiments of the present invention, before the ion bonding process, the dielectric layer 16 is immersed in sodium hydroxide (NaOH) to disrupt the PI surface bonds, thereby roughening the surface and creating micropores (crack / fracture structure 20) to increase the plating area during subsequent electroless plating and improve the bonding force between the via 50 and the fan-out layer 12. Embodiments of the present invention increase the surface roughness of the dielectric layer 16 through pretreatment, creating a fan-out substrate structure with a roughened PI surface, thereby improving process yield and reducing production costs. This application allows the diameter of the via 50 to be controlled between 10 μm and 50 μm, and further, between 10 μm and 20 μm, to increase design flexibility and further reduce package size.

[0047] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method of forming a fan-out substrate, the method comprising: Comprising: forming a fan-out layer on a substrate; forming an opening through the fan-out layer to expose the substrate; surface-roughening the fan-out layer; after the roughening, soaking the surface of a dielectric layer of the fan-out layer in potassium permanganate to surface-treat the surface of the dielectric layer to produce a negative charge on the surface of the dielectric layer; electroplating Pd on the surface of the dielectric layer, the positive charge of the Pd ion-bonding with the negative charge on the surface of the dielectric layer to form a Pd seed layer; forming a via in the opening; wherein forming the via includes using Ni to contact and surface-ion-bond with the dielectric layer exposed by the Pd seed layer to form a first seed layer on the fan-out layer and in the opening.

2. The method of claim 1, wherein The surface-roughening includes soaking in sodium hydroxide.

3. The method of claim 1, wherein Before the surface-ion-bonding, electroplating Pd on the surface of the dielectric layer of the fan-out layer after the surface-roughening.

4. The method of claim 1, wherein Forming the via further includes: after the surface-ion-bonding, electroplating a first metal layer on the first seed layer.

5. The method of claim 4, wherein, Forming the via further includes: overlying a second metal layer on the first metal layer; removing portions of the first seed layer, the first metal layer, and the second metal layer outside the opening.

6. The method of claim 5, wherein Portions of the first seed layer in a crack structure on the upper surface of the dielectric layer are not removed.

7. The method of claim 5, wherein The first metal layer and the second metal layer include the same material.

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