Light detector

Abstract

A photodetector (100) comprises: a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; an epitaxial layer formed on the semiconductor substrate; a multiplication region in the epitaxial layer that is substantially parallel to the first main surface and avalanche multiplies charges generated by photoelectric conversion on the semiconductor substrate; and a separation region that separates at least two of the multiplication regions.

Description

[0001] This application is a divisional application of the invention patent application with application date of March 28, 2019, application number 201980021367.2, and invention name “Photodetector”. Technical Field

[0002] The present disclosure relates to light detectors. Background Art

[0003] In recent years, highly sensitive photodetectors have been used in a wide range of fields, including medicine, communications, biology, chemistry, surveillance, automotive applications, and radiation detection. One method for achieving this high sensitivity is the use of avalanche photodiodes (APDs). APDs multiply the signal charge generated by photoelectric conversion of light incident on a photoelectric conversion layer through avalanche breakdown, thereby increasing light detection sensitivity. APDs can also detect even small amounts of photons.

[0004] For example, a photon counting type photodetector using an APD (for example, see Patent Document 1) and a high-sensitivity image sensor (for example, see Patent Document 2) have been proposed.

[0005] Furthermore, for example, as an example of the structure of an APD, a pull-through type APD is disclosed (for example, refer to Patent Documents 2 and 3).

[0006] Furthermore, a structure has been proposed in which the avalanche breakdown voltage is not increased even if the photoelectric conversion layer is thickened (for example, see Patent Document 4).

[0007] According to this structure, a built-in potential gradient is formed in the photoelectric conversion layer, thereby causing charge to drift. Therefore, the photoelectric conversion film can be thickened without increasing the avalanche breakdown voltage.

[0008] Furthermore, in order to increase the degree of freedom of a circuit for reading out the charge detected by the APD, a structure has been proposed in which pixels and pixel circuits are arranged close to each other (for example, see Patent Documents 5 and 6).

[0009] Furthermore, a structure has been proposed in which a wafer having an APD array formed thereon is bonded to another wafer having an interface circuit to thereby increase the degree of freedom of the circuit (for example, see Patent Document 7).

[0010] (Prior art literature)

[0011] (Patent Document)

[0012] Patent Document 1: International Publication No. 2008 / 004547

[0013] Patent Document 2: International Publication No. 2014 / 097519

[0014] Patent Document 3: Japanese Patent Application Laid-Open No. 2015-5752

[0015] Patent Document 4: U.S. Patent Application Publication No. 2016 / 0163906

[0016] Patent Document 5: Japanese Patent Application Laid-Open No. 2004-363437

[0017] Patent Document 6: Japanese Patent Application Laid-Open No. 2004-319576

[0018] Patent Document 7: U.S. Patent No. 8,093,624

[0019] Patent Document 8: U.S. Patent No. 9178100 Summary of the Invention

[0020] The present disclosure provides a photodetector with high sensitivity.

[0021] In order to solve the above-mentioned problem, one form of the present disclosure involves a photodetector comprising: a semiconductor substrate having a first main surface and a second main surface on the side opposite to the first main surface; an epitaxial layer formed on the semiconductor substrate; a multiplication region in the epitaxial layer that is approximately parallel to the first main surface and avalanche multiplies the charge generated by photoelectric conversion on the semiconductor substrate; and a separation region that separates at least two of the multiplication regions.

[0022] With this structure, the first charge, or carriers of the first conductivity type among the charges generated in the photoelectric conversion layer, drift within the photoelectric conversion layer and enter the multiplication region, generating avalanche multiplication. The charges generated by photoelectric conversion are amplified by avalanche multiplication, enabling light detection even when the intensity of the incident light is low. This structure improves the sensitivity of the photodetector (i.e., its light-receiving sensitivity).

[0023] For example, the structure disclosed in Patent Document 7 cannot be manufactured by a CMOS (Complementary Metal Oxide Semiconductor) process.

[0024] On the other hand, a photodetector according to one aspect of the present disclosure can form an APD and pixel circuits such as discrete transistors within the same semiconductor substrate, allowing for manufacturing using a standard CMOS process. Consequently, the photodetector according to one aspect of the present disclosure can be manufactured at a lower cost.

[0025] Furthermore, for example, the photodetector further has a second contact member formed on the second main surface, and a second charge among the charges generated by photoelectric conversion between the first semiconductor layer and the second semiconductor layer flows to the outside of the semiconductor substrate through the second contact member, and the polarity of the second charge is different from that of the first charge.

[0026] With this structure, the second conductivity type carriers, ie, the second charges, generated by photoelectric conversion and avalanche multiplication are discharged to the outside of the photodetector via the second contact located on the second main surface, which is the back side of the semiconductor substrate.

[0027] According to one aspect of the present disclosure, a photodetector can quickly discharge the second charge, which is not used as a signal during light detection, through the back surface of the semiconductor substrate. This reduces temporal variations and positional nonuniformity in the voltage on the back surface of the semiconductor substrate (e.g., the first and second semiconductor layers). This reduces spatial and temporal variations in light detection efficiency.

[0028] For example, according to the structure disclosed in Patent Document 8, the anode and cathode are arranged on the same surface. Therefore, the drift direction of the charge during avalanche multiplication is opposite to the direction of the charge movement during charge discharge. Therefore, the time until the charge is discharged becomes longer and the detection efficiency is reduced.

[0029] Furthermore, for example, the separation region separates the first semiconductor layer and the circuit region by an electric potential.

[0030] This structure can narrow the isolation region, improve the aperture ratio, and achieve pixel miniaturization. In addition, it can be formed more simply than when forming a trench or the like to form the isolation region.

[0031] Furthermore, for example, the potential is greater than a voltage change of the first semiconductor layer caused by charges generated by the avalanche multiplication.

[0032] According to such a structure, even when a voltage change occurs in the first semiconductor layer, the first semiconductor layer and the circuit region can be electrically isolated by the isolation region.

[0033] And, for example, the separation region is depleted.

[0034] In a photodetector according to one aspect of the present disclosure, the first semiconductor layer and the circuit region are separated by a separation region. By making the separation region depleted, the first semiconductor layer and the circuit region can be separated with a short separation width, and the electric field in the separation region is mitigated. Consequently, the photodetector according to one aspect of the present disclosure can maintain light sensitivity while achieving miniaturization. Consequently, the photodetector according to one aspect of the present disclosure has an improved aperture ratio, thereby enhancing light sensitivity.

[0035] Furthermore, for example, no STI (Shallow Trench Isolation) or contact is formed in the region where the first semiconductor layer and the isolation region are formed.

[0036] According to this structure, unlike the structure disclosed in Patent Document 4, no STI or first contact is formed on the isolation region, thereby suppressing dark current.

[0037] Furthermore, for example, the second semiconductor layer has the same shape as that of the first semiconductor layer in a planar view, or is wider than the first semiconductor layer.

[0038] According to such a structure, the avalanche multiplication region is expanded, and thus the photosensitivity of the photodetector is further improved.

[0039] Furthermore, for example, the second semiconductor layer is formed on the entire surface of the first main surface.

[0040] According to such a structure, the avalanche multiplication region is further expanded, and therefore the photosensitivity of the photodetector is further improved.

[0041] When a contact is provided in the isolation region as in Patent Documents 4 and 8, the avalanche multiplication region cannot be expanded to prevent electric field concentration at the end of the avalanche multiplication region.

[0042] In Patent Document 4, the enriched region needs to be formed narrower than the anode region, and the multiplication region cannot be expanded.

[0043] Furthermore, in Patent Document 8, a guard ring is provided between the avalanche multiplication region and the contact in order to prevent electric field concentration at the end of the avalanche multiplication region. Therefore, the avalanche multiplication region cannot be expanded.

[0044] Furthermore, for example, the impurity concentration of the second semiconductor layer increases toward the depth direction.

[0045] The photoelectric conversion layer stacked in the avalanche multiplication region needs to be thickened. However, in the structures disclosed in Patent Documents 1, 2, and 3, this increases the avalanche breakdown voltage. Furthermore, the structure disclosed in Patent Document 5 requires applying a high voltage, exceeding the avalanche breakdown voltage, to the wiring.

[0046] On the other hand, according to the photodetector according to one aspect of the present disclosure, the photoelectric conversion film can be thickened without increasing the avalanche breakdown voltage, thereby achieving both low avalanche breakdown voltage and high light receiving sensitivity.

[0047] Furthermore, for example, the impurity concentration distribution of the second semiconductor layer is substantially constant in a direction parallel to the first main surface.

[0048] With this structure, the potential of the isolation region fluctuates less horizontally relative to the semiconductor substrate surface, and the electric field in the avalanche multiplication region becomes uniform. This allows the avalanche multiplication region to be further expanded, thereby further improving photosensitivity.

[0049] Furthermore, for example, a photodetector according to one embodiment of the present disclosure further includes at least one first well formed in the circuit region, the first well being of the first conductivity type, and an impurity concentration at a boundary between the first well and the second semiconductor layer being lower than that of the first semiconductor layer.

[0050] According to this structure, the electric field and current generated in the first well can be reduced, thereby reducing power consumption.

[0051] Furthermore, for example, the first well is formed closer to the second main surface than the first semiconductor layer.

[0052] According to such a structure, the electric field generated in the first well can be further reduced, thereby further reducing power consumption.

[0053] Furthermore, for example, the impurity concentration distribution of the second semiconductor layer has a steep concentration gradient from the first main surface toward the second main surface.

[0054] This structure allows the first charge generated in the deep region to drift at a higher speed. Therefore, the response time from when the photodetector according to one aspect of the present disclosure receives light to when the charge is read out by the readout circuit can be shortened, and the variation in the response time can be reduced.

[0055] Furthermore, for example, the interface between the first semiconductor layer and the second semiconductor layer is formed on a side closer to the second main surface than a portion of the upper surface of the second semiconductor layer.

[0056] According to such a structure, the variation in avalanche breakdown voltage is reduced.

[0057] Furthermore, for example, in a region including the interface between the first semiconductor layer and the second semiconductor layer, the impurity concentration of the first semiconductor layer is higher than the impurity concentration of the second semiconductor layer.

[0058] According to such a structure, the difference in avalanche breakdown voltage is further reduced.

[0059] Furthermore, for example, the impurity concentration of the second semiconductor layer is 10 16 cm -3 above.

[0060] With such a structure, the avalanche breakdown voltage can be set to 50 V or less.

[0061] Furthermore, for example, the first semiconductor layer has a region where the impurity concentration increases toward the depth direction.

[0062] With this structure, the charges generated at the Si-SiO2 interface (first main surface) of the first semiconductor layer drift away from the avalanche multiplication region, thereby reducing the DCR (Dark Count Rate).

[0063] Furthermore, for example, the first semiconductor layer includes a second conductivity type layer in contact with the first main surface of the semiconductor substrate.

[0064] According to such a structure, DCR is further reduced.

[0065] Furthermore, for example, a photodetector according to one aspect of the present disclosure includes a plurality of first contacts and a plurality of separation transistors. The plurality of separation transistors are connected to any one of the plurality of first contacts, and the plurality of separation transistors are formed in one circuit region.

[0066] With such a structure, the photodetector according to one aspect of the present disclosure can reduce the circuit area, thereby further improving the aperture ratio and achieving miniaturization.

[0067] And, for example, at least two separation transistors among the plurality of separation transistors share the readout circuit.

[0068] With such a structure, the photodetector according to one aspect of the present disclosure can further reduce the circuit area, thereby further improving the aperture ratio and achieving miniaturization.

[0069] Furthermore, for example, at least two of the separation transistors share a drain connected to the readout circuit.

[0070] According to such a structure, the circuit area can be further reduced, thereby further improving the aperture ratio and achieving miniaturization.

[0071] Furthermore, for example, in a planar view, N first semiconductor layers are formed within an N-gon having M-fold rotational symmetry in a manner that maintains the M-fold rotational symmetry, and the circuit area is formed at the rotational symmetry center of the N-gon having the M-fold rotational symmetry. Within the circuit area, N separate transistors are formed, where M is a natural number greater than 2 and N is a natural number greater than 3.

[0072] According to such a structure, the difference in sensitivity between pixels included in the repetition period is reduced. Therefore, the photodetector according to one aspect of the present disclosure can improve the quality of the captured image.

[0073] Furthermore, for example, the readout circuit includes, within the circuit area, a reset transistor connected to the drain of the separation transistor for resetting the first semiconductor layer via the separation transistor; a source follower transistor for reading out an output signal from the separation transistor; and a selection transistor connected to the source follower transistor.

[0074] With this configuration, the signal for each pixel can be amplified, thereby improving the S / N ratio.

[0075] Furthermore, one form of the present disclosure involves a photodetector comprising: a semiconductor substrate having a first main surface and a second main surface on a side opposite to the first main surface; a first semiconductor layer having a first conductivity type, formed on the first main surface side of the semiconductor substrate; a second semiconductor layer having a second conductivity type, formed between the first semiconductor layer and the second main surface of the semiconductor substrate, the second conductivity type being a conductivity type different from the first conductivity type; a multiplication region, in which charges generated by photoelectric conversion in the semiconductor substrate are avalanche multiplied in the first semiconductor layer and the second semiconductor layer; and a separation region, which separates at least two of the multiplication regions.

[0076] With this structure, the charge generated in the photoelectric conversion layer drifts within the layer and enters the multiplication region, generating avalanche multiplication. The charge generated by photoelectric conversion is amplified by avalanche multiplication, enabling light detection even when the incident light intensity is low. This structure improves the sensitivity of the photodetector (i.e., its light-receiving sensitivity).

[0077] Furthermore, according to such a structure, it is not necessary to form a contact or STI in the isolation region, and the isolation region can be narrowed. Therefore, the area of ​​the multiplication region of the photodetector can be expanded, thereby improving the photosensitivity.

[0078] Furthermore, for example, the photodetector further includes a second contact member formed on the second main surface, and one of a first charge generated by photoelectric conversion between the first semiconductor layer and the second semiconductor layer and a second charge having a polarity different from that of the first charge flows to the outside of the semiconductor substrate via the second contact member.

[0079] With this structure, for example, the second-conductivity-type carriers (i.e., second charges) generated by photoelectric conversion and avalanche multiplication are discharged to the exterior of the photodetector via contacts located on the back side (i.e., the second main surface) of the semiconductor substrate. This reduces temporal variations and positional variations in the voltage on the back side of the semiconductor substrate. This also reduces spatial and temporal variations in the photodetection efficiency of the photodetector.

[0080] And, for example, the separation region separates at least two of the multiplication regions by an electric potential.

[0081] According to such a structure, compared with the case where a contact or STI is formed in the isolation region as in Patent Documents 4 and 8, the isolation region can be narrowed, the aperture ratio can be increased, and the photosensitivity can be improved.

[0082] Furthermore, for example, the potential is greater than a voltage change of the first semiconductor layer caused by charges generated by the avalanche multiplication.

[0083] According to such a structure, even when a voltage change occurs in the first semiconductor layer, the two multiplication regions can be electrically separated by the separation region, so that electrical mixed colors due to overflow do not occur.

[0084] And, for example, the separation region is depleted.

[0085] With this structure, the separation region is depleted, allowing the two multiplication regions to be separated by a shorter separation width, and the electric field in the separation region is mitigated. Accordingly, a photodetector according to one embodiment of the present disclosure can increase the aperture ratio and improve light sensitivity. Furthermore, light sensitivity can be ensured, and miniaturization can be achieved. Therefore, a photodetector according to one embodiment of the present disclosure can increase the aperture ratio.

[0086] Furthermore, for example, in the region where the first semiconductor layer and the isolation region are formed, the STI and the contact are not formed.

[0087] According to such a structure, the defect level density on the surface of the semiconductor substrate can be reduced, and the generation of dark current can be suppressed.

[0088] Furthermore, for example, the second semiconductor layer has the same shape as that of the first semiconductor layer in a planar view, or is wider than the first semiconductor layer.

[0089] According to such a structure, the avalanche multiplication region is expanded, and the photosensitivity of the photodetector is further improved.

[0090] Furthermore, for example, the photodetector further includes a plurality of the first semiconductor layers, and the second semiconductor layer is continuously formed on the semiconductor substrate so as to overlap with the plurality of the first semiconductor layers in a plan view.

[0091] According to such a structure, the avalanche multiplication region is further expanded, and therefore the photosensitivity of the photodetector is further improved.

[0092] When a contact is provided in the isolation region as in Patent Documents 4 and 8, the avalanche multiplication region cannot be expanded to prevent electric field concentration at the end of the avalanche multiplication region.

[0093] Furthermore, in Patent Document 4, the enriched region needs to be formed narrower than the anode region, and the multiplication region cannot be expanded.

[0094] Furthermore, in Patent Document 8, a guard ring is provided between the avalanche multiplication region and the contact in order to prevent electric field concentration at the end of the avalanche multiplication region. Therefore, the avalanche multiplication region cannot be expanded.

[0095] Furthermore, for example, the impurity concentration of the second semiconductor layer increases toward the depth direction.

[0096] The photoelectric conversion layer stacked in the avalanche multiplication region needs to be thickened. However, in the structures disclosed in Patent Documents 1, 2, and 3, this increases the avalanche breakdown voltage. Furthermore, the structure disclosed in Patent Document 5 requires applying a high voltage, exceeding the avalanche breakdown voltage, to the wiring.

[0097] On the other hand, according to the photodetector according to one aspect of the present disclosure, the photoelectric conversion film can be thickened without increasing the avalanche breakdown voltage, thereby achieving both low avalanche breakdown voltage and high light receiving sensitivity.

[0098] Furthermore, for example, the impurity concentration distribution of the second semiconductor layer is substantially constant in a direction parallel to the first main surface.

[0099] With this structure, the potential of the isolation region fluctuates less horizontally relative to the semiconductor substrate surface, and the electric field in the avalanche multiplication region becomes uniform, thereby further expanding the avalanche multiplication region and improving the photosensitivity.

[0100] According to the present disclosure, a photodetector with high sensitivity can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0101] Figure 1 This is a plan view showing a photodetector according to Embodiment 1 of the present disclosure.

[0102] Figure 2 It shows Figure 1 A cross-sectional view of the photodetector according to Embodiment 1 of the present disclosure, taken along line II-II.

[0103] Figure 3 It shows Figure 2 Graph showing the potential of the photodetector according to Embodiment 1 of the present disclosure on line IIIA-IIIA and line IIIB-IIIB.

[0104] Figure 4 It shows Figure 2 FIG. 4 is a diagram showing the potential of the photodetector according to the first embodiment of the present disclosure on line IIIC-IIIC.

[0105] Figure 5 This is a diagram showing a circuit configuration example of a photodetector according to Embodiment 1 of the present disclosure.

[0106] Figure 6 This is a cross-sectional view showing a modified example of the photodetector according to the first embodiment of the present disclosure.

[0107] Figure 7 It shows Figure 6 Graphs showing potentials of a modified example of the photodetector according to Embodiment 1 of the present disclosure on line VIIA-VIIA, line VIIB-VIIB, and line VIIC-VIIC.

[0108] Figure 8 It is a plan view showing a photodetector according to Embodiment 2 of the present disclosure.

[0109] Figure 9 It shows Figure 8 A cross-sectional view of the photodetector according to Embodiment 2 of the present disclosure, taken along line IX-IX.

[0110] Figure 10 It shows Figure 9 Graph showing the potential of the photodetector according to Embodiment 2 of the present disclosure on the XA-XA line and the XB-XB line.

[0111] Figure 11 It shows Figure 9 FIG. 4 is a graph showing an impurity concentration curve of the photodetector according to the second embodiment of the present disclosure on the XA-XA line.

[0112] Figure 12 It shows Figure 9 FIG. 4 is a diagram showing a modified example of the impurity concentration profile of the photodetector according to the second embodiment of the present disclosure, on the XA-XA line.

[0113] Figure 13 This is a diagram showing an example of the current-voltage characteristics of the photodetector according to the second embodiment of the present disclosure.

[0114] Figure 14 This is a diagram for explaining an example of the effect of reducing the variation in avalanche breakdown voltage of the photodetector according to the second embodiment of the present disclosure.

[0115] Figure 15 This is a plan view showing a first modification of the photodetector according to the second embodiment of the present disclosure.

[0116] Figure 16 It shows Figure 15 1 is a cross-sectional view of Modification 1 of the photodetector according to Embodiment 2 of the present disclosure, taken along line XVI-XVI.

[0117] Figure 17 It shows Figure 16 FIG. 4 is a graph showing an impurity concentration curve of Modification 1 of the photodetector according to Embodiment 2 of the present disclosure, taken on line XVIIA-XVIIA.

[0118] Figure 18 This is a plan view showing a second modification of the photodetector according to the second embodiment of the present disclosure.

[0119] Figure 19 It shows Figure 18 1 is a cross-sectional view of a second modification of the photodetector according to the second embodiment of the present disclosure, taken along line XIX-XIX.

[0120] Figure 20 It shows Figure 19 FIG. 4 is a graph showing an impurity concentration curve of Modification 2 of the photodetector according to Embodiment 2 of the present disclosure, taken on line XXA-XXA.

[0121] Figure 21 This is a plan view showing a third modification of the photodetector according to the second embodiment of the present disclosure.

[0122] Figure 22 It shows Figure 21 XXII-XXII line, showing a cross-sectional view of a third modification of the photodetector according to the third embodiment of the present disclosure.

[0123] Figure 23 This is a plan view showing a first example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0124] Figure 24 It is a plan view showing a second example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0125] Figure 25 It is a plan view showing a third example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0126] Figure 26 It is a plan view showing a fourth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0127] Figure 27 It is a plan view showing a fifth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0128] Figure 28 It is a plan view showing a sixth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0129] Figure 29 It is a plan view showing a seventh example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0130] Figure 30 It is a plan view showing an eighth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0131] Figure 31 It is a plan view showing a ninth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0132] Figure 32 It is a plan view showing a tenth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0133] Figure 33 This is a plan view showing an eleventh example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0134] Figure 34 This is a plan view showing a twelfth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0135] Figure 35 It shows Figure 34 XXXV-XXXV line of the twelfth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0136] Figure 36 This is a diagram showing a first modification of the circuit configuration of the photodetector according to the present disclosure.

[0137] Figure 37 This is a plan view showing an example of a pixel array according to Modification 1 of the circuit configuration of the photodetector according to the present disclosure.

[0138] Figure 38 This is a diagram showing an example of a driving sequence according to Modification 1 of the circuit configuration of the photodetector according to the present disclosure.

[0139] Figure 39 This is a diagram showing a second modification of the circuit configuration of the photodetector according to the present disclosure.

[0140] Figure 40 This is a plan view showing an example of a pixel array according to a second modification of the circuit structure of the photodetector according to the present disclosure.

[0141] Figure 41 This is a plan view showing another example of a pixel array according to Modification 2 of the circuit structure of the photodetector according to the present disclosure.

[0142] Figure 42 This is a diagram showing an example of a driving sequence according to a second modification of the circuit configuration of the photodetector according to the present disclosure.

[0143] Figure 43 This is a cross-sectional view showing a first example of a photodetector package according to the present disclosure.

[0144] Figure 44 This is a cross-sectional view showing a second example of the photodetector package according to the present disclosure.

[0145] Figure 45 This is a cross-sectional view showing a third example of the photodetector package according to the present disclosure.

[0146] Figure 46 It is a cross-sectional view for explaining the manufacturing process of the photodetector according to the present disclosure.

[0147] Figure 47 It is a cross-sectional view for explaining the manufacturing process of the photodetector according to the present disclosure.

[0148] Figure 48 It is a cross-sectional view for explaining the manufacturing process of the photodetector according to the present disclosure.

[0149] Figure 49 It is a cross-sectional view for explaining the manufacturing process of the photodetector according to the present disclosure.

[0150] Figure 50 It is a cross-sectional view for explaining the manufacturing process of the photodetector according to the present disclosure.

[0151] Figure 51 It is a cross-sectional view for explaining the manufacturing process of the photodetector according to the present disclosure.

[0152] Figure 52 It is a cross-sectional view for explaining the manufacturing process of the photodetector according to the present disclosure.

[0153] Figure 53 This is a plan view showing a photodetector according to Embodiment 3 of the present disclosure.

[0154] Figure 54 It shows Figure 53 A cross-sectional view of the photodetector according to Embodiment 3 of the present disclosure, taken along line LIV-LIV.

[0155] Figure 55 It shows Figure 54 Graph showing the potential of the photodetector according to Embodiment 3 of the present disclosure on the LVA-LVA line and the LVB-LVB line.

[0156] Figure 56 It shows Figure 54 Graph showing the potential of the photodetector according to Embodiment 3 of the present disclosure on the LVC-LVC line.

[0157] Figure 57 This is a cross-sectional view showing a first modification of the photodetector according to the third embodiment of the present disclosure.

[0158] Figure 58 This is a cross-sectional view showing a second modification of the photodetector according to the third embodiment of the present disclosure.

[0159] Figure 59 It shows Figure 58 Graph showing potentials of Modification 2 of the photodetector according to Embodiment 3 of the present disclosure on the LIXA-LIXA line, the LIXB-LIXB line, and the LIXC-LIXC line. DETAILED DESCRIPTION

[0160] Hereinafter, the embodiments of the present disclosure will be described using the accompanying drawings. Moreover, the embodiments described below all illustrate a preferred specific example of the present disclosure. Therefore, the numerical values, constituent elements, configuration positions of constituent elements, connection forms, processes (steps), and the order of processes shown in the following embodiments are examples and do not limit the purpose of the present disclosure. Therefore, the constituent elements that are not recorded in the implementation scheme that illustrates the highest concept of the present disclosure among the constituent elements of the following embodiments are described as arbitrary constituent elements.

[0161] Furthermore, each figure is a schematic diagram and is not necessarily a true representation. Therefore, scales, etc., in each figure are not necessarily the same. In each figure, substantially the same content is assigned the same reference numerals, and repeated descriptions may be omitted or simplified.

[0162] Furthermore, the photodetector according to the present disclosure may be a combination of a plurality of embodiments.

[0163] Furthermore, in the following embodiments, expressions using "substantially" are used, such as "substantially horizontal" For example, "substantially consistent" means not only completely consistent but also substantially consistent, that is, including a difference of, for example, several percent.

[0164] Furthermore, the voltage values ​​described in this specification are based on the ground.

[0165] Furthermore, in this specification, the terms "above" and "below" do not indicate the absolute upward direction (vertically above) and downward direction (vertically below) for spatial identification, but are used as terms defined by a relative positional relationship based on the stacking order of the stacked structure. In this specification, with the semiconductor substrate as the reference, the side on which the first principal surface is provided is referred to as "above," and the side on which the second principal surface is provided is referred to as "below." Furthermore, the terms "above" and "below" are applicable not only to situations where two components are arranged to be spaced apart from each other and there is another component between the two components, but also to situations where the two components are arranged to be in close contact with each other.

[0166] Furthermore, in this specification, the term "depth direction" does not indicate an absolute spatially recognized direction, but is used as a term defined by the stacking direction of the stacked structure. In this specification, the "depth direction" is a direction parallel to the normal to the first principal surface of the semiconductor substrate and extending from the first principal surface toward the second principal surface of the semiconductor substrate.

[0167] In this specification, "planar view" refers to the view from the normal direction of the light-receiving surface of the photoelectric conversion layer. Furthermore, terms such as "upper" and "shallow" in this specification refer to the first principal surface side of the epitaxial layer in a cross-sectional view, and "lower" and "deep" refer to the second principal surface side of the epitaxial layer in a cross-sectional view.

[0168] (Implementation Method 1)

[0169] First, refer to Figure 1 as well as Figure 2 , describing the structure of the photodetector involved in embodiment 1.

[0170] Figure 1 1 is a plan view showing the photodetector 100 according to the first embodiment of the present disclosure. Figure 2 It shows Figure 1 1 is a cross-sectional view of the photodetector 100 according to the first embodiment of the present disclosure, taken along line II-II.

[0171] Moreover, in Figure 1 as well as Figure 21 shows the components of the photodetector 100, including the first semiconductor layer 101, the isolation region 103, the first well 104 (circuit region), the second well 105 (circuit region), the isolation transistor 201, the first wiring 203, and the readout circuit 407 (see FIG. Figure 5 ) of the pixel 6 of the photodetector 100, and a part of the structure of the photodetector 100 is omitted. Figure 1 In the figure, some components such as wiring connected to the gate of the isolation transistor 201 are omitted. In addition, in other figures described later, part of the structure of the photodetector according to the present disclosure may be omitted.

[0172] The photodetector 100 according to Embodiment 1 is a light detection sensor utilizing an APD (Avalanche Photo Diode) and includes a semiconductor substrate 600 having an epitaxial layer 1 and a semiconductor substrate layer 3, and a wiring layer 2. Specifically, the photodetector 100 includes an epitaxial layer 1 of the second conductivity type, a wiring layer 2 formed on the first principal surface S1 of the semiconductor substrate 600 (specifically, the epitaxial layer 1), and a semiconductor substrate layer 3 formed on the back side of the semiconductor substrate 600. In this specification, the epitaxial layer and the semiconductor substrate layer serving as a growth substrate for growing the epitaxial layer are collectively referred to as a semiconductor substrate.

[0173] The photodetector 100 includes a circuit region where the isolation transistor 201 is disposed, and a readout circuit 407 connected to the drain of the isolation transistor 201 and configured to read out first charges generated by photoelectric conversion between the first semiconductor layer 101 and the second semiconductor layer 102 (see FIG. Figure 5 ).

[0174] The epitaxial layer 1 is a layer including at least one first semiconductor layer 101 of the first conductivity type, a second semiconductor layer 102 of the second conductivity type, a first well 104 of the first conductivity type, a second well 105 of the second conductivity type, a separation region 103 of the second conductivity type formed between the first semiconductor layer 101 and the first well 104, and a separation transistor 201 of the first conductivity type formed in the second well 105.

[0175] The circuit region is, for example, a region including a first well 104 having a first conductivity type and a second well 105 having a second conductivity type. The isolation transistor 201 is, for example, of the first conductivity type.

[0176] This improves the light receiving sensitivity of the photodetector 100. Furthermore, with such a configuration, the degree of freedom in designing the circuit of the photodetector 100 is improved.

[0177] The first semiconductor layer 101 has a first conductivity type and is formed on the first main surface S1 side of the semiconductor substrate 600. On the first semiconductor layer 101, a first contact 202 is formed as an electrode for electrical connection to the isolation transistor 201 and the like.

[0178] The second semiconductor layer 102 is formed between the first semiconductor layer 101 and the semiconductor substrate layer 3. The second semiconductor layer 102 has a second conductivity type that is opposite to the first conductivity type. The second semiconductor layer 102 avalanche multiplies the charge converted photoelectrically between the second semiconductor layer 102 and the first semiconductor layer 101.

[0179] The first well 104 is formed in parallel with the first main surface S1 of the semiconductor substrate 600 and aligned with the first semiconductor layer 101. The first well 104 is a circuit region in which circuits such as one or more isolation transistors 201 are formed.

[0180] The wiring layer 2 includes a first contact 202 , which is an electrode formed on the first main surface S1 of the first semiconductor layer 101 , and a first wiring 203 , which is a metal wiring electrically connecting the first contact 202 to the source of the isolation transistor 201 .

[0181] The semiconductor substrate layer 3 is a growth substrate for forming the epitaxial layer 1. The semiconductor substrate layer 3 has a growth surface S2 for forming the epitaxial layer 1 and a second main surface S3 opposite to the growth surface S2. A back electrode, i.e., a second contact 204, is formed on the back surface of the semiconductor substrate layer 3, which is also the back surface of the semiconductor substrate 600. When a back bias voltage V is applied to the semiconductor substrate layer 3, back , the voltage on the growth surface S2 side of the epitaxial layer 1 through the semiconductor substrate layer 3 is fixed to V back .

[0182] Furthermore, the second well 105 is electrically connected to the ground. Furthermore, the transistor according to the first embodiment may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a bipolar transistor, and the type is not limited.

[0183] A multiplication region 301 is formed between the first semiconductor layer 101 and the second semiconductor layer 102 and is substantially parallel to the first main surface S1 of the epitaxial layer 1 .

[0184] The multiplication region 301 is a region where the received light ( Figure 2 The hν) shown is a region where the charge generated by photoelectric conversion is multiplied.

[0185] The magnitude of the electric field in the multiplication region 301 is, for example, 3 to 5×10 5V / cm, and the impurity concentrations of the first semiconductor layer 101 and the second semiconductor layer 102 are, for example, 10 16 cm -3 to 10 20 cm -3 , the impurity concentration of the epitaxial layer 1 is, for example, 10 14 cm -3 to 10 16 cm -3 .

[0186] Also, in this case, the amount of potential change in the depth direction of the multiplication region 301 is, for example, 20V.

[0187] Furthermore, in each of the drawings in this specification, received light (ie, incident light) is described as hν.

[0188] When the second-conductivity-type carriers (i.e., second charges) generated by photoelectric conversion in the photoelectric conversion layer 302 stacked beneath the multiplication region 301 drift and reach the multiplication region 301, they undergo avalanche multiplication, multiplying the number of carriers by 1 to 100,000. At this point, the first-conductivity-type carriers (i.e., first charges) generated by photoelectric conversion and avalanche multiplication accumulate in the first semiconductor layer 101. Furthermore, the second charges generated by photoelectric conversion and avalanche multiplication drift to the second contact 204 and are discharged outside the photodetector 100. In other words, among the charges generated by photoelectric conversion between the first and second semiconductor layers 101, 102, the second charges, which have a different polarity than the first charges, flow through the second contact 204 to the exterior of the semiconductor substrate layer 3.

[0189] Here, the second contact 204 is preferably formed entirely on the second main surface S3. The second contact 204 is formed of a conductive material on the second conductivity type semiconductor layer (second semiconductor layer 102) or on the back surface (i.e., the second main surface S3). In particular, the growth substrate used to grow the epitaxial layer 1, i.e., the semiconductor substrate layer 3, can also be used as the second contact 204. Furthermore, the second contact 204 can also be formed by adjusting the carrier density of the second conductivity type semiconductor layer using methods such as impurity diffusion or ion implantation.

[0190] Furthermore, the present invention also encompasses the case where a second contact is formed on the first main surface side of the substrate and a voltage is applied to the second contact through the semiconductor substrate.

[0191] As a result, the second charges not used as signals are quickly discharged to the outside of the photodetector 100. This suppresses temporal variation and spatial non-uniformity of the voltage inside the photodetector 100, thereby improving light detection efficiency.

[0192] Furthermore, the first charge accumulated in the first semiconductor layer 101 is transferred to the readout circuit 407 (see FIG. 1 ) by turning on the separation transistor 201 for reading out the charge generated by photoelectric conversion in the semiconductor substrate 600 (specifically, the first semiconductor layer 101 and the second semiconductor layer 102). Figure 5 ), is processed into a signal. Based on this, the light detector 100 detects the incident light.

[0193] Furthermore, a structure in which the first conductivity type is positive (i.e., P-type) and the second conductivity type is negative (i.e., N-type) is also possible, but it is sufficient to set the first conductivity type to negative and the second conductivity type to positive. In other words, the first charges are electrons and the second charges are holes.

[0194] The ionization rate of electrons is higher than that of holes, so avalanche multiplication is more likely to occur. Therefore, with such a structure, the light receiving sensitivity of the photodetector 100 is improved.

[0195] Here, the charges generated by photoelectric conversion within the isolation region 103, the first well 104, the second well 105, and the lower portion of the second well 105 do not contribute to light sensitivity. Therefore, the isolation region 103, the first well 104, and the second well 105 can be made small, while the multiplication region 301 can be made wide.

[0196] In particular, in the photodetector 100 according to Embodiment 1, no contacts (specifically, the first contact 202) or STI (Shallow Trench Isolation) are formed on the isolation region 103. Furthermore, the isolation region 103 is depleted and has an unstable potential. Specifically, no STI is formed in the region where the first semiconductor layer 101 and the isolation region 103 are formed.

[0197] This allows the width of the isolation region 103 to be reduced, thereby increasing the aperture ratio of the photodetector 100 .

[0198] It is particularly preferable that the depletion layer width in the longitudinal direction (perpendicular to the first main surface S1) of the multiplication region 301 be greater than the depletion layer width in the lateral direction (parallel to the first main surface S1) of the separation region 103 (i.e., approximately half the width of the separation region 103). This structure can alleviate electric field concentration at the ends of the multiplication region 301 and make the electric field intensity uniform. Consequently, the avalanche multiplication region can be expanded, and photosensitivity can be improved.

[0199] Furthermore, the width of the separation region 103 is, for example, 0.1 μm to 1 μm, and the impurity concentration is 10 15 cm -3 to 10 18cm -3 The potential of the isolation region 103 is determined by the potential of the first semiconductor layer 101, the potential of the first well 104, and the back bias voltage V back Decide.

[0200] Here, if the potential difference V between the first semiconductor layer 101 and the isolation region 103 is small, the saturated electron count decreases, making charge leakage to adjacent pixels more likely to occur. On the other hand, if the potential difference V between the first semiconductor layer 101 and the isolation region 103 is large, the electric field generated on the device surface (e.g., the first main surface S1) increases, causing problems such as increased dark current and dark count. Therefore, the potential difference between the first semiconductor layer 101 and the isolation region 103 is preferably in the range of approximately 0.1V to 10V.

[0201] Furthermore, the light incident surface in the first embodiment is the first principal surface S1 of the epitaxial layer 1 .

[0202] This eliminates the need for special processes such as backside processing, reducing costs. In particular, long-wavelength light, such as near-infrared light, has a low absorption coefficient and is not attenuated until near the semiconductor substrate layer 3. Therefore, even if the photoelectric conversion layer 302 is formed in an area far from the first principal surface S1 of the epitaxial layer 1, the light sensitivity is almost unchanged compared to when it is formed near the first principal surface S1. For example, the absorption coefficient of silicon (Si) for 940nm light, where the spectral intensity of sunlight in the near-infrared region is extremely low, is 1% / μm. Therefore, even if the photoelectric conversion layer 302 is formed 1μm deep from the first principal surface S1, the reduction in light sensitivity is only 1%.

[0203] Furthermore, an optical waveguide may be provided on the multiplication region 301 in the wiring layer 2, and a microlens may be provided on the wiring layer 2. This can improve light-collecting efficiency.

[0204] Furthermore, the first semiconductor layer 101 and the source of the isolation transistor 201 are connected via a first wiring 203 on the isolation region 103. The drain of the isolation transistor 201 is connected to the readout circuit 407 (see Figure 5 ) are connected, and multiple pixel circuits (for example, the separation transistor 201) are formed in the same well (for example, the second well 105), thereby reducing the area of ​​the circuit region and improving the aperture ratio. Figure 1 as well as Figure 2 FIG. 2 shows an example in which the drain of the separation transistor 201 is connected to a column signal line.

[0205] Next, refer to Figure 3 as well as Figure 4 , describing the potential of the first charge.

[0206] Figure 3 It shows Figure 2 Graph showing the potential of the photodetector 100 according to the first embodiment of the present disclosure on line IIIA-IIIA and line IIIB-IIIB. Figure 4 It shows Figure 2 FIG. 1 is a diagram showing the potential of the photodetector 100 according to the first embodiment of the present disclosure on the IIIC-IIIC line.

[0207] and, Figure 3 The solid line shown is, Figure 2 The potential on the IIIA-IIIA line in FIG, the potential of the first semiconductor layer 101, the multiplication region 301, and the photoelectric conversion layer 302.

[0208] The first semiconductor layer 101 turns on the separation transistor 201, thereby connecting to the readout circuit 407 (see Figure 5 ) is connected and fixed to the readout circuit 407 (refer to Figure 5 ) power supply voltage V dd On the other hand, the growth surface S2 side of the epitaxial layer 1 is fixed to V through the semiconductor substrate layer 3. back .

[0209] The photoelectric conversion layer 302 is depleted, and a potential gradient is formed that causes the charge to drift toward the multiplication region 301 .

[0210] When the photoelectric conversion layer 302 is depleted, the potential change of the photoelectric conversion layer 302 is, for example, 20 V when the thickness of the photoelectric conversion layer 302 is 5 μm, and approximately 40 V when the thickness of the photoelectric conversion layer 302 is 15 μm.

[0211] Hereinafter, in this specification, the voltage difference between the first contact 202 and the second contact 204 when the threshold voltage that causes avalanche multiplication in the multiplication region 301 is applied is referred to as the avalanche breakdown voltage. In this case, for example, when the thickness of the photoelectric conversion layer 302 is 5 μm, the avalanche breakdown voltage is 40 V.

[0212] like Figure 3 It shows that the potential on line IIIA-IIIA and line IIIB-IIIB approaches V as it goes deeper. back On the other hand, the potential on the line IIIA-IIIA and the line IIIB-IIIB increases as the distance to the first main surface S1 increases. The potential on the line IIIA-IIIA approaches V dd Preferably, the potential on the IIIB-IIIB line is depleted on the first main surface S1 and becomes unstable.

[0213] like Figure 4 As shown, the first semiconductor layer 101 is biased to Vdd , the first well 104 is also biased to V dd However, the separation region 103 is depleted and has an indeterminate potential, so the first semiconductor layer 101 is electrically separated from the first well 104. Moreover, the potential difference between the first semiconductor layer 101 and the separation region 103 is V dd to 10V.

[0214] According to the above-described structure, the photodetector 100 can miniaturize the separation region 103 and expand the multiplication region 301, thereby improving the light receiving sensitivity.

[0215] For example, in the case where a contact is provided instead of depleting the separation region 103 as in Patent Document 4, in order to ensure electrical separation and mitigate the electric field in a direction roughly parallel to the epitaxial layer 1 (i.e., a direction parallel to the first main surface S1), a separation width of more than 1 μm is typically required in a direction parallel to the first main surface S1.

[0216] In contrast, in the photodetector 100 according to Embodiment 1, the isolation region 103 is depleted. Due to the depletion of the isolation region 103, the electric field between the first semiconductor layer 101 and the isolation region 103 is reduced. Consequently, the isolation width can be narrowed to 0.1 μm to 1 μm. This allows for miniaturization of the photodetector 100.

[0217] Next, refer to Figure 5 , a circuit configuration of the photodetector 100 according to the first embodiment will be described.

[0218] Figure 5 1 is a diagram showing an example of a circuit configuration of the photodetector 100 according to the first embodiment of the present disclosure. Figure 5 , an example of connecting the readout circuit 407 to the vertical signal line 404, the horizontal scanning circuit 408, and the buffer amplifier 409 is shown. Figure 5 In the figure, only one of the APD 401 and the transfer transistor 402 is shown, but they may be formed in a matrix to form an array.

[0219] like Figure 5 As shown, the photodetector 100 includes an APD 401 , a transfer transistor 402 , a horizontal signal line 403 , a vertical signal line 404 , a vertical scanning circuit 406 , a readout circuit 407 , a horizontal scanning circuit 408 , and a buffer amplifier 409 .

[0220] APD401 is comprised of, Figure 2 The APD shown includes the first semiconductor layer 101 , the multiplication region 301 , and the photoelectric conversion layer 302 .

[0221] The signal charge stored after photoelectric conversion by the APD 401, that is, the first charge, turns on the transfer transistor 402 of the row selected by the vertical scanning circuit 406. Figure 1 The column signal line 205 and the vertical signal line 404 are shown, and are transmitted to the readout circuit 407. The transfer transistor 402 is, for example, Figure 2 The first charge transferred to the readout circuit 407 is output to a subsequent signal processing circuit (not shown) via a buffer amplifier 409. After the signal processing circuit performs signal processing such as white balance, the charge is transferred to a display (not shown) or memory (not shown) to be converted into an image, for example.

[0222] Preferably, a back bias voltage V back A circuit that selectively applies voltage to the APD 401 by switching between a voltage Va (eg, -20 V) higher than the avalanche breakdown voltage or a voltage Vn (eg, -10 V) lower than the avalanche breakdown voltage.

[0223] Accordingly, for example, when the illumination of the object to be photographed is high, Vn is applied, and when the illumination of the object to be photographed is low, Va is applied to shoot. Accordingly, it is possible to shoot at illuminations ranging from very dark illuminations where one photon to a few photons are incident on an APD401, to illuminations where more than 10,000 photons are incident, which can be shot by a general camera.

[0224] Furthermore, by switching the applied voltages Va and Vn for each frame and performing image capturing and synthesizing the images, it is possible to capture a moving image with a wide dynamic range.

[0225] As described above, the photodetector 100 involved in embodiment 1 comprises: a semiconductor substrate 600 having a first main surface S1 and a second main surface S3 on the side opposite to the first main surface S1; a first semiconductor layer 101 having a first conductivity type, formed on the first main surface S1 side of the semiconductor substrate 600; a second semiconductor layer 102 having a second conductivity type, formed between the first semiconductor layer 101 and the second main surface S3 of the semiconductor substrate 600, the second conductivity type being a conductivity type different from the first conductivity type; and a multiplication region 301, which avalanche multiplies the charge generated by photoelectric conversion in the semiconductor substrate 600 in the first semiconductor layer 101 and the second semiconductor layer 102. Furthermore, the photodetector 100 comprises: a circuit region (specifically, a first well 104 and a second well 105), which is arranged in a direction parallel to the first main surface S1 and arranged with the first semiconductor layer 101; one or more separation transistors 201 formed in the circuit region; a separation region 103 formed between the first semiconductor layer 101 and the circuit region; one or more first contacts 202 formed on the first semiconductor layer 101; a first wiring 203 connecting the first contact 202 and the source of the separation transistor 201; and a readout circuit 407, which is connected to the drain of the separation transistor 201 and reads out a first charge among the charges generated by photoelectric conversion between the first semiconductor layer 101 and the second semiconductor layer 102.

[0226] With this structure, the first semiconductor layer 101 and the first well 104 are electrically isolated by the isolation region 103. This allows the photodetector 100 to maintain light sensitivity while being miniaturized. Therefore, the photodetector 100 can improve the aperture ratio.

[0227] <Modification>

[0228] Figure 6 This is a cross-sectional view showing Modification 1 of the photodetector according to Embodiment 1 of the present disclosure.

[0229] The photodetector 100c according to the modification example includes an epitaxial layer 1i in the pixel 63 that is different from that of the photodetector 100. Specifically, the epitaxial layer 1i, the epitaxial layer 1i, and the second semiconductor layer 102c differ in size when viewed in plan. More specifically, the width of the second semiconductor layer 102c in the photodetector 100c according to the modification example differs from that of the photodetector 100 in cross-section. In other words, the width of the second semiconductor layer 102c in the photodetector 100c according to the modification example is different from that of the photodetector 100 in a direction parallel to the first main surface S1.

[0230] Thus, for example, the second semiconductor layer 102c may have the same shape as the first semiconductor layer 101 in a plan view, or may be wider than the first semiconductor layer 101. Furthermore, the second semiconductor layer 102c may be shared by a plurality of pixels 63.

[0231] This structure makes the electric field more uniform in a direction substantially parallel to the first main surface S1 of the semiconductor substrate 602, and the multiplication region 301 is formed wider. Specifically, the second semiconductor layer 102c is wider than the first semiconductor layer 101. This further improves the aperture ratio of the photodetector 100c, thereby further enhancing its photosensitivity.

[0232] Figure 7 It shows Figure 6 Graphs showing the potentials of the photodetector 100 c on line VIIA-VIIA, line VIIB-VIIB, and line VIIC-VIIC.

[0233] like Figure 7 As shown in the figure, it can be seen that in the first semiconductor layer 101, even if the position changes in a direction parallel to the first main surface S1, the way the potential changes remains almost unchanged. Therefore, the electric field is more uniform relative to the direction substantially parallel to the first main surface S1 of the semiconductor substrate 602, and the multiplication region 301 is formed wider. Specifically, the second semiconductor layer 102c is wider than the first semiconductor layer 101. As a result, the aperture ratio of the photodetector 100c is further improved, thereby further enhancing the photosensitivity.

[0234] (Implementation Method 2)

[0235] Next, refer to Figure 8 as well as Figure 9 , describing the structure of the photodetector involved in embodiment 2.

[0236] In the description of the photodetector according to the second embodiment, substantially the same components as those of the photodetector according to the first embodiment are denoted by the same reference numerals, and part of the description may be omitted or simplified.

[0237] Furthermore, the peripheral circuit structure of the photodetector according to the second embodiment may be, for example, Figure 5 The circuit configuration of the photodetector 100 according to the illustrated embodiment 1 is the same, and therefore its description is omitted.

[0238] Figure 8 It is a plan view showing a photodetector 100 a according to Embodiment 2 of the present disclosure. Figure 9 It shows Figure 8 IX-IX line of the photodetector 100a according to the second embodiment of the present disclosure.

[0239] The second semiconductor layer 102a included in the pixel 6a of the photodetector 100a according to the second embodiment is formed from the lower surface of the first semiconductor layer 101a to the growth plane S2 and has an impurity concentration gradient in the depth direction of the epitaxial layer 1a.

[0240] The epitaxial layer 1a is formed so that the impurity concentration gradually increases, with the concentration being higher on the growth plane S2 side than on the first main surface S1. Here, "gradually increasing" means that the impurity concentration increases uniformly or monotonically in the depth direction, including regions with a constant impurity concentration or regions where the impurity concentration increases in a stepwise manner.

[0241] The first charges generated by photoelectric conversion in the photoelectric conversion layer 302 drift from the built-in potential to the multiplication region 301 , and are avalanche multiplied in the multiplication region 301 .

[0242] And, as Figure 9 As shown, the second semiconductor layer 102a is formed to cover the entire first principal surface S1 of the semiconductor substrate layer 3. Specifically, the second semiconductor layer 102a is formed to expand in a direction parallel to the first principal surface S1 of the semiconductor substrate (i.e., the epitaxial layer 1a and the semiconductor substrate layer 3) over the entire surface. In other words, the second semiconductor layer 102a is formed to cover the entire growth surface S2 of the semiconductor substrate layer 3.

[0243] As a result, the electric field in the second semiconductor layer 102a is substantially perpendicular to the first principal surface S1 of the epitaxial layer 1a, thereby reducing the lateral movement of the first charge (i.e., parallel to the first principal surface S1). Consequently, the sensitivity of the photodetector 100a is enhanced. Furthermore, the photodetector 100a exhibits reduced color mixing.

[0244] Next, refer to Figure 10 , describing the potential of the first charge.

[0245] Figure 10 It shows Figure 9 Graph showing the potential of the photodetector 100a according to Embodiment 2 of the present disclosure on the XA-XA line and the XB-XB line. Figure 10 The solid line shown is, Figure 9 The potential on the XA-XA line in FIG, the potential of the first semiconductor layer 101a, the multiplication region 301, and the photoelectric conversion layer 302.

[0246] like Figure 10 As shown, the potential gradient of the first charge in the photoelectric conversion layer 302 is formed by the built-in potential. Therefore, the potential at both ends of the photoelectric conversion layer 302 in the vertical direction hardly changes.

[0247] As a result, the avalanche breakdown voltage matches the potential difference between the upper and lower ends of the multiplication region 301. With such a potential, the avalanche breakdown voltage is reduced compared to the conventional pull-through APDs described in Patent Documents 2 and 3.

[0248] For example, the impurity concentration of the first semiconductor layer 101a is 10 19 cm -3 The impurity concentration of the second semiconductor layer 102a in the multiplication region 301 is 10 16 cm -3 above.

[0249] As a result, the avalanche breakdown voltage is reduced to 20V.

[0250] Furthermore, in a plane substantially parallel to the first main surface S1 of the epitaxial layer 1 , the potential of the first charge is substantially constant.

[0251] As a result, the first charge potentials on the XA-XA line and the XB-XB line within the photoelectric conversion layer 302 coincide. Consequently, the impurity concentration profile (impurity concentration distribution) on the XB-XB line can be controlled by the impurity concentration profile of a region shallower than the multiplication region 301, making it possible to easily reduce the potential difference in the isolation region 103. This improves the yield of the photodetector 100a.

[0252] Furthermore, when manufacturing an APD image sensor in which the pixels 6a are arrayed, variations in dark current and dark count among the pixels 6a are reduced. Therefore, the photodetector 100a including a plurality of pixels 6a can output an image with less variation.

[0253] It is particularly preferable that the depletion layer width in the longitudinal direction (perpendicular to the first main surface S1) of the multiplication region 301 be greater than the depletion layer width in the lateral direction (parallel to the first main surface S1) of the separation region 103 (i.e., approximately half the width of the separation region 103). This structure can alleviate electric field concentration at the ends of the multiplication region 301 and make the electric field intensity uniform. Consequently, the avalanche multiplication region can be expanded, and photosensitivity can be improved.

[0254] Next, refer to Figure 11 as well as Figure 12 , illustrating the impurity concentration of the photodetector 100a.

[0255] Figure 11 It shows Figure 9 FIG. 4 is a graph showing an impurity concentration curve of the photodetector 100 a according to the second embodiment of the present disclosure on the XA-XA line.

[0256] In the first semiconductor layer 101a, the impurity concentration near the first main surface S1 is high so that the first main surface S1 does not become depleted. The impurity concentration decreases with depth in the multiplication region 301. Furthermore, a PN junction is formed between the first semiconductor layer 101a and the second semiconductor layer 102a.

[0257] On the other hand, the impurity concentration of the second semiconductor layer 102 a gradually increases toward the depth direction.

[0258] This allows the first charges to drift from the photoelectric conversion layer 302 to the multiplication region 301 .

[0259] Furthermore, in the case of such an impurity concentration profile, it is preferable that the impurity concentration of the first semiconductor layer 101a is higher than the impurity concentration of the second semiconductor layer 102a, and that the second semiconductor layer 102a is shallower than the first semiconductor layer 101a. Specifically, the interface between the first semiconductor layer 101a and the second semiconductor layer 102a is formed closer to the second main surface S3 than a portion of the upper surface of the second semiconductor layer 102a.

[0260] Furthermore, in a region including the interface between the first semiconductor layer 101 a and the second semiconductor layer 102 a , the impurity concentration of the first semiconductor layer 101 a is higher than the impurity concentration of the second semiconductor layer 102 a .

[0261] Furthermore, the impurity concentration gradient of the second semiconductor layer 102a within the multiplication region 301 only needs to be smaller than the impurity concentration gradient of the second semiconductor layer 102a within the photoelectric conversion layer 302. Specifically, the impurity concentration gradient of the second semiconductor layer 102a is steeper on the back side of the semiconductor substrate layer 3, i.e., the second main surface S3 side, than on the surface of the epitaxial layer 1a, i.e., the first main surface S1 side.

[0262] With these structures, the avalanche breakdown voltage is less likely to depend on the concentration and depth of the first semiconductor layer 101a. Therefore, variations in avalanche breakdown voltage are reduced. Consequently, variations in light sensitivity of the photodetector 100a are reduced.

[0263] Furthermore, the impurity concentration gradient of the second semiconductor layer 102a can be large in the deep region of the epitaxial layer 1a and small in the shallow region of the epitaxial layer 1a. Specifically, the impurity concentration gradient of the second semiconductor layer 102a is steeper on the back side of the semiconductor substrate layer 3, i.e., the second main surface S3 side, than on the surface of the epitaxial layer 1a, i.e., the first main surface S1 side.

[0264] This allows the first charges generated in the deep regions of the photoelectric conversion layer 302 to drift at a higher speed, while the first charges generated in the shallow regions of the photoelectric conversion layer 302 can drift at a lower speed. This reduces response time differences and further reduces mixed colors.

[0265] Furthermore, the impurity concentration distribution of the second semiconductor layer 102 a only needs to be substantially constant in a direction parallel to the first main surface S1 of the epitaxial layer 1 a .

[0266] According to such a structure, the potential of the separation region 103 is further stabilized.

[0267] Figure 12 It shows Figure 9 FIG. 4 is a diagram showing a modified example of the impurity concentration profile of the photodetector 100 a according to the second embodiment of the present disclosure, taken on the XA-XA line.

[0268] Figure 12 The impurity concentration distribution is shown, and Figure 11 The impurity concentration distribution shown is different. The impurity concentration of the first semiconductor layer 101a increases from the surface of the epitaxial layer 1a in the depth direction and then decreases with depth. Thus, the impurity concentration of the first semiconductor layer 101a has a region where it increases with depth.

[0269] This can suppress thermal diffusion of charges generated on the first main surface S1 of the epitaxial layer 1a to the multiplication region 301. Therefore, such an impurity concentration distribution can further reduce dark current and dark count.

[0270] Next, refer to Figure 13 as well as Figure 14 , the current-voltage characteristics of the photodetector 100a when the pixels 6a are arrayed will be described.

[0271] Figure 13 This is a diagram showing an example of the current-voltage characteristics of the photodetector 100 a according to the second embodiment of the present disclosure. Figure 14 This is a diagram for explaining an example of the effect of reducing the variation in avalanche breakdown voltage of the photodetector 100 a according to the second embodiment of the present disclosure.

[0272] like Figure 14 It is shown that in the photodetector 100a according to Embodiment 2, the avalanche breakdown voltage does not depend on the thickness of the photoelectric conversion layer 302. The avalanche breakdown voltage is, for example, 24V.

[0273] On the other hand, in the pull-through type APDs disclosed in Patent Documents 2 and 3, as shown in FIG. Figure 14 In the comparative example shown, when the thickness of the photoelectric conversion layer 302 is 5 μm ( Figure 13 Comparative Example 1 shown), the avalanche breakdown voltage is 37V, and when the thickness of the photoelectric conversion layer 302 is 15μm ( Figure 13 In the comparative example 2 shown, the avalanche breakdown voltage is 64V.

[0274] As described above, according to the photodetector 100 a according to the second embodiment, the avalanche breakdown voltage can be reduced.

[0275] In Embodiment 2, when the thickness of the photoelectric conversion layer 302 is 5 μm and also when the thickness of the photoelectric conversion layer 302 is 15 μm, the avalanche breakdown voltage is 24 V, and the standard deviation of the avalanche breakdown voltage is 0.15 V. On the other hand, in the pull-through APDs having the structures disclosed in Patent Documents 2 and 3, when the thickness of the photoelectric conversion layer 302 is 5 μm, the avalanche breakdown voltage is 37 V, and the standard deviation of the avalanche breakdown voltage is 0.62 V. Furthermore, when the thickness of the photoelectric conversion layer 302 is 15 μm, the avalanche breakdown voltage is 64 V, and the standard deviation of the avalanche breakdown voltage is 4.7 V.

[0276] Thus, the photodetector 100a according to Embodiment 2 can reduce variations in avalanche breakdown voltage. Therefore, when multiple pixels 6a are arranged in an array, variations in light sensitivity among the individual pixels 6a can be reduced. Furthermore, the photodetector 100a according to Embodiment 2 can further improve yield. Furthermore, the photodetector 100a according to Embodiment 2 can reduce manufacturing costs.

[0277] Here, the first well 104 is of the first conductivity type, and the impurity concentration at the boundary between the first well 104 and the first semiconductor layer 101 a is lower than that of the first semiconductor layer 101 a .

[0278] According to such a structure, it is possible to reduce the electric field and current generated in the first well 104. Therefore, it is possible to reduce power consumption when driving the photodetector 100a.

[0279] Furthermore, the first well 104 may be formed closer to the second main surface S3 than the first semiconductor layer 101 a .

[0280] According to such a structure, it is possible to further reduce the electric field generated in the first well 104. Therefore, it is possible to further reduce power consumption.

[0281] Furthermore, the shallow regions of the first well 104 can be formed from arsenic, while the deep regions can be formed from phosphorus. Phosphorus has a greater thermal diffusion coefficient than arsenic. Therefore, phosphorus diffuses during the heat treatment, reducing the concentration of first well 104 at the boundary between the second semiconductor layer 102a and the first well 104 and lowering the electric field strength. This reduces the current flowing in the first well 104, thereby reducing power consumption.

[0282] [Modifications of Epitaxial Layer and Semiconductor Layer]

[0283] Next, refer to Figures 15 to 22 Modifications of the epitaxial layer and the semiconductor layer of the photodetector 100a according to the second embodiment will be described.

[0284] <Variation 1>

[0285] Figure 15 It is a plan view showing a first modification of the photodetector 100 a according to the second embodiment of the present disclosure. Figure 16 It shows Figure 15 1 is a cross-sectional view of Modification 1 of the photodetector 100 a according to Embodiment 2 of the present disclosure, taken along line XVI-XVI. Figure 17 It shows Figure 16 FIG. 4 is a graph showing an impurity concentration curve of Modification 1 of the photodetector 100 a according to Embodiment 2 of the present disclosure, taken on line XVIIA-XVIIA.

[0286] like Figure 16 1 , the epitaxial layer 1 c of the pixel 6 c of the first modification of the photodetector 100 a according to the second embodiment further includes a fourth semiconductor layer 107 in addition to the structure of the pixel 6 a of the photodetector 100 a according to the second embodiment.

[0287] The fourth semiconductor layer 107 is formed between the first semiconductor layer 101a and the second semiconductor layer 102a and has the second conductivity type.

[0288] And, as Figure 17 As shown, the fourth semiconductor layer 107 has an impurity concentration higher than that of the second semiconductor layer 102a in the multiplication region 301. In this case, the fourth semiconductor layer 107 only needs to be depleted.

[0289] According to such a structure, a large electric field is generated in the multiplication region 301. Therefore, the avalanche breakdown voltage can be further reduced.

[0290] <Variation 2>

[0291] Figure 18 It is a plan view showing a second modification of the photodetector 100 a according to the second embodiment of the present disclosure. Figure 19 It shows Figure 18 1 is a cross-sectional view of a second modification of the photodetector 100 a according to the second embodiment of the present disclosure, taken along line XIX-XIX. Figure 20 It shows Figure 19 FIG. 2 is a graph showing an impurity concentration curve of a second modification of the photodetector 100 a according to the second embodiment of the present disclosure, taken on line XXA-XXA.

[0292] like Figure 19 1 , a pixel 6 d of a second modification of the photodetector 100 a according to the second embodiment includes a fourth semiconductor layer 107 a , similar to the pixel 6 c of the first modification.

[0293] The fourth semiconductor layer 107a and the isolation region 103 are formed below the first semiconductor layer 101b. The second semiconductor layer 102b is formed below the fourth semiconductor layer 107a and the isolation region 103. That is, in the epitaxial layer 1d of the pixel 6d, the first semiconductor layer 101b and the second semiconductor layer 102b are formed so as not to be in direct contact.

[0294] And, as Figure 20 It is shown that the fourth semiconductor layer 107 a has a higher impurity concentration than the second semiconductor layer 102 b in the multiplication region 301 .

[0295] According to such a structure, the electric field generated in the multiplication region 301 is also large, so that the avalanche breakdown voltage can be further reduced.

[0296] <Variation 3>

[0297] Figure 21 This is a plan view showing a third modification of the photodetector according to the second embodiment of the present disclosure. Figure 22 It shows Figure 21 XXII-XXII line of the cross-sectional view of the third modification of the photodetector according to the second embodiment of the present disclosure.

[0298] The photodetector 1003 includes a second conductivity type layer 700, a layer having a different conductivity type from that of the first semiconductor layer 101c, within the first semiconductor layer 101c included in the epitaxial layer 1g. Specifically, the photodetector 1003 includes the second conductivity type layer 700 of the second conductivity type within the first semiconductor layer 101c located closer to the first principal surface S1 of the semiconductor substrate 601 than the multiplication region 301. More specifically, the first semiconductor layer 101c includes the second conductivity type layer 700 in contact with the first principal surface S1 of the semiconductor substrate 601.

[0299] The second conductive layer 700 is connected to the contact 701 (electrode) and a voltage is applied via the contact 701. A lower voltage is applied to the second conductive layer 700 than to the first semiconductor layer 101c. In other words, the second conductive layer 700 and the first semiconductor layer 101c are in a reverse bias relationship. Here, a reverse bias is applied to the second conductive layer 700 and the first semiconductor layer 101c to a degree that does not cause breakdown. As a result, the charge generated by defects in the first main surface S1 is discharged from the contact 701 to the outside of the semiconductor substrate 601. Therefore, dark current and dark count (DCR), which are the causes of noise, can be reduced.

[0300] [Pixel Array]

[0301] Next, refer to Figures 23 to 35 , explaining the arrangement layout of the pixel array when the pixels of the light detector involved in the present disclosure are arrayed. Figures 23 to 35 In FIG, the first semiconductor layer, the isolation transistor, and the vertical signal line of the pixel array are shown, and a part of the components of the pixel array is omitted. Figures 23 to 35 The pixel array shown may also use any one of the above-mentioned pixels 6, 63, 6a, 6c, and 6d. Figures 23 to 35 The pixel array described in can also be adopted in any of the photodetector 100 according to Embodiment 1, the photodetector 100a according to Embodiment 2, and their modified examples.

[0302] And, in Figures 23 to 33 In the description, the same symbols may be attached to the components with the same functions for the sake of explanation. For example, for the first semiconductor layer, even if the shape is different in each pixel array, the symbols are all set to 101 for explanation. For other components such as separation transistors and vertical signal lines, the same symbols may be attached to each component for explanation. Figure 34 as well as Figure 35 In FIG. 1 , the first semiconductor layer is shown as the first semiconductor layer 101 a .

[0303] <Example 1>

[0304] Figure 23 This is a plan view showing a first example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0305] exist Figure 23 The pixel array 10 shown includes at least two first semiconductor layers 101 , a first well 104 , a second well 105 , and a separation transistor 201 . One second well 105 includes one separation transistor 201 .

[0306] Furthermore, adjacent first semiconductor layers 101 are separated by a separation region 103. The separation region 103 is depleted.

[0307] Here, the potential of the isolation region 103 may be made substantially uniform between adjacent first semiconductor layers 101 and between the first semiconductor layer 101 and the first well 104 .

[0308] Furthermore, the widths between adjacent first semiconductor layers 101 and the widths between the first semiconductor layer 101 and the first well 104 may be substantially the same. In particular, the first semiconductor layer 101 and the first well 104 are formed using the same mask, thereby reducing positional deviation between the first semiconductor layer 101 and the first well 104 and reducing variations in dark current between pixels.

[0309] <Example 2>

[0310] Figure 24 It is a plan view showing a second example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0311] Figure 24 The pixel array 11 shown includes four isolation transistors 201 connected to four different first semiconductor layers 101. The four isolation transistors 201 are formed in the same second well 105.

[0312] This allows the area of ​​the second well 105 to be reduced, thereby allowing the area of ​​the first semiconductor layer 101 to be wider, thereby improving the aperture ratio and the light receiving sensitivity.

[0313] <Example 3>

[0314] Figure 25 It is a plan view showing a third example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0315] Figure 25 The pixel array 12 shown has four separate transistors 201 connected to four different first semiconductor layers 101. The four separate transistors 201 share a drain. Thus, at least two separate transistors 201 share a readout circuit 407 (e.g., see FIG. 1 ). Figure 5 ) connected to the drain.

[0316] This can further reduce the area of ​​the second well 105. Therefore, the area of ​​the first semiconductor layer 101 can be formed to be wider, thereby further improving the aperture ratio and the light receiving sensitivity.

[0317] <Example 4>

[0318] Figure 26It is a plan view showing a fourth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0319] Figure 26 The pixel array 13 shown has a first semiconductor layer 101 that is pentagonal in plan view.

[0320] With this, for example, compared to the third example, where the first semiconductor layer 101 has a hexagonal shape in plan view, the shape of the protective film used when forming the first semiconductor layer 101 is more stable. Therefore, it is possible to reduce errors in the shape of the first semiconductor layer 101 when forming it. This further reduces variations in light sensitivity.

[0321] <Example 5>

[0322] Figure 27 It is a plan view showing a fifth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0323] Figure 27 The pixel array 14 shown has a first semiconductor layer 101 that is circular in plan view.

[0324] This can reduce electric field concentration at the end of the first semiconductor layer 101 and suppress edge breakdown.

[0325] Furthermore, the planar shape of the first semiconductor layer 101 is not limited to the aforementioned quadrangle, pentagon, and circle, but may be, for example, an ellipse or a triangle.

[0326] <Example 6>

[0327] Figure 28 It is a plan view showing a sixth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0328] Figure 28 The pixel array 15 shown has nine Figure 25 The pixel array 12 is shown. That is, the pixel array 15 is a pixel array having pixels arranged in a 6×6 matrix.

[0329] With this structure, the second wells 105 are formed across the two first semiconductor layers 101. This allows vertical signal lines 404 to be integrated for every two pixels, thereby reducing reflection of incident light by the wiring. Consequently, light sensitivity is improved.

[0330] <Example 7>

[0331] Figure 29 It is a plan view showing a seventh example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0332] Figure 29 The pixel array 16 shown has seven Figure 25 The illustrated pixel array 12 and the four pixels of the pixel array 12 are arranged in groups of two adjacent pixels. Specifically, in the pixel array 16, two adjacent pixel arrays 12 connected to different vertical signal lines 404 are arranged to be offset by one pixel in the extending direction of the vertical signal line 404. In other words, the plurality of second wells 105 are arranged to be staggered in plan view.

[0333] With this structure, similar to Example 6, the second wells 105 are formed across two first semiconductor layers 101. This allows vertical signal lines 404 to be integrated for every two pixels, reducing reflection of incident light from the wiring. Consequently, light sensitivity is improved. Furthermore, within the same row or column, pixels lacking the bottom left, top right, or bottom right positions are arranged in a four-pixel cycle, minimizing differences in light sensitivity between rows or columns.

[0334] <Example 8>

[0335] Figure 30 It is a plan view showing an eighth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0336] Figure 30 The pixel array 17 shown has a regular hexagonal shape when viewed in plan. At the center of this regular hexagon are formed a first well 104 and a second well 105, where isolation transistors 201 are formed. Furthermore, when viewed in plan, the first well 104 and the second well 105 are surrounded by six first semiconductor layers 101, each having a roughly trapezoidal shape. In other words, the pixel array 17 has a so-called honeycomb structure.

[0337] In particular, the six isolation transistors 201 connected to the six first semiconductor layers 101 are formed in the same second well 105. In other words, the pixel array 17 has the second well 105 formed at the rotation center of a six-fold rotationally symmetric pattern.

[0338] Thus, the photodetector disclosed herein includes a plurality of first contacts 202 and a plurality of separation transistors 201 connected to any one of the plurality of first contacts 202 . The plurality of separation transistors 201 can be formed in one circuit region (for example, the first well 104 and the second well 105 ).

[0339] With such a structure, the photodetector according to one aspect of the present disclosure is further miniaturized.

[0340] Furthermore, when the photodetector according to the present disclosure includes a plurality of separation transistors 201 , at least two separation transistors 201 among the plurality of separation transistors 201 may share the readout circuit 407 .

[0341] With such a structure, the photodetector according to one aspect of the present disclosure is further miniaturized.

[0342] Moreover, in Figures 25 to 27 In the third to fifth examples shown, the second well 105 is formed at the rotation center of the four-fold rotationally symmetric pattern.

[0343] Thus, the pixel array of the present disclosure uses an N-gon having M-fold rotational symmetry as a repetitive period. N first semiconductor layers 101 are formed, and the first well 104 and the second well 105 are formed around the rotational symmetry center of the N-gon, so as to maintain the M-fold rotational symmetry within the N-gon. Furthermore, N is a natural number greater than 3, and M is a natural number greater than 2. For example, for pixel arrays 11 to 14, N = M = 4, and for pixel array 17, N = M = 6.

[0344] Thus, in a planar view, N first semiconductor layers 101 can be formed within an N-gon (N is a natural number greater than or equal to 3) having M-fold rotational symmetry (M is a natural number greater than or equal to 2), maintaining the M-fold rotational symmetry. In this case, the circuit region (the first well 104 and the second well 105) is formed at the rotational center of the N-gon having rotational symmetry, and N discrete transistors 201 can be arranged within this circuit region.

[0345] As a result, each pixel included in the photodetector according to the present disclosure can maintain a symmetrical shape when viewed in plan, thereby suppressing distortion of an image formed by the charge read out by the readout circuit 407, etc. In particular, as N increases, the number of separation transistors 201 formed in the common first well 104 and second well 105 increases, so N can be set to a larger value.

[0346] Furthermore, from the perspective of symmetry, N = M is sufficient, and a regular polygon can be used as the repetition period. Among the regular polygons that can fill an infinite plane, the regular hexagon has the largest number of sides, so a honeycomb structure with a repetition period of a regular hexagon (N = M = 6) is more preferred.

[0347] <Example 9>

[0348] Figure 31 It is a plan view showing a ninth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0349] Figure 31The pixel array 18 shown has seven pixel arrays 17 .

[0350] With this structure, each pixel included in the photodetector according to the present disclosure can maintain a symmetrical shape, thereby suppressing distortion of the image formed by the charge read out by the readout circuit 407, etc. Furthermore, the pixels can be arranged more densely, resulting in a more miniaturized structure according to the structure of the pixel array 18.

[0351] <Example 10>

[0352] Figure 32 It is a plan view showing a tenth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0353] about Figure 32 In the illustrated pixel array 19, first wells 104 and second wells 105 are formed in rows in a plan view. Furthermore, multiple isolation transistors 201 are formed within the second well 105. Arranging the first wells 104 and second wells 105 in rows reduces the area of ​​the first wells 104, second wells 105, and isolation region 103. This increases the plan view area of ​​the first semiconductor layer 101. Consequently, pixel array 19 further improves the aperture ratio and light sensitivity.

[0354] <Example 11>

[0355] Figure 33 This is a plan view showing an eleventh example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0356] about Figure 33 In the illustrated pixel array 20, first wells 104 and second wells 105 are formed in rows in a plan view. Furthermore, multiple isolation transistors 201 are formed within the second wells 105. In particular, the isolation transistors 201 connected to the first semiconductor layer 101 in columns adjacent to the first well 104 or second well 105 in the figure are arranged within the same second well 105. Arranging the first wells 104 and second wells 105 in rows reduces the areas of the first wells 104, second wells 105, and isolation region 103. This increases the area of ​​the first semiconductor layer 101 in a plan view. Consequently, the pixel array 20 further improves the aperture ratio and light sensitivity.

[0357] <Example 12>

[0358] Figure 34 This is a plan view showing a twelfth example of the arrangement layout of pixels of the photodetector according to the present disclosure. Figure 35 It shows Figure 34XXXV-XXXV line of the twelfth example of the arrangement layout of pixels of the photodetector according to the present disclosure.

[0359] Figure 34 as well as Figure 35 The pixel array 22 shown has three pixels arranged in two rows and two columns, and a first well 104 and a second well 105 .

[0360] Therefore, the number of pixels included in the pixel array is large, and therefore the area for forming the circuit must be wide. Moreover, even if the area of ​​the first well 104 and the second well 105 cannot be reduced, it is difficult to reduce the light sensitivity. In particular, the device used for signal processing, supplementing the signal in the area where the first well 104 and the second well 105 are formed, and outputting the image can be arranged in the area where the first well 104 and the second well 105 are formed.

[0361] [Modification 1 of Circuit Configuration]

[0362] Next, refer to Figures 36 to 38 , a first modification of the circuit structure of the photodetector according to one aspect of the present disclosure will be described.

[0363] exist Figure 5 In the circuit structure of the photodetector 100 shown in FIG. 1 , the pixel array 9 is connected to a vertical scanning circuit 406, a horizontal scanning circuit 408, a readout circuit 407, and a buffer amplifier 409. However, the photodetector of the present disclosure is not limited to Figure 5 The circuit structure shown.

[0364] Figure 36 1 is a diagram showing a first modification of the circuit configuration of the photodetector 100 d according to the present disclosure. Figure 37 1 is a plan view showing an example of a pixel array 23 including pixels 6 f according to Modification 1 of the circuit configuration of the photodetector 100 d according to the present disclosure. Figure 38 1 is a diagram showing an example of a driving sequence according to Modification 1 of the circuit configuration of the photodetector 100 d according to the present disclosure.

[0365] and, Figures 36 to 38 The circuit configuration described in can also be adopted in any of the photodetector 100 according to the first embodiment, the photodetector 100a according to the second embodiment, and their modified examples.

[0366] And, in Figure 36 as well as Figure 37In the description, the same symbols may be attached to the components with the same functions for the sake of explanation. For example, the first semiconductor layer is described as the first semiconductor layer 101 even if the shape is different from that of the first semiconductor layer 101 of the photodetector 100 according to the first embodiment. The other components such as the first well and the second well may also be described with the same symbols. In addition, the pixel array 21 of the photodetector 100d may be, for example, Figures 23 to 35 Pixel arrays 10 to 20, 22 are shown.

[0367] and, Figure 38 (a) shows the time variation of the gate voltage of the reset transistor 410, Figure 38 (b) shows the temporal change of the gate voltage of the selection transistor 412 .

[0368] like Figure 36 as well as Figure 37 As shown, a photodetector 100d according to a first variation of the circuit structure includes a readout circuit 407, a reset transistor 410 for resetting the APD, a source follower transistor 411 for amplifying the first charge, a selection transistor 412 for transmitting the signal of the selected column to the vertical signal line 404, and a floating diffusion capacitor 413. Here, the isolation transistor 201 corresponds to the source follower transistor 411.

[0369] And, as Figure 37 As shown, a reset transistor 410 , a source follower transistor 411 , and a select transistor 412 are formed in the second well 105 in a plan view.

[0370] like Figure 37 As shown, the source of the reset transistor 410 and the gate of the source follower transistor 411 are connected by wiring. The source of the source follower transistor 411 is shared with the drain of the selection transistor 412. The source of the selection transistor 412 is connected to the vertical signal line 404.

[0371] According to these structures, the signal based on the first charge is amplified in the pixel 6f, thereby reducing the influence of circuit noise in the subsequent stage.

[0372] Furthermore, the source of the source follower transistor 411 and the drain of the selection transistor 412 may not be shared.

[0373] Figure 38 This is an example of a driving method of the readout circuit 407.

[0374] First, the reset transistor 410 is turned on to reset the first semiconductor layer 101 to Vdd.

[0375] Then, the reset transistor 410 is turned off, the selection transistor 412 is turned on, and the potential of the APD is read through the source follower transistor 411. The signal at this time is stored in a circuit such as a memory located in a subsequent stage (not shown).

[0376] After the exposure time Δt has elapsed after the reset transistor 410 is turned off, the selection transistor 412 is turned on, and the potential of the APD is read out via the source follower transistor 411 , and the difference with the signal immediately after the reset is obtained.

[0377] Based on this, background noise overlapping with the signal is removed.

[0378] [Modification 2 of Circuit Configuration]

[0379] Next, refer to Figures 39 to 42 , describing a modification of the circuit structure of a photodetector according to one aspect of the present disclosure.

[0380] exist Figure 5 In the circuit structure of the photodetector 100 shown in FIG. 1 , the pixel array 9 is connected to a vertical scanning circuit 406, a horizontal scanning circuit 408, a readout circuit 407, and a buffer amplifier 409. However, the photodetector of the present disclosure is not limited to Figure 5 The circuit structure shown.

[0381] Figure 39 1 is a diagram showing a second modification of the circuit configuration of the photodetector 100 b according to the present disclosure. Figure 40 1 is a plan view showing an example of a pixel array 23 a including pixels 6 e according to a second modification of the circuit configuration of the photodetector 100 b according to the present disclosure. Figure 41 1 is a plan view showing another example of a pixel array 23 a including pixels 6 e according to Modification 2 of the circuit structure of the photodetector according to the present disclosure. Figure 42 1 is a diagram showing an example of a driving sequence according to a second modification of the circuit configuration of the photodetector 100 b according to the present disclosure.

[0382] and, Figure 42 (a) shows the time variation of the gate voltage of the reset transistor 410, Figure 42 (b) shows the time variation of the gate voltage of the transfer transistor 402, Figure 42 (c) shows the temporal change of the gate voltage of the selection transistor 412 .

[0383] and, Figures 39 to 42 The circuit configuration described in can also be adopted in any of the photodetector 100 according to the first embodiment, the photodetector 100a according to the second embodiment, and their modified examples.

[0384] And, in Figure 40 as well as Figure 41 In the description, the same symbols may be attached to the components with the same functions for the sake of explanation. For example, the first semiconductor layer is described as the first semiconductor layer 101 even if the shape is different from that of the first semiconductor layer 101 of the photodetector 100 according to the first embodiment. The other components such as the first well and the second well may also be described with the same symbols. In addition, the pixel array 23 or the pixel array 23a of the photodetector 100b may be described as follows. Figures 23 to 35 Pixel arrays 10 to 20, 22 are shown.

[0385] like Figure 39 as well as Figure 40 As shown, the photodetector 100b of the modified example of the circuit structure includes a readout circuit 407, a reset transistor 410 for resetting the drain of the separation transistor 201, a source follower transistor 411 for amplifying the first charge, a selection transistor 412 for transmitting the signal of the selected column to the vertical signal line 404, and a floating diffusion capacitor 413.

[0386] And, as Figure 40 As shown, a reset transistor 410 , a source follower transistor 411 , and a select transistor 412 are formed in the second well 105 in a plan view.

[0387] Furthermore, regarding the separation transistor 201, as Figure 40 The pixel array 23 shown in the figure can also be electrically connected to the first semiconductor layer 101 located on the left and right sides of the figure, such as Figure 41 The pixel array 23 a shown may also be electrically connected to only one of the first semiconductor layers 101 located on the left and right sides of the drawing.

[0388] like Figure 41 As shown, the drain of the isolation transistor 201, the source of the reset transistor 410, and the gate of the source-follower transistor 411 are connected by wiring. Furthermore, the source of the source-follower transistor 411 is shared with the drain of the selection transistor 412. Furthermore, the source of the selection transistor 412 is connected to the vertical signal line 404.

[0389] According to these structures, the signal based on the first charge is amplified in the pixel 6e, thereby reducing the influence of circuit noise in the subsequent stage.

[0390] Furthermore, the source of the source follower transistor 411 and the drain of the selection transistor 412 may not be shared.

[0391] And, as Figure 40As shown, two isolation transistors 201 share a drain. The drain of isolation transistor 201, the source of reset transistor 410, and the gate of source-follower transistor 411 are connected by wiring. Furthermore, the source of source-follower transistor 411 shares a drain with select transistor 412. Furthermore, the source of select transistor 412 is connected to vertical signal line 404.

[0392] According to these structures, the signal based on the first charge is amplified in the pixel 6e, thereby reducing the influence of circuit noise in the subsequent stage.

[0393] Figure 42 1 and 2. An example of a driving method of the readout circuit 407 is shown, and driving by correlated double sampling is shown.

[0394] First, the reset transistor 410 ( Figure 42 (a)) and the transfer transistor 402 ( Figure 42 (b)) is turned on, resetting the first semiconductor layer 101 to Vdd.

[0395] Then, the reset transistor 410 and the transfer transistor 402 are turned off, and the selection transistor 412 ( Figure 42 (c) is turned on. The signal at this time is stored in a circuit such as a memory located in the subsequent stage (not shown in the figure).

[0396] After the exposure time Δt has elapsed after the reset transistor 410 and the transfer transistor 402 are turned off, the separation transistor 201 is turned on, thereby transferring the first charge accumulated in the first semiconductor layer 101 to the floating diffusion capacitor 413 .

[0397] Then, the selection transistor 412 is turned on, and the potential of the floating diffusion capacitor 413 is read through the source follower transistor 411 , and the difference between the potential and the signal immediately after the reset is obtained.

[0398] Based on this, background noise overlapping with the signal is removed.

[0399] [Package]

[0400] Next, refer to Figures 43 to 45 , illustrating the packaging structure of the light detector involved in the present disclosure.

[0401] and, Figures 43 to 45 The package structure described in the above can also be adopted in the photodetector 100 according to the first embodiment, the photodetector 100a according to the second embodiment, and any of their variations. Figures 43 to 45 As an example, it is shown Figure 9 The illustrated example shows an example in which the pixel 6a is arranged in a package.

[0402] and, Figures 43 to 45 is shown, for example with Figure 8 The cross-sectional view of the cross section corresponding to the IX-IX line.

[0403] <Example 1>

[0404] Figure 43 1 is a cross-sectional view showing a first example of the photodetector 30 according to the present disclosure.

[0405] The photodetector 30 includes a pixel 6 a and a package PKG1 .

[0406] The package PKG1 is a package for mounting the pixel 6a and includes a metal plate 501 electrically connected to an external power source B such as an external commercial power source.

[0407] The metal plate 501 is formed on a molded object such as a resin material that serves as the matrix material of the package PKG1, and is in contact with and connected to the second main surface S3 of the semiconductor substrate layer 3. In order to eliminate the charge generated by avalanche multiplication, the metal plate 501 needs to be in ohmic contact with the semiconductor substrate layer 3. In addition, the size of the metal plate 501 can be smaller. In particular, the contact resistance between the metal plate 501 on the package PKG1 and the semiconductor substrate layer 3 needs to be set to about 0.1Ω to 10Ω. In order to achieve this, the type of metal used for the metal plate 501 can be Ag, Au, Cu, Al, Ta, Pt, Ti, TiN, Si, etc.

[0408] like Figure 43 As shown, the photodetector 30 may also have a structure in which a voltage is directly applied to the semiconductor substrate layer 3 from the metal plate 501 on the package PKG1.

[0409] According to this, the back bias voltage V can be applied to the entire second main surface S3 of the semiconductor substrate layer 3. back Therefore, according to the photodetector 30 , the applied voltage can be made uniform, and when the photodetector 30 is used in an image sensor, variations in image quality can be suppressed.

[0410] <Example 2>

[0411] Figure 44 It is a cross-sectional view showing a second example of the photodetector 31 according to the present disclosure.

[0412] The photodetector 31 and the photodetector 30 differ only in the thickness of the semiconductor substrate layer 3 .

[0413] Here, the photodetector 31 may be configured such that the semiconductor substrate layer 3 is thinned and light transmitted through the pixel 6 a is reflected by the metal plate 501 of the package PKG1 .

[0414] Accordingly, the light reflected from the metal plate 501, i.e., the reflected light, can be photoelectrically converted by the first semiconductor layer 101a and the second semiconductor layer 102a. The charge generated by the photoelectric conversion can also be detected as a signal. Therefore, the light sensitivity of the photodetector 31 is further improved. In particular, silicon has a small absorption coefficient with respect to near-infrared light, and more light passes through the pixel 6a. For example, in the case of detecting light with a peak wavelength of 940nm in the photodetector 31, when the thickness of the epitaxial layer 1a and the semiconductor substrate layer 3 is 10μm, 80% of the incident light is not photoelectrically converted but passes through the pixel 6a. Therefore, according to Figure 44 The structure can perform photoelectric conversion on the light reflected by the metal plate 501 again, thereby increasing the light receiving sensitivity by 1.8 times.

[0415] Furthermore, an SOI (Silicon On Insulator) substrate can be used for the semiconductor substrate layer 3. In this case, the epitaxial layer 1a and the semiconductor substrate layer 3 can be thinned without performing back grinding or other processing on the semiconductor substrate layer 3. Therefore, there is no processing damage to the back surface (second main surface S3) of the semiconductor substrate layer 3, and the noise generated from the back surface of the semiconductor substrate layer 3 is reduced, thereby achieving low noise.

[0416] <Example 3>

[0417] Figure 45 It is a cross-sectional view showing a third example of the package PKG2 of the photodetector 32 according to the present disclosure.

[0418] The photodetector 32 includes a pixel 6a and a package PKG2. The package PKG2 includes a metal plate 501a and a metal wire 501b.

[0419] The pixel 6a is arranged on a molded article such as a resin material that is the base material of the package PKG 2, with the wiring layer 2 facing downward. That is, the photodetector 32 is a back side illumination (BSI) photodetector.

[0420] A transparent metal 4, which is a transparent electrode, is formed on the second main surface S3 of the semiconductor substrate layer 3. For example, ITO (Indium Tin Oxide) or the like is used as the transparent metal 4.

[0421] Furthermore, a support substrate 5 is bonded to the wiring layer 2 to reinforce the pixel 6a. The pixel 6a is bonded to the package PKG2 via the support substrate 5. The material of the support substrate 5 is not particularly limited, but for example, a metal substrate or a ceramic substrate can be used.

[0422] The power source B is electrically connected to the transparent metal 4 via the metal plate 501a and the metal wire 501b. back , is supplied from the power source B to the transparent metal 4 via the metal plate 501a and the metal wire 501b of the package PKG2.

[0423] The materials of the metal plate 501 a and the metal wire 501 b are not particularly limited, but for example, Ag, Au, Cu, Al, Ta, Pt, Ti, TiN, Si, etc. are used.

[0424] (Manufacturing Method)

[0425] Next, refer to Figures 46 to 52 , describing a method for manufacturing a light detector according to the present disclosure.

[0426] Figures 46 to 52 : is a cross-sectional view for explaining the method for manufacturing the photodetector according to the present disclosure.

[0427] like Figure 46 As shown, first, an epitaxial layer 703 is formed on a growth substrate 702. The growth substrate 702 is, for example, a Si substrate of the second conductivity type, and the epitaxial layer 703 is formed by epitaxially growing Si on the Si substrate.

[0428] Next, boron is implanted into the epitaxial layer 703 to form the second semiconductor layer 704 .

[0429] like Figure 47 As shown, subsequently, either phosphorus or arsenic, or both, are implanted into the epitaxial layer 703 , thereby forming a first semiconductor layer 705 on the second semiconductor layer 704 .

[0430] like Figure 48 As shown, next, at a position adjacent to the first semiconductor layer 705 and the second semiconductor layer 704, on the epitaxial layer 703 ( Figure 48 In the well 706, for example, a Figure 2 The pixel region shown includes the first well 104 and the second well 105 .

[0431] like Figure 49 As shown, next, a gate electrode 707 is formed on the well 706. The material used for the gate electrode 707 is, for example, polysilicon, aluminum, Ti, or the like.

[0432] like Figure 50As shown, an insulating film 708 is then formed on the surface of the epitaxial layer 703. The insulating film 708 is formed by, for example, a CVD (Chemical Vapor Deposition) method and a CMP (Chemical Mechanical Polishing) method.

[0433] like Figure 51 As shown, a contact 709 (electrode) connected to the well 706 is formed, and a contact 709 connected to the first semiconductor layer 705 is formed. The material used for the contact 709 is, for example, W, Ti, TiN, Ni, etc. The contact 709 is formed by, for example, photolithography, dry etching, metal CVD method, and CMP method.

[0434] like Figure 52 As shown, a first wiring 710 is formed to connect the contact 709 connected to the well 706 and the contact 709 connected to the first semiconductor layer 705, and further, a first wiring 710 is formed to connect the contact 709 connected to the well 706 and the first semiconductor layer 705. Figure 51 The insulating film 708 shown is thickened, and a wiring layer (eg, a 112a, 112b) is formed on the epitaxial layer 703. Figure 2 Wiring layer 2 shown).

[0435] Moreover, for Figures 46 to 52 The photodetector manufacturing process shown in the present disclosure employs, for example, a common dual damascene method. The dual damascene method is a film formation method that includes, for example, CVD to form a thin insulating film 708, photolithography and dry etching to form grooves in the thin insulating film 708, PVD (Physical Vapor Deposition) or CVD to form contacts 709, Cu plating to form first wiring 710, and CMP to thicken the insulating film 708 to form an insulating film 711.

[0436] (Implementation 3)

[0437] Next, refer to Figures 53 to 56 , describing the structure of the photodetector involved in embodiment 3.

[0438] In the description of the photodetector according to the third embodiment, substantially the same components as those of the photodetectors according to the first and second embodiments are denoted by the same reference numerals, and part of the description may be omitted or simplified.

[0439] Figure 53 It is a plan view showing a photodetector 1000 according to Embodiment 3 of the present disclosure. Figure 54 It shows Figure 53 1 is a cross-sectional view of the photodetector 1000 according to the third embodiment of the present disclosure, taken along line LIV-LIV.

[0440] Moreover, in Figure 53 as well as Figure 54 , among the components of the photodetector 1000, the first semiconductor layer 101, the isolation region 1030 (first isolation region), and a portion of the first wiring 203, i.e., the column signal line, are shown. A portion of the structure of the photodetector 1000 is omitted. For example, Figure 53 In the figure, some components such as wiring connected to the first wiring 203 are omitted. In addition, in other figures in the following description, part of the structure of the photodetector according to the present disclosure may be omitted.

[0441] The photodetector 1000 according to the third embodiment is a light detection sensor using an APD (Avalanche Photo Diode) and includes a semiconductor substrate 6000 having an epitaxial layer (semiconductor substrate) 1h and a semiconductor substrate layer 3, and a wiring layer 2. Specifically, the photodetector 1000 includes a second conductivity type epitaxial layer 1h, a wiring layer 2 formed on the first main surface S1 of the semiconductor substrate 6000 (more specifically, the epitaxial layer 1h), and a semiconductor substrate layer 3 formed on the back side of the epitaxial layer 1h.

[0442] The semiconductor wafer 6000 includes an epitaxial layer 1 h and a semiconductor substrate layer 3 .

[0443] The epitaxial layer 1h includes at least one first semiconductor layer 101 of the first conductivity type, a second semiconductor layer 102 of the second conductivity type, a multiplication region 301 for avalanche multiplying the charges generated by photoelectric conversion in the epitaxial layer 1h in the first semiconductor layer 101 and the second semiconductor layer 102, and a separation region 1030 for separating at least two multiplication regions 301.

[0444] The first semiconductor layer 101 is a semiconductor layer of the first conductivity type formed on the first main surface S1 side of the epitaxial layer 1h. A first contact 202 is formed on the first semiconductor layer 101.

[0445] The second semiconductor layer 102 is formed between the first semiconductor layer 101 and the semiconductor substrate layer 3. The second semiconductor layer 102 has a second conductivity type that is opposite to the first conductivity type. The second semiconductor layer 102 avalanche multiplies the charge converted by photoelectric conversion between the second semiconductor layer 102 and the first semiconductor layer 101.

[0446] The wiring layer 2 is a layer including first contacts 202 , which are electrodes, formed on the first main surface S1 of the first semiconductor layer 101 , and first wirings 203 , which are metal wirings.

[0447] The semiconductor substrate layer 3 is a growth substrate for forming the epitaxial layer 1h. The semiconductor substrate layer 3 has a growth surface S2 for forming the epitaxial layer 1h and a second main surface S3 opposite to the growth surface S2. A back electrode, or second contact 204, is formed on the back surface of the semiconductor substrate layer 3, i.e., on the back surface of the semiconductor substrate 6000, i.e., on the second main surface S3. back Applied to the semiconductor substrate layer 3, the voltage on the growth surface S2 side of the epitaxial layer 1h is fixed to V back .

[0448] A multiplication region 301 is formed between the first semiconductor layer 101 and the second semiconductor layer 102 and is substantially parallel to the first main surface S1 of the epitaxial layer 1 h .

[0449] The multiplication area 301 is a region where the received light ( Figure 54 The region shown is where the charge generated by hν) photoelectric conversion is multiplied by avalanche multiplication.

[0450] The magnitude of the electric field in the multiplication region 301 is, for example, 3 to 5×10 5 V / cm, and the impurity concentrations of the first semiconductor layer 101 and the second semiconductor layer 102 are, for example, 10 16 cm -3 to 10 20 cm -3 , the impurity concentration of the epitaxial layer 1 is, for example, 10 14 cm -3 to 10 16 cm -3 .

[0451] Also, in this case, the amount of potential change in the depth direction of the multiplication region 301 is, for example, 20V.

[0452] Furthermore, in each of the drawings in this specification, light received by the photodetector according to the present disclosure (ie, incident light) is represented as hν.

[0453] The second charge, a charge carrier of the second conductivity type generated by photoelectric conversion in the photoelectric conversion layer 302 stacked beneath the multiplication region 301, drifts to the multiplication region 301, where it undergoes avalanche multiplication, multiplying the number of carriers by 1 to 100,000. At this point, the first charge, a charge carrier of the first conductivity type generated by photoelectric conversion and avalanche multiplication, accumulates in the first semiconductor layer 101. Furthermore, the second charge generated by photoelectric conversion and avalanche multiplication drifts to the second contact 204 and is discharged outside the photodetector 1000. In other words, the second charge, of the charge generated by photoelectric conversion between the first semiconductor layer 101 and the second semiconductor layer 102, that has a different polarity from the first charge, flows through the second contact 204 to the outside of the semiconductor substrate layer 3.

[0454] Here, the second contact 204 is preferably formed on the entire surface of the second main surface S3. The second contact 204 is a conductive material formed on the second conductivity type semiconductor layer (the second semiconductor layer 102) or the back surface (ie, the second main surface S3).

[0455] For example, the semiconductor substrate layer 3, which is the growth substrate for growing the epitaxial layer 1h, may be used as the second contact 204. Alternatively, the second contact 204 may be formed by adjusting the carrier density of the second conductivity type semiconductor layer by impurity diffusion or ion implantation.

[0456] Furthermore, a voltage may be applied to the second contact 204 via the semiconductor substrate 6000 from a contact (not shown) formed on the first main surface S1 side of the semiconductor substrate 6000 .

[0457] This allows the second charges not used as signals to be discharged within a short period of time to the outside of the photodetector 1000. This suppresses temporal variation and spatial non-uniformity of the voltage within the photodetector 1000, thereby improving light detection efficiency.

[0458] Then, the first charge accumulated in the first semiconductor layer 101 is transferred from the first semiconductor layer 101 and the second semiconductor layer 102 of the semiconductor substrate 6000 to the readout circuit 407 (see Figure 12 ), is processed into a signal. Based on this, the light detector 1000 detects the incident light.

[0459] There is no particular limitation on the structure of the readout circuit 407. The readout circuit 407 is, for example, a current amplifier or an AD (Analog to Digital) converter circuit.

[0460] Furthermore, a structure in which the first conductivity type is positive (i.e., P-type) and the second conductivity type is negative (i.e., N-type) is also possible, but it is sufficient to set the first conductivity type to negative and the second conductivity type to positive. In other words, the first charges are electrons and the second charges are holes.

[0461] The ionization rate of electrons is higher than that of holes, so avalanche multiplication is more likely to occur. Therefore, with such a structure, the light receiving sensitivity of the photodetector 1000 is improved.

[0462] In particular, in the photodetector 1000 according to Embodiment 3, no contact or STI (Shallow Trench Isolation) is formed on the isolation region 1030. Furthermore, the isolation region 1030 is depleted and has an unstable potential. Specifically, no STI is formed in the region where the first semiconductor layer 101 and the isolation region 1030 are formed.

[0463] This allows the width of the isolation region 1030 to be reduced, thereby increasing the aperture ratio of the photodetector 1000 .

[0464] In the SPADs (Single Photon Avalanche Diodes) described in Patent Documents 4 and 8, contacts are formed in the isolation region. Consequently, an electric field is generated at the end of the avalanche multiplication region in a direction parallel to the surface of the semiconductor substrate, and the electric field is concentrated at the end of the avalanche multiplication region. To prevent this electric field concentration, a so-called guard ring structure is formed to mitigate the electric field, thereby expanding the isolation region and shrinking the multiplication region.

[0465] On the other hand, in this embodiment, no STI or contact is formed in the isolation region 103. Therefore, even without a guard ring, the lateral electric field can be suppressed. This eliminates electric field concentration, allowing the multiplication region 301 to be expanded and improving photosensitivity.

[0466] It is particularly preferable that the depletion layer width in the longitudinal direction (perpendicular to the first main surface S1) of the multiplication region 301 be greater than the depletion layer width in the lateral direction (parallel to the first main surface S1) of the separation region 1030 (i.e., approximately half the width of the separation region 1030). This structure can easily alleviate electric field concentration at the ends of the multiplication region 301 and make the electric field intensity uniform. Consequently, the avalanche multiplication region can be expanded, and photosensitivity can be easily improved.

[0467] Furthermore, the width of the separation region 1030 is, for example, 0.1 μm to 1 μm, and the impurity concentration is 10 15 cm -3 to 10 18cm -3 The potential of the isolation region 1030 is determined by the potential of the first semiconductor layer 101 and the back bias voltage V back Decide.

[0468] Here, if the potential difference between the first semiconductor layer 101 and the isolation region 1030 is small, the number of saturated electrons decreases, making charge leakage to adjacent pixels more likely to occur. If the potential difference V between the first semiconductor layer 101 and the isolation region 1030 is large, the electric field generated on the device surface (e.g., the first main surface S1) increases, causing problems such as increased dark current and dark count (DCR). Therefore, the potential difference between the first semiconductor layer 101 and the isolation region 1030 is preferably approximately 0.1 to 10 V.

[0469] Furthermore, the light incident surface in the third embodiment is the first principal surface S1 of the epitaxial layer 1 h .

[0470] This eliminates the need for special processes such as backside processing, reducing costs. In particular, long-wavelength light, such as near-infrared light, has a low absorption coefficient and is not attenuated until near the semiconductor substrate layer 3. Therefore, even if the photoelectric conversion layer 302 is formed in an area far from the first principal surface S1 of the epitaxial layer 1h, the light-receiving sensitivity remains virtually unchanged compared to when it is formed near the first principal surface S1. For example, the absorption coefficient of silicon (Si) for 940nm light, which has minimal spectral intensity in the near-infrared region of sunlight, is 1% / μm. Therefore, even if the photoelectric conversion layer 302 is formed 1μm deep from the first principal surface S1, the reduction in light-receiving sensitivity is only 1%.

[0471] Furthermore, an optical waveguide may be provided on the multiplication region 301 in the wiring layer 2, and a microlens may be provided on the wiring layer 2. This can improve light-collecting efficiency.

[0472] Next, refer to Figure 55 as well as Figure 56 , describing the potential of the first charge.

[0473] Figure 55 It shows Figure 54 FIG. 1 is a diagram showing the potentials of the photodetector 1000 according to the third embodiment of the present disclosure on the LVA-LVA line and the LVB-LVB line. Figure 56 It shows Figure 54 FIG. 1 is a diagram showing the potential of the photodetector 1000 according to the third embodiment of the present disclosure on the LVC-LVC line.

[0474] and, Figure 55 The solid line shown is, Figure 54 The potential on the LVA-LVA line in the circuit, the potential of the first semiconductor layer 101, the multiplication region 301 and the photoelectric conversion layer 302.

[0475] The first semiconductor layer 101 and the readout circuit 407 (for example, Figure 5 ) is connected, and is at least temporarily fixed to the power supply voltage V of the readout circuit 407 dd On the other hand, the growth surface S2 side of the epitaxial layer 1h is fixed to V via the semiconductor substrate layer 3. back .

[0476] Furthermore, the photoelectric conversion layer 302 is depleted, and a potential gradient is formed that causes the charge to drift toward the multiplication region 301 .

[0477] When the photoelectric conversion layer 302 is depleted, the potential change of the photoelectric conversion layer 302 is, for example, approximately 20 V when the thickness of the photoelectric conversion layer 302 is 5 μm, and approximately 40 V when the thickness of the photoelectric conversion layer 302 is 15 μm.

[0478] Hereinafter, in this specification, the voltage difference between the first contact 202 and the second contact 204 when the threshold voltage that causes avalanche multiplication in the multiplication region 301 is applied is referred to as the avalanche breakdown voltage. In this case, for example, when the thickness of the photoelectric conversion layer 302 is 5 μm, the avalanche breakdown voltage is 40 V.

[0479] like Figure 55 It is shown that the potential on the LVA-LVA line and the LVB-LVB line approaches V as it goes deeper, that is, as the depth increases. back On the other hand, the closer to the first main surface S1 side, that is, the shallower the depth, the greater the potential on the LVA-LVA line and the LVB-LVB line. For example, the potential on the LVA-LVA line is close to V dd Furthermore, it is preferable that the potential on the LVB-LVB line is depleted on the first main surface S1 and the potential is unstable.

[0480] like Figure 56 As shown, the adjacent first semiconductor layers 101 are biased to V dd Furthermore, the separation region 1030 between adjacent first semiconductor layers 101 is depleted and has an indeterminate potential, thereby electrically separating the adjacent first semiconductor layers 101. Furthermore, the potential difference between the first semiconductor layer 101 and the separation region 1030 may be 0.1 to 10V.

[0481] Thus, the separation region 1030 separates two adjacent first semiconductor layers 101, i.e., adjacent multiplication regions 301, by electric potential. Furthermore, the potential of the separation region 1030 is greater than the voltage change of the first semiconductor layer 101 due to the charge generated by avalanche multiplication, because the separation region 1030 is depleted.

[0482] According to the above-described structure, the photodetector 1000 can miniaturize the separation region 1030 and expand the multiplication region 301, thereby improving the light receiving sensitivity.

[0483] For example, when a contact is provided without depleting the separation region 1030 as in Patent Document 4, in order to ensure electrical separation and mitigate the electric field in a direction roughly parallel to the epitaxial layer 1h (i.e., a direction parallel to the first main surface S1), a separation width of more than 1 μm is typically required in a direction parallel to the first main surface S1.

[0484] In contrast, in the photodetector 1000 according to Embodiment 3, the isolation region 1030 is depleted. Due to the depletion of the isolation region 1030, the electric field between the first semiconductor layer 101 and the isolation region 1030 is reduced. Consequently, the isolation width can be narrowed to 0.1 μm to 1 μm. In other words, the photodetector 1000 can increase the area of ​​the multiplication region 301, thereby improving the aperture ratio and thereby enhancing photosensitivity.

[0485] As described above, the photodetector 1000 involved in embodiment 3 comprises: a semiconductor substrate 6000 having a first main surface S1 and a second main surface S3 on the side opposite to the first main surface S1; a first semiconductor layer 101 having a first conductivity type, formed on the first main surface S1 side of the semiconductor substrate 6000; a second semiconductor layer 102 having a second conductivity type, formed between the first semiconductor layer 101 and the second main surface S3 of the semiconductor substrate 6000, the second conductivity type being a conductivity type different from the first conductivity type; a multiplication region 301, which avalanche multiplies the charge generated by photoelectric conversion in the semiconductor substrate 6000 in the first semiconductor layer 101 and the second semiconductor layer 102; and a separation region 1030, which separates at least two multiplication regions 301.

[0486] According to such a structure, the separation region 1030 can be narrowed, thereby enabling the photodetector 1000 to be miniaturized.

[0487] Furthermore, with this structure, the charges generated in the photoelectric conversion layer 302 drift within the photoelectric conversion layer 302 and enter the multiplication region 301, resulting in avalanche multiplication. The charges generated by photoelectric conversion are amplified by avalanche multiplication, enabling light detection even when the intensity of the incident light is low. In other words, this structure improves the sensitivity (i.e., light-receiving sensitivity) of the photodetector 1000.

[0488] Furthermore, for example, the photodetector 1000 further includes a second contact 204 formed on the second main surface S3. One of first charges generated by photoelectric conversion between the first semiconductor layer 101 and the second semiconductor layer 102 and second charges having a polarity different from the first charges flows to the outside of the semiconductor substrate 6000 via the second contact 204.

[0489] With this structure, for example, second-conductivity-type carriers generated by photoelectric conversion and avalanche multiplication, i.e., second charges, are discharged to the exterior of the photodetector 1000 via the second contact 204 located on the back side of the semiconductor substrate 6000, i.e., the second main surface S3. This reduces temporal variations and positional variations in the voltage on the back side of the semiconductor substrate 6000. This reduces spatial and temporal variations in the light detection efficiency of the photodetector 1000.

[0490] Furthermore, for example, the separation region 1030 separates two adjacent multiplication regions 301 by an electric potential.

[0491] According to this structure, compared with the case where the isolation region 1030 is formed by forming a groove or the like, the aperture ratio can be increased, the photosensitivity can be improved, and the dark current and DCR can be reduced.

[0492] Furthermore, for example, the potential of the separation region 1030 is larger than the voltage change of the first semiconductor layer 101 based on the charge generated by avalanche multiplication.

[0493] With such a structure, even when a voltage change occurs in the first semiconductor layer 101 , the adjacent first semiconductor layers 101 can be electrically separated by the isolation region 1030 .

[0494] Also, for example, the separation region 1030 is depleted.

[0495] According to this structure, the separation region 1030 is depleted, thereby separating the two multiplication regions 301 with a short separation width and relaxing the electric field in the separation region 1030. Thus, the photodetector 1000 can ensure light sensitivity and achieve miniaturization. Therefore, according to the photodetector 1000, the aperture ratio is improved. Furthermore, the separation region 103 is depleted, thereby suppressing the concentration of the electric field in the multiplication region 301. Therefore, it is not necessary to form a guard ring around the multiplication region 301, which is required in conventional photodetectors. Therefore, the photodetector 1000 can further narrow the separation region 1030, increase the aperture ratio, and improve light sensitivity. Moreover, even if the pixel 60 is miniaturized, the sensitivity is unlikely to decrease, thus facilitating miniaturization.

[0496] Furthermore, for example, in the region where the first semiconductor layer 101 and the isolation region 1030 are formed, no STI or contact is formed.

[0497] According to such a configuration, the generation of dark current can be suppressed.

[0498] (Variation)

[0499] Next, a modification of the photodetector 1000 according to Embodiment 3 will be described. The description of the modification will focus on differences from the photodetector 1000, and substantially identical components will be assigned the same reference numerals, with some descriptions being simplified or omitted.

[0500] <Variation 1>

[0501] Figure 57 This is a cross-sectional view showing a first modification of the photodetector according to the third embodiment of the present disclosure.

[0502] The photodetector 1001 according to Modification 1 includes an epitaxial layer 1e in the pixel 61, which is different from that of the photodetector 1000. Specifically, the epitaxial layer 1e has a different dimension of the second semiconductor layer 1020 when viewed in plan view than the epitaxial layer 1h. More specifically, the photodetector 1001 according to Modification 1 has a different width of the second semiconductor layer 1020 when viewed in cross section than the photodetector 1000. In other words, the photodetector 1001 according to Modification 1 has a different width of the second semiconductor layer 1020 in a direction parallel to the first main surface S1 than the photodetector 1000.

[0503] In this embodiment, in a cross-sectional view, the width (lateral direction in the drawing) of the second semiconductor layer 1020 is substantially the same as that of the first semiconductor layer 101 .

[0504] Thus, for example, the second semiconductor layer 1020 has the same shape as the first semiconductor layer 101 or is wider than the first semiconductor layer 101 in a planar view.

[0505] This structure makes the electric field more uniform in a direction substantially parallel to the first main surface S1 of the semiconductor substrate 6000, and the avalanche multiplication region (multiplication region 301) is formed wider. Specifically, the multiplication region 301 is the same width as the first semiconductor layer 101, or wider than the first semiconductor layer 101, when viewed in cross section. This further increases the aperture ratio and improves the light sensitivity.

[0506] <Variation 2>

[0507] Figure 58 This is a cross-sectional view showing a second modification of the photodetector according to the third embodiment of the present disclosure.

[0508] The photodetector 1002 according to Modification 2 includes an epitaxial layer 1f, which is different from that of the photodetector 1000, in the pixel 62. Specifically, the second semiconductor layer 1020a in the epitaxial layer 1f has a different size in plan view than that in the epitaxial layer 1h. More specifically, in the photodetector 1002 according to Modification 2, the second semiconductor layer 1020a extends over the entire surface of the epitaxial layer 1f in plan view. In other words, for example, the photodetector 1002 includes multiple first semiconductor layers 101, and the second semiconductor layer 1020a is continuously formed on the semiconductor substrate 6001 so as to overlap with the multiple first semiconductor layers 101 in plan view.

[0509] Figure 59 It shows Figure 58 Graph showing the potential of the photodetector 1002 on the LIXA-LIXA line, the LIXB-LIXB line, and the LIXC-LIXC line.

[0510] like Figure 59 As shown in the figure, it can be seen that in the first semiconductor layer 101, even if the position changes in a direction parallel to the first main surface S1, the way the potential changes remains almost unchanged. Therefore, the electric field is more uniform relative to the direction substantially parallel to the first main surface S1 of the semiconductor substrate 6001, and the multiplication region 301 is formed wider. Specifically, the multiplication region 301 is wider than the first semiconductor layer 101. This can further increase the aperture ratio and improve the photosensitivity.

[0511] Furthermore, combinations of the contents of the invention described in Embodiment 3, Embodiment 1, and / or Embodiment 2 are also included in the scope of the present invention.

[0512] Specifically, in this third embodiment, the concentration of the second semiconductor layers 102, 1020, and 1020a can gradually increase from the first principal surface S1 toward the second principal surface S3 of the semiconductor substrates 6000 and 6001. Furthermore, the second semiconductor layers 102, 1020, and 1020a can also be formed by epitaxial growth. Any of the circuit structures and layouts described in the first and second embodiments can also be applied to the third embodiment.

[0513] (other)

[0514] The photodetectors according to the embodiments of the present disclosure have been described above based on Embodiments 1, 2, and 3, as well as their respective variations. However, the present disclosure is not limited to these embodiments. Any variations of the present embodiment conceived by those skilled in the art, or any combination of components from different embodiments, may fall within the scope of one or more embodiments of the present disclosure, provided that they do not depart from the spirit of the present disclosure.

[0515] The photodetector according to the present disclosure can be applied to a CMOS (Complementary Metal Oxide Semiconductor) image sensor or the like that has high light-receiving sensitivity and can detect weak light.

[0516] Explanation of symbols

[0517] 1, 1a, 1c, 1d, 1e, 1f, 1g, 1h, 1i epitaxial layer

[0518] 2 wiring layers

[0519] 3 Semiconductor substrate layer

[0520] 4 Transparent Metal

[0521] 5 Support substrate

[0522] 6, 6a, 6c, 6d, 6e, 6f, 60, 61, 62, 63 pixels

[0523] 9 to 20, 21, 22, 23, 23a pixel array

[0524] 30 to 32, 100, 100a, 100b, 100c, 100d, 1000, 1001, 1002, 1003 Photodetectors

[0525] 101, 101a, 101b, 101c first semiconductor layer

[0526] 102, 102a, 102b, 1020, 1020a second semiconductor layer

[0527] 103, 1030 separation area

[0528] 104 First well (circuit area)

[0529] 105 Second well (circuit area)

[0530] 107, 107a fourth semiconductor layer

[0531] 201 Discrete Transistor

[0532] 202 first contact

[0533] 203 First Wiring

[0534] 204 second contact

[0535] 205 signal lines

[0536] 301 Doubling Area

[0537] 302 Photoelectric conversion layer

[0538] 401 APD

[0539] 402 pass transistor

[0540] 403 horizontal signal line

[0541] 404 vertical signal line

[0542] 406 vertical scanning circuit

[0543] 407 Readout Circuit

[0544] 408 horizontal scanning circuit

[0545] 409 Buffer Amplifier

[0546] 410 Reset transistor

[0547] 411 Source Follower Transistor

[0548] 412 Select transistor

[0549] 413 floating diffusion capacitor

[0550] 501, 501a metal plate

[0551] 501b metal wire

[0552] 600, 601, 602, 6000, 6001 semiconductor substrates

[0553] 700 Second conductivity type layer

[0554] 701 Contact

[0555] 702 Growth Substrate

[0556] 703 epitaxial layer

[0557] 704 second semiconductor layer

[0558] 705 first semiconductor layer

[0559] 706 Trap

[0560] 707 Gate Electrode

[0561] 708, 711 insulating film

[0562] 709 Contact

[0563] 710 First Wiring

[0564] B Power Supply

[0565] S1 first main surface

[0566] S2 growth surface

[0567] S3 Second main surface

[0568] PKG1, PKG2 packages

Claims

1. A light detector, wherein: have: A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; an epitaxial layer formed on the semiconductor substrate; a multiplication region in the epitaxial layer, substantially parallel to the first main surface, and avalanche multiplying charges generated by photoelectric conversion in the semiconductor substrate; as well as a separation region, separating at least two of the multiplication regions, The impurity concentration distribution of the epitaxial layer has a region that increases sharply from a substantially constant region toward the second main surface.

2. The light detector according to claim 1, wherein A first semiconductor layer is provided, the first semiconductor layer being formed on the first main surface side of the semiconductor substrate and having a first conductivity type, The epitaxial layer includes a fourth semiconductor layer having a second conductivity type, the second conductivity type being a conductivity type different from the first conductivity type, A maximum value of the impurity concentration of the fourth semiconductor layer is lower than a maximum value of the impurity concentration of the first semiconductor layer.

3. The light detector according to claim 1 or 2, wherein The epitaxial layer comprises: a fourth semiconductor layer; and a photoelectric conversion layer that causes the charges generated by the photoelectric conversion to drift to the multiplication region; The maximum value of the impurity concentration of the fourth semiconductor layer is greater than the maximum value of the impurity concentration of the photoelectric conversion layer.

4. The light detector according to claim 1 or 2, wherein The epitaxial layer includes a fourth semiconductor layer, The impurity concentration of the fourth semiconductor layer is lower than a maximum value of the impurity concentration of the sharply increased region.

5. The light detector according to claim 1 or 2, wherein The coefficient of variation of the avalanche breakdown voltage is less than 0.

015.

6. The light detector according to claim 1 or 2, wherein The coefficient of variation of the avalanche breakdown voltage is less than 0.

007.

7. The light detector according to claim 1 or 2, wherein The coefficient of variation of the avalanche breakdown voltage is greater than or equal to 0.005 and less than or equal to 0.

015.

8. A light detector, wherein: have: A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; an epitaxial layer formed on the semiconductor substrate; a multiplication region in the epitaxial layer, substantially parallel to the first main surface, and avalanche multiplying charges generated by photoelectric conversion in the semiconductor substrate; as well as A first semiconductor layer and a second semiconductor layer are included in the epitaxial layer, the first semiconductor layer is formed on the first main surface side, and the second semiconductor layer is formed between the first semiconductor layer and the second main surface. The second semiconductor layer has the same shape as the first semiconductor layer in a plan view, or is wider than the first semiconductor layer. The impurity concentration distribution of the epitaxial layer has a region that increases sharply from a substantially constant region toward the second main surface.

9. A light detector, wherein: have: A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; an epitaxial layer formed on the semiconductor substrate; a multiplication region in the epitaxial layer, substantially parallel to the first main surface, and avalanche multiplying charges generated by photoelectric conversion in the semiconductor substrate; as well as A first semiconductor layer and a second semiconductor layer are included in the epitaxial layer, the first semiconductor layer is formed on the first main surface side, and the second semiconductor layer is formed between the first semiconductor layer and the second main surface. The impurity concentration distribution of the second semiconductor layer is substantially constant in a direction substantially parallel to the first main surface. The impurity concentration distribution of the epitaxial layer has a region that increases sharply from a substantially constant region toward the second main surface.

Images