Semiconductor device

Abstract

Embodiments of the present application provide a semiconductor device, comprising: a substrate; a first well and a second well disposed in the substrate and adjacent to each other; an isolation structure disposed on the first well; a first field plate disposed on the isolation structure; a gate structure across the first well and the second well, and an opening between the first field plate and the gate structure, the opening exposing an edge of the isolation structure close to the gate structure; a drain structure disposed in the first well; and a source structure disposed in the second well, reducing or preventing hot carrier effect.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device comprising a field plate. Background Technology

[0002] Semiconductor devices can be used in a variety of fields, such as display driver ICs, power management ICs (or high-power power management ICs), discrete power devices, sensing devices, fingerprint recognition ICs, and memory, etc. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements.

[0003] To improve the breakdown voltage of semiconductor devices, in addition to optimizing the well and drift regions located between the source and drain, the gate is typically extended (e.g., over the drift region or isolation structure) to serve as a field plate. While existing gate field plates are generally satisfactory, they are not perfect in every aspect. Summary of the Invention

[0004] This invention provides a semiconductor device, comprising: a substrate; a first well and a second well disposed in the substrate and adjacent to each other; an isolation structure disposed on the first well; a first field plate disposed on the isolation structure; a gate structure spanning the first well and the second well, wherein an opening is provided between the first field plate and the gate structure, the opening exposing an edge of the isolation structure near the gate structure; a drain structure disposed in the first well; and a source structure disposed in the second well. Attached Figure Description

[0005] Figures 1 to 8 This is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0006] Icon labels:

[0007] 100, 200, 300, 400, 500, 600, 700, 800: Semiconductor devices

[0008] 110: Substrate

[0009] 112: First Trap

[0010] 114: Second Trap

[0011] 116: Isolation Structure

[0012] 116E: Edge

[0013] 118, 126, 128, 130, 132: Field boards

[0014] 118a: Part One

[0015] 118b: Part Two

[0016] 118c: Part Three

[0017] 120: Gate structure

[0018] 120a: Gate dielectric layer

[0019] 120b: Gate electrode

[0020] 122: Drain structure

[0021] 122a, 122b, 124a, 124b, 134, 136, 138: Doped regions

[0022] 124: Source Structure

[0023] 140: Interlayer dielectric layer

[0024] 142, 142a, 142b: Drain contacts

[0025] 144, 144a, 144b, 144c: Field plate contact components

[0026] 146: Source contact

[0027] D: Distance

[0028] L: Length

[0029] OP: Open Detailed Implementation

[0030] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments of the invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0031] Furthermore, in some embodiments of the present invention, terms such as "connection" and "interconnection," unless specifically defined, may refer to two structures in direct contact, or they may refer to two structures not in direct contact, wherein another structure is disposed between the two structures. Moreover, these terms regarding joining and connecting may also include cases where both structures are movable or both structures are fixed.

[0032] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0033] The terms "about," "approximately," and "roughly" as used herein generally mean within ±20%, preferably ±10%, and even more preferably ±5%, or ±3%, or ±2%, or ±1%, or 0.5%, of a given value. The values ​​given herein are approximate; that is, unless specifically stated otherwise, the given values ​​may imply the meaning of "about," "approximately," or "roughly."

[0034] The following describes some embodiments of the invention in which additional steps may be provided before, during, and / or after the multiple stages described in these embodiments. Some of the stages may be replaced or omitted in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components may be replaced or omitted in different embodiments. Although some of the embodiments discussed perform the steps in a particular order, these steps may still be performed in another logical order.

[0035] The following detailed description, in conjunction with the accompanying drawings, best illustrates the embodiments of the invention. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the invention.

[0036] Impact ionization points (II points) in semiconductor devices typically occur in isolation structures (such as shallow trench isolation (STI) or localized silicon oxide (LOCOS) structures) adjacent to the source structure. The electric field in the semiconductor device causes the electron-hole pairs generated by the impact ionization points to be injected into nearby components, resulting in hot carrier injection (HCI) and affecting the reliability of the semiconductor device.

[0037] This invention provides a semiconductor device in which the field plate on the isolation structure does not extend to the edge of the isolation region, and the gate structure does not extend to the isolation region. In other words, the field plate on the isolation structure and the gate structure have an opening exposing the edge of the isolation structure, thereby reducing the electric field strength at impact ionization points near the isolation structure and further reducing or preventing hot carrier effects.

[0038] For ease of explanation, embodiments of the present invention will be described below using a laterally diffused metal-oxide-semiconductor (LDMOS) device with an insulator-on-semiconductor superposition (IOS) as an example, and examples of applying the embodiments of the present invention to other devices (e.g., laterally insulated-gate bipolar transistors (LIGBTs)) will be presented, but the embodiments of the present invention are not limited thereto. Some embodiments of the present invention can also be applied to other types of metal-oxide-semiconductor devices, such as vertically diffused metal-oxide-semiconductor (VDMOS) devices, extended-drain metal-oxide-semiconductor (EDMOS) devices, or similar metal-oxide-semiconductor devices. Furthermore, the present invention can also be applied to other types of semiconductor devices, such as diodes, insulated-gate bipolar transistors (IGBTs), bipolar junction transistors (BJTs), or similar semiconductor devices.

[0039] Figure 1This is a schematic cross-sectional view of a semiconductor device 100 according to some embodiments of the present invention. The semiconductor structure 100 includes: a substrate 110, a first well 112, a second well 114, an isolation structure 116, a field plate 118, a gate structure 120, an opening OP, a drain structure 122, a source structure 124, a field plate 126, an interlayer dielectric layer 140, a drain contact 142, a field plate contact 144, and a source contact 146. The substrate 110 may be a doped (e.g., doped with p-type or n-type dopant) or undoped semiconductor substrate. For example, substrate 110 may include: elemental semiconductors, including silicon or germanium; compound semiconductors, including gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and / or indium antimonide (InSb); alloy semiconductors, including silicon-germanium alloys, gallium arsenide-gallium phosphide alloys, aluminum arsenide-indium phosphide alloys, aluminum arsenide-gallium phosphide alloys, indium arsenide-gallium phosphide alloys, and / or combinations of the foregoing materials.

[0040] In some embodiments, substrate 110 may also be a semiconductor-on-insulator (SGOI) substrate, such as silicon-on-insulator (SOI) or silicon-germanium-on-insulator (SGOI). In other embodiments, substrate 110 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an alumina (Al2O3) substrate (or sapphire substrate), or other similar substrates. In other embodiments, substrate 110 may include a ceramic substrate and a pair of barrier layers respectively disposed on the upper and lower surfaces of the ceramic substrate, wherein the ceramic substrate may contain a ceramic material, and the ceramic material may contain a metallic inorganic material. For example, the ceramic substrate may contain silicon carbide, aluminum nitride, a sapphire substrate, or other suitable materials. The aforementioned sapphire substrate may be alumina.

[0041] A first well 112 is disposed in a substrate 110. The method for forming the first well 112 includes, but is not limited to: forming a patterned mask layer (not shown) on the substrate 110 using photolithography and etching processes. This patterned mask layer exposes the area in the substrate 110 where the first well 112 is to be formed and covers other areas of the substrate 110. Then, a dopant is implanted into the area where the first well 112 is to be formed, and then the patterned mask layer is removed. The aforementioned patterned mask layer can be a hard mask or a photoresist. In embodiments where an N-type first well 112 is to be formed, the aforementioned dopant can be an N-type dopant, such as phosphorus, arsenic, or antimony ions. In embodiments where a P-type first well 112 is to be formed, the aforementioned dopant can be a P-type dopant, such as boron, indium, or BF2. + ion.

[0042] The second well 114 is disposed in the substrate 110 and adjacent to the first well 112. The method for forming the second well 114 is similar to the method for forming the first well 112 described above. In this embodiment of the invention, the second well 114 and the first well 112 have opposite conductivity types. For example, in an embodiment where the first well 112 is N-type, the dopant used to implant the second well 114 is a P-type dopant (e.g., boron, indium, or BF2). + In embodiments where the first well 112 is P-type, the dopant used to implant the second well 114 is an N-type dopant (e.g., phosphorus, arsenic, or antimony ions) to form an N-type second well 114.

[0043] In some embodiments, the first well 112 has a first conductivity type, and the second well 114 has a second conductivity type opposite to the first conductivity type. Alternatively, the first well 106 has a second conductivity type and the second well 108 has a first conductivity type. Specifically, in some embodiments, the first well 106 may be a p-type well, and the second well 108 may be an n-type well, serving as an n-type metal-oxide-semiconductor field-effect transistor (NMOS). In some embodiments, the first well 112 may be an n-type well, and the second well 114 may be a p-type well, serving as a p-type metal-oxide-semiconductor field-effect transistor (PMOS). In some embodiments, the doping concentration of the first well 112 is between approximately 1 × 10⁻⁶. 10 cm -3 Up to 1×10 20 cm -3 The doping concentration of the second well 114 is approximately 1 × 10⁻⁶. 10 cm -3 Up to 1×10 20 cm -3 .

[0044] An isolation structure 116 is disposed on the first well 112. The isolation structure 116 may include shallow trench isolation (STI), localized silicon oxide (LOCOS), or a combination thereof. In some embodiments, the process of forming the shallow trench isolation may include: forming a mask layer (not shown) on the first well 112 and patterning it; using the patterned mask layer as an etching mask to etch trenches in the first well 112; performing a deposition process to fill the trenches with isolation material; performing a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, to remove excess portion of the isolation material; and removing the patterned mask layer. The aforementioned isolation material may include oxides, nitrides, or oxynitrides, such as silicon oxide, carbon-doped silicon oxide (SiO2). x C) Silicon oxynitride (SiON), silicon carbon oxynitride (SiOCN), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon nitride (Si)x N y Alternatively, it may be SiN), silicon-oxycarbide (SiCO), silicon oxide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxy-carbonitride, any other suitable material, or a combination thereof. In some embodiments, the silicon local oxidation process for forming the isolation structure 116 may include: depositing a mask layer (e.g., a silicon nitride layer) on the first well 112, patterning the mask layer using photolithography and etching processes to expose a portion of the first well 112, thermally oxidizing the exposed portion of the first well 112 to form a silicon oxide layer, and removing the patterned mask layer.

[0045] A field plate 118 is disposed on the isolation structure 116. In some embodiments, the field plate 118 has the effect of reducing the surface field (RESURF) and can reduce the electric field strength at and near the impact ionization point of the isolation structure 116. The material of the field plate 118 may include conductive materials, such as metals, metal nitrides, or doped semiconductors. For example, metals may be Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, similar materials, combinations thereof, or the aforementioned multilayer structures; metal nitrides may be MoN, WN, TiN, TaN, or similar materials; and doped semiconductors may be doped polycrystalline silicon or doped polycrystalline germanium. The aforementioned conductive materials can be formed by deposition processes, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (e.g., sputtering or evaporation), and then the conductive materials are patterned to form the field plate 118.

[0046] Reference Figure 1The gate structure 120 spans the first well 112 and the second well 114, and an opening OP is provided between the field plate 118 and the gate structure 120, exposing the edge 116E of the isolation structure 116 near the gate structure 120. In some embodiments, the gate structure 120 may include a gate dielectric layer 120a on the first well 112 and / or the second well 114 and a gate electrode 120b on the gate dielectric layer 120a. In known semiconductor devices, a vertical electric field can cause electron-hole pairs generated by impact ionization points at the edge of the isolation structure to acquire sufficient kinetic energy to overcome the potential barrier and be injected into the components above (e.g., the gate structure), resulting in severe hot carrier injection and reduced device reliability or lifetime. In this embodiment of the invention, the opening OP between the field plate 118 and the gate structure 120 exposes the edge 116E of the isolation structure 116 near the gate structure 120, which can effectively reduce the damage to the semiconductor structure caused by hot carrier injection and improve the reliability of the semiconductor structure.

[0047] In some embodiments, the method of forming the gate structure 120 includes: sequentially depositing a dielectric material layer (for forming the gate dielectric layer 120a) and a conductive material layer thereon (for forming the gate electrode 120b), and then patterning the dielectric material layer and the conductive material layer respectively by photolithography and etching processes to form the gate dielectric layer 120a and the gate electrode 120b spanning the first well 112 and the second well 114. In some embodiments, such as Figure 1 As shown, in the direction from the source structure 124 to the isolation structure 116, the length L of the gate structure 120 is greater than the distance D between the source structure 124 and the first well 112 to ensure that the device can operate normally. If the length L is less than the distance D, the channel may not be able to open. The gate dielectric layer 120a may contain one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In other embodiments, the gate dielectric layer 120a may include metal oxides, metal nitrides, metal silicides, metal aluminates, zirconium silicates, zirconium aluminates, or combinations thereof, but is not limited thereto. For example, spin coating, chemical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, other suitable methods, or combinations thereof can be used to form the gate dielectric layer 120a. The material and formation method of the gate electrode 120b are the same as or similar to those of the field plate 118 described above, and can be formed by the same deposition and photolithography process, or by different processes.

[0048] In embodiments where the gate electrode 120b and the field plate 118 are formed in the same process, a conductive material can be formed by a deposition process, such as chemical vapor deposition, atomic layer deposition, or physical vapor deposition (e.g., sputtering or evaporation). The conductive material is then patterned to form the field plate 118 on the isolation structure 116, the gate electrode 120b spanning the first well 112 and the second well 114, and the opening OP exposing the edge 116E of the isolation structure 116 near the gate electrode 120b. Figure 1 As shown. In some embodiments, the opening OP simultaneously exposes the edge 116E of the isolation structure 116 and part of the first well 112, further reducing the possibility of electrons and holes being injected into the upper gate structure 120 or field plate 118 due to the influence of the electric field, thereby ensuring improved hot carrier effect.

[0049] A drain structure 122 is disposed in a first well 112 and a source structure 124 is disposed in a second well 114. The drain structure 122 includes a doped region having the same conductivity type as the first well 112. The source structure 124 includes adjacent doped regions 124a and 124b having opposite conductivity types. The formation of the doped regions in the drain structure 122 and source structure 124 is similar to the doping method of the first well 112. In some embodiments, the semiconductor device 100 further includes a doped region 134 disposed below the source structure 124, wherein the doping concentration of the doped region 124b is greater than the doping concentration of the doped region 134. In one embodiment, the doping concentration of the source structure 124 and the doped regions 124a and 124b is between approximately 10⁻⁶. 13 cm -3 Up to 10 21 cm -3 The doping concentration of doped region 134 is between 10 12 cm -3 Up to 10 13 cm -3 The doped region 134 can reduce the on-resistance (R). on ).

[0050] Continue to refer to Figure 1An interlayer dielectric layer 140 is located on the substrate 110. The interlayer dielectric layer 140 may comprise one or more single-layer or multi-layer dielectric materials, such as: silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-dielectric-constant dielectric materials, and / or other suitable dielectric materials. Low-dielectric-constant dielectric materials may include (but are not limited to): fluorinated silica glass (FSG), hydrogensilsesquioxane (HSQ), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. For example, spin coating, chemical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, other suitable methods, or combinations thereof can be used to form the interlayer dielectric layer 140.

[0051] like Figure 1 As shown, drain contact 142, field contact 144, and source contact 146 pass through interlayer dielectric layer 140 and are electrically connected to drain structure 122, field plate 118, and source structure 124, respectively. The aforementioned contacts can be formed in the same process, including: performing a patterning process on interlayer dielectric layer 140 to form openings in interlayer dielectric layer 140, then filling the openings with conductive material and performing a planarization process (such as chemical mechanical polishing) or an etchback process to remove excess material outside the openings. The conductive material and formation method of the contacts can be the same as or similar to the conductive material of field plate 118. In some embodiments, the materials of drain contact 142, field contact 144, and source contact 146 can be formed of polysilicon, metal, or other suitable conductive materials. In some embodiments, the materials of the drain contact 142, the field plate contact 144, and the source contact 146 may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), iridium (Ir), rhodium (Rh), copper alloys, aluminum alloys, molybdenum alloys, tungsten alloys, gold alloys, chromium alloys, nickel alloys, platinum alloys, titanium alloys, iridium alloys, rhodium alloys, other suitable conductive materials, or combinations thereof.

[0052] Reference Figure 1A field plate 126 is disposed above a field plate 118 and electrically connected to the field plate 118 and the source structure 124 via a field plate contact 144 and a source contact 146, respectively. The field plate 126 spans the exposed isolation structure 116 and gate structure 120 through the opening OP. Besides reducing the surface electric field, it also reduces the electric field strength below the opening OP (e.g., reducing the electric field strength at and near the impact ionization point of the isolation structure 116 below the opening OP) and below the gate structure 120. This can mitigate or prevent the injection of electron-hole pairs generated by the impact ionization point of the isolation structure 116 into the gate structure 120 or the field plate 118, thereby improving hot carrier injection and enhancing the reliability or lifetime of the device without affecting its breakdown voltage. In some embodiments of the present invention, the source structure 124 can be connected to a ground terminal.

[0053] One objective of this invention is to address the reduced reliability or lifetime of components caused by vertical and lateral electric fields. For example, in addition to hot carrier injection, the vertical electric field causes electron-hole pairs generated at the impact ionization point near the edge 116E of the gate structure 120 of the isolation structure to generate sufficient kinetic energy to overcome the potential energy barrier and be injected into adjacent components (e.g., the source structure), resulting in severe hot carrier injection. This leads to damage or degradation of the source or drain structure, thereby reducing the reliability or lifetime of the component. In this embodiment of the invention, the field plate 126 above the field plate 118 spans the isolation structure 116 and the gate structure 120 exposed by the opening OP, and electrically connects the field plate 118 and the source structure 124, so that the field plate 118, the field plate 126, and the source structure 124 are at the same potential. In addition to reducing the surface electric field, it can also reduce the transverse electric field intensity at the impact ionization point of the isolation structure 116 below the opening OP and its vicinity, as well as the transverse electric field intensity below the gate structure 120. This can slow down or prevent the electron-hole pairs generated by the impact ionization point of the isolation structure 116 from being injected into the source structure 124 by the transverse electric field, thereby improving hot carrier injection and improving the reliability or lifespan of the device without affecting the device breakdown voltage.

[0054] Figure 2 This is a schematic cross-sectional view of a semiconductor device 200 according to some embodiments of the present invention. The semiconductor device 200 and Figure 1Similar to the semiconductor device 100, the difference is that the field plate 118 of the semiconductor device 200 has a first portion 118a and a second portion 118b that are separated from each other. The first portion 118a and the second portion 118b of the field plate 118 are electrically connected to the field plate 126 via field plate contacts 144a and 144b, respectively, and a portion of the isolation structure 116 is exposed between the first portion 118a and the second portion 118b. In some embodiments, the field plate 118 having the first portion 118a and the second portion 118b that are separated from each other can be formed by a patterning process. For simplicity, in Figure 2 Zhongyu Figure 1 Identical components are designated with the same reference numerals and their descriptions are omitted. The materials and forming methods of field plate contacts 144a and 144b are the same as or similar to those of field plate contact 144 described above, and will not be repeated here.

[0055] Semiconductor structure 200, like semiconductor structure 100, includes an opening OP between field plate 118 and gate structure 120, ensuring that neither field plate 118 nor gate structure 120 is directly above the edge 116E of isolation structure 116. This mitigates or prevents the injection of electron-hole pairs generated by the vertical electric field impacting ionization points into the components above, thus improving hot carrier injection. Semiconductor structure 200 also includes a field plate 126 disposed above field plate 118. In addition to reducing the surface electric field, field plate 126 further reduces the electric field strength between isolation structure 116 and source structure 124 (e.g., the electric field strength below opening OP and below gate structure 120), mitigating or preventing the injection of electron-hole pairs generated by impacting ionization points into gate structure 120, field plate 118, or source structure 124, thereby improving hot carrier injection and enhancing device reliability or lifetime.

[0056] In some embodiments, the separated first portion 118a and second portion 118b of the field plate 118 of the semiconductor device 200 can improve the electrical uniformity of the device. For example, depending on the design or requirements of the device, the first portion 118a and second portion 118b of the field plate 118, which are separated from each other, can be provided on the isolation structure 116 to improve the high local electric field and thus improve the electrical uniformity of the device. If the electric field distribution below the isolation structure 116 is uneven, the first portion 118a and second portion 118b of the field plate 118, which are separated from each other, can be provided on the corresponding isolation structure 116 directly above it, which can also improve the high local electric field and thus improve the electrical uniformity of the device. The embodiments of the present invention do not limit the number of the multiple portions of the separated field plate 118. Figure 2The first part 118a and the second part 118b are merely examples. Those skilled in the art can adjust the number or spacing of the separated parts according to the actual situation. If a single field plate still has an excessively high electric field, separated field plates can be used to help improve the local electric field, thereby improving the electrical uniformity of the component and enhancing its reliability.

[0057] Figure 3 This is a schematic cross-sectional view of a semiconductor device 300 according to some embodiments of the present invention. The semiconductor device 300 and Figure 1 Similar to the semiconductor device 100, the difference is that the field plate 128 disposed above the field plate 118 is electrically connected to the field plate 118 and the drain structure 122 via field plate contacts 144 and drain contacts 142, respectively. For simplicity, in Figure 3 Zhongyu Figure 1 Identical parts are labeled with the same designation and their descriptions are omitted.

[0058] Figure 4 This is a schematic cross-sectional view of a semiconductor device 400 according to some embodiments of the present invention. The semiconductor device 400 and Figure 3 Similar to the semiconductor device 300, the difference lies in that the field plate 118 of the semiconductor device 400 has a first portion 118a and a second portion 118b that are separated from each other. The first portion 118a and the second portion 118b of the field plate 118 are electrically connected to the field plate 128 via field plate contacts 144a and 144b, respectively, and a portion of the isolation structure 116 is exposed between the first portion 118a and the second portion 118b. In some embodiments, the field plate 118 having the first portion 118a and the second portion 118b that are separated from each other can be formed by a patterning process. For simplicity, in Figure 4 Zhongyu Figure 3 Identical components are referred to by the same designation and their descriptions are omitted. This invention does not limit the number of separate portions of the field plate 118; those skilled in the art can adjust it according to actual circumstances.

[0059] Figure 5 This is a schematic cross-sectional view of a semiconductor device 500 according to some embodiments of the present invention. The field plate 118 of the semiconductor device 500 has a first portion 118a and a second portion 118b separated from each other, and a partial isolation structure 116 is exposed between the first portion 118a and the second portion 118b. For simplicity, in... Figure 5 Components that are the same as or similar to those in the aforementioned figures are labeled with the same numbers and their descriptions are omitted. For example... Figure 5As shown, the field plate 130 is disposed above the field plate 118 and is electrically connected to the first portion 118a of the field plate 118 and the drain structure 122 of the field plate 118 via field plate contact 144a and drain contact 142, respectively. The field plate 132 is disposed above the field plate 118 and is electrically connected to the second portion 118b of the field plate 118 and the source structure 124 via field plate contact 144b and source contact 146, respectively. In some embodiments, such as Figure 5 As shown, in the direction from the source structure 124 to the isolation structure 116, the length L of the gate structure 120 is greater than the distance D between the source structure 124 and the first well 112 to ensure that the device can operate normally. If the length L is less than the distance D, the channel may not be able to open and the device will not be able to operate.

[0060] In such Figure 5 In some embodiments shown, the field plate 130 spans the region between the drain structure 122 and the isolation structure 116, reducing the electric field between the drain structure 122 and the isolation structure 116. This mitigates or prevents the injection of electron-hole pairs generated by the impact ionization points of the isolation structure 116 into the drain structure 122, thus improving hot carrier injection. The field plate 132 spans the isolation structure 116 exposed by the opening OP and the gate structure 120, reducing the electric field strength below the opening OP (e.g., reducing the electric field strength at and near the impact ionization points of the isolation structure 116 below the opening OP) and below the gate structure 120. This mitigates or prevents the injection of electron-hole pairs generated by the impact ionization points of the isolation structure 116 into the gate structure 120, the field plate 118, or the source structure 124, thus improving hot carrier injection. Furthermore, as previously described, the first portion 118a and the second portion 118b of the field plate 118, which are separated from each other, improve the electrical uniformity of the device. These embodiments can simultaneously mitigate the impact of hot carrier injection on the drain structure 122, gate structure 120, field plate 118, and source structure 124, improving device reliability, lifetime, and overall performance. In some embodiments, the drain structure 122 or source structure 124 may be electrically connected to ground.

[0061] Those skilled in the art to which this invention pertains can adjust the configuration of the field plate 118 according to actual needs, such as... Figure 6 The illustrated embodiment shows a schematic cross-sectional view of a semiconductor device 600, which is related to... Figure 5 Similar to semiconductor device 500, the difference lies in that the field plate 118 of semiconductor device 600 is composed of three separate parts, comprising: a first part 118a, a second part 118b, and a third part 118c, with a partial isolation structure 116 exposed between the three separate parts. For simplicity, in Figure 5Components identical or similar to those in the aforementioned figures are referred to by the same reference numerals and their descriptions are omitted. The field plate 130 of the semiconductor device 600 is electrically connected to the first portion 118a and the drain structure 122 of the field plate 118 via field plate contacts 144a and drain contacts 142, respectively. The field plate 132 is electrically connected to the second portion 118b, the third portion 118c, and the source structure 124 via field plate contacts 144b, 144c, and 146, respectively. In some embodiments, the field plate 118 can be formed by a patterning process to have a first portion 118a, a second portion 118b, and a third portion 118c that are separated from each other. As described above, this embodiment can simultaneously improve the impact of hot carrier injection on the drain structure 122, gate structure 120, field plate 118, and source structure 124, avoiding component damage or deterioration, thereby improving the overall performance of the device. Furthermore, the spacing or number of the separated portions of the field plate 118 can be adjusted through patterning processes according to the design and functional requirements of the device, providing process flexibility.

[0062] Figure 7 This is a schematic cross-sectional view of a semiconductor device 700 according to some embodiments of the present invention. The semiconductor device 700 and Figure 4 Similar to semiconductor device 400, the difference lies in that the drain structure 122 of semiconductor device 700 includes doped regions 122a and 122b of opposite conductivity types, and semiconductor device 700 further includes doped regions 136 and 138. For simplicity, in Figure 7 Zhongyu Figure 4 Identical components are referred to by the same designations and their descriptions are omitted. In semiconductor device 700, doped region 136 is located below isolation region 116, and doped region 138 is located below doped region 136 and forms a junction with it. Doped regions 136 and 138 have opposite conductivity types. In some embodiments, doped regions 136 and 138 are formed using ion implantation. In these embodiments, doped region 136 or doped region 138 includes at least two sub-implant regions with different implantation concentrations. In some embodiments, the sub-implant region with a higher implantation concentration is adjacent to the junction, and the sub-implant region with a lower implantation concentration is away from the junction. In this embodiment, in addition to improving hot carrier implantation, doped regions 136 and 138 of semiconductor device 700 can also be used to reduce the surface electric field of isolation region 116 and homogenize the surface electric field of isolation region 116. Figure 7 The widths of doped regions 136 and 138 are merely examples. For instance, the widths of doped regions 136 and 138 may differ from the bottom width of isolation region 112, or in another example, the width of doped region 136 may differ from the width of doped region 138.

[0063] Figure 8 This is a schematic cross-sectional view of a semiconductor device 800 according to some embodiments of the present invention. The semiconductor device 800 and Figure 3 Similar to the semiconductor device 300, the difference lies in that the drain structure 122 of the semiconductor device 800 includes doped regions 122a and 122b that are separated from each other and have opposite conductivity types. Doped regions 122a and 122b are electrically connected to the field plate 128 via drain contacts 142a and 142b, respectively. The materials and forming methods of the drain contacts 142a and 142b are the same as or similar to those of the drain contact 142 described above, and will not be repeated here. For simplicity, in... Figure 8 Zhongyu Figure 3 Identical components are referred to by the same reference numerals and their descriptions are omitted. In these embodiments, in addition to improving hot carrier injection, the separation of doped regions 122a and 122b in the semiconductor device 800 allows for a larger entry point into the drain contact 142b via doped region 122b, thereby increasing the voltage difference between doped region 122b and the first well 112, enabling the semiconductor device 800 to be triggered more quickly. Furthermore, the trigger voltage of the semiconductor device 800 can be adjusted by changing the distance between doped regions 122a and 122b. In other embodiments, the semiconductor device 800 may also include an optional doped region located between isolation region 116 and doped region 122b, and not connected to drain contact 142a or 142b; this optional doped region can improve the breakdown voltage of the semiconductor device 800.

[0064] The semiconductor device provided in this invention has an opening exposing a portion of the isolation structure between the field plate on the isolation structure and the gate structure. This can mitigate or prevent electron-hole pairs generated by the electric field impacting the ionization points of the isolation structure from being injected into the upper gate structure or field plate, thereby improving hot carrier injection and enhancing device reliability or lifetime without affecting the device breakdown voltage. In some embodiments, the field plate on the isolation structure comprises multiple separated portions, which can improve the electrical uniformity of the device. Furthermore, by providing an additional field plate electrically connected to at least one of the source or drain structures and the field plate on the isolation structure, this invention further reduces the electric field below the opening, below the gate structure, between the isolation structure and the source structure, or between the isolation structure and the drain structure. This further mitigates or prevents electron-hole pairs generated by the electric field impacting the ionization points of the isolation structure from being injected into adjacent components, thereby improving hot carrier injection and preventing component damage or degradation.

[0065] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the various aspects of the invention. Those skilled in the art will understand that they can readily utilize this invention as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and replacements can be made therein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, characterized in that, include: A substrate; A first well and a second well are disposed in the substrate and are adjacent to each other; An isolation structure is provided on the first well; A first field plate is disposed on the isolation structure, and the first field plate has a first part, a second part, and a third part that are separated from each other, and a portion of the isolation structure is exposed between the first part, the second part, and the third part; A gate structure spans the first well and the second well, and an opening is provided between the first field plate and the gate structure, the opening exposing an edge of the isolation structure near the gate structure; A drain structure is disposed in the first well, the drain structure including a first doped region and a second doped region adjacent to each other and having opposite conductivity types, and the first doped region and the second doped region are separated by the first well; and A source structure is disposed in the second well and electrically connected to the first field plate; and A second field plate and a third field plate are disposed above the first field plate, and the second field plate is electrically connected to the drain structure and the first part of the first field plate, and the third field plate is electrically connected to the source structure and the second and third parts of the first field plate.

2. The semiconductor device according to claim 1, characterized in that, The second field plate spans at least a portion of the isolation structure and the gate structure exposed by the opening.

3. The semiconductor device according to claim 1, characterized in that, The source structure or the drain structure is electrically connected to a ground terminal.

4. The semiconductor device according to claim 1, characterized in that, The third field plate spans at least a portion of the isolation structure and the gate structure exposed by the opening.

5. The semiconductor device according to claim 1, characterized in that, The drain structure is electrically connected to a ground terminal and the source structure is electrically connected to another ground terminal.

6. The semiconductor device according to claim 1, characterized in that, The opening exposes part of the first well.

7. The semiconductor device according to claim 1, characterized in that, The source structure includes a first doped region and a second doped region that are adjacent to each other and have opposite conductivity types.

8. The semiconductor device according to claim 7, characterized in that, It further includes a third doped region disposed below the source structure, wherein the doping concentration of the second doped region is greater than the doping concentration of the third doped region.

9. The semiconductor device according to claim 1, characterized in that, It further includes a third doped region disposed below the isolation structure, and a fourth doped region disposed below the third doped region and forming a junction with the third doped region, wherein the third doped region and the fourth doped region have opposite conductivity types.

10. The semiconductor device according to claim 1, characterized in that, Including: An interlayer dielectric layer is disposed on the substrate; A drain contact, passing through the interlayer dielectric layer and electrically connected to the drain structure; and A source contact passes through the interlayer dielectric layer and is electrically connected to the source structure.

11. The semiconductor device according to claim 1, characterized in that, In one direction from the source structure to the isolation structure, the length of the gate structure is greater than the distance between the source structure and the first well.

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