Method and apparatus for facilitating pipelined read-modify-write support in a cache

Abstract

Methods, apparatus, systems, and articles of manufacture are described for facilitating fully pipelined read-modify-write support in level one data caches using storage queues and data forwarding. An example apparatus includes a first storage region (214), a second storage region (218), a storage queue (212, 216) coupled to the first storage region (214) and the second storage region (218), the storage queue (212, 216) usable to receive a first memory operation specifying a first set of data, process the first memory operation to store the first set of data in at least one of the first storage region (214) and the second storage region (218), receive a second memory operation, and feed back the first set of data for the second memory operation prior to storing the first set of data in the at least one of the first storage region (214) and the second storage region (218).

Description

TECHNICAL FIELD

[0001] This specification generally relates to computer architecture, and more specifically, to methods and apparatuses for facilitating fully pipelined read-modify-write support in level one data caches using storage queues and data forwarding. BACKGROUND

[0002] Computing systems include one or more processing cores for executing instructions by accessing data stored in memory. However, the time it takes for a processing core to access data from memory can be very long. Therefore, most computing systems include a cache that stores an amount of data from memory (e.g., typically less than the total amount of data in memory) that is highly likely to be accessed by a processing core in the future. Thus, when a processing core calls for data, the cache can provide the data to the processing core faster than the processing core retrieving the data from memory, thereby improving the speed and efficiency of the computing system. BRIEF DESCRIPTION OF DRAWINGS

[0003] Figure 1 is an example computing system described in connection with the examples described herein.

[0004] Figure 2 is Figure 1 a block diagram of an example level one cache of the example computing system of

[0005] Figures 3A-3D shows Figure 1 an example circuit implementation of a level one cache of the example computing system of

[0006] Figure 4A is Figures 3A-3D an example circuit implementation of a primary cache storage queue of

[0007] Figure 4B is an example circuit implementation of example data forwarding logic implemented in connection with Figures 3A-4A a primary cache storage queue of

[0008] Figure 4C is an additional example circuit implementation of a primary cache storage queue and / or victim cache storage queue.

[0009] Figure 4D is Figure 4A an example hardware implementation of merged circuitry of

[0010] Figure 5 shows Figures 3A-3D an example victim cache-based section of a level one cache of

[0011] Figure 6 shows an example circuit implementation for implementingFigures 3A-3D and 5.

[0012] Figure 7A An example encapsulated data cache system including a victim cache storage queue and a victim storage area is shown.

[0013] Figure 7B Another example encapsulated data cache system including a primary cache storage queue and a primary storage area is shown.

[0014] Figure 7C An example victim cache bank structure is shown.

[0015] Figure 7D An example primary cache bank structure is shown.

[0016] Figure 7E An example unified cache bank structure is shown.

[0017] Figure 8A A schematic illustration of an example implementation of a victim cache tag random access memory is shown.

[0018] Figure 8B Another schematic illustration of an example implementation of a victim cache tag random access memory of Figure 8A is shown.

[0019] Figures 9A-9B An example instruction service workflow is shown.

[0020] Figures 10A-1 and 10A-2 An example data cache system is shown.

[0021] Figures 10B-1 and 10B-2 A second example data cache system is shown.

[0022] Figure 11A An example circuit implementation of a victim cache storage queue of Figures 3A-3D is shown.

[0023] Figures 11B-1 and 11B-2 An example circuit implementation of an example unified cache storage queue is shown.

[0024] Figures 12-33 is a flowchart representing a stream of machine-readable instructions that can be executed to implement a level one cache of Figures 1-3D .

[0025] Figure 34is structured to execute instructions of Figures 3A-3D Figures 1-3D a block diagram of an instance processing platform of a level one cache. DETAILED DESCRIPTION

[0026] The drawings are not to scale. Instead, the dimensions of the layers or regions shown in the drawings can be exaggerated relative to other layers or regions to illustrate aspects of a particular design. Throughout the drawings and the accompanying written description, like reference numerals will be used to refer to like or similar elements. As used in this patent, a statement that any portion (e.g., layer, film, region, area, or plate) is on (e.g., positioned on, located on, disposed on, or formed on) another portion indicates that the portion being referenced is either in contact with the other portion, or that the portion being referenced is above the other portion with one or more intervening portions therebetween. Unless indicated otherwise, connection references (e.g., attached, coupled, connected, and joined) should be construed broadly and can include intermediate parts and relative movement between elements. Thus, connection references do not necessarily infer that two elements are directly connected and in fixed relation to one another. A statement that any portion is “in contact” with another portion means that there are no intervening portions between the two portions. Although layers and regions are shown in the drawings with clear lines and boundaries, some or all of these lines and / or boundaries can be idealized. In practice, the boundaries and / or lines can be unobservable, blended, and / or irregular.

[0027] The term “coupled” is used in various forms throughout the present specification. These terms can encompass a connection, communication, or signal pathway that achieves a functional relationship consistent with the description of the present specification. For example, if device A generates a signal to control device B to perform an action, in a first example device A is coupled to device B by a direct connection, or in a second example device A is coupled to device B through intermediate component C if the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A through the control signal generated by device A.

[0028] The term “configured to” describes a structural and functional characteristic of one or more tangible non-transitory components consistent with the present specification. For example, a device “configured to” perform a function means that the device has a particular configuration designed or dedicated to perform the particular function. If a device includes a tangible non-transitory component that can be enabled, activated, or powered to perform a particular function, such a device is “configured to” perform the particular function. While the term “configured to” can encompass being configurable, this term is not limited to such a narrow definition. Thus, when used to describe a device, the term “configured to” does not require that the device be configurable at any given point in time.

[0029] ​Moreover, the term“example” is used herein to mean serving as an instance, an illustration, etc., and not necessarily as a favorable or advantageous example. Also, although the description has been shown and described with respect to one or more implementations, equivalent alterations and modifications will become apparent to others skilled in the art based upon the description and the appended claims. All such modifications and alterations are intended to fall within the scope of the description, and are intended to be covered by the appended claims insofar as is not otherwise permitted by the prior art. In particular regard to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond, unless otherwise indicated or unless it is clear from the context, to any component which performs the described functionality of that component (e.g., a functional equivalent), whether or not the other components are equivalent in structure or function. In addition, while a particular feature can have been described above with respect to only one or more of several implementations, such feature can be combined with one or more other features of the other implementations as can be desired and advantageous for any given or particular application. In addition, the description above can refer to acts performed by a server, content provider, and / or the like. Such acts can be performed by one or more computing devices specifically configured and / or programmed to perform the described acts, and / or by one or more computing devices operating in conjunction with one or more other computing devices to perform the described acts. In addition, the description above can refer to acts performed by a user. Such acts can be performed by a user specifically configured and / or programmed to perform the described acts, and / or by a user operating in conjunction with one or more other computing devices to perform the described acts.

[0030] While the specification contains many specifics, these should not be construed as limiting the scope of the application but as merely providing illustrations of features specific to particular embodiments. Some features described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented in a plurality of embodiments separately or in any suitable sub-combination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claimed combination can be directed to a sub-combination or a sub-combination variant.

[0031] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such order nor that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing can be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments.

[0032] When identifying multiple elements or components that can be individually referenced, the descriptor“first,”“second,”“third,” etc. is used herein. Unless otherwise indicated or understood from the context of their usage, such descriptors do not impart any meaning of priority, physical order or arrangement in a list, or temporal ordering, but are merely used as labels for referring to the multiple elements or components, respectively, for ease of understanding the described examples. In some examples, the descriptor“first” can be used to refer to an element in the detailed description, while the same element can be referred to with a different descriptor in the claims, such as“second” or“third.” In such cases, the use of such descriptors is merely for ease of referring to the multiple elements or components.

[0033] A central processing unit (CPU) is electronic circuitry that executes instructions that make up a program or workload. The CPU can include one or more processor cores for executing instructions by accessing data from a main memory (e.g., an expanded memory). Because accessing data from the main memory takes time, the one or more processor cores can obtain data from the memory and store it locally in a local memory (e.g., a data cache). The local memory is smaller and faster than the main memory. In this way, the processor core can use and / or manipulate data locally instead of interfacing with the main memory. Because the latency of reading and / or correcting data (e.g., the amount of time needed to read data from memory and / or write data to memory) is smaller when accessing a cache, storing data from an expanded memory in a cache increases the speed and efficiency of the computing system.

[0034] Some local memory devices (e.g., caches) include one or more victim caches. A victim cache is an additional storage area included in or connected to a cache. A victim cache improves (e.g., reduces) cache miss rates, specifically, reduces conflict misses, by storing recently evicted data from the corresponding cache. The addition of a victim cache can have a similar impact on cache performance. The benefits are most apparent in the case of adding a victim cache to a direct-mapped cache, as direct-mapped caches have a relatively high conflict miss rate.

[0035] Some examples described herein include improved data cache and victim cache architectures that reduce overall cache latency. In some alternative cache designs, a victim cache is located at the end of a cache controller. When a line is evicted out of the cache controller (e.g., removed to make room for additional data) rather than removing the data line and sending the evicted data line all the way to the next level cache (e.g., L2) for storage, the victim cache holds the evicted data line (e.g., victim data) until it is justified to evict it due to capacity or other reasons. In such a system, when a subsequent miss occurs in the corresponding cache (e.g., Ll cache), the victim cache can service the miss and return the line to the corresponding cache, and thus to the requesting processor core, thereby reducing read miss latency. However, because some example systems include a victim cache in series with a main cache, the victim cache must wait for the main cache to determine that the main cache does not have data corresponding to a memory operation (also referred to herein as a memory instruction, memory request, and / or memory transaction (e.g., read operation, instruction, request, and / or transaction, write operation, instruction, request, and / or transaction, read-modify-write operation, instruction, request, and / or transaction, atomic operation, instruction, and / or transaction, histogram operation, instruction, request, and / or transaction, etc.) from a CPU before the victim cache can determine whether the memory address is stored in the victim cache. Examples described herein include cache systems that reduce latency (e.g., increase speed), reduce the number of loops to perform write operations, atomic operations (e.g., manipulating data stored at a location to increase, decrease, exchange with other data, etc.), and / or histogram operations (e.g., determining a total number of each value in a cache line), and / or increase the efficiency of a computing system that includes a cache.

[0036] Figure 1 An example computing system 100 is shown. The example computing system 100 includes an example CPU 102, example processing cores 104a-104n, example expanded memory 106, and example data cache 108. The example data cache 108 includes an example level one (LI) cache 110, an example level two (L2) cache 112, and an example level three (L3) cache 114. Although the example computing system 100 includes an example CPU 102, the example computing system 100 can include any number of CPUs. Also, one or more of the example components in the computing system 100 can be implemented on the same die and / or different dies in the same chip and / or different chips. Figure 1 The example computing system 100 includes N processing cores and three cache levels, but the example computing system 100 can include any number of processing cores and / or cache levels. Also, one or more of the example components in the computing system 100 can be implemented on the same die and / or different dies in the same chip and / or different chips.

[0037] Figure 1The example CPU 102 includes example processing cores 104a-104n. The processing cores 104a-104n can be incorporated in the same die or separate dies (e.g., connected via one or more interfaces). The CPU 102 is connected to an example data cache 108 via one or more interfaces. For example, an example core 104a of the example CPU 102 can be connected to the data cache 108 via a scalar interface (e.g., a 64-bit wide bidirectional and / or unidirectional interface) and / or a vector interface (e.g., a 512-bit wide interface). The use of the scalar interface and the vector interface can be based on interface utilization, data size, and / or other considerations. For example, a scalar read operation can be via a scalar data transfer, while data corresponding to the scalar read can be transferred over the vector interface. Also, either the scalar interface and / or the vector interface can be used in the event that the other interface is busy. In some examples, the CPU 102 can use a different number and / or different types of interfaces to connect to the data cache 108.

[0038] Figure 1 The processing cores 104a-104n of the example CPU 102 access data from the example extended memory 106 and / or the example cache 108 to execute instructions stored in the example extended memory 106 and / or the example data cache 108. The example cores 104a-104n can concurrently execute different processes to speed up execution of tasks (e.g., instructions) of the computing system 100. For example, the cores 104a-104n can execute instructions from a workload of an application by writing data to and / or reading data from the extended memory 106 and / or the data cache 108. Because the data cache 108 includes a copy of some data stored in the example extended memory 106, when one of the example cores 104a needs to access (e.g., read and / or write) data from the extended memory 106, the example core 104a transmits a read and / or write instruction to the example data cache 108. As described further below, if the data cache 108 includes data corresponding to the instruction from the core 104a (e.g., corresponding to a cache hit), the data cache 108 fulfills the request and / or instruction from the processing core 104a. If the data cache 108 does not include data corresponding to the instruction from the core 104a (e.g., corresponding to a cache miss), the data cache 108 interfaces with the example extended memory 106 to execute the transaction from the core 104a.

[0039] Figure 1The instance extended memory 106 is connected to the instance data cache 108 via an interface (e.g., a 1024-bit wide extended memory interface). However, different numbers and / or different types of interfaces can additionally or alternatively be used. The instance extended memory 106 stores all data that the computing system 100 can access. The instance extended memory 106 can be incorporated into the computing system 100 and / or can be memory external to the computing system 100 (e.g., off-chip memory). In some instances, the extended memory 108 interacts with a controller of the highest cache (e.g., instance L3 cache 114), and the highest cache (e.g., L3 cache 114) interacts with the next highest cache (e.g., instance L2 cache 112), and so on. In such instances, the CPU 102 transmits memory operations to the instance LI cache 110, and if the memory operations cannot be serviced by the LI cache 110, the LI cache 110 transmits the memory operations to the L2 cache 112, and so on. In Figure 1 In instances where the L3 cache 114 (e.g., the highest level cache) cannot perform a read or write transaction (e.g., because the memory address is not located in the L3 cache 114’s local storage), the L3 cache 114 interacts with the extended memory 106 to read or write the corresponding data to the memory address. The extended memory 106 can be on-chip or off-chip memory (e.g., DDR), and the interface to the extended memory can be 2 N In some instances, there can be a prefetcher and / or pre- loader mechanism in any of the data caches that can pull data from the instance extended memory 106 before the execution of the problem to be stored locally at the cache before the CPU 102 executes any instructions, the memory 106 provides the instance data cache 108 with a copy of the data stored in memory. The data cache 108 can periodically, aperiodically, and / or based on a trigger, request additional information based on instructions from the CPU 102 and / or instruct the extended memory 106 to adjust the data stored in the extended memory 106.

[0040] Figure 1The instance data cache 108 stores blocks of data from the instance extended memory 106 (e.g., a cached subset of data stored in the extended memory 106) to reduce the time required for the instance CPU 102 to access the cached subset, thereby improving system performance. To achieve optimal performance, the data in the data cache 108 is attempted to correspond to data that the CPU 102 is most likely to use. The data cache 108 provides access to the cached data when requested by the CPU 102 during a cache hit (e.g., when the requested data is stored in the data cache 108). If the CPU 102 requests data that is not contained in the data cache 108 (e.g., a cache miss), the data cache 108 retrieves the corresponding data from the extended memory 106. For example, if the CPU 102 transmits a read operation corresponding to a particular address of the extended memory 106, the data cache 108 determines whether the data corresponding to the particular address of the extended memory 106 is cached in the data cache 108. If the data cache 108 determines that the data is cached, the data cache 108 provides the data to the CPU 102 for reading. If the data cache 108 determines that the data is not cached, the data cache 108 obtains the data from the extended memory 106 and returns the data to the CPU 102. Also, the instance data cache 108 can update the cached data based on a cache miss (e.g., thereby reducing future cache misses). For write transactions from the CPU 102, the instance data cache 108 can temporarily store the corresponding data and then provide the corresponding data to update the older data stored in the extended memory 106.

[0041] The instance data cache 108 includes an instance LI cache 110, an instance L2 cache 112, and an instance L3 cache 114. The hierarchy of caches can be based on speed and / or size. For example, the instance LI cache 110 can be the fastest smallest cache, followed by L2 112 (e.g., slower and larger than LI 110) and L3 114 (e.g., slower and larger than L2 112). The most frequently used data is often stored in LI 110, followed by L2 112 and L3 114. Thus, when the CPU 102 needs an address to write or read, the instruction from the CPU 102 is first sent to the LI cache 110, and if the corresponding data is not stored in the LI cache 110, the instruction is sent to the L2 cache 112. If the corresponding data is not stored in the L2 cache 112, the instruction is sent to the L3 cache 114. If the corresponding data is not stored in the L3 cache 114, the instance data cache 108 accesses the data from the extended memory 106.

[0042] As further described below, Figure 1 The example LI cache 110 includes a primary cache and a victim cache for parallel execution of instructions from the CPU 102. The victim cache stores victim data (e.g., data evicted from the primary cache to make room for new data corresponding to other address locations of the expanded memory 106). In this way, when there is a cache miss at the LI level, the primary LI cache evicts a first set of data (e.g., victim data) to make room for a second set of data corresponding to the transaction that caused the cache miss. The victim cache then stores the first set of data removed from the primary cache to make room for the second set of data in the primary cache.

[0043] Figure 2 is Figure 1 An example block diagram of the LI cache 110 of the example CPU 102. The example LI cache 110 includes an example CPU interface 202, example tag random access memory (RAM) accesses 204, 206, example tag RAM 208, 210, example primary cache storage queue 212, example main storage 214 (also referred to as primary cache storage or primary cache), example victim cache storage queue 216, example victim storage 218 (also referred to as victim cache storage or victim cache), example cache controller 220, example primary cache controller 222, example victim cache controller 224, and example L2 interface 228.

[0044] The example CPU interface 202 connects the CPU 102 (e.g., cores 104a-104n of the CPU 102) to components of the LI cache 110. The CPU interface 202 is connected to the tag RAM accesses 204, 206 and the cache controller 220. The example CPU interface 202 receives instructions from the example cores 104a-104n of the example CPU 102. The instructions can include read instructions, write instructions, read-modify-write instructions, atomic instructions, etc. When the CPU interface 202 obtains an instruction corresponding to a particular data stored at a particular address, the CPU interface 202 interfaces with the cache controller 220 and the primary tag RAM access 204 to determine whether the corresponding data is stored in the main storage 214 and / or the victim storage 218 to perform a transaction. Also, for some types of transactions (e.g., read transactions), the example CPU interface 202 returns the corresponding data to the example CPU 102. Moreover, when the CPU interface 202 obtains an instruction corresponding to data at a particular address, the primary components (e.g., the example primary tag RAM access 204, the example tag RAM 208, the example primary cache storage queue 212, the example main storage 214, and the example primary cache controller 222) and the victim components (e.g., the example tag RAM access 206, the example tag RAM 210, the example victim cache storage queue 216, the example victim storage 218, and the example victim cache controller 224) operate in parallel (e.g., simultaneously) to determine whether the data from the corresponding address is stored in the main storage 214 and / or the victim storage 218.

[0045] Figure 1Example primary tag RAM access 204 is coupled to tag RAM 208 and cache controller 220. Victim tag RAM access 206 is coupled to tag RAM 210 and cache controller 220. Primary tag RAM access 204 accesses tag RAM 208 to determine whether data from a memory address corresponding to an instruction from CPU 102 is present in main storage 214. In parallel with primary tag RAM access 204, example victim tag RAM access 206 accesses tag RAM 210 to determine whether data from a memory address corresponding to an instruction from CPU 102 is present in victim storage 218. In some examples, primary tag RAM access 204 is implemented in tag RAM 208 and victim tag RAM access 206 is implemented in tag RAM 210. When primary tag RAM access 204 and / or victim tag RAM access 206 determine that an address corresponding to an instruction from CPU 102 is present in the respective tag RAM 208, 210, primary tag RAM access 204 and / or victim tag RAM access 206 transmit the results (e.g., determination and / or any corresponding data) to example cache controller 220.

[0046] In some examples, the main storage is direct mapped. Thus, in such examples, a particular CPU memory address can only be stored at a particular location of main storage 214. Thus, for a CPU instruction, example tag RAM 208 can potentially have a fixed memory address. In a direct mapped cache, a given address is stored at a particular location of tag RAM 208.

[0047] Figure 2An example tag RAM 208 is coupled to the instance cache controller 220 and the instance main storage 214. The instance tag RAM 208 stores a table that records entries in the instance main storage 214 that correspond to memory addresses in the extended memory 106. In this way, the instance main tag RAM access 204 can check the table to determine if data corresponding to an instruction from the CPU 102 is available in the main storage 214. An instance tag RAM 210 is coupled to the instance cache controller 220 and the instance victim storage 218. The instance tag RAM 210 stores a table that records entries in the instance victim storage 218. In this way, the instance victim tag RAM access 206 can check the table to determine if data corresponding to an instruction from the CPU 102 is available in the victim storage 218. When data of the main storage 214 is updated, the instance tag RAM 208 can update the table to reflect any changes to the entries. For example, if the main storage 214 removes a first set of data corresponding to a first memory address in the extended memory 106 and replaces it with a second set of data corresponding to a second memory address in the extended memory 106, the instance tag RAM 208 updates the table to reflect that the first set of data for the first memory address is no longer stored in the main storage 214 and that the second set of data for the second memory address is now stored in the main storage 214. Likewise, when data from a first address location of the victim storage 218 becomes data from a second address location, the instance tag RAM 210 can update the table to reflect any changes to the entries.

[0048] The instance victim side tag RAM 210 can be a content addressable memory (CAM). In some examples, the victim storage 218 is fully associative (e.g., any location of the victim storage 218 can be used to store data from any CPU address). Thus, when the instance CPU 102 provides a memory address to the instance LI cache 110, the instance victim tag RAM 210 compares the provided memory address to all entries of the tag RAM 210. If a match between the provided address and an entry stored in the tag RAM 210, the address of the corresponding location in the victim storage 218 is output by the tag RAM 210. The address is used to obtain data corresponding to the CPU instruction from the victim storage 218.

[0049] Figure 2The instance primary cache store queue 212 is coupled to the instance main storage area 214 and the instance cache controller 220. The instance primary cache store queue 212 is used when the CPU 104 issues a store operation (e.g., a write operation, an atomic compare and swap, an atomic operation, etc.). The instance primary cache store queue 212 can implement a read-modify-write function. The read-modify-write function includes storing data in a local storage area that needs to first read an earlier version of the written data already present in the main storage area 214 for reasons including updating error correction code data. In this way, new bits included in a write portion of a read-modify-write transaction from the CPU 102 are buffered in the primary cache store queue 212 while a read operation is being performed to obtain a copy of the older data from the main storage area 214. When the older data is available, only the new bits that the CPU 102 is overwriting are updated in the store queue buffer, and the updated (e.g., merged) data is written back to the main storage area 214. For example, new bits (including corresponding memory addresses) that the CPU 102 is overwriting from a write portion of a read-modify-write transaction (e.g., from the CPU 102) are buffered in the primary cache store queue 212 until old data for the corresponding write (e.g., store) instruction is read from the main storage area 214. When the new bits included in the write portion of the read-modify-write transaction are merged with the old data from the main storage area 214, the updated (e.g., merged) data is written back into the main storage area 214. Additional pipelining for store instructions provided by the primary cache store queue 212 enables instructions from the CPU 104 to continue execution while a previous store instruction is waiting for load data from the main storage area 214 to become available. In some instances, the main storage area 214 includes SRAM, as further described below in connection with sections 5 and 16. The instance primary cache store queue 212 is further described below in connection with sections 5 and 16. Figure 3A , 3B and 4.

[0050] Figure 2An example victim cache store queue 216 is coupled to an example victim store 218 and an example cache controller 220. The example victim cache store queue 216 buffers data to be stored in the example victim store 218. For example, a victim value containing a corresponding memory address and / or store data from a store instruction (e.g., from the cache controller 220) is buffered in the victim cache store queue 216 until a previous or old value for the corresponding store instruction is read from the victim store 218. When the stored byte is merged with the previous / old data from the victim store 218, the value is written back into the victim store 218. Although the victim cache store queue 216 can handle read-modify and / or write operations from the cache controller 220 transmitted in response to a retirement point being satisfied (e.g., when one or more cache lines are evicted from the Ll cache 110 to the L2 cache 112), in other examples described herein, the victim cache store queue 216 can handle read, modify, and / or write operations from the cache controller 220 transmitted directly from the CPU 102. The example victim cache store queue 216 is described further below.

[0051] Figure 2 An example main store 214 is coupled to the example tag RAM 208, the example main cache store queue 212, and the example cache controller 220. The example main store 214 stores data (e.g., entries) corresponding to data at memory address locations in the extended memory 106. The main store 214 stores data that is highly likely to be invoked by the example CPU 102. The stored data can be updated when, for example, the CPU 102 attempts to access (e.g., read, write, etc.) data that is not cached in the example main store 214. The example main store 214 can be or include static RAM (SRAM) and / or any other type of store that provides single-cycle access to stored data.

[0052] Figure 2 An example victim store 218 is coupled to the example tag RAM 210, the example victim cache store queue 216, and the example cache controller 220. The example victim store 218 stores data (e.g., entries) corresponding to memory address locations that have been evicted from the example main store 214 to make room for other address locations that are recently accessed or more likely to be accessed from the CPU 102. The example victim store 218 can be or include a register file, static RAM (SRAM), and / or any other type of store.

[0053] In operation, initially, instance main storage 214 stores data from different addresses in instance extended memory 106 based on likelihood of use. If instance CPU 102 sends instructions corresponding to memory addresses stored in main storage 214, instance cache controller 220 controls the components to perform transactions. For example, cache controller 220 can transmit instructions to main cache storage queue 212 for subsequent processing and storage in main storage 214. If instance CPU 102 sends instructions corresponding to memory addresses not stored in main storage (e.g., stored in victim storage 218), instance main storage 214 can store data at the corresponding memory address after retrieving the data from another storage. Main storage 214 removes some data corresponding to one or more memory address locations to make room for data. The removed data and the corresponding memory address locations are referred to as victims or evictions. The data selected as victims is based on various parameters according to a replacement policy. After removal from main storage 214, the victims are stored in instance victim storage 218. If victim storage 218 is full, victim storage 218 removes data (e.g., second victims) to make room to store victims from main storage 214. After the second victims are removed from victim storage 218, the second victims are transmitted to L2 cache 112 for storage.

[0054] Although Figure 1The example LI cache 110 includes one primary cache storage queue 212 with a corresponding primary storage area 214 and one example victim cache storage queue 216 with a corresponding victim storage area 218, although the example primary cache storage queue 212 and / or the example victim cache storage queue 216 can include multiple storage queues corresponding to multiple storage areas. For example, the primary storage area 214 and / or the victim storage area 218 can be divided into multiple independently addressable groups (e.g., any number of storage devices with any number of line widths, rows, etc.), where each group can have its own corresponding storage queue. For example, a primary storage area 214 consisting of 256 rows (each row having a line width of 1024 bits) can be divided into 16 primary storage groups (e.g., groups) of 64 bits per row in a particular group, where each group can have their own primary storage queue. In this example, if the vector data of a read and / or write request that hits the LI cache 110 is 512 bits wide, the cache controller 220 can process the request as 8 parallel writes and / or reads to the 8 groups. In such a multi-group setup, read and / or write operations can be sent in parallel to the groups, and the groups arbitrate their own processes in response to the read and / or write operations. By operating independently, the multi-group approach is more efficient than a single primary storage area (e.g., because the entire full cache line is not locked when a request is received, and only the portion of the cache line assigned to the group that received such a request is locked), but can be more complex and / or have more parts.

[0055] Figure 2An example cache controller 220 is coupled to the L1 components to control how data is read and / or written in the instance storage 214, 216 and / or how data is updated in the instance storage 214, 218. For example, when a read request, write request, atomic request, read-modify-write request, and / or the like is received at the instance CPU interface 202, the cache controller 220 obtains the request and instructs the other components accordingly. For example, during a read request for data at a particular location of the extended memory 106, the instance cache controller 220 instructs the primary tag RAM access 204 to access the tag RAM 208 to determine whether the main storage 214 is storing data from the read request that corresponds to the location of the extended memory 106. If the primary tag RAM access 204 determines that the entry is in the main storage 214 (e.g., a cache hit), the cache controller 220 determines the location of the particular entry based on the data in the tag RAM 208 and interfaces with the primary cache storage queue 212 to read the value from the instance main storage 214 and return the value to the CPU 102 via the CPU interface 202. The instance cache controller 220 includes a primary cache controller 222 to control the primary cache components (e.g., the instance primary tag RAM access 204, the instance tag RAM 208, the instance primary cache storage queue 212, and the instance main storage 214) and an instance victim cache controller 224 to control the victim cache components (e.g., the instance victim tag RAM access 206, the instance tag RAM 210, the instance victim cache storage queue 216, and the instance victim storage 218) in parallel with the primary cache controller 222 controlling the primary cache components. In some instances, the cache controllers 222, 224 can be separate controllers and / or operate in combination in a single controller.

[0056] Figure 2The instance cache controller 220 interfaces with the instance L2 interface 228 to obtain data to be stored in the instance main memory 214 (e.g., initially, after a cache miss, etc.). Furthermore, when new data is written (e.g., when old data is overwritten), the instance cache controller 220 can transmit updates to the data in the main memory 214 and / or the victim memory 218 to the L2 cache 112, such that read instructions from the CPU 102 are propagated to the L2 cache 112 via the L2 interface 228. The instance cache controller 220 interfaces with the instance L2 interface 228 to transfer and / or receive data from the L2 cache 112 and / or the L3 cache 114 (e.g., directly or via the L2 cache 112). For example, when main memory 214 and victim memory 218 do not contain memory address locations corresponding to data from instructions from CPU 102 (e.g., corresponding to cache misses), instance cache controller 220 transmits instructions to instance L2 cache 112 via L2 interface 228. If the data is stored in L2 cache 112 or L3 cache 114, cache controller 220 can receive the corresponding data from L2 cache 112 via L2 interface 228. In this example, cache controller 220 can store the corresponding information from L2 cache 112 in main memory 214. In some instances, when victim memory 218 needs to remove data from a specific location (e.g., old victims) to make room for new victims from main memory 214, instance cache controller 220 can transfer old victims to L2 cache 112 via L2 interface 228 for storage in the L2 cache.

[0057] Figures 3A-3D Show Figure 1 An example circuit implementation scheme for the L1 cache 110 of the example computing system 100. Figures 3A-3D The example implementation includes Figure 2 The instance CPU interface 202, instance tag RAM 208, 210, instance main cache storage queue 212, instance main storage area 214, instance victim cache storage queue 216, instance victim storage area 218 and instance cache controller 220. Figures 3A-3D The instance implementation further includes instance modification, exclusive, shared, invalid (MESI) RAM 300, instance address processing components 302a-c, instance group processing logic 303, instance hit / miss comparison logic 304, 306, instance replacement strategy component 308, instance flush engine 309, instance error correction code (ECC) logic 310, 312, instance data multiplexer (MUX) circuitry 314, 316, instance MUX 318, 320, and instance latch 322.

[0058] exist Figures 3A-3D In one example implementation, the instance CPU interface 202 includes two interfaces (e.g., a scalar interface and a vector, each interface having two parts, one for inputting data from the CPU 102 and the other for outputting data to the CPU 102). Figures 3A-3D The input CPU interface 202 includes a flexible buffer for buffering incoming data from the CPU 102, a multiplexer for selecting between buffered data from the flexible buffer when there are pending CPU instructions in the flexible buffer and instructions directly from the CPU 102 when the flexible buffer queue is empty, and divides the incoming instructions into corresponding addresses, operations (e.g., read, write, etc.) and write data (e.g., if the instruction corresponds to a write operation). Figures 3A-3D The output CPU interface 202 transmits data back to CPU 102.

[0059] Figures 3A-3D The instance primary cache queue 212 contains blocks corresponding to the primary cache queue 212. For example, the primary cache queue 212 contains blocks that perform read-modify-write operations, write merging, write data forwarding, write operations, complete checksum block writes, weighted histogram operations, load and increment operations, and compare and swap operations. The instance primary cache queue 212 is described below in conjunction with... Figure 4A Further description. The instance's main cache storage queue 212 operates in conjunction with the instance's main memory area 214. Figures 3A-3D In this example, main memory area 214 is data RAM (DRAM).

[0060] Figures 3A-3D The instance victim cache queue 216 contains blocks corresponding to operations performed on the victim cache queue 216. For example, the victim cache queue 216 contains blocks implementing read-modify-write operations, write merges, write data forwarding, write operations, full checksum block writes, load and increment operations, and compare and swap operations. The instance victim cache queue 216 is described below in conjunction with... Figure 5 Further description. The instance victim cache storage queue 216 operates in conjunction with the instance victim storage area 218. In Figures 3A-3D In this example, main memory area 214 is the register file.

[0061] Figures 3A-3DThe example MESI RAM 300 is connected to the command lines of the example CPU interface 202 and the example DRAM 214. The example MESI RAM 300 tracks the state of data in the example main memory region 214 based on commands from the CPU 102. For example, the MESI RAM 300 tracks the state of a cache line by marking the cache line as modified, exclusive, shared, or invalid. Modified or invalid correspond to cases where the cache line contains data that is not stored in any other similarly- tiered cache and the data has been modified from the value in main memory (e.g., so that a read of the data in the extended memory 106 is marked or permitted because it is not up-to-date or valid). Exclusive is the case where the cache line contains data that is not stored in any other similarly-tiered cache and the data is clean (e.g., matches the data in the extended memory 106). Shared indicates that the cache line contains data that can be stored in other caches and is clean (e.g., the line can be evicted because it exists in another cache). Invalid indicates that the cache line is invalid or unused. The MESI RAM 300 can be invoked when the main memory region 214 and / or the extended memory 106 is updated. The example MESI RAM 300 of the victim cache is implemented in conjunction with the example tag RAM 210.

[0062] Figures 3A-3D The example MESI RAM 300 adds coherency to the system by tracking, tagging, marking, etc. The state of a memory address can prevent a data write from occurring at a particular time so that data mismatches do not occur in different tiers of caches. The state tracked by the MESI RAM 300 can be communicated in the case of a cache miss so that higher-tier caches understand what the data at the memory address will be used for. For example, if the LI cache issues a cache miss for a read operation, the cache miss contains a shared state so that the higher-tier caches know that the data will be read but not manipulated. If the LI cache 110 issues a cache miss for a write operation, the cache miss contains an exclusive state so that the higher-tier caches know that the data will be modified. The state from the example MESI RAM 300 can be used to figure out how to evict when the example main memory region 214 and / or the victim memory region 218 evicts a victim. For example, if the data is shared, the main memory region 214 and / or the victim memory region 218 can simply evict (e.g., because the data at the memory address is already in a higher cache). If the data is exclusive or modified, the cache controller 220 instructs the interface 228 to transfer the victim to a higher-tier cache (e.g., because the data at the memory address is not in a higher-tier cache or is in a higher-tier cache but is stale).

[0063] Figures 3A-3D The example address processing components 302a-c are connected to the CPU interface 202, the instance main storage area 214, the instance main cache storage queue 212 (e.g., via MUX 318), the instance victim storage area 218 (e.g., via instance MUX 320), and each other. The instance address processing components 302a-c include an instance first address processing component 302a, a second address processing component 302b, and a third address processing component 302c. The first address processing component 302a performs address translation, the second address processing component 302b performs data rotation, and the third address processing component 302c facilitates group organization. Alternatively, one or more of the first address processing component 302a, the second address processing component 302b, and the third address processing component 302c can be included in the same hardware, logic circuit, integrated chip, etc. The instance address processing components 302a-c organize data to be written into the instance main storage area 214 and the victim storage area 218 according to a particular storage protocol, ensuring that data is stored correctly. For example, in a multi-group instance (e.g., where the main cache storage queue 212, the main storage area 214, the victim cache storage queue 216, and the victim storage area 218 are divided into multiple groups), the address processing components 302a-c can use a memory address from a CPU operation to determine which group of the main cache storage queue 212, the main storage area 214, the victim cache storage queue 216, and the victim storage area 218 to divide into multiple groups needed for a given CPU operation.

[0064] The instance group processing logic 303 is coupled to the CPU interface 202, the instance main storage area 214, the instance main cache storage queue 212 (e.g., via MUX 318), and the instance victim storage area 218 (e.g., via instance MUX 320). In operation, the group processing logic 303 is configured to analyze read, modify, and / or write instructions from the CPU interface 202. In this way, the group processing logic 303 is configured to determine the nature of the read, modify, and / or write instructions to facilitate efficient partial group read, modify, and / or write instructions. In the examples described herein, the group processing logic 303 detects whether an incoming write instruction is indicative of a write of an entire group or a write of a partial group. In this way, the group processing logic 303 can indicate whether to operate a read-modify-write operation when a negative transmission read instruction. Example descriptions of the operation of the group processing logic 303 are described below.

[0065] Figures 3A-3DInstance hit / miss comparison logic 304 is connected to input CPU interface 202, tag RAM 208, main memory 214, main cache storage queue 212, cache controller 220, and / or instance MUX circuit 314 (e.g., via data forwarding latches). Hit / miss comparison logic 304 obtains the address from tag RAM 208 and the address of the instruction from CPU 102 and compares the two (e.g., using exclusive-NOR (XNOR) logic) to determine whether the address from the instruction is a hit or miss (e.g., whether the data corresponding to the address is stored in instance DRAM 214). Instance hit-miss comparison logic 304 includes tag comparison logic to output the comparison result to instance main cache storage queue 212, instance cache controller 220, and / or instance MUX circuit 314.

[0066] Figures 3A-3D Instance hit / miss comparison logic 306 is connected to input CPU interface 202, tag RAM 210, victim cache storage queue 216, and / or instance replacement policy component 308. Hit / miss comparison logic 306 obtains the victim cache entry number (e.g., location) from tag RAM 210 and the address of the instruction from CPU interface 202 and compares the two to determine whether the access (e.g., the instruction from CPU interface 202) is a hit or miss (e.g., whether the data corresponding to the address is stored in instance victim storage 218). Instance hit-miss comparison logic 306 outputs the result to replacement policy component 308, address encoder 326, multiplexer 330, and / or victim cache storage queue 216.

[0067] Figures 3A-3D Address encoder 326 is connected to tag RAM 210 (via hit / miss comparison logic 306) and multiplexer 330. Address encoder 326 encodes the address of tag RAM 210 into a form that can be interpreted by victim storage 218. For example, tag RAM 210 can store a 16-bit memory address, while victim storage 218 stores a 4-bit memory address corresponding to the 16-bit memory address. Thus, address encoder 326 can transform the 16-bit memory address into a 4-bit memory address to locate and / or access the corresponding memory address in victim storage 218. Additionally and / or alternatively, address encoder 326 encodes the memory address into any bit value. Address encoder 326 is coupled to instance multiplexer 330 such that address encoder 326 provides the encoded address to multiplexer 330.

[0068] Figures 3A-3DThe example replacement policy component 308 is connected to the hit-miss comparison logic 306 and the replacement address encoder 328. In some examples, the replacement policy component 308 is connected to the tag RAM 210. The example replacement policy component 308 controls the replacement policy for data stored in the example victim storage area 218 (e.g., the data is moved out of the victim cache if a new victim is to be stored in the victim storage area 218). In some examples, the example home storage area 214 can have a replacement policy component. However, a replacement policy does not require a direct-mapped cache (e.g., if the example home storage area 214 is direct-mapped because a particular address will only be present in one location). The example eviction engine (e.g., eviction engine component) 309 is coupled to the replacement policy 308. In some examples, the eviction engine 309 is used and / or otherwise invoked at a predefined period to evict a write miss stored inside the victim storage area 218.

[0069] Figures 3A-3D The replacement address encoder 328 is coupled to the multiplexer 330 such that the replacement address encoder 328 provides an encoded replacement address to the multiplexer 330. The replacement address encoder 328 encodes an address selected by the replacement policy component 308. For example, the replacement policy component 308 outputs a 16-bit replacement memory address to the replacement address encoder 328 and the replacement address encoder 328 transforms the 16-bit replacement memory address to a 4-bit replacement memory address. Additionally and / or alternatively, the replacement address encoder 328 encodes the replacement memory address to any bit value.

[0070] Figures 3A-3D The multiplexer 330 is connected to the hit / miss comparison logic 306, the address encoder 326, the replacement address encoder 328, and the address read 332. The multiplexer 330 selects an encoded address based on the result of the hit / miss comparison logic 306 (e.g., based on whether the access was a hit or a miss). The multiplexer 330 provides the selected memory address to the address read 332 to read into the victim storage area 218. For example, the multiplexer 330 outputs a location of the victim storage area 218 from which a CPU instruction can be used to read data or store data in the case of a write instruction.

[0071] Figures 3A-3DInstance error correction code (ECC) logic 310 is connected to instance main memory 214 via latch 322, and multiplexing circuit 314. If instance LI cache 110 supports ECC memory, instance main memory 214 stores data in blocks and a set of ECC syndrome bits corresponding to the blocks. When a read operation is received, instance main memory 214 can provide the stored block of data and corresponding ECC syndrome bits to ECC logic 310. Instance ECC logic 310 can regenerate the ECC syndrome bits based on the block of data read from main memory 214 and compare the regenerated ECC syndrome bits to the previously stored bits. Instance ECC logic 310 can determine that the block of data was read in error if there is a discrepancy, and can correct the error in the block of data.

[0072] Figures 3A-3D Instance error correction code (ECC) logic 312 is connected to instance victim memory 218 via latch 324, and MUX circuit 316. Instance ECC logic 312 performs ECC correction logic in a similar manner as instance ECC logic 310. However, instance ECC logic 312 performs ECC syndrome bit comparison with respect to instance victim memory 218.

[0073] Figures 3A-3D Instance primary data MUX circuit 314 is connected to primary cache memory queue 212, ECC logic 310, output of hit / miss comparison logic 304 (e.g., via latch), instance output CPU interface 202 (e.g., via instance latch 322), instance victim data MUX 316, and instance cache controller 220. Instance primary data MUX circuit 314 has the inverse operation of instance address processing components 302a-c to convert data in a data address for transmission to instance CPU 102. The MUXs within instance MUX circuit 314 are controlled by cache controller 220 via respective select inputs.

[0074] Figure 3A Instance victim data MUX circuit 316 is connected to victim cache memory queue 216, ECC logic 312, instance primary data MUX circuit 314, L2 cache 112 (e.g., via latch), and instance cache controller 220. Instance primary data MUX circuit 314 has the inverse operation of instance address processing components 302a-c to convert data in a data address for transmission to instance CPU 102. The MUXs within instance MUX circuit 316 are controlled by cache controller 220 via respective select inputs.

[0075] Write miss cache in L1 data cacheInstance MUX 318 is connected to L2 cache 112, to instance CPU interface 202 via a latch, and to address processing components 302a-c, main cache storage queue 212, main storage area 214, and cache controller 220. Instance cache controller 220 controls MUX 318 to control all ways in which data can be written into or read from instance main storage area 214 (e.g., via direct memory access (DMA), snoop transactions (e.g., when L2 cache 112 wants data from Ll cache 110), main cache storage queue 212, read hit buffer, etc.). Instance MUX 320 is connected to instance main storage area 214 (e.g., via an eviction line for storage of victims), address processing components 302a-c (e.g., via write stream and / or CPU load), instance L2 cache 112 (e.g., via L2W and / or snoop lines), victim storage area 218, and / or cache controller 220. Instance cache controller 220 controls MUX 320 to control all ways in which data can be written into or read from instance victim storage area 218 (e.g., via direct memory access (DMA), snoop transactions, victim cache storage queue 216, eviction from instance main storage area 214, via L2 cache 112, etc.). Instance MUXs 318, 320 are controlled by instance cache controller 220 via respective select inputs.

[0076] Figures 3A-3D and 3B The elements of FIG. 1 are arranged in a manner that represents a flow of transaction processing. The temporal elements are represented by stages El- E5. Each stage represents a discrete period of time, and in some instances, each stage represents one clock cycle or an integer number of clock cycles.

[0077] Figures 3A-3D

[0078] In operation, the instance CPU 102 transmits instructions (e.g., return data based on a read operation, write data to a particular memory location). When the instance CPU 102 first requests data for a particular memory address, if the data for the memory address is not stored in the main storage 214, the tag RAM 208 will output a read miss, and the LI cache will issue a read miss message (e.g., to the L2 cache 112, the L3 cache 114, and / or the extended memory 106) for service (e.g., return data corresponding to the address requested from the CPU 102). The LI cache 110 can then perform a read allocation. A read allocation is performed if the LI cache 110 stores the data in the main storage 214, updates the tag RAM 208, etc., such that it recognizes that the data for the address is now stored in the main data storage. The LI cache 110 can return the data to the CPU 102 and / or wait for the CPU 102 to send a subsequent read request for the same address. If the CPU 102 issues a subsequent read request for the same address, the tag RAM 208 will recognize that the data for the address is now present in the main storage 214, resulting in a read hit. If the CPU 102 proceeds to a write for the same address, the tag RAM 208 will recognize a write hit because the address is stored in the main storage 214. For a write hit, the CPU 102 will provide data for the write, and the LI cache 110 will write the data to the main storage 214 corresponding to the address.

[0079] If the initial action from the CPU 102 (or a subsequent action from the CPU 102) results in a write miss (e.g., the memory address that the CPU 102 attempts to write is not stored in the instance main storage), the LI cache 110 can perform a write miss. During a write miss, the LI cache 110 sends a write miss to a higher level cache (e.g., the L2 cache 112, the L3 cache 114, etc.) and / or the extended memory 106 to retrieve the data from the memory address, store the data in the main storage 214, and then write the data from the CPU 102 to the main storage 214 at a location corresponding to the memory address.

[0080] However, when the CPU 102 performs a write operation, it often does not have the information it needs to write immediately. Thus, some example cache systems include a write buffer to store write instructions from the CPU in case the CPU stalls (e.g., by attempting to load memory addresses from a higher cache before the write data is ready). In this way, when the L1 cache interfaces with a higher level cache to obtain data in the memory addresses corresponding to the write instructions in the buffer, the CPU can continue sending instructions and store the data in the main storage area and write the data (e.g., in the write buffer) in parallel with subsequent instructions from the CPU. However, the CPU can only write a few bytes for each write instruction, and the interface between the L1 cache and the higher level cache and / or extended memory is capable of sending a large number of bytes (e.g., 64 byte bandwidth). Thus, it is inefficient to transfer a few bytes per cycle over a large byte interface.

[0081] In Figure 4A In the system of FIG. 1, a segment of the victim storage 218 is dedicated to write miss information, rather than implementing a write buffer. Thus, the example victim storage 218 is a victim cache and a write miss buffer. The segment of the victim storage is referred to as a write miss cache. In some examples, the write miss cache can additionally or alternatively be implemented in the main storage 214. In some examples, the write miss cache is a 128 byte cache line. The write miss cache stores all write miss data until the write miss cache is full and / or the number of bytes that can be sent to the higher level cache and / or extended memory is greater than a first threshold. Once the write miss cache is full or a first threshold amount of write miss data is added to the write miss cache, the victim storage 218 combines a second threshold amount of write miss data in the write miss cache into a signal that is sent to the higher level cache (e.g., via the example L2 interface 228) to write in the address stored in the higher level cache (e.g., L2 cache 112) and / or extended memory 106. In this way, most or all of the bandwidth of the interface can be used for a particular cycle. The second threshold can be the same or different than the first threshold. Also, the write data is stored locally in the main storage 214 or the victim storage 218. Thus, if additional read or write operations are sent from the CPU 102 before the write operation is passed to the higher cache (e.g., L2 cache 112, example L3 cache 114, etc.) and / or extended memory 106, the cache controller 220 can read and / or write the data to the corresponding address within the write miss cache, which is then transferred to the higher level cache and / or extended memory 106.

[0082] In some examples, the structure of the write miss cache in victim storage 218 includes a byte enable register bank that represents the value bytes of the write miss information (e.g., the bytes to write). For example, if a write miss corresponding to the first byte and third byte of data for a write memory address is stored in the write miss cache, victim storage 218 stores the write miss data for the first and third bytes in conjunction with the memory address, and fills the respective entries of the byte enable register bank with a first value (e.g., '1') for the entry elements corresponding to the first and third bytes and a second value (e.g., '0') for the remaining elements of the entry. In this way, when the write miss data is sent to a higher level cache, the byte enable bits of the entry are included in the transmission such that the higher level cache knows which data is valid (e.g., which bytes to write) and which data is invalid (e.g., which bytes should not be written).

[0083] In certain cases, the results of victim storage 218 can be ignored if the read or write request is a hit to main storage 214. When main storage 214 is configured as a unidirectional associative cache, cache request conflicts from multiple data paths are straightforward. A data path is one or more logic circuits that, when executed and / or otherwise invoked, effectuate the transfer or delivery of data (e.g., logical signals, bit vectors, etc.) from a source to a destination. Cache request conflicts from the multiple data paths can be problematic for victim storage 218 because victim storage 218 is fully associative and can store write miss entries as well as cache entries. Cache request conflicts from two data paths can be handled as described in the following examples. Notably, in the following examples, the cache operations are described in the context of a particular data path. However, the examples are with respect to the combination of particular cache operations, not which data path the particular cache operations are on.

[0084] In a first example, a first data path has a cache read miss and a second data path has a cache write hit, with two different memory addresses. In certain cases where victim storage 218 is fully associative, the cache requests can go to anywhere within victim storage 218. With reference to FIG. 2, a first data path 202 has a cache read miss for a memory address 204 and a second data path 206 has a cache write hit for a memory address 208. In this example, the cache read miss for memory address 204 is stored in victim storage 218 at a first location 210 and the cache write hit for memory address 208 is stored in victim storage 218 at a second location 212. In this example, the first location 210 and the second location 212 are the same location in victim storage 218. In this case, the cache read miss for memory address 204 is overwritten by the cache write hit for memory address 208. In this case, the cache write hit for memory address 208 is stored in victim storage 218 at the first location 210 and the cache read miss for memory address 204 is lost. Figure 2The address generation for the location within the victim cache tag RAM 210 and the address lookup against the location within the victim storage 218 are performed in the E2 pipeline stage, so the address generation for the location within the victim cache is performed before it is known whether the cache request is a hit or a miss. After the controller 220 determines that there is a read miss on the main storage 214, a request is issued to a higher level cache or memory for the memory address of the read request. In the case where the main storage 214 is a one-way associative, the memory address of the read request of the first data path maps to a single location in the main storage 214. If there is cached data in the single location, the cached data is evicted from the main storage 214 to a pre-generated location within the victim storage 218. If this pre-generated location is the same as the location where the cache write of the second data path hits, a conflict occurs. This conflict can be detected by the cache controller 220. As noted above, the address generation for the location within the victim storage 218 is performed before it is known whether the cache request is a hit or a miss, so there is an address generated for a second location within the victim storage 218 for the cache write of the second data path before it is determined that the cache write is a hit. Based on the detection of the conflict, this second location within the victim cache can be used to store the data evicted from the main storage 214 by the read miss.

[0085] In another example, there can be a cache read miss for the first data path and a cache write hit for the second data path, as in the first example. In this example, due to the read miss, a request is issued to a higher level cache or memory for the memory address of the read request, and the cached data is evicted from the main storage 214 to a pre-generated location within the victim storage 218, here location A. In this example, the cache write of the second data path also hits location A within the victim storage 218, creating a set conflict. One possible resolution of such a conflict is to load the requested read miss directly from the higher level cache or memory to a separate location of the victim cache. Another resolution of the conflict is to have the cache controller 220 stall the read miss so that the cached data is evicted to the victim storage 218 after the cache write of the second data path to location A is complete and location A is evicted to the higher level cache or memory. In some cases, the stall can be performed while waiting for the higher level cache or memory to return the read miss data.

[0086] As another example, a first cache write can be received on a first data path for victim storage 218, and a second cache write is also received on a second data path for victim storage 218. If the first cache write and the second cache write address to different memory addresses, then the two cache writes can proceed in parallel to victim storage 218. If the first cache write and the second cache write both address to the same memory address and are both cache misses, then victim cache controller 224 allocates a single location in allocated victim cache write miss storage and merges the first cache write and the second cache write in victim cache store queue 216. The merged data can then be written to the victim cache write miss storage along with the merged byte enable, priority, and color tag information. If the first cache write and the second cache write both address to the same memory address and are both cache hits, then the first cache write and the second cache write merge to the hit location in cache.

[0087] As another example, a cache read can be received on a first data path for victim storage 218, and a cache write can be received on a second data path for victim storage 218. In the case where the cache read is a hit and the cache write is a hit to a different location in victim storage 218, the cache read and the cache write proceed in parallel without conflict. In the case where the cache read is a hit and the cache write is a miss to a different location in victim storage 218, the cache read and the cache write also proceed in parallel without conflict. In the case where the cache read is a miss and the cache write is a hit to a different location in victim storage 218, the cache read can use the address generated for the location within victim storage 218 for the cache write as described above. In the case where the cache read is a miss and the cache write is a miss to a different location in victim storage 218, both the cache read and the cache write use the address generated for the location within victim storage 218.

[0088] In another example, a cache read can be received on a first data path for a victim storage 218, and a cache write can be received on a second data path for the victim storage 218. In some cases, the cache read can be a hit to a first address in a set of addresses stored in the victim storage 218. The cache write can also be a hit to a second address in the same set of addresses stored in the victim storage 218. In this case, the cache read and the cache write can proceed in parallel without conflict. In another case, the cache read can be a hit to a first address in a set of addresses stored in the victim storage 218. The cache write can be a miss to a second address in the same set of addresses stored in the victim storage 218. In this case, the cache read and the cache write can proceed in parallel without conflict. In another case, the cache read can be a miss to a first address in a set of addresses stored in the victim storage 218. The cache write can be a hit to a second address in the same set of addresses stored in the victim storage 218. In this case, similar to the case described above, the cache read can stop until the cache write by the second data path to the location in the victim storage 218 is completed and evicted to a higher level cache or memory. Then, the cache read proceeds to read the set of addresses from the higher level cache or memory into the victim storage 218. In another case, the cache read can be a miss to a first address in a set of addresses stored in the victim storage 218. The cache write can also be a miss to a second address in the same set of addresses stored in the victim storage 218. In this case, the cache read and the cache write can proceed in parallel without conflict.

[0089] In another example, a cache read can be received on a first data path for victim storage 218, and a cache write can be received on a second data path for victim storage 218. In some cases, the cache read can be a hit on an address stored in victim storage 218. The cache write can also be a hit on the same address stored in victim storage 218. In this case, the cache read can proceed first, and the cache write can stop until after the cache read is complete. Alternatively, the order of the cache write and the cache read can be based on the data path that receives the cache write and the cache read, where the cache operation that arrives on the lower (or higher) numbered data path is completed before the other cache operation. In some cases, the cache read can be a miss on an address stored in victim storage 218. The cache write can also be a miss on the same address stored in victim storage 218. In this case, after the cache write operation is complete to store into victim storage 218, the cache write operation can be forwarded to a higher level cache or memory, and then the cache read can obtain data from the higher level cache or memory.

[0090] In another example, a first cache read can be received on a first data path for victim storage 218, and a second cache read can be received on a second data path for victim storage 218. If the first cache read and the second cache read are for different memory addresses, there is no conflict for a hit or a miss. In some cases, the first cache read can be a miss on a first address in a group of addresses. The second cache read can also be a miss on a second address in the same group of addresses. If the first cache read and the second cache read have different priorities, the higher level cache or memory is accessed based on the higher priority of the different priorities. Otherwise, the higher level cache or memory is accessed and the group of memory addresses is obtained for storage in victim storage 218. The case where the first cache read and the second cache read are for the same address is handled in the same way.

[0091] Described herein are example methods, apparatuses, systems, and articles of manufacture to facilitate write miss caching in an LI data cache. Other examples and combinations thereof include the following. Example 1 includes an apparatus comprising: a first cache storage area; a second cache storage area; wherein the second cache storage area includes a first portion and a second portion available to store a first set of data evicted from the first cache storage area; a cache controller coupled to the first cache storage area and the second cache storage area and available to receive a write operation, determine that the write operation results in a miss in the first cache storage area, and in response to the miss in the first cache storage area, provide write miss information associated with the write operation to the second cache storage area for storage in the second portion.

[0092] Example 2 includes the apparatus of Example 1, wherein the cache controller is available to compare the second portion of the second cache storage area to a threshold and, based on the second portion exceeding the threshold, cause the write miss information to be transmitted to a second cache.

[0093] Example 3 includes the apparatus of Example 2, wherein the threshold corresponds to an interface bandwidth.

[0094] Example 4 includes the apparatus of Example 2, wherein the threshold corresponds to a size of the second portion.

[0095] Example 5 includes the apparatus of Example 1, wherein the write miss information is first write miss information, and the cache controller available to the second cache storage area will not provide the first write miss information from the first cache storage area to the second cache storage area if the second cache storage area includes second write miss information corresponding to a memory address of the first write miss information.

[0096] Example 6 includes the apparatus of Example 1, wherein the first cache storage area and the second cache storage area are connected in parallel to a central processing unit.

[0097] Example 7 includes the apparatus of Example 1, wherein the write miss information is first write miss information, and the cache controller is available to merge the first write miss information with second write miss information stored in the second portion when a first memory address of the first write miss information from the first cache storage area matches a second memory address of the second write miss information.

[0098] Example 8 includes the apparatus of example 7, wherein the cache controller is to merge the first write miss information with the second write miss information by at least one of: (a) retaining first write information of the first write miss information, or (b) discarding second write information of the second write miss information when the second write information corresponds to the same one or more bytes as the first write miss information.

[0099] Example 9 includes the apparatus of example 1, wherein the second portion includes a byte enable register, the cache controller to store a value in the byte enable register based on the write miss information.

[0100] Example 10 includes the apparatus of example 9, wherein the value corresponds to an element of the write miss information to be written.

[0101] Example 11 includes a system comprising: a central processing unit to output a write command corresponding to a memory address; a first cache storage area to output write miss information from a first storage area to a second storage area when the first cache storage area does not store data of the memory address; and a second cache storage area, wherein the second cache storage area includes a first portion and a second portion available to store a first set of data evicted from the first cache storage area, the second cache storage area to store the write miss information in a dedicated section of the second storage area dedicated to the write miss information.

[0102] Example 12 includes the system of example 11, wherein the second cache storage area is to output the write miss information to a second cache when the dedicated section has more than a threshold amount of write miss information.

[0103] Example 13 includes the system of example 12, wherein the threshold corresponds to a bandwidth of an interface to the second cache.

[0104] Example 14 includes the system of example 12, wherein the threshold corresponds to a size of the second portion.

[0105] Example 15 includes the system of example 11, wherein the second cache storage area is to not store the write miss information from the first storage area in the second portion if the second cache storage area includes a second write instruction corresponding to the same memory address as the write miss information from the central processing unit.

[0106] Example 16 includes the system of Example 11, wherein the first cache storage region and the second cache storage region are connected in parallel to the central processing unit.

[0107] Example 17 includes the system of Example 11, wherein the write miss information is first write miss information, the system further including a controller to merge the first write miss information with second write miss information stored in the second portion when a first memory address of the first write miss information from the first cache storage region matches a second memory address of the second write miss information.

[0108] Example 18 includes the system of Example 17, wherein the cache controller is to merge the first write miss information with the second write miss information by at least one of: (a) retaining first write information of the first write miss information, or (b) discarding second write information of the second write miss information when the second write information corresponds to the same one or more bytes as the first write miss information.

[0109] Example 19 includes a method comprising: receiving a write operation; determining that the write operation results in a miss in a first cache storage region; and in response to the miss in the first cache storage region, validating write miss information associated with the write operation for storage in a second portion of a second cache storage element having a first portion and the second portion, the first portion storing a first set of data evicted from the first cache storage region.

[0110] Example 20 includes the method of Example 19, further including comparing the second portion of the second cache storage region to a threshold, and based on the second portion exceeding the threshold, outputting the write miss information to a second cache.

[0111] Figure 4A is Figure 4A and / or 3. In Figure 4AIn the main cache storage queue 212, there are instance latches 402a, 402b, 402c, 402d, 402e, instance merging circuits 403a-c, instance arithmetic component 404, instance atomic comparison component 406, instance read-modify-write merging component 408, instance selection multiplexer 410, instance ECC generator 412, instance arbitration manager 414, instance pending storage address data storage area 416, instance priority multiplexer 418, instance read port 424, and instance write port 426. Instance merging circuits 403a-d include instance comparator 420 and instance switch 422. Figure 4A The example illustrates a single pipeline for the primary cache storage queue 212. However, the primary storage element 214 can be arranged as more than one independent copy relative to different sets of supporting pipelines, as indicated by dashed box 400. Therefore, Figure 4A The pipeline can be regenerated multiple times for different groups, as further described below.

[0112] exist Figure 4A In this context, instance latches 402a, 402b, 402c, 402d, and 402e are electronic devices configured to store information (e.g., bytes, bits, etc.) obtained through the main cache storage queue 212. Instance latches 402a-c pass write data and information corresponding to whether the write data needs to be combined with read and correction data outside the ECC logic 310 in the arithmetic unit 404, atomic unit 406, and / or RMW merging component 408. Figure 4A In this example, latch 402a is communicatively coupled to cache controller 220 to receive read, write, and / or modify instructions. Such read, modify, and / or write instructions may originate from CPU 102 and be transmitted to latch 402a via cache controller 220. Latch 402a is coupled to latch 402b, tag RAM 208, arbitration manager 414, and pending memory address data storage area 416 to transmit such read, modify, and / or write instructions to latch 402b, tag RAM 208, arbitration manager 414, and pending memory address data storage area 416 in response to subsequent clock cycles of cache controller 220.

[0113] exist Figure 4A In this example, latch 402b is coupled to latch 402a, pending memory address data storage area 416, latch 402c, priority multiplexer 418, and comparator 420 to transmit acquired read, modify, and / or write instructions in response to subsequent clock cycles of cache controller 220. In this manner, values ​​obtained from read, modify, and / or write instructions (e.g., byte values, bit values, etc.) are propagated through main cache storage queue 212.

[0114] The example latch 402c is coupled to the latch 402b, the priority multiplexer 418, the arithmetic component 404, the atomic compare component 406, and the read-modify- write merge component 408. This coupling enables the latch 402c to transfer values obtained from read, modify, and / or write instructions (e.g., byte values, bit values, etc.) to the arithmetic component 404, the atomic compare component 406, and / or the read-modify-write merge component 408 in response to subsequent clock cycles of the cache controller 220. In some examples described herein, the latch 402c can transfer values obtained from read, modify, and / or write instructions (e.g., byte values, bit values, etc.) to one or more of the arithmetic component 404, the atomic compare component 406, and / or the read-modify-write merge component 408. For example, in the case that the cache controller 220 transfers an instruction to write a bit into a currently stored word, the latch 402c can transfer values obtained from read, modify, and / or write instructions (e.g., byte values, bit values, etc.) to the read-modify-write merge component 408. In other examples described herein, although the cache controller 220 can transfer an instruction to write a bit into a currently stored word, the latch 402c can transfer values obtained from read, modify, and / or write instructions (e.g., byte values, bit values, etc.) to the arithmetic component 404, the atomic compare component 406, and / or the read-modify-write merge component 408.

[0115] The example latch 402d is coupled to the first multiplexer 410, the ECC generator 412, and the latch 402e. This coupling enables the latch 402d to transfer values obtained from the first multiplexer 410 to the ECC generator 412 and / or the merge circuit 403a in response to subsequent clock cycles of the cache controller clock 220.

[0116] The example latch 402e is coupled to the priority multiplexer 418 and the MUX circuit 314 of FIGS. 3 and / or 4. This coupling enables the latch 402e to transfer values obtained from the priority multiplexer 418 to the MUX circuit 314 in response to subsequent clock cycles of the cache controller 220. For example, in a read operation by the CPU 102 on an address that hits the primary storage element 214, a previous write to the same address can still be in flight (e.g., not fully written to the primary storage element 214). In this example, the latch 402e collects the unwritten data byte and provides it to the MUX 314, which is ultimately sent back to the CPU 102.

[0117] Instance merging circuit 403a is coupled to latch 402d, merging circuit 403b, arithmetic component 404, atomic comparison component 406, and read-modify-write merging component 408. Instance merging circuit 403b is coupled to merging circuit 403a, priority multiplexer 418, and merging circuit 403c. Instance merging circuit 403c is coupled to merging circuit 403b and latch 402b. Instance merging circuits 403a-c facilitate comparisons of read operations in different segments of the main cache memory queue 212 to potentially reroute write operations to be merged with write operations corresponding to the same memory address location, as further described below. Although Figure 4A The example includes three merging circuits 403a-c, but additional merging circuits may exist to merge write operations from other segments of the main cache memory queue 212 (e.g., merging circuits that couple the output of latch 402d to the outputs of latch 402b and / or latch 402a, etc.). In some instances, merging circuits 403a-c are combined into a single circuit for comparing write operations from different latches 402b-d and rerouting based on matching memory addresses in any two or more of the different latches 402b-d.

[0118] exist Figure 4A In the example shown, arithmetic component 404 is coupled to latch 402c, first multiplexer 410, and ECC logic 310 to perform arithmetic operations (e.g., increment, decrement, etc.) on data from main memory 214. Furthermore, arithmetic component 404 performs histogram operations on the data stored in main memory 214. Figure 4A The example arithmetic component 404 shown is implemented by logic circuitry, such as a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of such implementation, such as one or more analog or digital circuits, logic circuits, programmable processors, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable logic devices (FPLDs), digital signal processors (DSPs), etc. The operation of the example arithmetic component 404 is further described below.

[0119] exist Figure 4A In the example shown, atomic comparison component 406 is coupled to latch 402c, first multiplexer 410 and ECC logic 310 to compare data and a key at a memory address and replace the data if the data at the memory address matches the key. Figure 4AThe example atomic compare component 406 of the illustrated example is implemented by logic circuitry, such as a hardware processor. However, any other type of circuitry can additionally or alternatively be used, such as one or more analog or digital circuits, logic circuits, programmable processor(s), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), field programmable logic device(s) (FPLD(s)), digital signal processor(s) (DSP(s)), etc. Operation of the example atomic compare component 406 is described further below.

[0120] In Figure 4A The read-modify-write merge component 408 of the illustrated example is coupled to the latch 402c, the first multiplexer 410, and the ECC logic 310 to facilitate read, modify, and / or write instructions sent by the cache controller 220. For example, the read-modify-write merge component 408 is coupled to the ECC logic 310 to obtain a currently stored word that will be affected by the read, modify, and / or write instruction. In an example write operation, the read-modify-write merge component 408 is configured to update the currently stored word obtained from the ECC logic 310 with new bits, bytes, etc. obtained from the latch 402c. Additional description of the read-modify-write merge component 408 is described below. Figure 4A The example read-modify-write merge component 408 of the illustrated example is implemented by logic circuitry, such as a hardware processor. However, any other type of circuitry can additionally or alternatively be used, such as one or more analog or digital circuits, logic circuits, programmable processor(s), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), field programmable logic device(s) (FPLD(s)), digital signal processor(s) (DSP(s)), etc.

[0121] The example first multiplexer 410 is coupled to the arithmetic component 404, the atomic compare component 406, and the read-modify-write merge component 408 to transmit an output of the arithmetic component 404, the atomic compare component 406, or the read-modify-write merge component 408 to the latch 402d based on an indication from the cache controller 220. For example, where the cache controller 220 indicates that a write function is to be performed (e.g., the cache controller transmits a write request to the latch 402b), an indication is sent by the cache controller 220 to the first multiplexer 410 to select the input connected to the read-modify-write merge component 408 for transmission to the latch 402d. Figure 4A The example first multiplexer 410 of the illustrated example is implemented by logic circuitry, such as a hardware processor. However, any other type of circuitry can additionally or alternatively be used, such as one or more analog or digital circuits, logic circuits, programmable processor(s), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), field programmable logic device(s) (FPLD(s)), digital signal processor(s) (DSP(s)), etc.

[0122] exist Figure 4A In the example shown, ECC generator 412 is coupled to latch 402d and merging circuitry 403a to facilitate error detection and correction of values ​​(e.g., bytes, bits, etc.) stored in latch 402d. For example, ECC generator 412 is configured to regenerate ECC (e.g., generate error detection codes) values ​​stored along with data (e.g., merged words output from read-modify-write merging component 1108). The ECC values ​​are used by error detection and correction circuitry to determine whether an error has occurred during read and / or write operations, as further described above. Figure 4A The example ECC generator 412 shown is implemented by logic circuitry, such as a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of such implementation, such as one or more analog or digital circuits, logic circuits, programmable processors, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable logic devices (FPLDs), digital signal processors (DSPs), etc.

[0123] exist Figure 4A In this configuration, instance arbitration manager 414 is coupled to latches 402a and 402b, pending memory address data storage area 416, and main memory area 214 to facilitate read, modify, and / or write instructions received from cache controller 220. For example, in the case of receiving a write instruction from cache controller 220, arbitration manager 414 is configured to transfer the corresponding read instruction for the currently stored word to main memory area 214. Additionally, arbitration manager 414 is coupled to main memory area 214 to arbitrate conflicting accesses to main memory area 214. When multiple operations attempt to access main memory area 214 in the same loop, arbitration manager 414 may select the operations permitted to access main memory area 214 based on a priority scheme. Suitable priority schemes are described in more detail below; however, in one instance, arbitration prioritizes read operations over write operations because write data in main cache storage queue 212 is available for subsequent operations, even before it is written to main memory area 214. Therefore, the performance impact is minimal when write data is allowed to wait in the primary cache queue 212. However, when the primary cache queue 214 is full of write data that has not yet been written back, the priority of write operations can be increased until they take precedence over competing read operations.

[0124] Figure 4AThe example arbitration manager 414 of the illustrated example is implemented by a logic circuit, such as a hardware processor. However, any other type of circuitry can additionally or alternatively be used, such as one or more analog or digital circuits, logic circuits, programmable processor, application specific integrated circuit (ASIC), programmable logic device (PLD), field programmable logic device (FPLD), digital signal processor (DSP) etc.

[0125] In the example of FIG. 4, the pending store address data store 416 is configured to store addresses of read, modify, and / or write instructions obtained from the cache controller 220. In this manner, the pending store address data store 416 maintains a record of the addresses associated with each value stored in any of the latches 402a, 402b, 402c, 402d, 402e and / or each of the merge circuits 403a, 403b, and / or 403c. Method and apparatus for facilitating fully pipelined read-modify- write support in level 1 data cache using store queue and data forwarding In the example of FIG. 4, the pending store address data store 416 is configured to store addresses of read, modify, and / or write instructions obtained from the cache controller 220. In this manner, the pending store address data store 416 maintains a record of the addresses associated with each value stored in any of the latches 402a, 402b, 402c, 402d, 402e and / or each of the merge circuits 403a, 403b, and / or 403c. Figure 2 The example pending store address data store 416 of the illustrated example can be implemented by any means for storing data, such as flash memory, magnetic media, optical media, etc. Further, the data stored in the pending store address data store 416 can be in any data format, such as binary data, comma delimited data, tab delimited data, structured query language (SQL) structures, etc.

[0126] The example priority multiplexer 418 is coupled to the latches 402b, 402c, 402d, and the merge circuit 403a to facilitate read operations if the latches 402b, 402c, 402d, or the merge circuit 403a are storing values corresponding to write instructions. For example, the cache controller can initiate four write instructions for a four byte word having addresses A3, A2, Al, and A0: a write to address A0 with byte Oxll, a write to address Al with byte 0x22, a write to address A3 with byte 0x23, and a write to address A0 with byte 0x44. In this example, if the cache controller 220 initiates a read instruction to read the entire four byte word, the priority multiplexer 418 is configured to obtain the byte value 0xll stored in the merge circuit 403a, the byte value 0x22 stored in the latch 402d, the byte value 0x23 stored in the latch 402c, and the byte value 0x22 stored in the latch 402b. Also, the pending store address data store 416 transmits instructions to the priority multiplexer 418 indicating which address value is associated with the byte values stored in the latches 402b, 402c, 402d, and the merge circuit 403a. In this example, because the byte value stored in the latch 402b is associated with address A0 and the byte value stored in the merge circuit 403a is also associated with address A0, the priority multiplexer 418 is configured to transmit a packet to the latch 402e indicating that address A0 is 0x44 (e.g., the most recent write instruction associated with address A0), address Al is 0x22, and address A3 is 0x23.

[0127] In this way, the MUX circuit 314 is configured to update the currently stored value of the word with the byte values obtained from the priority multiplexer 418. Such operations ensure that read instructions transmitted by the primary cache storage queue 212 are likely to indicate the correct word, even if write instructions can not have fully propagated through the primary cache storage queue 212.

[0128] An example read path (e.g., read input to tag RAM 208) can run in parallel with the main cache store queue 212. Because read operations (e.g., read instructions) can reference data that can not yet be complete in write operations (e.g., write instructions), the main cache store queue 212 can include a write forwarding function that allows the read path to obtain data from the main cache store queue 212 that has not yet been written back to the main storage 214. In examples, the main cache store queue 212 includes a pending store address data store 416 to record addresses of operations at each stage of the main cache store queue 212, a priority multiplexer 418 to select data for forwarding from one stage (e.g., latch) in the main cache store queue 212, and a MUX circuit 314 to select between the output of the main storage 214 (through error detection and correction circuit 310) and the forwarded main cache store queue 212 data from the data priority multiplexer 418.

[0129] Alternatively, because read operations (e.g., read instructions, read commands, etc.) can reference victim (e.g., evicted) data that can not yet be complete in write operations (e.g., write instructions, write commands, etc.), the main cache store queue 212 includes a read invalidation function that forwards in-flight data (e.g., data of the store queue 212 that has not yet been stored in the main storage element 214) to the victim storage element 214 and / or L2 cache 212 and invalidates the remaining in-flight data in the store queue 212.

[0130] An example read port 424 is coupled to the read path and the data store 416. The read port 424 can be implemented by an interface that interfaces with the main cache controller 222 whenever a read miss occurs. For example, the read port 424 is to receive a victim address and a read invalidation command from the main cache controller 222. The read port 424 sends the victim address to the data store 416 to compare with pending addresses stored in the data store 416.

[0131] An example write port 426 is coupled to the write path and the latch 402a. The write port 426 can be implemented by an interface that interfaces with the main cache controller 222 (e.g., cache controller 220) to obtain write instructions. For example, the write port 426 is to receive an address and a value from the cache controller 220 for a write.

[0132] Figure 2 The elements of FIG. 1 are arranged in a manner that represents a flow of transactions. The temporal elements are represented by stages El- E5. Each stage represents a discrete period of time, and in some examples, each stage represents one clock cycle or an integer number of clock cycles.

[0133] An example flow of a read operation through the primary cache store queue 212 will now be described. In a first cycle corresponding to stage E1, the L1 data cache 110 retrieves the record associated with the address of the read operation from the tag RAM 208 to determine if the data is stored in the primary storage 214. In a direct-mapped instance, the L1 data cache 110 need not wait for the tag RAM 208 comparison before requesting the data from the primary storage 214, and thus, the comparison between the read operation's address and the record of the cached address by the tag RAM 208 can extend into a second or third clock cycle.

[0134] In a second cycle corresponding to stage E2, the L1 data cache 110 can request the data and ECC syndrome bits from the primary storage 214 if granted by the arbitration manager 414. In this cycle, the L1 data cache 110 can also determine if newer data is available in the primary cache store queue 212 by comparing the read address to the pending store address data store 416. If so, the priority multiplexer 418 is set to forward the appropriate data from the primary cache store queue 212.

[0135] The data and ECC can be provided by the primary cache storage 214 in a third cycle corresponding to stage E3. However, this data can or can not correspond to the memory address specified by the read operation, as the L1 data cache 110 can assign multiple extended memory addresses to the same entry in the cached primary storage 214. Thus, in the third cycle, the L1 data cache 110 determines if the provided data and ECC from the primary storage 214 correspond to the memory address in the read operation based on the comparison of the tag RAM 208 record (e.g., a cache hit). In the case of a cache hit, the data and ECC bits are received by the error detection and correction circuit 310, which corrects any errors in the data in a fourth cycle corresponding to stage E4.

[0136] As described above, newer data that has not yet been written to the primary storage 214 can exist in the primary cache store queue 212 and can be forwarded from the primary cache store queue 212 through the priority multiplexer 418. If so, the MUX circuit 314 selects the forwarded data instead of the corrected data from the primary storage 214.

[0137] The corrected data from the primary storage 214 or the forwarded data from the primary cache store queue 212 is provided to the L1 data cache 110 in a fifth cycle corresponding to stage E5. In this way, the controller 220 can provide a full ECC check and correction to the data in approximately 5 cycles in the case of a cache hit.

[0138] In the event that data and ECC bits are not present in the main storage 214 (e.g., a cache miss), the main cache store queue 212 can stall until the data can be retrieved from the expanded memory 106 and / or the victim storage 218, at which point the data can be written to the main storage and the tag RAM 208 can be updated.

[0139] Figure 4B Figures 3A-4A

[0140] In the examples described herein, there are two cache systems operating in tandem (e.g., the main storage 214 and the victim cache storage 218). In the examples described herein, the main storage 214 is a direct-mapped cache element, and the victim cache storage 218 is a fully-associative cache storage. Both the direct-mapped main storage 214 and the fully-associative victim cache storage 218 are protected with error-correcting code (ECC). Thus, example applications include reading a line from the main storage 214 and / or moving a line from the main storage 214. As such, the ECC logic will correct the cache line and regenerate the ECC syndrome before writing the line to the victim cache storage 218. Such applications can use two additional clock cycles of the CPU (e.g., one clock cycle for error correction by the ECC logic, and another clock cycle for ECC syndrome regeneration). To shorten this latency, the examples described herein include using the same check block size between the main storage 214 and the victim cache storage 218. Thus, the main storage 214 and the victim cache storage 218 both compute and / or otherwise determine parity of 32-bit boundaries. In this way, the LI cache 110 can move cache lines from the main storage 214 to the victim cache storage 218 directly with less latency.

[0141] In the examples described herein, the LI data cache 110 supports multiple operations that read data from the cache and change the data before rewriting the data. For example, the LI data cache 110 can support a read-modify-write operation. The read-modify-write operation reads existing data and overwrites at least a portion of the data. In ECC embodiments, the read-modify-write operation can be performed when writing less than a full group width (e.g., when writing less than 32-bit 4-byte words). The reason for using a read function of the read-modify-write is that the portion of the data in the group that is not overwritten still contributes to the ECC syndrome bits.

[0142] The read-modify-write operation can be split into write operations and read operations, and the primary cache storage queue 212 can be structured such that read operations in the read path remain synchronized with write operations in the primary cache storage queue 212. The read operations and write operations remain synchronized until the read-modify-write merge component 408 overwrites at least a portion of the read data with the write data to produce merged data. The merged data is provided to the ECC generator 412 to generate new ECC syndrome bits for the merged data, and then the merged data and ECC syndrome bits can be provided to the arbitration manager 414 for storage in the main storage 214.

[0143] In an example read-modify-write operation, Figure 4B The cache controller 220 of and / or 3 transmits a write request indicating a subset of bytes of a word or the entire word (e.g., a first set of data) to be written. In this example, the write request transmitted by the cache controller 220 includes an address value of the bytes to be written and data to be written to the indicated bytes. For example, Figure 4B The main storage 214 of and / or 3 can include a four-byte word 0x12345678 associated with addresses A3, A2, Al, A0. In this example, address A3 corresponds to byte 0x12 of the stored word, address A2 corresponds to byte 0x34, address Al corresponds to byte 0x56, and address A0 corresponds to byte 0x78. In this example operation, the cache controller 220 can transmit the following write requests: replace address A3 with byte 0x33 of the currently stored word 12345678, replace address Al with byte 0x22, and replace address A0 with byte 0x11. Additionally, in this example, the first write request to replace address A3 of the stored word with byte 0x33 will cause the stored word to become 0x33345678, the second write request to replace address Al of the stored word with byte 0x22 will cause the stored word to become 0x33342278, and the third write request to replace address A0 of the stored word with byte 0x11 will cause the stored word to become 0x33342211.

[0144] To handle such a request, the LI data cache 110 compares the address of the read operation to the entries of the tag RAM 208 and the LI data cache requests the data and ECC syndrome bits from the main storage 214 and / or the primary cache storage queue 212. Because the read-modify-write operation will modify the data, in instances where the MESI (modified, exclusive, shared, and invalid) state of the entry in the main storage 214 is tracked, a cache hit that is not in the modified or exclusive state can be treated as a cache miss. Upon obtaining the data in the correct state and any errors are corrected, it is provided to the read-modify-write merge component 408. In this same cycle, the read-modify-write merge component 408 can overwrite at least a portion of the corrected data with the write data to produce merged data. The ECC generator 412 generates new ECC syndrome bits for the merged data.

[0145] In instances described herein, the ECC generator 412 operates at a word granularity. Thus, the ECC generator 412 computes the ECC syndrome for a block of data. In instances described herein, the block of data can be four bytes (e.g., a word). The primary cache storage queue 212 processes the write instruction at the first instance cycle (e.g., completing the first write request to replace the byte at address A3 with byte 0x33), because the ECC generator 412 operates at a word granularity (e.g., 4 bytes or 32-bit word), the cache controller 220 initiates a read request for the current storage byte in address A3 of the current storage word. In this instance, the byte and address in the first write request (e.g., 0x33 and A3) are stored in the latch 402b. Additionally, the cache controller 220 transmits a read request for the entire current storage word to the main storage 214. Thus, at the end of the first cycle, the read request for the entire current storage word is transmitted to the main storage 214 and byte 0x33 is stored in the first latch 402b.

[0146] At an example second cycle (e.g., completing a second write request to replace byte 0x22 at address Al), the byte from the first write request is transferred to latch 402c, the entire current storage word is transferred from main storage 214 to ECC logic 310, and the second write request (e.g., replace byte 0x22 at address Al) is transferred by cache controller 220 to be stored in latch 402b. During the second cycle, read-modify-write merge component 408 obtains the byte stored in latch 402c and the entire current storage word is transferred through ECC logic 310. In this way, read-modify-write merge component 408 identifies the address of the byte in the current storage word to be updated. Once read-modify-write merge component 408 identifies and / or otherwise obtains: (a) the value (e.g., byte value, bit value, etc.) of the portion of the current storage word from latch 402c to be updated and (b) the current storage word from ECC logic 310, read-modify-write merge component 408 writes the portion of the current storage word with the value obtained from latch 402c (e.g., replaces the portion of the current storage word with the value, merges the portion of the current storage word with the value, etc.). For example, read-modify-write merge component 408 writes the value of the portion of the word to the address value corresponding to the portion of the word in the current storage word. This example write portion output by read-modify-write merge component 408 can be referred to herein as a merged word. In some examples described herein, such merged words are provided by read-modify-write merge component 1108 for writing to victim storage 218.

[0147] In response, to initiate the write portion of the example read-modify-write operation, multiplexer 410 transfers the merged word from read-modify-write merge component 408 to be stored in latch 402d. At a subsequent clock cycle, ECC generator 412 obtains the merged word from latch 402d and generates corresponding ECC syndrome bits. In the same or a subsequent clock cycle, ECC generator 412 transfers the merged word through merge circuits 403a, 403b, and 403c to be processed by arbitration manager 414 for storage in main storage 214.

[0148] However, in this example described above, because cache controller 220 transferred three write instructions corresponding to the same stored word in main storage 214 in succession, read-modify-write merge component 408 can merge the three write instructions into one transaction when writing the three values of the three write instructions to the current storage word. For example, main storage queue 212 feeds back (e.g., transfers) the merged word from the first write instruction for the subsequent second write instruction before storing the merged word from the first write instruction in main storage 212.

[0149] Figure 4B It is a combination Figure 4B The main cache storage queue 212 is implemented as an instance of the data forwarding logic 460. Although... Figure 4B The instance data forwarding logic 460 is described as being implemented in conjunction with the main cache storage queue 212, but in other instances described herein, in Figure 4B Any of the instances described can be implemented in conjunction with the victim cache storage queue 216.

[0150] exist Figure 4B In this instance, instance address line 462 (RD_ADDR) is coupled to cache controller 220 to obtain instance read instructions from CPU 102. Figure 4B In this instance, address line 462 receives a read instruction from the main cache queue 212. In this way, the main cache queue 212 can forward any data from in-flight write transactions while executing a read instruction from CPU 102. In the main cache queue 212, instructions from CPU 102 (e.g., read instructions and / or other transactions, and / or write instructions and / or other transactions) contain an address, a byte enable, and associated data. Figure 4B The topology includes instance address storage area 464a (e.g., pending address data storage area 416 in Figure 4), instance byte storage area 464b (e.g., byte-enabled storage area), and instance data storage area 464c (e.g., any one of latches 402a, 402b, 402c, etc.). Figure 4B In the address storage area 464a, address addr0 corresponds to the earliest read and / or write instruction in the main cache storage queue 212, and address addr3 corresponds to the latest read and / or write instruction in the main cache storage queue 212.

[0151] The address passed via address line 462 (e.g., a read instruction) is compared by instance comparison logic 466 with all addresses (e.g., addr0, addr1, addr2, and addr3) in address memory 464a. In the instance described herein, comparison logic 466 can compare the address of the read instruction with any number of entries, since addresses addr0, addr1, addr2, and addr3 can be completely or partially equivalent (e.g., identical). In this way, the instance output of comparison logic 466 is a 4-bit signal. This 4-bit signal is generated based on the corresponding byte enable signal in the byte memory 464b. This 4-bit signal can have any value (e.g., all zeros, all one, partially zeros, and partially one, etc.).

[0152] In example operations, the four addresses of address storage 464a can include one or more valid bytes (e.g., a logical high byte). In examples described herein, the primary cache storage queue 212 is 64 bits (e.g., 8 bytes), and thus the primary cache storage queue 212 can perform a write of any number of bytes, such as one to eight bytes.

[0153] In response to the comparison logic 466 identifying the addresses of the address storage 464a that include based on the byte enables in the byten storage 464b, the example output lines 468 transmit an 8-bit result for each address in the address storage 464a. In examples described herein, there are four output lines 468 (e.g., dram hit DP0[0][7:0], dram hit dp0[1][7:0], dram hit dp0[2][7:0], and dram hit dp0[3][7:0]). In operation, a bit set to a logical high (e.g., 1) in any one of the output lines 468 indicates that the corresponding byte of the corresponding address of the address storage 464a has valid data to be forwarded. For example, if the first of the output lines 468 includes dram hit dp0[0], then the byte value for the corresponding read instruction can be obtained from any one of the addresses in the address storage 464a.

[0154] Figure 4B Examples of the include example selection logic 470 and example selection lines 472. In examples described herein, the selection lines 472 include eight 2-byte outputs. Thus, each of the corresponding byte enables in the byten storage 464c is one of the selection signals. In example operations, in the case where a read instruction indicates to read multiple addresses with multiple enabled bytes, the example selection logic 720 selects the most recent data. Such outputs of the selection logic 470 (e.g., selection lines 472) control example multiplexers 474a-474h (multiplexers 474e-h not shown), respectively. In Figure 4B In examples of the, the multiplexers 474a-h include 8 one-byte input terminals. In operation, the multiplexers 474a-h obtain their respective selection line in the selection lines 472, indicating which byte of each of the data storage 464c to forward. In this way, the primary cache storage queue 212 can forward data from different flight storage (e.g., any of the data storage 464c) based on the address comparison (e.g., comparison performed by the comparator 466), the corresponding byte enables of the byten storage 464b, and the order in which the primary cache storage queue 212 issues write instructions (e.g., comparison performed by the selection logic 470).

[0155] In the examples described herein, any of the address lines 462, address storage region 464a, byten storage region 464b, data storage region 464c, comparison logic 466, output lines 468, selection logic 470, selection lines 472, and / or multiplexers 474a-h can be implemented in the victim cache storage queue 216. In Figure 4B In the examples described herein, the output terminals of the multiplexers 474a-h are coupled to an example cache multiplexer 476. In Figure 4B In the examples described herein, the cache multiplexer 476 is also coupled to similar multiplexers implemented in this manner in association with the victim cache storage queue 216. In operation, the cache multiplexer 476 obtains a selection signal from the cache controller (e.g., the primary cache controller 222 or the victim cache controller 224) that transmitted the read instruction. In this manner, the cache multiplexer 476 facilitates data forwarding to the CPU 102.

[0156] In some examples, Figure 4B The topology of the examples described herein can correspond to the example write data forwarding component of the primary cache storage queue 212, the write data forwarding component of the victim cache storage queue 216, and the MUX circuit 314, 316. In this example, the cache multiplexer 476 can be implemented by the example MUX circuit 314, 316. Also, in this example, any of the address lines 462, address storage region 464a, byten storage region 464b, data storage region 464c, comparison logic 466, output lines 468, selection logic 470, selection lines 472, and / or multiplexers 474a-h can be implemented by the example write data forwarding component of the primary cache storage queue 212, the address lines 462, address storage region 464a, byten storage region 464b, data storage region 464c, comparison logic 466, output lines 468, selection logic 470, selection lines 472, and / or multiplexers 474a-h implemented in association with the victim storage queue 216 can be implemented by the example write data forwarding component of the victim cache storage queue 216.

[0157] In some examples, Figure 4B The topology of the examples described herein can correspond to the example write data forwarding component of the primary cache storage queue 212, the write data forwarding component of the victim cache storage queue 216, and the MUX circuit 314, 316. In this example, the cache multiplexer 476 can be implemented by the example MUX circuit 314, 316. Also, in this example, any of the address lines 462, address storage region 464a, byten storage region 464b, data storage region 464c, comparison logic 466, output lines 468, selection logic 470, selection lines 472, and / or multiplexers 474a-h can be implemented by the example write data forwarding component of the primary cache storage queue 212, the address lines 462, address storage region 464a, byten storage region 464b, data storage region 464c, comparison logic 466, output lines 468, selection logic 470, selection lines 472, and / or multiplexers 474a-h implemented in association with the victim storage queue 216 can be implemented by the example write data forwarding component of the victim cache storage queue 216.

[0158] In the examples described herein, Method and apparatus for reducing read-modify-write cycles of misaligned writesThe topology of 8 is used for each group of the home storage 214 and victim storage 218. For example, if the home storage 214 has 8 groups, then Figure 4A The topology of 8 is replicated 8 times, once for each group.

[0159] Described herein are example methods, apparatuses, systems, and articles of manufacture that use a store queue and data forwarding to facilitate fully pipelined read-modify-write support in a level one data cache. Other examples and combinations thereof include the following:

[0160] Example 1 includes an apparatus comprising a first storage, a second storage, a store queue coupled to the first storage and the second storage, the store queue operable to receive a first memory operation specifying a first set of data, process the first memory operation to store the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and feed back the first set of data for the second memory operation prior to storing the first set of data in the at least one of the first storage and the second storage.

[0161] Example 2 includes the apparatus of example 1, wherein the second memory operation is a read-modify-write operation and specifies a second set of data, and the store queue is operable to merge the first set of data and the second set of data to produce a third set of data prior to storing the first set of data in the at least one of the first storage and the second storage, and provide the third set of data for storage in at least one of the first storage and the second storage.

[0162] Example 3 includes the apparatus of example 2, further comprising receiving a third memory operation indicating to read the third set of data.

[0163] Example 4 includes the apparatus of example 1, wherein the second storage is configured as a victim storage of the first storage.

[0164] Example 5 includes the apparatus of example 1, wherein the store queue further comprises a data store configured to store a first address value of the first set of data.

[0165] Example 6 includes the apparatus of example 1, wherein the store queue further comprises an error code correction generator to generate an error detection code.

[0166] Example 7 includes the apparatus of example 6, wherein the error code correction generator generates the error detection code in response to processing the first memory operation.

[0167] Example 8 includes a method comprising receiving a first memory operation specifying a first set of data, processing the first memory operation to store the first set of data in at least one of a first storage region and a second storage region, receiving a second memory operation, and transferring the first set of data for the second memory operation prior to storing the first set of data in the at least one of the first storage region and the second storage region.

[0168] Example 9 includes the method of example 8, wherein the second memory operation is a read-modify-write operation specifying a second set of data, the method further comprising merging the first set of data and the second set of data to produce a third set of data prior to storing the first set of data in the at least one of the first storage region and the second storage region, and providing the third set of data for storage in at least one of the first storage region and the second storage region.

[0169] Example 10 includes the method of example 9, further comprising receiving a third memory operation indicating to read the third set of data.

[0170] Example 11 includes the method of example 8, wherein the second storage region is configured as a victim storage region of the first storage region.

[0171] Example 12 includes the method of example 8, further comprising storing a first address value for the first set of data.

[0172] Example 13 includes the method of example 8, further comprising generating an error detection code.

[0173] Example 14 includes the method of example 13, further comprising generating the error detection code in response to processing the first memory operation.

[0174] Example 15 includes a system comprising: a central processing unit configured to transfer a first memory operation and a second memory operation; a first storage region coupled to the central processing unit; a second storage region coupled to the central processing unit; a store queue coupled to the first storage region, the second storage region, and the central processing unit, the store queue operable to receive the first memory operation specifying a first set of data, process the first memory operation to store the first set of data in at least one of the first storage region and the second storage region, receive the second memory operation, and feed back the first set of data for the second memory operation prior to storing the first set of data in the at least one of the first storage region and the second storage region.

[0175] Example 16 includes the system of Example 15, wherein the second memory operation is a read-modify-write operation and specifies a second set of data, and the store queue is operable to merge the first set of data and the second set of data to produce a third set of data prior to storing the first set of data in the at least one of the first storage region and the second storage region, and provide the third set of data for storage in at least one of the first storage region and the second storage region.

[0176] Example 17 includes the system of Example 16, further comprising receiving a third memory operation indicating to read the third set of data.

[0177] Example 18 includes the system of Example 15, wherein the second storage region is configured as a victim storage region of the first storage region.

[0178] Example 19 includes the system of Example 15, wherein the store queue further comprises a data store configured to store a first address value of the first set of data.

[0179] Example 20 includes the system of Example 15, wherein the store queue further comprises an error code correction generator to generate an error detection code in response to processing the first memory operation.

[0180] Aggressive write merging for reducing bank stress

[0181] In issuing a write instruction to multiple sets of storage regions, such write instruction can be transmitted with a corresponding read instruction, regardless of the size of the write instruction, attempting to perform a full read-modify-write cycle of such write instruction. For example, in such an application, a write instruction indicating to write 128 bits starting from address A0 from a first memory set across two 64-bit memory sets can be obtained by a CPU. In this example, although both example memory sets are written completely, such an application keeps a read instruction to read the data currently stored in the two example memory sets. However, such a method is inefficient as twice the processing power (e.g., write and read instructions) is used. Also, such a method does not provide any control logic and / or processing circuitry to analyze the write instruction.

[0182] In Figure 4AIn the illustrated example, the home storage region 214 and / or the victim storage region 218 can be multiple sets of storage regions. For example, the home storage region 214 can include sixteen sets of memory (e.g., sixteen sub-RAMs), each 64 bits wide. In this example, where the cache controller 220 transmits a write instruction to write all 64 bits to the first set of the home storage region 214 (e.g., a write instruction to write a 64-bit word starting at the first address of the first set), the write instruction can be executed without initiating a read instruction. For example, the set processing logic 303 can detect that such a write to the entire set is to be performed, and thus instruct the cache controller 220 to initiate a read-modify-write operation, overriding transmission of a read instruction.

[0183] Similarly, where the cache controller 220 transmits a write instruction to write all 128 bits to the first set and the second set of the home storage region 214 (e.g., a write instruction indicating to write a 128-bit word starting at the first address of the first set and ending at the last address of the second set), the write instruction can be implemented without initiating a read instruction. For example, the set processing logic 303 can detect that such a write to the entire multiple sets is to be performed, and thus instruct the cache controller 220 to initiate a read-modify-write operation, overriding transmission of a read instruction.

[0184] However, in some examples described herein, the cache controller 220 can transmit a write instruction to write 130 data bits (or any write instruction that indicates a write to a subset of memory banks). Of the 130 data bits, 64 data bits can be written to a first bank, 64 data bits can be written to a second bank, and 2 data bits can be written to a third bank of the main memory area (e.g., a write instruction that indicates a write of a 130-bit word starting at a first address of the first bank and ending at a second address of the third bank). In this example, the bank processing logic 303 detects that all addresses of the first and second banks of the main memory area 214 are to be written to in full, and thus instructs the cache controller to initiate a read-modify-write operation for the first and second banks of the main memory area, overriding the transmission of a read instruction. In this example, the bank processing logic 303 can detect (e.g., determine) that a subset of memory banks of the main memory area 214 (e.g., the third bank of the memory area) are to be written to in part (e.g., two of 64 addresses are to be written to), and thus instructs the cache controller 220 to initiate a full read-modify-write operation for the third bank of the main memory area 214. In examples described herein, the bank processing logic 303 determines whether to enable a read operation to be performed (e.g., whether to initiate a full read-modify-write operation) in response to a write operation based on whether a number of addresses in the subset of the plurality of memory banks to be written to satisfies a threshold. In examples described herein, the threshold is not satisfied when the number of addresses in the subset of the plurality of memory banks is greater than 0 and / or less than a number of addresses in the memory. In this example, the bank processing logic 303 generates an indication to the CPU 102 to execute the write instruction as a full read-modify-write transaction. In examples described herein, the threshold is satisfied when the number of addresses in the subset of the plurality of memory banks is equal to a number of addresses in the memory bank. In this example, the bank processing logic 303 generates an indication to the CPU 102 to execute the write instruction as a partial read-modify-write transaction (e.g., overrides a read). Examples of read-modify-write operations are described above.

[0185] Example methods, apparatus, systems, and articles of manufacture are described herein for reducing read-modify-write cycles of misaligned writes. Other examples and combinations thereof include the following:

[0186] Example 1 includes a device comprising: a memory including a plurality of memory banks; an interface configured to be coupled to a central processing unit, the interface to obtain a write operation from the central processing unit, wherein the write operation is to write to a subset of the plurality of memory banks; bank processing logic coupled to the interface and the memory, the bank processing logic to determine the subset of the plurality of memory banks to write to based on the write operation, and to determine whether to perform a read operation in response to the write operation based on whether a number of addresses in the subset of the plurality of memory banks to write to satisfies a threshold.

[0187] Example 2 includes the device of Example 1, wherein the threshold is satisfied when all addresses of the at least one of the plurality of memory banks of the number are included in the write operation.

[0188] Example 3 includes the device of Example 1, wherein the bank processing logic is to generate a second indication to the central processing unit to perform the write operation to the at least one of the plurality of memory banks of the number that issued the read operation when a number of addresses of the at least one of the plurality of memory banks of the number to write to does not satisfy the threshold.

[0189] Example 4 includes the device of Example 1, wherein the bank processing logic is to determine a number of the plurality of memory banks to write to based on the write operation by determining a total number of addresses included in the write operation and determining the number of the plurality of memory banks based on addresses having addresses included in the total number of addresses.

[0190] Example 5 includes the device of Example 1, wherein the write operation indicates a number of the plurality of memory banks to rewrite.

[0191] Example 6 includes the device of Example 1, wherein the plurality of memory banks is sixteen memory banks.

[0192] Example 7 includes the device of Example 1, wherein the memory is a victim storage area.

[0193] Example 8 includes a system comprising: a central processing unit configured to generate a write operation indicating a write to a subset of a plurality of memory banks; a victim storage area including the plurality of memory banks; and bank processing logic coupled to the central processing unit and the victim storage area, the bank processing logic to determine the subset of the plurality of memory banks to write to based on the write operation, and to determine whether to perform a read operation in response to the write operation based on whether a number of addresses in the subset of the plurality of memory banks to write to satisfies a threshold.

[0194] Example 9 includes the system of example 8, wherein the threshold is satisfied when all addresses of the at least one of the number of the plurality of memory banks are included in the write operation.

[0195] Example 10 includes the system of example 8, wherein the bank processing logic is to generate a second indication to the central processing unit to perform the write operation to the at least one of the number of the plurality of memory banks from which the read operation was issued when a number of addresses of the at least one of the number of the plurality of memory banks to be written to does not satisfy the threshold.

[0196] Example 11 includes the system of example 10, wherein the central processing unit is further to generate a read-modify-write operation for execution by the at least one of the number of the plurality of memory banks in response to the second indication.

[0197] Example 12 includes the system of example 8, wherein the bank processing logic is to determine the number of the plurality of memory banks to be written to based on the write operation by determining a total number of addresses included in the write operation and determining the number of the plurality of memory banks based on addresses having addresses included in the total number of addresses.

[0198] Example 13 includes a method comprising determining a subset of a plurality of memory banks of a memory to be written to based on a write operation and determining whether to perform a read operation in response to the write operation based on whether a number of addresses in the subset of the plurality of memory banks to be written to satisfies a threshold.

[0199] Example 14 includes the method of example 13, further comprising transmitting an indication to a central processing unit in response to the threshold being satisfied.

[0200] Example 15 includes the method of example 13, wherein the threshold is satisfied when all addresses of the at least one of the number of the plurality of memory banks are included in the write operation.

[0201] Example 16 includes the method of example 13, further comprising generating a second indication to perform the write operation to the at least one of the number of the plurality of memory banks from which the read operation was issued when a number of addresses of the at least one of the number of the plurality of memory banks to be written to does not satisfy the threshold.

[0202] Example 17 includes the method of example 13, wherein determining the number of the plurality of memory banks to be written to is performed by determining a total number of addresses included in the write operation and determining the number of the plurality of memory banks based on addresses having addresses included in the total number of addresses.

[0203] Example 18 includes the method according to Example 13, wherein the write operation indicates the number of the plurality of memory groups to be rewritten.

[0204] Example 19 includes the method according to Example 14, further comprising obtaining the write operation from the central processing unit, the write operation indicating the number of the plurality of memory groups to be written.

[0205] Example 20 includes the method according to Example 14, wherein the memory is a victim storage area.

[0206] Figure 4D

[0207] exist Figure 4D In this example, the instance primary cache queue 212 stores several write operations at different sections of the primary cache queue 212 (e.g., at instance latches 402a-e). For example, when CPU 102 transmits three separate write operations in a row, the first write operation provided by CPU 102 is stored at the first latch 402b, and moves to the second latch 402c when the second operation is received at the first latch 402b. Therefore, after receiving the three write operations, the first latch 402b will store and / or output the last write operation in time (e.g., its last storage in main memory 214), the second latch 402c will have the second write operation (e.g., its second storage in main memory 214), and the third latch 402d will have the first write operation (e.g., its first storage in instance main memory 214). Whenever data in the primary cache queue 212 is to be stored in the main memory 214, the instance arbitration manager 414 maintains a cycle for data to be written to the instance main memory 214. Therefore, during this reserved cycle, the main memory 214 may not be available for read operations. However, if two or more data operations stored in latches 402b, 402c, and 402d correspond to the same memory address, the data can be merged so that the data is written to the memory address in the main memory 214 once, instead of twice or three times. For example, if a write operation stored in latch 402d corresponds to writing a byte to a memory address and a write operation stored in latch 402c corresponds to writing the same byte to a memory address, then the second write will overwrite the first write.

[0208] The primary cache storage queue 212 combines the two writes into one write such that only one cycle is used to write the second transaction (e.g., freeing up the cycle reserved for the first write), rather than reserving a cycle to write the first byte into the primary storage 214, which will be overwritten in a subsequent cycle. Such aggressive combining reduces the number of cycles reserved for write operations. In this way, the primary storage 214 will have an extra cycle to perform read operations, thereby reducing latency of the overall system.

[0209] To enable aggressive combining of write operations to the same memory address, the outputs of the example latches 402b-402d are coupled to example combining circuits 403a-403c. For example, the output of the third latch 402d can be coupled to combining circuit 403a, the output of the second latch 402c can be coupled to combining circuit 403b, and the output of the first latch 402b can be coupled to combining circuit 403c. The output of combining circuit 403a can additionally be coupled to the output of the second latch 402c and combining circuit 403b, combining circuit 403b can be coupled to combining circuit 403c, and combining circuit 403c can be coupled to the input of the first latch 402b. Additionally or alternatively, there can be additional comparator circuits for comparing the outputs of another set of latches (e.g., a comparator circuit for comparing the output of latch 402b to the output of latch 402d). The example combining circuits 403a-c include an example comparator 420 and an example switch 422.

[0210] The comparator 420 compares the memory address locations of each write operation stored in the respective latches 402b-402d to determine whether any of the write operations in the example storage queue correspond to the same memory address. The example comparator 420 can be one comparator that compares all of the write operations of latches 402b-402d, or can be separate comparators 420 that compare two of latches 402b-d (e.g., a first comparator that compares the memory address of latch 402b to the memory address of latch 402c, a second comparator that compares the memory address of 402b to the memory address of latch 402d, etc.). The comparator 420 outputs the comparison result (e.g., with one or more signals corresponding to the one or more comparisons) to the example switch 422 and / or the arbitration manager 414. If the example arbitration manager 414 receives a signal indicating a match, the arbitration manager 414 will not reserve a cycle for the first write operation while the first write operation is combined with the second write operation to the same memory location (e.g., freeing up the cycle for other cache operations).

[0211] Instance switch 422 reroutes write operations in instance latches 402b-402d based on comparison. For example, if the memory address of a write operation stored in instance latch 402d is the same as the memory address stored in latch 402c, then instance switch 422 enables and / or disables rerouting the output of latch 402d to latch 402c instead of to instance arbitration manager 414. In this way, the two write operations are combined and written to main memory 214 as a single write operation instead of two write operations in subsequent cycles. Switch 422 can be an electrical switch, a transistor (e.g., MOSFET), a demultiplexer, and / or any other component that can reroute signals in the circuit.

[0212] When one of the MUXs in the merging circuits 403a-c receives a rerouted write operation, the MUX executes a merging protocol for the one or more rerouted write operations, prioritizing the latest write operation. For example, if comparator 420 determines that a write operation stored in instance latch 402c corresponds to the same memory address as a write operation stored in instance latch 402d, then the MUX of comparator 420 merges the data (such as combined) Figure 4D (Further description), and switch 422 reroutes the merged write operations stored in instance latch 402d to latch 402c. In this example, if a write operation in instance latch 402c corresponds to writing data to byte 0 and byte 2 of memory address and a write operation from latch 404d corresponds to writing data to byte 0 and byte 1, then instance merging circuit 403a merges the two write operations to retain the write data stored in latch 402c (e.g., writes to byte 0 and byte 2) and includes non-overlapping write data from latch 402d (e.g., byte 2). In this example, as part of the merging operation, merging circuit 403a discards the write data of byte 0 from latch 404d because the data to be written to byte 0 of latch 404d will be overwritten by the write instruction of latch 402c. Therefore, in the above example, the merged data corresponds to the write data of byte 0 from latch 402c, the write data of byte 1 from latch 404d, and the write data of byte 2 from latch 402c. When subsequent write operations are added to the main cache storage queue 212, the merged write data from latch 402c can be manipulated (e.g., via one of instance blocks 404, 406, 408) and / or pushed to the next latch 402d for storage in the instance main memory area 214 during subsequent cycles. An instance hardware implementation of the merging protocol is described below in conjunction with... Figure 4A Further description.

[0213] Figure 11A Show Figure 4D The merging circuit 402c and / or Figure 4A A hardware implementation of 1102c (e.g., for merging data from latch 402d into latch 402c). Similar hardware setups may be implemented to merge data between any two latches. Figure 4A The instance includes instance latches (e.g., memory areas) 402b-402d and is used for... Figure 11A The hardware components of comparator 420 and switch 422. Example comparator circuit 420 includes comparator and / or logic gates 480a-480f, and switch circuit 422 includes OR gate 482 and MUX 484. Although combined... Figure 11A Describe it, but if combined Figure 4D The victim cache storage queue 216 is described, then it can be used Figure 4D The latches 1102a-d, the instance comparator 1120, and the instance switch 322.

[0214] exist Figure 4C In one instance, instance latch 402d outputs the stored data to instance storage (e.g., via arbitration managers 414, 1114 to main storage 214 or victim storage 218), and locks its group in the first cycle. Optimized atomic and histogram operation support in L1 cache This illustrates how, when writing old data to a group of memory areas merged together, the old data is locked to the same address before another memory area / latch containing the newly written data. Although Figure 4A The example illustrates the merging between instance latch 402d and instance latch 402c, but a similar structure can be used to merge data between any of latches 402a-402d. For example, if the data address at latch 402d matches the data address at latch 402b, then latch 402 can merge its data with the data at latch 402b. Furthermore, if data at three or more latches corresponds to the same address, then the data at those three or more latches can be merged into a single latch. As described above, if data at a particular latch is merged with data at a previous latch, then the data at that particular latch is invalidated (e.g., by setting bits to correspond to invalidated values) or discarded, so that arbitration is not performed on the data to lock it into a set in memory.

[0215] In operation, the example comparator 480b compares the address of the data at latch 402d to the address of the data at latch 403c. The output of comparator 480b is valid only when both latches 402c and 402d contain bits set to valid. Thus, the example comparator 480a compares the valid bits from latches 402c, 402d to ensure that both bits are valid. In this way, the example comparator 480d outputs a value (e.g., '1') only when the address at latch 402c and the address at latch 402d are the same and the valid bits of both latches 402c, 402d are valid. Otherwise, the example comparator 480d outputs a second value ('0'). The output of comparator 480d is input to the select line of MUX 484 of switch 422. Thus, if the addresses of latches 402c, 402d are the same value, then comparator 480d will control MUX 484 of switch 422 to output the merged data (e.g., from OR gate 482 of switch 422).

[0216] The example ADD gate 480c performs a logical AND function (e.g., using NOT gates) with the byten of latch 402d but not with the byten of latch 402c. The output of example ADD gate 480c ensures that if there is a byte written through both latches 402c and 402d, then latch 402c is kept and latch 402d is ignored because latch 402c has the most recent store issued by CPU 102. Thus, the example comparator 480f outputs only the most recent store issued by CPU 102 for the address in the store queue. The output of comparator 480f corresponds to dram_mrg_data_sel[7:0], which is a signal used to select the last merged data between logical gate 402d and logical gate 402c on a byte-by-byte basis. There is similar merging logic when merging the byten of latch 402c and latch 402d. The signal labeled (1) is used to select between store_byten or store3_byten (which is merged with store_4_byten) as described above.

[0217] Example methods, apparatus, systems, and articles of manufacture are described herein for facilitating aggressive write merging to reduce group pressure. Other examples and combinations thereof include the following. Example 1 includes an apparatus comprising a first cache storage area, a second cache storage area, a store queue coupled to at least one of the first cache storage area and the second cache storage area and operable to receive a first memory operation, process the first memory operation to store a first set of data in at least one of the first cache storage area and the second cache storage area, receive a second memory operation, and merge the first memory operation and the second memory operation prior to storing the first set of data in the at least one of the first cache storage area and the second cache storage area.

[0218] Example 2 includes the apparatus of Example 1, wherein the first memory operation specifies a first set of data, the second memory operation specifies a second set of data, and the store queue is operable to merge the first set of data and the second set of data to produce a third set of data prior to storing the first set of data in the at least one of the first cache storage area and the second cache storage area, and provide the third set of data for storage in at least one of the first cache storage area and the second cache storage area.

[0219] Example 3 includes the apparatus of Example 2, wherein the store queue is operable to store the third set of data in the at least one of the first cache storage area or the second cache storage area in one cycle.

[0220] Example 4 includes the apparatus of Example 1, wherein the store queue is operable to merge the first memory operation and the second memory operation by canceling a portion of the first memory operation.

[0221] Example 5 includes the apparatus of Example 4, wherein the portion of the first memory operation is a byte to which the second memory operation is to write.

[0222] Example 6 includes the apparatus of Example 4, wherein the portion is a first portion, and the store queue is operable to merge the first memory operation and the second memory operation by retaining a second portion of the first memory operation.

[0223] Example 7 includes the apparatus of Example 6, wherein the second portion of the first memory operation is a byte to which the second memory operation does not write.

[0224] Example 8 includes the apparatus of Example 1, wherein the first cache storage is a primary cache storage and the second cache storage is a victim cache storage.

[0225] Example 9 includes a system comprising: a central processing unit coupled in parallel to a first cache storage and a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to process a first memory operation from the central processing unit for storing a first set of data in at least one of the first cache storage and the second cache storage and to merge the first memory operation and a second memory operation corresponding to a same memory address prior to storing the first set of data in the at least one of the first cache storage and the second cache storage.

[0226] Example 10 includes the system of Example 9, wherein the first memory operation specifies a first set of data, the second memory operation specifies a second set of data, and the store queue is operable to merge the first set of data and the second set of data to produce a third set of data prior to storing the first set of data in the at least one of the first cache storage and the second cache storage and to provide the third set of data for storage in at least one of the first cache storage and the second cache storage.

[0227] Example 11 includes the apparatus of Example 10, further comprising a store queue operable to store the third set of data in the at least one of the first cache storage or the second cache storage in one cycle.

[0228] Example 12 includes the system of Example 9, wherein the store queue is operable to merge the first memory operation and the second memory operation by canceling a portion of the first memory operation.

[0229] Example 13 includes the system of Example 12, wherein the portion of the first memory operation is a byte to which the second memory operation is to write.

[0230] Example 14 includes the system of Example 12, wherein the portion is a first portion, the store queue is operable to merge the first memory operation and the second memory operation by retaining a second portion of the first memory operation.

[0231] Example 15 includes the system of Example 14, wherein the second portion of the first memory operation is a byte to which the second memory operation does not write to

[0232] Example 16 includes the system of example 9, wherein the first cache storage region is a primary cache storage region and the second cache storage region is a victim cache storage region.

[0233] Example 17 includes a method comprising obtaining a first memory operation, processing the first memory operation by executing an instruction with a processor to store a first set of data in at least one of a first cache storage region and a second cache storage region, obtaining a second memory operation, and merging the first memory operation and the second memory operation by executing an instruction with the processor prior to storing the first set of data in the at least one of the first cache storage region and the second cache storage region.

[0234] Example 18 includes the method of example 17, wherein the first memory operation corresponds to a first set of data and the second memory operation corresponds to a second set of data, the method further comprising merging the first set of data and the second set of data to generate a third set of data prior to storing the first set of data in the at least one of the first cache storage region and the second cache storage region, and providing the third set of data for storage in at least one of the first cache storage region and the second cache storage region.

[0235] Example 19 includes the method of example 18, further comprising storing the third set of data in the at least one of the first cache storage region or the second cache storage region in one cycle.

[0236] Example 20 includes the method of example 17, further comprising merging the first memory operation and the second memory operation by canceling a portion of the first memory operation.

[0237] Figure 4B

[0238] Atomic operations are other examples of multi-part memory operations. For example, an atomic compare-and-swap operation manipulates a value stored at a memory location based on a comparison of an existing value stored at the memory location. For example, if the existing value stored in the LI cache 110 matches a particular value, the CPU 102 can want to replace the data stored in the LI cache 110 with a new value.

[0239] In some example systems, when a CPU wants to perform an atomic operation, the CPU sends a read operation to a memory address, performs manipulations on the read data, and then performs a write operation to the same memory address to store the manipulated data. Also, in such example systems, the LI cache stalls, denies, prevents, and / or interrupts any transactions from other devices (e.g., other cores of the CPU, higher level caches, expanded memory, etc.) until the atomic operation is complete (e.g., to avoid manipulating the memory address corresponding to the atomic operation during the atomic operation). Thus, such example techniques require a significant amount of work on behalf of the CPU and require a significant reservation loop, which increases latency.

[0240] In Figure 4C In examples, the example primary cache store queue 212 handles atomic operations in conjunction with read-modify-write structures. In this way, the example CPU 102 can send a single atomic operation to the LI cache 110, and the primary cache store queue 212 handles the atomic data manipulation and write operation. Thus, the CPU 102 uses a single loop to perform the atomic operation, and can use other loops (e.g., for some example atomic protocols) to perform other functions, thereby reducing latency of the overall computing system 100.

[0241] In operation, when the CPU 102 transmits an atomic operation and / or an atomic compare-and-swap operation to increment data at a memory address by a value of 1 and / or to swap, for example, the atomic instruction is received by the latch 402a and the tag RAM 208 verifies whether the memory address is stored in the instance main storage area 214. If the memory address is stored in the instance main storage area 214, the tag RAM 208 instructs the instance main storage area 214 to output the data at the memory address while the atomic instruction is passed to the instance latch 402b. When the main storage area 214 outputs the data to the latch 322a, the instance latch 402b outputs the atomic operation to the latch 402c. At this point, the ECC logic 310 performs an error detection and / or correction protocol as described above and the data from the memory address location is forwarded to the instance arithmetic component 404 (e.g., for an atomic operation) or the atomic compare component 406 (e.g., for an atomic compare-and-swap operation). The arithmetic component 404 obtains the atomic operation (e.g., including data identifying how to manipulate the data) and / or the atomic compare-and-swap 406 obtains the atomic compare-and-swap operation (e.g., including a key and data to be written in the event the key matches the read data) from the latch 402c and the data from the corresponding memory address from the output of the ECC logic 310. The arithmetic component 404 performs the data manipulation (e.g., increments the data by 1) and / or the atomic compare component 406 can perform the swap (replaces the data in the event the read data matches the key, etc.) and outputs the incremented and / or swapped-in data (e.g., the atomic result) to the instance latch 402d via the instance MUX 410 to the corresponding memory address (e.g., which is enabled via the cache controller 220). The latch 402d outputs the new data corresponding to the memory address to the ECC generator 412 to generate the ECC bits and the arbiter manager 414 writes the new data (e.g., the atomic result and / or the atomic compare-and-swap result) to the memory address in conjunction with the ECC bits in the instance main storage area 214. Additionally or alternatively, a correction value outside of the EDD logic 412 is returned to the CPU 102. Thus, the atomic operation is performed with only one instruction from the CPU 102.

[0242] The atomic compare component 406 and / or the arithmetic component 404 has several inputs. For example, the atomic component 406 receives (e.g., obtains) the type of atomic operation to perform (e.g., atomic compare-and-swap or atomic swap), the new data to swap in, the ECC correction data read out from the cache 310, and the size of the data to manipulate during the atomic operation (e.g., 32 bits or 64 bits). In Figure 4CIn the example circuit implementation 450, the atomic compare component 406 receives atomic compare and exchange operations, and the arithmetic component 404 receives atomic operations. The atomic compare component 406 compares a compare value (e.g., a key) provided by the CPU 102 to the ECC data 310. Upon a match, new data replaces old data (e.g., ECC data 310) and is output to the MUX 410. The size of the new data that is swapped in is determined by the cas_acc_sz input (e.g., 32 bits or 64 bits). In Figure 4C In the example circuit implementation 450, the atomic compare component 406 can also receive atomic exchange operations. The atomic compare component 406 replaces the new data for the ECC data 310 regardless of the compare result and outputs the new value to the mux 410, old data from the main storage 214 is read from the address and provided back to the CPU 102. The size of the new data that is swapped in is determined by the cas_acc_sz input (e.g., 32 bits or 64 bits). In Figure 11A In the example circuit implementation 450, the arithmetic component 404 can also receive atomic operations. The arithmetic component 404 manipulates the ECC data 310 and stores the manipulated data in the main storage element 214. The size of the new data that is swapped in is determined by the cas_acc_sz input (e.g., 32 bits or 64 bits). Although Figure 4C The example circuit 450 is described above in connection with the main cache storage queue, but the circuit 450 can be described in connection with the victim cache storage queue, as described below in connection with Figure 4A Further described below.

[0243] Figure 11A An example circuit diagram is shown that illustrates Figure 4C a portion of the main cache storage queue 212 of the CPU 102 and / or Figure 4C a portion of the victim cache storage queue 216 of the CPU 102. Figure 4C A detailed circuit diagram is shown that illustrates the arithmetic unit 404, 1104.

[0244] Arithmetic unit 404 can be used for other types of memory transactions, such as histogram operations. Histogram operations retrieve values ​​from blocks stored in memory that represent histograms, and then modify the values ​​before storing them back at the same memory address or an alternative address. In an example, the first dataset contains the values ​​[0,0,2,0,0,3], and the second dataset contains blocks representing the number of occurrences of the corresponding values ​​within the first dataset. In some instance systems without arithmetic unit 404, to perform the histogram function, the CPU reads each value from the first dataset and increments the second dataset for each value. For example, to determine how many zeros are stored in a 10-byte dataset, the CPU might perform 10 reads. Then, to determine how many 1s are in the same dataset, the CPU would perform an additional 10 reads. Therefore, to perform histogram operations, such systems might require (N)(M) reads, where N is the size of the memory segment read (e.g., 10 bytes) and M is the number of values ​​that can be stored in each byte. Similar to atomic operations, L1 SRAM may need to block, pause, interrupt, discard, etc., all other read and / or write operations until the histogram operation is complete. In contrast, arithmetic unit 404 can be used to perform the same operation using a single transaction from the CPU.

[0245] Arithmetic units 404 and 1104 have several inputs, including the type of histogram (e.g., weighted or augmented, signed or unsigned), histogram size (e.g., byte, half-word, or word), histogram weights (e.g., signed weights to be added for each selected block group of a weighted histogram, or weights equal to one for a normal histogram), histogram sign (e.g., existing bits, signed or unsigned), and histogram saturation enabled.

[0246] Figure 4A Component 451 is for SaturationThe block group selection shown is read from ECC component 310. Component 452 selects weights to add to the block group from a weight vector provided by CPU 102. Cnt_value is the sum of the block group value from component 451 and the weights provided by CPU 102. Components 453, 454, and 458 serve as parts of the saturation circuit. Component 453 receives the histogram size (byte, half-word, or word) and a count value (the sum of the outputs of components 451 and 452) and determines whether the signed block group will saturate. Component 454 receives the histogram size (byte, half-word, or word) and a count value (the sum of the outputs of components 451 and 452) and determines whether the unsigned block group will saturate. The outputs of components 453 and 454 are sent to the MUX, which selects whether to use a signed saturation value or an unsigned saturation value based on the selected block group type (e.g., signed or unsigned). Component 458 receives the output of the MUX, histogram saturation enable, histogram type (e.g., signed or unsigned), sign bit of the block group, and sign bit of the weights, and outputs an updated cnt_value adjusted for the selected saturation type (e.g., based on Table 1 above). Components 455, 456, and 457 are used to position the resulting cnt_value and byte enable in the correct bit positions to write the new data group to the correct block group.

[0247] exist Saturation In this example, CPU 102 instructs main memory 214 to perform a histogram operation. This reduces the number of loops that CPU 102 must reserve for the operation from (N)(M) to 1. Furthermore, because the atomic operation protocol is already implemented in the memory queue, the histogram operation can be performed using arithmetic component 404 by performing N reads for the memory size N and incrementing the count for each value in the instance's main cache memory queue 212, thereby reducing the number of read operations from (N)(M) to N operations.

[0248] In operation, when the CPU 102 issues a histogram operation for a segment (e.g., SRAM row) corresponding to the main storage 214, the histogram operation is stored in the instance latch 402a while the tag RAM 208 verifies that the memory address corresponding to the histogram operation is available in the main storage 214. The instance cache controller 220 facilitates read operations of each byte of the segment identified in the histogram operation (e.g., where the histogram block group is accessed in parallel by reading up to 128 bytes at a time). If available, the tag RAM 208 instructs the main storage 214 to output the data at the first byte of the segment of the main storage 214 while the histogram operation is output by the instance latch 402a to the instance latch 402b. As the instance main storage 214 outputs the data that has been read from the memory address to the instance latch 322a, the latch 402b outputs the histogram operation to the instance latch 402c. After the ECC logic 310 performs the error detection and correction functions, the data read at the byte is sent to the instance arithmetic component 404.

[0249] After receiving the read value from the ECC logic 310 and the histogram instruction from the latch 402c, the arithmetic component 404 initiates data representing a histogram. For example, the arithmetic component 404 can initiate a vector (e.g., representing a histogram) having an initial value (e.g., zero) for each possible value that can be stored in a byte of the main storage. The arithmetic component 404 increases the value of the vector based on the output of the ECC logic 310 (e.g., the read byte). For example, if the read value of the byte is 0, then the arithmetic component 404 increases the value in the vector corresponding to 0.

[0250] Because each vector is increased in parallel, the resulting vector corresponds to a histogram of the values that have been read in parallel in the corresponding segment of the SRAM. Because the values of the histogram are increased for each bit, the resulting vector is a histogram of the values stored in the segment of memory identified in the histogram operation from the CPU 102. In some instances, the arithmetic component 404 can increase a certain weighted value (e.g., 1.5) in parallel. Upon completion, the instance histogram is input to the instance MUX 418 (e.g., controlled by the instance pending memory address table 416) that has been input to the MUX 314 by the instance latch 402e. Once the operation is complete, the instance cache controller 220 controls the MUX 314 to output the final histogram vector to the instance CPU interface 202 via the instance latch 322b, thereby ending the histogram operation.

[0251] In some instances, the Ll cache 110 supports functionality where a histogram block group can saturate after the histogram block group contains a block group bin size (e.g., bytes, half-words, words, etc.) that is greater than a threshold limit. Table 1 below shows an example of the saturation values. Using this functionality, the histogram block group values do not roll over once the maximum value is reached.

[0252] Table 1 - Histogram Saturation Values

[0253] Non-saturation ]]> ​ Non-saturation ]]> ​ Min ]]> ​ Max ]]> ​ Min ]]> ​ Max ]]> ​ Bytes ]]> ​ Signed ]]> ​ 0x7F ]]> ​ 0x7F ]]> ​ 0x80 Bytes 0x80 Unsigned 0xFF ]]> ​ 0xFF ]]> ​ 0x0 Halfword 0x0 Signed 0x7FFF ]]> ​ 0x7FFF ]]> ​ 0x8000 Halfword 0x8000 Unsigned 0xFFFF ]]> ​ 0xFF ]]> ​ 0x0 Word 0x0 Signed 0x7FFF_FFFF ]]> ​ 0x7FFF_FFFF ]]> ​ 0x8000_0000 Atomic compare and swap support in L1 cache of a coherent system 0x8000_0000 Figures 3A-3D

[0254] Example methods, apparatus, systems, and articles of manufacture are described herein for facilitating optimized atomic and histogram operations. Other examples and combinations thereof include the following. Example 1 includes a system comprising a cache storage coupled to an arithmetic component and a cache controller coupled to the cache storage, wherein the cache controller is operable to receive a memory operation specifying a set of data, retrieve the set of data from the cache storage, determine a set of counts of respective values in the set of data using the arithmetic component, generate a vector representing the set of counts, and provide the vector.

[0255] Example 2 includes the system of Example 1, wherein the cache controller is operable to provide the vector for storage in the cache storage.

[0256] Example 3 includes the system of Example 1, wherein the cache controller is operable to provide the vector to a processor.

[0257] Example 4 includes the system of Example 1, further comprising a store queue coupled to the cache controller, the store queue including the arithmetic component.

[0258] Example 5 includes the system of Example 1, wherein the cache storage is at least one of a home cache storage or a victim cache storage.

[0259] Example 6 includes the system of Example 1, wherein the arithmetic component is to: (a) obtain the set of data from the cache storage via an error detection and correction circuit, and (b) obtain the memory operation from a central processing unit via a latch.

[0260] Example 7 includes the system of Example 1, wherein the cache controller is operable to provide the vector to a central processing unit based on a single instruction from the central processing unit in a single cycle.

[0261] Example 8 includes a system comprising a cache storage, and a cache controller and an arithmetic component coupled to the cache storage, wherein the cache controller is operable to receive a memory operation specifying a first set of data and an arithmetic operation, retrieve the first set of data from the cache storage, perform the arithmetic operation on the first set of data using the arithmetic component to produce a second set of data, and provide the second set of data.

[0262] Example 9 includes the system of example 8, wherein the cache controller is operable to provide the second set of data for storage in the cache storage.

[0263] Example 10 includes the system of example 8, wherein the cache controller is operable to provide the second set of data to a processor.

[0264] Example 11 includes the system of example 8, further comprising a store queue coupled to the cache controller, the store queue including the arithmetic component.

[0265] Example 12 includes the system of example 8, wherein the cache storage is at least one of a home cache storage or a victim cache storage.

[0266] Example 13 includes the system of example 8, wherein the arithmetic component is to: (a) obtain the first set of data from the cache storage via an error detection and correction circuit, and (b) obtain the memory operation from a central processing unit via a latch.

[0267] Example 14 includes the system of example 8, wherein the cache controller is operable to provide the second set of data to a central processing unit based on a single instruction from the central processing unit in a single cycle.

[0268] Example 15 includes a method comprising: obtaining a memory operation specifying a set of data, obtaining the set of data from a cache storage, determining a set of counts of respective values in the set of data, generating a vector representing the set of counts, and providing the vector.

[0269] Example 16 includes the method of example 15, wherein the vector is provided to the cache storage.

[0270] Example 17 includes the method of example 15, wherein the vector is provided to a processor.

[0271] Example 18 includes the method of example 15, wherein the cache storage is at least one of a home cache storage or a victim cache storage.

[0272] Example 19 includes the method of example 15, further comprising: (a) obtaining the set of data from the cache storage via an error detection and correction circuit, and (b) obtaining the memory operation from a central processing unit via a latch.

[0273] Example 20 includes the method of example 15, wherein the providing the vector to a central processing unit is based on a single instruction from the central processing unit in a single cycle.

[0274] Method and apparatus for in-flight data forwarding and invalidation of pending writes in store queue

[0275] If data from a certain address is stored in the LI cache 110, data for the same address can also be cached in other caches (e.g., the L2 cache 112 and / or the L3 cache 114). Thus, memory addresses need to be tracked and / or monitored to ensure that any changes to data in one cache are identified, tracked, and / or reflected to other caches (e.g., the L2 cache 112 and the L3 cache 114). As described above in connection with Figure 5 The example MESI RAM 300 tracks the state of data stored in the main storage 214 so as to be able to avoid the problem of data mismatch in different caches corresponding to the same memory address. For example, if the CPU 102 transmits a read operation, the example MESI RAM 300 changes the state of the memory address to shared because the data in the memory address will not be manipulated. If the CPU 102 transmits a write operation, the example MESI RAM 300 changes the state of the memory address to exclusive because the data in the memory address will be manipulated and the main storage 214 needs write permission for the address. After the data in the memory address is written to the main storage 214, the MESI RAM 300 updates the state of the memory address to modified (e.g., indicating that the memory address has been modified).

[0276] As described above, during atomic and / or histogram protocols, data from a certain memory address is read from the main storage 214 and provided to the primary cache storage queue 212 for updating (e.g., incrementing) and written back into the main storage 214. However, if the MESI RAM 300 has identified the state of the corresponding memory address to be in the shared state, the write operation of the atomic protocol can cause problems with other level caches (e.g., because the write will mismatch the data in different caches).

[0277] To avoid such data mismatches during atomic operations (e.g., atomic compare-and- swap inclusive), the instance cache controller 220 flags a cache hit corresponding to a shared state as a cache miss. In this way, the cache controller 220 can instruct the L2 interface 228 to send a cache miss to a higher level cache with an exclusive state request. In this way, the higher level cache can grant exclusive state to the Ll cache 110, and the Ll cache 110 can perform read and write operations as part of an atomic operation in response to receiving the granted exclusive state.

[0278] After a cache miss with an exclusive request is sent to a higher level cache and the higher level cache responds with write data and an exclusive response, the instance atomic operation logic 406 instructs the MESI RAM 300 to mark the data as modified. The data received from the L2 cache 112 is transferred into the primary cache storage queue 212 for storage in the primary storage area 214. Because the operation is an atomic operation (e.g., a regular atomic operation or an atomic compare-and-swap) or a histogram protocol, the data from the higher level cache is manipulated by the instance arithmetic component 404 and / or the instance atomic compare component 406 and stored in the instance primary storage area 215 via the instance ECC generator 412 and the instance arbiter manager 414.

[0279] Example methods, apparatus, systems, and articles of manufacture are described herein for facilitating atomic compare-and-swap. Other examples and combinations thereof include the following: Example 1 includes a system comprising a cache storage area, a cache controller coupled to the cache storage area, wherein the cache controller is operable to receive a memory operation specifying a key, a memory address, and a first set of data, retrieve a second set of data corresponding to the memory address, compare the second set of data to the key, based on the second set of data corresponding to the key, store the first set of data at the memory address, and based on the second set of data not corresponding to the key, complete the memory operation without storing the first set of data at the memory address.

[0280] Example 2 includes the system of Example 1, further including a store queue for the cache storage area, the store queue including: a latch for interfacing with a tag random access memory (RAM) to retrieve the second set of data from the cache storage area; an atomic compare component, the cache controller causing the atomic compare component to compare the second set of data with the key and discard the first set of data if the key does not match the second set of data; and an arbitration manager for storing the first set of data at the memory address in the cache storage area if the key matches the second set of data.

[0281] Example 3 includes the system of Example 1, wherein the cache storage area is at least one of a primary cache storage area or a victim cache storage area.

[0282] Example 4 includes the system of Example 2, wherein the latch is a first latch, the atomic compare component for: (a) obtaining the second set of data from the cache storage area via an error detection and correction circuit, and (b) obtaining the atomic compare and swap command from the first latch via a second latch.

[0283] Example 5 includes the system of Example 1, wherein the cache controller is operable to complete the memory operation based on a single instruction from a central processing unit in a single cycle.

[0284] Example 6 includes the system of Example 1, further including a modified, exclusive, shared, invalid (MESI) component for determining a state of the memory address of the memory operation, and the cache controller is operable to provide a miss instruction to another cache if the memory address of the memory operation corresponds to a shared state, the miss instruction including an exclusive state request.

[0285] Example 7 includes the system of Example 6, wherein the cache controller, after the exclusive state request from the other cache is granted, is to cause an arbitration manager to store the first set of data at the memory address in the cache storage area if the first data matches the key.

[0286] Example 8 includes the system of Example 6, wherein the cache controller, after the exclusive state request from the other cache is granted, is to cause a tag RAM to retrieve the second set of data from the memory address of the cache storage area.

[0287] Example 9 includes a store queue for a cache storage, the store queue comprising: a latch to retrieve a memory operation specifying a key, a memory address, and a first set of data, and to retrieve a second set of data corresponding to the memory address; and an atomic compare component to compare the second set of data to the key, cause the first set of data to be stored at the memory address based on the second set of data corresponding to the key, and complete the memory operation without causing the first set of data to be stored at the memory address based on the second set of data not corresponding to the key.

[0288] Example 10 includes the store queue of Example 9, wherein the cache storage is at least one of a home cache storage or a victim cache storage.

[0289] Example 11 includes the store queue of Example 9, wherein the latch is a first latch, the atomic compare component to: (a) obtain the second set of data from the cache storage via an error detection and correction circuit, and (b) obtain the atomic compare and swap command from the first latch via a second latch.

[0290] Example 12 includes the store queue of Example 9, wherein, if the first data matches the key, the store queue is to execute the atomic compare and swap command based on a single instruction from a central processing unit in a single cycle.

[0291] Example 13 includes the store queue of Example 9, further comprising: a modified, exclusive, shared, invalid (MESI) component to determine a state of the memory address of the memory operation; and an interface to provide a miss instruction to another cache when the memory address of the memory operation corresponds to a shared state, the miss instruction including an exclusive state request.

[0292] Example 14 includes the store queue of Example 13, further comprising an arbitration manager to store the first set of data at the memory address if the first data matches the key after the exclusive state request from the other cache is granted.

[0293] Example 15 includes the store queue of Example 13, wherein the latch is to interface with a tag RAM to read the second set of data after the exclusive state request from the other cache is granted.

[0294] Example 16 includes a method comprising: receiving a memory operation specifying a key, a memory address, and a first set of data, retrieving a second set of data corresponding to the memory address, comparing the second set of data to the key, based on the second set of data corresponding to the key, storing the first set of data at the memory address, and based on the second set of data not corresponding to the key, completing the memory operation without storing the first set of data at the memory address.

[0295] Example 17 includes the method of Example 16, further comprising: interfacing with a tag random access memory (RAM) to retrieve the second set of data from a cache storage area, comparing the second set of data to the key, and discarding the first set of data if the key does not match the second set of data, and storing the first set of data at the memory address in the cache storage area if the key matches the second set of data.

[0296] Example 18 includes the method of Example 17, further comprising: (a) obtaining the second set of data via an error detection and correction circuit, and (b) obtaining the memory operation from a central processing unit.

[0297] Example 19 includes the method of Example 16, wherein the completing the memory operation is based on a single instruction from a central processing unit in a single cycle.

[0298] Example 20 includes the method of Example 16, further comprising: determining a state of the memory address of the memory operation, and providing a miss instruction to another cache if the memory address of the memory operation corresponds to a shared state, the miss instruction including an exclusive state request.

[0299] Figure 1

[0300] In the examples described herein, when the CPU 102 issues a read operation, the tag RAM accesses 204, 206 determine whether the read operation hits the primary storage element 214 and / or the victim storage element 218. In examples where the tag RAM accesses 204, 206 determine that the read command misses the primary storage element 214 and the victim storage element 214, the cache controller 220 sends a create victim operation to the primary storage element 214 (e.g., to determine a line in the primary storage element 214 to evict). In some examples, an issue can arise when the primary storage element 214 evicts a line corresponding to a pending write. For example, a line in the primary storage element 214 that currently has data to be written through the store queue 212 can have a pending write located in any of the latches 402a-d. In some examples, an error can occur when a new address replaces a line in the primary storage element 214 that has been evicted and the store queue 212 is still attempting to write data from a previous write operation into the same line.

[0301] The examples described herein include a read invalidate operation issued to the store queue 212 when the cache controller 220 determines that the read operation is a read miss. When the primary storage element 214 creates a victim, the cache controller 220 sends a read invalidate operation to the store queue 212. The read invalidate operation notifies the store queue 212 to compare the address of the victim to all of the addresses stored in the latches 402a-d. If any of the addresses in the latches 402a-d match the address of the victim, the priority multiplexer 418 sends the data in the matching address to the latch 402e to transfer the data to the MUX circuit 314. Such an operation can be referred to as data forwarding of in-flight data. For example, when the priority multiplexer 418 sends the data corresponding to the victim to the MUX circuit 314 via the latch 402e, the MUX circuit 314 forwards the data of the victim to the victim storage element 218 and / or the L2 cache 112. Also, when the latches 402a-d include an address corresponding to the victim, the read invalidate operation invalidates the data stored in the latches 402a-d. For example, each of the latches 402a-d includes a valid tag. The valid tag indicates to the latches 402a-d whether data is to be stored in the primary storage element 214. When the read invalidate operation invalidates the valid tag, the latches 402a-d discontinue writing the invalid data to the primary storage element 214.

[0302] In an example operation, the CPU 102 issues a write operation. In some examples, the write operation corresponds to an address A.

[0303] For example:

[0304] Write operation = Write (Address A): Data 1 / / Write Data 1 to cache line corresponding to Address A

[0305] The store queue 212 obtains the write operation and begins the process of writing the data to address A of the primary storage element 214. In some instances, address A corresponds to cache line 1 in the primary storage element 214. Subsequently, the CPU 102 issues a read operation. In some instances, the read operation corresponds to address B. For example:

[0306] Read operation = read (address B) / / read data 2 in cache line corresponding to address B

[0307] The example tag RAM accesses 204, 206 check the addresses in the tag RAM 208 and the tag RAM 210 and determine that neither tag RAM 208, 210 contains address B. The cache controller 220 obtains a read miss result from the tag RAM accesses 204, 206 and issues an allocate operation to determine a victim in the primary storage element 214 to evict to the victim storage element 218 and / or the L2 cache 112. When the cache controller 220 obtains a response corresponding to a victim, the cache controller 220 issues a read invalidate operation to the store queue 212.

[0308] The read port 424 of the store queue 212 obtains the read invalidate operation and obtains the address of the victim. The read port 424 sends the address of the victim to the data store 416 to compare to all of the addresses stored in the latches 402a-d. If the data store 416 determines that any of the addresses stored in the latches 402a-d match the address of the victim, the data store 416 outputs an operation to the priority multiplexer 418 to send the data corresponding to the victim address to the latch 402e. The latch 402e forwards the data to the MUX circuit 314 to send to the victim storage element 218 and / or the L2 cache 112.

[0309] Also, in response to an address stored in the latches 402a-d matching the victim address, the latches 402a-d invalidate the data corresponding to the victim address. For example, the valid tag in the latches 402a-d is updated to indicate that the data in the latches corresponding to the victim address is invalid. In this example, the store queue 212 will not attempt to write the data to the cache line corresponding to the previous address that was evicted.

[0310] Example methods, apparatus, systems, and articles of manufacture for in-flight data forwarding and invalidation are described herein. Other examples and combinations thereof include the following:

[0311] Example 1 includes an apparatus comprising a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read invalidate command specifying the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and provide data associated with a second memory operation of the set of memory operations in response to the victim address matching a first address of the set of addresses corresponding to the second memory operation.

[0312] Example 2 includes the apparatus of Example 1, wherein the cache controller is to issue the read invalidate command upon a tag random access memory access issuing a read miss.

[0313] Example 3 includes the apparatus of Example 1, wherein the cache controller is to determine the victim address to evict from the cache storage to make room for data of a third memory operation.

[0314] Example 4 includes the apparatus of Example 1, wherein the cache controller is operable to stall writing data associated with the second memory operation in the cache storage.

[0315] Example 5 includes the apparatus of Example 1, further comprising a first latch, a second latch, a third latch, and a fourth latch, wherein the first latch, the second latch, the third latch, or the fourth latch is to store data of the victim address.

[0316] Example 6 includes the apparatus of Example 5, wherein the first latch, the second latch, the third latch, and the fourth latch comprise a valid tag that is to update to invalid when any of the first latch, the second latch, the third latch, or the fourth latch stores the data of the victim address.

[0317] Example 7 includes the apparatus of Example 1, further comprising a read port to initiate a comparison between the victim address and the set of addresses associated with the set of memory operations being processed by the cache controller when the read port obtains the read invalidate command and the victim address.

[0318] Example 8 includes a method of invalidating a write operation, the method comprising receiving a first memory operation, determining that the first memory operation corresponds to a read miss in a cache storage area, determining a victim address to evict in the cache storage area in response to the read miss, issuing a read invalidate command specifying the victim address, comparing the victim address to a set of addresses associated with a set of memory operations being processed by a cache controller, and providing data associated with a second memory operation of the set of memory operations in response to the victim address matching a first address of the set of addresses corresponding to the second memory operation.

[0319] Example 9 includes the method of example 8, further comprising issuing the read invalidate command when a tag random access memory access issues a read miss.

[0320] Example 10 includes the method of example 8, further comprising determining the victim address to evict from the cache storage area to make room for data of a third memory operation.

[0321] Example 11 includes the method of example 8, further comprising interrupting writing the data associated with the second memory operation in the cache storage area.

[0322] Example 12 includes the method of example 8, further comprising storing data of the victim address in at least one of a first latch, a second latch, a third latch, and a fourth latch.

[0323] Example 13 includes the method of example 12, further comprising updating a valid tag of the first latch, the second latch, the third latch, or the first latch to invalid when any of the first latch, the second latch, the third latch, and the fourth latch stores the data of the victim address.

[0324] Example 14 includes the method of example 8, further comprising initiating a comparison between the victim address and the set of addresses associated with the set of memory operations being processed by the cache controller when a read port obtains the read invalidate command and the victim address.

[0325] Example 15 includes a system comprising a central processing unit to output a first memory operation, a cache coupled to the central processing unit, the cache comprising a cache storage, a cache controller coupled to the cache storage and operable to receive the first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read invalidate command specifying the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation and invalidate the second memory operation.

[0326] Example 16 includes the system of Example 15, wherein the cache is a first cache, and wherein the first cache is operable to retrieve data associated with the first memory operation from a second cache in response to the cache storage not including the data associated with the first memory operation.

[0327] Example 17 includes the system of Example 15, wherein the cache comprises a store queue to store write data of the second memory operation into the cache storage over a plurality of clock cycles, each clock cycle to write at least one portion of the data associated with the second memory operation to the cache storage.

[0328] Example 18 includes the system of Example 17, wherein the cache is a first cache, and wherein the cache controller is operable to provide remaining portions of data in the store queue to a second cache for storage when the second memory operation is invalidated.

[0329] Example 19 includes the system of Example 15, wherein the cache comprises a store queue to store pending writes, the second memory operation corresponding to a pending write.

[0330] Example 20 includes the system of Example 15, wherein the central processing unit outputs the first memory operation after outputting the second memory operation. Figure 5 Example 21 includes the system of Example 20, wherein the cache controller is operable to provide the data associated with the first memory operation to the second cache for storage in response to the first memory operation being a read operation. Figure 5 Examples of a level one (LI) cache 110 of Figures 1, 2, and 3 are based on a victim cache segment. Figure 5It includes tag RAM 210, victim storage area 218, MESI RAM 300, instance hit / miss comparison logic 306a, 306b, 306c, instance replacement policy 308 (e.g., replacement policy component 308), instance address encoder 326a, 326b, 326c, instance multiplexer (MUX) 330a, 330b, 330c, instance address read 332a, 332b, 332c, instance scalar interface 502, instance vector interface 504, instance listening address component 506, and instance response multiplexer 508. Figure 1 This illustrates a victim cache system that supports dual data paths and a consistency pipeline.

[0331] exist Figure 5 In the context of the instance scalar interface 502, the scalar interface 502 is used to... Figure 1 The L1 cache 110 of the data cache 108 is coupled to an interface of the instance processing core 104a. In some instances, the scalar interface 502 is an interface corresponding to the first data path (DP0) in a dual-data-path victim cache system. In some instances, the scalar interface 502 is an interface corresponding to the second data path (DP1) in a dual-data-path cache system. The instance scalar interface 502 is a 64-bit wide bidirectional and / or unidirectional interface. Alternatively, the instance scalar interface 502 may support different numbers of bits (e.g., 32 bits, 128 bits, etc.). In some instances, the scalar interface 502 receives and / or obtains data from the core 104a. In some instances, the scalar interface 502 sends data from the victim memory 218 to the core 104a. The instance scalar interface 502 is coupled to the instance tag RAM 210 and compare logic 306 to compare the address from the CPU 102 with the address in the tag RAM 210.

[0332] exist Figure 2 In the context of the instance vector interface 504, the 504 is... Figure 5The LI cache 110 of the data cache 108 is coupled to the interface of the instance processing core 104a. In some instances, the vector interface 504 is the interface corresponding to the second data path (DP1) in a dual data path cache system. In some instances, the vector interface 504 is the interface corresponding to the first data path (DP0) in a dual data path cache system. The instance vector interface 504 is a 512-bit wide interface. Alternatively, the instance vector interface 504 can support a different number of bits (e.g., 256 bits, 1024 bits, etc.). In some instances, the vector interface 504 receives and / or obtains data from the core 104a. In some instances, the vector interface 504 sends data from the victim storage 218 to the core 104a. The instance vector interface 504 is coupled to the instance tag RAM 210, the snoop address component 506, and the comparison logic 306b to compare an address from the CPU 102 to an address from the tag RAM 210. In some instances, the scalar interface 502 and the vector interface 504 are implemented by the CPU interface 202 Figure 2 For example, the scalar interface 502 and the vector interface 504 can be included in the CPU interface 202.

[0333] In Figure 2 , the instance tag RAM 210 is connected to the instance interfaces 502, 504. However, in some instances, the tag RAM 210 can be coupled to the interfaces 502, 504 via the instance victim tag RAM access 206 Figure 5 The instance tag RAM 210 is a fully-associative tag RAM to support dual data paths (e.g., a scalar data path and a vector data path). As used herein, a fully-associative tag RAM 210 permits data from the main storage 214 Figure 5 to be stored in any cache block, rather than forcing each memory address into a particular block. In some instances, because the tag RAM 210 is fully-associative, the victim storage 218 is also fully-associative.

[0334] In Figure 2In particular, comparison logic 306a is connected to scalar interface 502, tag RAM 210, address encoder 326a, and replacement policy component 308. Comparison logic 306b is connected to vector interface 504, tag RAM 210, address encoder 326b, and replacement policy component 308. Comparison logic 306a, 306b supports scalar and vector data paths. For example, comparison logic 306 can compare scalar data to data of tag RAM 210 and / or compare vector data to data of tag RAM 210. Comparison logic 306 provides a hit or miss output to replacement policy component 308 and address encoders 326a, 326b. In some instances, comparison logic 306 provides the hit or miss output to multiplexers 330a, 330b.

[0335] In particular, comparison logic 306a is connected to scalar interface 502, tag RAM 210, address encoder 326a, and replacement policy component 308. Comparison logic 306b is connected to vector interface 504, tag RAM 210, address encoder 326b, and replacement policy component 308. Comparison logic 306a, 306b supports scalar and vector data paths. For example, comparison logic 306 can compare scalar data to data of tag RAM 210 and / or compare vector data to data of tag RAM 210. Comparison logic 306 provides a hit or miss output to replacement policy component 308 and address encoders 326a, 326b. In some instances, comparison logic 306 provides the hit or miss output to multiplexers 330a, 330b. Figure 6 In particular, comparison logic 306a is connected to scalar interface 502, tag RAM 210, address encoder 326a, and replacement policy component 308. Comparison logic 306b is connected to vector interface 504, tag RAM 210, address encoder 326b, and replacement policy component 308. Comparison logic 306a, 306b supports scalar and vector data paths. For example, comparison logic 306 can compare scalar data to data of tag RAM 210 and / or compare vector data to data of tag RAM 210. Comparison logic 306 provides a hit or miss output to replacement policy component 308 and address encoders 326a, 326b. In some instances, comparison logic 306 provides the hit or miss output to multiplexers 330a, 330b. Figure 5 ) is to remove an entry from victim storage 218 or to input an entry to victim storage 218. Control logic of replacement policy component 308 is configured to resolve the address conflict between the 2 addresses (e.g., scalar and vector) in a manner that maintains data coherency. Figures 3A-3D Control logic of an example replacement policy component 308 is shown.

[0336] In particular, comparison logic 306a is connected to scalar interface 502, tag RAM 210, address encoder 326a, and replacement policy component 308. Comparison logic 306b is connected to vector interface 504, tag RAM 210, address encoder 326b, and replacement policy component 308. Comparison logic 306a, 306b supports scalar and vector data paths. For example, comparison logic 306 can compare scalar data to data of tag RAM 210 and / or compare vector data to data of tag RAM 210. Comparison logic 306 provides a hit or miss output to replacement policy component 308 and address encoders 326a, 326b. In some instances, comparison logic 306 provides the hit or miss output to multiplexers 330a, 330b. Figure 5 In particular, comparison logic 306a is connected to scalar interface 502, tag RAM 210, address encoder 326a, and replacement policy component 308. Comparison logic 306b is connected to vector interface 504, tag RAM 210, address encoder 326b, and replacement policy component 308. Comparison logic 306a, 306b supports scalar and vector data paths. For example, comparison logic 306 can compare scalar data to data of tag RAM 210 and / or compare vector data to data of tag RAM 210. Comparison logic 306 provides a hit or miss output to replacement policy component 308 and address encoders 326a, 326b. In some instances, comparison logic 306 provides the hit or miss output to multiplexers 330a, 330b. Figure 5

[0337] In particular, comparison logic 306a is connected to scalar interface 502, tag RAM 210, address encoder 326a, and replacement policy component 308. Comparison logic 306b is connected to vector interface 504, tag RAM 210, address encoder 326b, and replacement policy component 308. Comparison logic 306a, 306b supports scalar and vector data paths. For example, comparison logic 306 can compare scalar data to data of tag RAM 210 and / or compare vector data to data of tag RAM 210. Comparison logic 306 provides a hit or miss output to replacement policy component 308 and address encoders 326a, 326b. In some instances, comparison logic 306 provides the hit or miss output to multiplexers 330a, 330b. Figure 5 ​In this configuration, multiplexers 330a and 330b select an address in response to the execution of comparison logic 306a and 306b. For example, multiplexer 330a may obtain an input corresponding to a hit from comparison logic 306a and thus select an encoded address from address encoder 326a. Alternatively and alternatively, multiplexer 330a may obtain an input corresponding to a miss from comparison logic 306a and thus select a memory address selected by alternative strategy component 308. Example multiplexers 330a and 330b are coupled to address reads 332a and 332b.

[0338] exist Figure 5 In this process, instance address reads 332a and 332b read the address value selected by the multiplexer into the victim storage area 218. For example, address reads 332a and 332b can identify addresses to be stored and / or removed from the victim storage area 218.

[0339] exist Figure 5 In this context, the victim store 218 is a fully associative cache. For example, the fully associative victim store 218 may place data in any unused block of the cache when data is retrieved from main memory 214 (e.g., victimized). The placement of data in the victim store 218 is based on the substitution policy component 308. For example, the substitution policy component 308 may determine when and where a row of data from main memory 214 should be placed in the victim store 218. In some instances, the victim store 218 outputs a response when address reads 332a, 332b read data into the victim store 218. In some instances, the victim store 218 generates DP0, DP1, and listener responses to transfer to the L2 data cache 112. In some instances, the response contains the data requested by CPU 102. For example, based on address reads 332a, 332b, if CPU 102 has requested such data, then the victim store 218 may output the data from the memory address location. Additionally and / or alternatively, based on address reads 332a, 332b, if the substitution policy component 308 is substituted for data in the victim storage area 218, then the victim storage area 218 may output the evicted data to the L2 cache 112.

[0340] exist Figure 5In the example shown in FIG. 3, the example snoop address component 506 is implemented by a snoop data path and / or otherwise by an interface. In addition to the two CPU data paths (e.g., DP0 and DP1), the L1 cache 110 includes a snoop data path to add coherency to the L1 cache 110. The example snoop address component 506 is connected to the tag RAM 210 and the comparison logic 306c. In some examples, the snoop address component 506 obtains a snoop request address issued by a higher level data cache (e.g., the L2 data cache 112) that issues an address read to the tag RAM 210. For example, the snoop address component 506 attempts to read a memory address from the tag RAM 210. Also, the snoop address component 506 provides the address read to the comparison logic 306c. The snoop address component 506, and more generally the coherency pipeline, is used to store the MESI state of each cache line in the victim storage 218 in the MESI RAM 300. By storing the MESI state of each cache line in the MESI RAM 300, the victim cache system supports coherency.

[0341] In Method and apparatus for multiple sets of victim caches with dual data paths In the example topology shown in FIG. 3, the example MESI RAM 300 is connected to the comparison logic 306c. The example MESI RAM 300 tracks the state of cache lines in the home storage 214 and the victim storage 218 by tagging the cache lines as modified, exclusive, shared, or invalid based on the comparison logic 306c. For example, when the snoop address component 506 issues a read to the tag RAM 210, the tag RAM 210 returns or does not return the correct memory address. Thus, the comparison logic 306c compares the memory address of the snoop issued read and the tag RAM 210 result to determine the state of the cache line.

[0342] In Figure 2 In the example topology shown in FIG. 3, the response multiplexer 508 is coupled to the victim storage 218 and the victim cache storage queue 216. In this way, the response multiplexer 508 is configured to select between data obtained through the victim storage 214 and / or data obtained through the victim cache storage queue 216 to transmit the most recent data of the system. An example operation of the priority multiplexer 508 is described below.

[0343] Figure 2

[0344] In some victim caches, multi-banked architectures are not supported. For example, a victim cache can be a monolithic storage device that does not support a processor (e.g., a CPU) to make multiple accesses during the same clock cycle. For example, a request to access data in a single victim cache can lock the entire victim cache. In such examples, there is a single register file capable of supporting an access to a full victim cache line per clock cycle. In some such examples, the entire victim cache line associated with the single victim storage region can be locked to service the request because the single register file is allocated to the victim storage region data bank that received such a request.

[0345] Examples described herein include multi-banked victim caches with dual data paths. In some described examples, Figure 7A The victim storage 218 of the victim cache 200 has multiple banks, and thus is multi-banked, or has a multi-banked data or memory structure. Advantageously, the multi-banked structure of the victim storage 218 can enable support for two or more accesses (e.g., CPU accesses) per clock cycle. Advantageously, the multi-banked structure of the victim storage 218 allows the two or more accesses to be serviced and / or implemented without performance overhead.

[0346] In some described examples, the victim storage 218 has a dual port fully associative tag ram (e.g., Figure 1 The tag ram 210 of the victim cache 200). In some described examples, both scalar and vector addresses support hit / miss comparisons. In such described examples, the victim storage 218 is locked based on the hit / miss decision for each data path (e.g., scalar data path, vector data path, etc.). In examples where the access to the victim storage 218 is a hit, the location of the hit entry is selected. In examples where the access to the victim storage 218 is a miss, the allocation policy is checked for a particular bank of the victim storage 218.

[0347] In some described examples, in a subsequent pipe stage, the victim storage 218 for the selected bank of the two addresses is read, and a response is sent back to the CPU. In some described examples, the selection logic is set to resolve the address conflict between the two addresses (e.g., scalar address and vector address) in a manner that maintains data coherency. In some described examples, control logic also resolves the address conflict.

[0348] In some of the described instances, group arbitration logic computes and / or otherwise determines the required group for each address and selects each group for reading. In some of the described instances, control logic resolves any group conflicts between the two addresses to serialize the two memory operations. In some of the described instances where both data paths access the same address, the control logic can prevent multiple allocation requests for the same address from being issued. Once data is read from victim memory 218, instance data multiplexing logic can fold the data into the correct data path before returning it to the CPU as a read response.

[0349] Figure 1 This is a schematic diagram of the first instance of the encapsulated data cache system 700. The first encapsulated data cache system 700 can be... Figure 7A L1 cache 110 or a portion thereof and / or more generally Figure 7A An example circuit implementation of the data cache 108 or a portion thereof. The first encapsulated data cache system 700 is encapsulated to provide a unified storage view to external systems (e.g., one or more CPUs, one or more processors, external hardware, etc.). For example, the first encapsulated data cache system 700 may use firmware, software, hardware logic, etc., and / or combinations thereof for encapsulation to encapsulate and / or otherwise abstract all complexities related to read-after-write (RAW) hazards, write-after-write (WAW) hazards, data forwarding, etc. Advantageously, in Figure 2 The unified architecture depicted in the example provides a separate port to external systems (e.g., CPU 102) to simplify access to the latest version of the data of interest.

[0350] exist Figure 2 In the example, the first encapsulated data cache system 700 contains Figure 7A The victim cache storage queue 216 and Figure 7C Victim storage area 218. In Figure 7E In the context of the victim cache storage queue 216, multiple first instance independently addressable groups (e.g., data groups, storage area groups, data storage area groups, etc.) 702 are included. For example, the first independently addressable group 702 can be a group queue, a group sub-queue, etc. In such instances, the group queue, group sub-queue, etc., can contain multiple storage elements, as described below. Figure 7A and / or Figure 7A Described in the text. The first independently addressable group 702 is a victim cache storage queue group (e.g., a victim cache storage queue data group, a victim cache group queue, a victim cache group sub-queue, etc.). Figure 7AIn particular embodiments, the victim cache storage queue 216 includes 16 victim cache storage queue groups 702. Alternatively, there can be fewer or more than 16 instances of victim cache storage queue groups 702.

[0351] In particular embodiments, the victim cache storage queue 216 includes 16 victim cache storage queue groups 702. Alternatively, there can be fewer or more than 16 instances of victim cache storage queue groups 702. Figure 7A In particular embodiments, the victim storage area 218 includes a plurality of second independently addressable groups (e.g., data groups, storage area groups, data storage area groups, etc.) 704. The second independently addressable groups 704 are victim storage area groups (e.g., victim storage area data groups). In particular embodiments, the victim storage area 218 includes 16 victim storage area groups 704. Alternatively, there can be fewer or more than 16 instances of victim storage area groups 704. Figure 7A In particular embodiments, the victim cache storage queue 216 includes 16 victim cache storage queue groups 702. Alternatively, there can be fewer or more than 16 instances of victim cache storage queue groups 702.

[0352] In some instances, the victim cache storage queue 216 and the victim storage area 218 each have 256 rows, with each row having a line width of 1024 bits, and divided into 16 groups, as shown in Figure 7A In some instances, the victim cache storage queue 216 and the victim storage area 218 each have 384 rows, with each row having a line width of 1024 bits, and divided into 16 groups, as shown in Figure 7C In some instances, the victim cache storage queue 216 and the victim storage area 218 each have 384 rows, with each row having a line width of 1024 bits, and divided into 16 groups, as shown in Figure 1 In particular embodiments, each first group 702 corresponds to one of the second groups 704. For example, the first group (group 1) of the victim cache storage queue 216 forms a loop with the first group (group 1) of the victim storage area 218, and thus corresponds to the first group of the victim storage area 218.

[0353] Advantageously, the multi-group structure of the victim cache storage queue 216, the victim storage area 218, and / or more generally the first encapsulated data cache system 700 can service read and write operations sent to the groups in parallel. In some instances, each group arbitrates its own process in response to read and / or write operations. By allowing each group of the first encapsulated data cache system 700 to operate independently, the operation of the first encapsulated data cache system 700 is more efficient, as the entire cache line is not locked when a request is received. Rather, only the portion of the cache line assigned to the group that received such a request is locked.

[0354] Figure 2 The instance victim cache has a multi-set structure of 720. In some instances, Figure 2 The L1 cache 110, L2 cache 112, and / or L3 cache 114 may have a victim cache set structure 720. In some instances, Figure 7C The victim cache storage queue 216 and / or Figure 7C The victim storage area 218 may have a victim cache multi-set structure 720. For example, the victim cache multi-set structure 720 may be an instance implementation of the victim cache storage queue 216 and / or the victim storage area 218.

[0355] The victim cache multi-set structure 720 is a data or memory structure containing 16 instance sets (sets 0-15) 722, where each set 722 has a data width of 64 bytes (e.g., bytes 0-7). Each set 722 contains 16 instance rows (rows 0-15) 724, where each row 724 has a data width of 128 bytes (e.g., 128 bytes = 8 bytes / set * 16 sets). Figure 7C In this context, each group of 722 can store 128 bytes (e.g., 128 bytes = 8 bytes / row * 16 rows). Figure 8A In this context, the victim cache multi-set structure 720 can store 2048 bytes (e.g., 2048 bytes = 128 bytes / set * 16 sets). The victim cache multi-set structure 720 can be independently addressed by set. For example, the first line in line 724 has a start line address of 0 and an end line address of 127, the second line in line 724 has a start line address of 128 and an end line address of 255, and so on.

[0356] In some instances, a cache line can be 128 bytes of data adapted to the width of a memory (e.g., DRAM) or a memory cell (e.g., main memory 214, victim memory 218, etc.). ​ In this example, a cache line can occupy an entire row of the victim cache set structure 720. For instance, a cache line can use a row 724 of 16 sets, where each set is 8 bytes wide. Advantageously, the victim cache set structure 720 allows 16 different cache lines to access the data stored therein.

[0357] ​ A schematic illustration shows the Instance Victim Cache Tag (VCT) Random Access Memory (RAM) 800. The VCT RAM 800 can be... Figure 2 Example implementation of tag RAM 210. For example, VCT RAM 800 can be stored in Figure 2the victim cache storage queue 216, the victim storage area 218, and so forth. The VCT RAM 800 is a multi-bank VCT RAM. For example, the VCT RAM 800 can include a plurality of banks (e.g., data banks, memory banks, and so forth), such as 16 banks, although the VCT RAM 800 can have a different number of banks.

[0358] The VCT RAM 800 includes instance allocation ports 802, 804, 806, including a first instance allocation port (AP0) 802, a second instance allocation port (AP1) 804, and a third instance allocation port (AP2) 806. The VCT RAM 800 includes instance read ports 808, 810, 812, including a first instance read port (RP0) 808, a second instance read port (RP1) 810, and a third instance read port (RP2) 812. The VCT RAM 800 includes an instance LRU read port 814. The VCT RAM 800 includes instance output ports 816, 818, 820, 822, including a first instance output port (OP0) 816, a second instance output port (OP1) 818, a third instance output port (OP2) 820, and a fourth instance output port (OP3) 822. Alternatively, the VCT RAM 800 can have more or fewer allocation ports, read ports, LRU read ports, and / or output ports than depicted in FIG. 8. Figure 8A fewer or more allocation ports, read ports, LRU read ports, and / or output ports than depicted in FIG. 8.

[0359] The VCT RAM 800 includes the allocation ports 802, 804, 806 to populate the victim storage area 218. For example, the allocation ports 802, 804, 806 can be configured to receive requests from external hardware (e.g., the CPU 102, the main storage area 214, and so forth) to store data in the victim storage area 218. The first allocation port 802 is configured to receive first instance data 824. For example, the first allocation port 802 can receive the first data 824 from a write state machine associated with a scalar data path (DP0). The first data 824 includes WRM_TAG_UPDATE0 data, which can represent a request to store data in the victim storage area 218. The WRM_TAG_UPDATE0 data can include a tag value, a data value, and a tag update value. The tag value can be a value that identifies the data value. The data value can be a value that is to be stored in the victim storage area 218. The tag update value can be a value that indicates that the tag value is to be updated. The second allocation port 804 is configured to receive second instance data 826. For example, the second allocation port 804 can receive the second data 826 from a write state machine associated with a vector data path (DP1). The second data 826 includes WRM_TAG_UPDATE1 data, which can represent a request to store data in the victim storage area 218. The WRM_TAG_UPDATE1 data can include a tag value, a data value, and a tag update value. The tag value can be a value that identifies the data value. The data value can be a value that is to be stored in the victim storage area 218. The tag update value can be a value that indicates that the tag value is to be updated. The third allocation port 806 is configured to receive third instance data 828. For example, the third allocation port 806 can receive the third data 828 from a write state machine associated with a vector data path (DP2). The third data 828 includes WRM_TAG_UPDATE2 data, which can represent a request to store data in the victim storage area 218. The WRM_TAG_UPDATE2 data can include a tag value, a data value, and a tag update value. The tag value can be a value that identifies the data value. The data value can be a value that is to be stored in the victim storage area 218. The tag update value can be a value that indicates that the tag value is to be updated. Figure 2control signals generated by CPU interface 202 (e.g., scalar data path (DP0)). The control signals can be generated to inform VCT RAM 800 that CPU interface 202 has a cache line moving from CPU interface 202 to victim storage 218, and thus CPU interface 202 has an address moving from CPU interface 202 to tag ram 210. First data 824 includes VTAG_WR_TAG0 data, which can represent an address in VCT RAM 800 that can correspond to a data address (e.g., a tag address) to be stored in victim cache 218. First data 824 includes VTAG_WR_SET0 data, which can represent an address in victim cache 218 where data is to be stored (e.g., victim cache tag for DP0).

[0360] Second allocation port 804 is configured to receive second instance data 826. For example, second allocation port 804 can receive second data 826 from a write state machine associated with a vector data path (DP1). Second data 826 includes WRM_TAG_UPDATE1 data, which can represent an address in VCT RAM 800 that can correspond to a data address (e.g., a tag address) to be stored in victim cache 218. Second data 826 includes VTAG_WR_SET1 data, which can represent an address in victim cache 218 where data is to be stored (e.g., victim cache tag for DP1). Figure 2 control signals generated by CPU interface 202 (e.g., scalar data path (DP0)). The control signals can be generated to inform VCT RAM 800 that CPU interface 202 has a cache line moving from CPU interface 202 to victim storage 218, and thus CPU interface 202 has an address moving from CPU interface 202 to tag ram 210. First data 824 includes VTAG_WR_TAG0 data, which can represent an address in VCT RAM 800 that can correspond to a data address (e.g., a tag address) to be stored in victim cache 218. First data 824 includes VTAG_WR_SET0 data, which can represent an address in victim cache 218 where data is to be stored (e.g., victim cache tag for DP0).

[0361] The third allocation port 806 is configured to receive third instance data 828. The third data 828 includes ARB_EVT_TAG_UPDATE data, which can represent a control signal generated from the home storage 214. The control signal is an arbitration (ARB) eviction (EVT) tag update control signal, which can be generated to inform the VCT RAM 800 that the home storage 214 has a cache line moved from the home storage 214 to the victim storage 218, and thus the home storage 214 has an address moved from the tag ram 208 to the tag ram 210. The third data 828 includes ADP_EVT_WR_TAG data, which can represent an address (e.g., a tag address) in the VCT RAM 800 that can correspond to a data address to be stored in the victim cache 218. The third data 828 includes ADP_EVT_WR_SET data, which can represent an address in the victim cache 218 where data is to be stored (e.g., a victim cache tag for a line moved from the home cache to the victim cache). For example, the ADP_EVT_WR_TAG and ADP_EVT_WR_SET data can be referred to as address data path (ADP) data. The first data 824, the second data 826, and / or the third data 828 can be one or more packets of data, one or more signals based on a communication protocol (e.g., an inter-integrated circuit (I2C) protocol), and / or the like.

[0362] The VCT RAM 800 includes read ports 808, 810, 812 to provide an interface through which external hardware (e.g., the CPU 102) can request to read and / or otherwise access data stored in the victim storage 218. The first read port 808 is configured to receive fourth instance data 830. For example, the first read port 808 can receive the fourth data 830 from the scalar interface 502 of the CPU 102. The fourth data 830 includes ADP_ADDR_E2_DP0 data, which can represent an address in the victim storage 218 that the scalar interface 502 requests to access.

[0363] The second read port 810 is configured to receive fifth instance data 832. For example, the second read port 810 can receive the fifth data 832 from the vector interface 504 of the CPU 102. The fifth data 832 includes ADP_ADDR_E2_DP1 data, which can represent an address in the victim storage 218 that the vector interface 504 requests to access.

[0364] The third read port 812 is configured to receive sixth instance data 834. For example, the third read port 812 can receive the sixth data 834 from the vector interface 504 of the CPU 102. The sixth data 834 includes ADP_ADDR_E2_DP2 data, which can represent an address in the victim storage 218 that the vector interface 504 requests to access. Figure 5The listening address component 506 (e.g., a listening interface) receives sixth data 834. The sixth data 834 includes SNP_ADDR_E2_DP0 data, which can represent an address in the victim storage 218 that the listening address component 506 requests access to.

[0365] The LRU read port 814 is configured to receive seventh instance data 836. For example, the LRU read port 814 can receive the seventh instance data 836 from the replacement policy component 308. Figures 3A-3D The replacement policy component 308 receives the seventh data 836. The seventh data 836 includes LRU_SET_DP0 and LRU_SET_DP1, which can represent respective addresses associated with least recently used (LRU) cache lines of the victim storage 218. For example, the LRU read port 814 can be a victim least recently used (VLRU) read port configured to receive LRU data from the replacement policy component 308.

[0366] The VCT RAM 800 includes output ports 816, 818, 820, 822 for transmitting outputs to external hardware (e.g., the CPU 102, the main storage 214, etc.) in response to read requests or write requests (e.g., allocation requests) associated with the victim storage 218. The first output port 816 is configured to transmit first instance output data 838. For example, the first output port 816 can transmit the first output data 838 to the scalar interface 502. The first output data 838 includes VTAG_HIT_DP0 data, which can indicate that data requested by the scalar interface 502 is stored in the victim storage 218. The first output data 838 includes VTAG_MISS_DP0 data, which can indicate that data requested by the scalar interface 502 is not stored in the victim storage 218. The first output data 838 includes VTAG_SET_DP0 data, which can represent an address in the victim storage 218 where data requested by the scalar interface 502 is stored.

[0367] The second output port 818 is configured to transmit second instance output data 840. For example, the second output port 818 can transmit the second output data 840 to the vector interface 504. The second output data 840 includes VTAG_HIT_DP1 data, which can indicate that data requested by the vector interface 504 is stored in the victim storage 218. The second output data 840 includes VTAG_MISS_DP1 data, which can indicate that data requested by the vector interface 504 is not stored in the victim storage 218. The second output data 840 includes VTAG_SET_DP1 data, which can represent an address in the victim storage 218 where data requested by the vector interface 504 is stored.

[0368] The third output port 820 is configured to transmit third instance output data 842. For example, the third output port 820 may transmit the third output data 842 to the replacement policy component 308. The third output data 842 contains VTAG_ADDR_DP0 data, which may represent an address in the victim memory 218 associated with a request LRU_SET_DP0 received at the replacement policy component 308 at the LRU read port 814.

[0369] The fourth output port 822 is configured to transmit fourth instance output data 844. For example, the fourth output port 822 may transmit the fourth output data 844 to the replacement policy component 308. The fourth output data 844 contains VTAG_ADDR_DP1 data, which may represent the address in the victim memory 218 associated with the request LRU_SET_DP1 received at the replacement policy component 308 at the LRU read port 814.

[0370] Figure 8B Show Figure 8A Another schematic illustration of an example implementation of the VCT RAM 800. For example, Figure 8B Can correspond to Figure 5 The L1 cache 110 is a segment or portion of the victim cache.

[0371] Figure 8B Depicting Figure 8A Another example implementation of the VCT RAM 800. In Figure 8B In this context, VCT RAM 800 contains 16 instance sets 846. For example, set 846 contains a first set VCT_ADDR[0], a second set VCT_ADDR[1], and so on. Alternatively, VCT RAM 800 may contain fewer or more sets 846 than 16.

[0372] VCT RAM 800 is a victim cache tag storage area configured to store addresses (e.g., tag addresses) corresponding to set 846. Each set 846 is coupled to a corresponding entity in a first instance comparator 850 and a corresponding entity in a second instance comparator 852. The first comparator 850 may be an instance implementation of the comparison logic 306a of Figures 3 and / or 5. The second comparator 852 may be an instance implementation of the comparison logic 306b of Figures 3 and / or 5. The first set VCT_ADDR[0] is coupled to the first entity in the first comparator 850 and the first entity in the second comparator 852, the second set VCT_ADDR[1] is coupled to the second entity in the first comparator 850 and the second entity in the second comparator 852, and so on.

[0373] The first comparator 850 and the second comparator 852 are coupled to respective instance address encoder logic circuits 854, 856, including a first instance address encoder logic circuit 854 and a second instance address encoder logic circuit 856. The first comparator 850 is coupled to the first address encoder logic circuit 854. The second comparator 852 is coupled to the second address encoder logic circuit 856.

[0374] The address encoder logic circuits 854, 856 can be instance implementations of the address encoders 326a, 326b of FIGS. 3 and / or 5. For example, the first address encoder logic circuit 854 can be an instance implementation of the address encoder 326a. In other instances, the second address encoder logic circuit 856 can be an instance implementation of the address encoder 326b.

[0375] The first instance multiplexer 858A is coupled to the first address encoder logic circuit 854. The first address encoder logic circuit 854 includes a first instance decoder 860A, a first instance inverter (e.g., a logic gate, an inverting logic gate, etc.) 862A, a first instance AND gate (e.g., a logic gate, an AND logic gate, etc.) 864A, a first instance OR gate (e.g., a logic gate, an OR logic gate, etc.) 866A, a first instance encoder 868A, a third instance comparator 870A, and a fourth instance comparator 872A.

[0376] For clarity, Figure 8B Only one instance of each of the first AND gate 864A, the first OR gate 866A, the third comparator 870A, and the fourth comparator 872A is depicted. However, each of the first AND gate 864A, the first OR gate 866A, the third comparator 870A, and the fourth comparator 872A can represent 16 instances of the component. For example, the first AND gate 864A can represent and / or otherwise implement 16 instances of the first AND gate 864A, the first OR gate 866A can represent and / or otherwise implement 16 instances of the first OR gate 866A, and so on.

[0377] The first multiplexer 858A has a first input to receive ADP_ADDR_E2_DP0, which represents an address requested by the DP0 interface to the E2 arbitration stage of the Figures 3A-3D The first multiplexer 858A has a second input to receive SNP_ADDR_E2_DP0, which represents an address requested by the snooping interface to the E2 arbitration stage of the Figures 3A-3Dthe E2 arbitration level request. The first multiplexer 858A has a select input to receive SNP ADDR EN DP0, which represents an enable signal from the snooping interface that, when asserted, can invoke the first multiplexer 858A to select the second input. The output of the first multiplexer 858A is coupled to an input of the first comparator 850. For example, each of the first comparators 850 can compare the address from the output of the first multiplexer 858A to a corresponding one of the set of VCT RAM 800. In such an example, a first one of the first comparators 850 can compare the address included in ADP ADDR E2 DP0 to the address stored in VCT ADDR[0]. In some such examples, the first one of the first comparators 850 can output and / or otherwise generate a logical one in response to the address from the first multiplexer 858A matching the address stored in VCT ADDR[0].

[0378] The output of the first multiplexer 858A is coupled to a first input of the third comparator 870A. The output of an example DP0 read finite state machine (READ FSM DP0) 873 and / or the output of an example DP0 write finite state machine (WRITE FSM DP0) 874 is coupled to a second input of the third comparator 870A. The DP0 read finite state machine 873 and the DP0 write finite state machine 874 are hardware-implemented finite state machines that operate on data from the scalar interface 502 to perform logic. For example, the DP0 read finite state machine 873 and / or the DP0 write finite state machine 874 can transmit one or more of WRM TAG UPDATE0, VTAG WR TAG0, and VTAG WR SET0 to the third comparator 870A and / or the fourth comparator 872A. The DP0 read finite state machine 873 and / or the DP0 write finite state machine 874 can transmit VTAG WR TAG0 to a sixth example comparator 872B included in the second address encoder logic circuit 856. WRM TAG UPDATE0, VTAG WR TAG0, and VTAG WR SET0 are described above in connection with the scalar interface 502. Figure 5 Figure 8A

[0379] ​​The first decoder 860A is a 4x16 decoder. The first decoder 860A has an input to receive VTAG_WR_SET0 data, which can represent a fly-by address from the scalar interface 502 to the victim storage 218. The first decoder 860A has an output coupled to an input of the first inverter 862A. The first decoder 860A can convert the fly-by address into a bit vector, where each bit is inverted through one of the 16 instances of the first inverter 862A. The output of the first inverter 862A is coupled to a first input of the first AND gate 864A. A second input of the first AND gate 864A is coupled to a result bit of the first comparator 850 comparing the tag of set 0 (e.g., VCT_ADDR[0]) and an output of the first multiplexer 858A. For example, the second input of the first AND gate 864A can be configured to receive HIT_DP0 data, which can represent a 16-bit vector, where each bit can correspond to whether the ADP_ADDR_E2_DP0 data is a hit (e.g., bit value of 1) or a miss (e.g., bit value of 0) in the victim storage 218.

[0380] The output of the first AND gate 864A is coupled to a first input of the first OR gate 866A. An output of the third comparator 870A is coupled to a second input of the first OR gate 866A. An output of the fourth comparator 872A is coupled to a third input of the first OR gate 866A. The output of the first OR gate 866A is coupled to an input of the first encoder 868A. The first encoder 868A is a 16x4 encoder. For example, the first encoder 868A can generate HIT_ADDR0 data, which can represent a VTAG_SET_DP0 of Figure 8A In such examples, HIT_ADDR0 can correspond to the first output data 838 of Figure 8A

[0381] The second address encoder logic circuit 856 includes a second instance decoder 860B, a second instance inverter (e.g., logic gate, inverting logic gate, etc.) 862B, a second instance AND gate (e.g., logic gate, AND logic gate, etc.) 864B, a second instance OR gate (e.g., logic gate, OR logic gate, etc.) 866B, a second instance encoder 868B, a fifth instance comparator 870B, and a sixth instance comparator 872B.

[0382] For clarity, Figure 8B ​Only one instance of each of the second AND gate 864B, the second OR gate 866B, the fifth comparator 870B, and the sixth comparator 872B is depicted. However, each of the second AND gate 864B, the second OR gate 866B, the fifth comparator 870B, and the sixth comparator 872B can represent 16 instances of the component. For example, the second AND gate 864B can represent and / or otherwise implement 16 instances of the second AND gate 864B, the second OR gate 866B can represent and / or otherwise implement 16 instances of the second OR gate 866B, and so on.

[0383] The second address encoder logic circuit 856 has a first input to receive ADP_ADDR_E2_DP1, which represents an address requested by the E2 arbitration stage of the DP1 interface to the VCT RAM 800. The ADP_ADDR_E2_DP1 is coupled to an input of the second comparators 852. For example, each of the second comparators 852 can compare the address contained in the ADP_ADDR_E2_DP1 to a corresponding one of the set of VCT RAM 800. In such an example, a first one of the second comparators 852 can compare the address contained in the ADP_ADDR_E2_DP1 to the address stored in VCT_ADDR[0]. In some such examples, the first one of the second comparators 852 can output and / or otherwise generate a logical one in response to the address contained in the ADP_ADDR_E2_DP1 matching the address stored in VCT_ADDR[0]. Figures 3A-3D

[0384] The ADP_ADDR_E2_DP1 is coupled to a first input of the fifth comparator 870B. An output of an example DP1 read finite state machine (READ FSM DP1) 875 and / or an output of an example DP1 write finite state machine (WRITE FSM DP1) 876 is coupled to a second input of the fifth comparator 870B. The DP1 read finite state machine 875 and the DP1 write finite state machine 876 are hardware-implemented finite state machines that perform logic on data from the vector interface 504. For example, the DP1 read finite state machine 875 and / or the DP1 write finite state machine 876 can transmit one or more of WRM_TAG_UPDATE1, VTAG_WR_TAG1, and VTAG_WR_SET1 to the fifth comparator 870B and / or the sixth comparator 872B. The DP1 read finite state machine 875 and / or the DP1 write finite state machine 876 can transmit VTAG_WR_TAG1 to the fourth comparator 872A included in the first address encoder logic circuit 854. WRM_TAG_UPDATE1, VTAG_WR_TAG1, and VTAG_WR_SET1 are described above in connection with the first address encoder logic circuit 854. Figure 5 Figure 8A ​​Description.

[0385] The second decoder 860B is a 4x16 decoder. The second decoder 860B has an input to receive VTAG_WR_SET1 data, which can represent a fly-by address from the vector interface 504 to the victim storage area 218. The second decoder 860B has an output coupled to an input of the second inverter 862B. The second decoder 860B can convert the fly-by address into a bit vector, where each bit is inverted through one of the 16 instances of the second inverter 862B. The output of the second inverter 862B is coupled to a first input of the second AND gate 864B. A second input of the second AND gate 864B is coupled to a result bit of the second comparator 852 comparing the tag of set 0 (e.g., VCT_ADDR[0]) and ADP_ADDR_E2_DP1. For example, the second input of the second AND gate 864B can be configured to receive HIT_DP1 data, which can represent a 16-bit vector where each bit can correspond to whether the ADP_ADDR_E2_DP1 data is a hit (e.g., bit value of 1) or a miss (e.g., bit value of 0) in the victim storage area 218.

[0386] The output of the second AND gate 864B is coupled to a first input of the second OR gate 866B. The output of the fifth comparator 870B is coupled to a second input of the second OR gate 866B. The output of the sixth comparator 872B is coupled to a third input of the second OR gate 866B. The output of the second OR gate 866B is coupled to an input of the second encoder 868B. The second encoder 868B is a 16x4 encoder. For example, the second encoder 868B can generate HIT_ADDR1 data, which can represent Figure 8A VTAG_SET_DP1. In such examples, HIT_ADDR1 can correspond to Figure 8A the second output data 840.

[0387] In example operating conditions, the first address encoder logic circuit 854 can receive a first read address (e.g., ADP_ADDR_E2_DP0) of a store instruction requested by the CPU 102, where the first read address is from Figure 1 the victim storage area 218. The first address encoder logic circuit 854 can generate a first output data 840, which can represent Figures 3A-3DE2 pipeline stage (arbitration) receive. Responsive to the first multiplexer 858A selecting the first input, the first multiplexer 858A can transmit the first read address to the first comparator 850. The first comparator 850 can compare the read address to a respective one of the set 846. If a first one of the first comparator 850 determines that the read address matches an address stored at a corresponding one of the set 846, the first one of the first comparator 850 can assert and / or otherwise output a logic one, otherwise the first one of the first comparator 850 outputs a logic zero. Thus, the first comparator 850 can generate a HIT_DP0 as a 16-bit vector on the 16-bit data bus responsive to the comparison. For example, the 16-bit vector can be an implementation of a signal string (e.g., pulse string) representing a bit vector. The first comparator 850 can transmit the HIT_DP0 to the first AND gate 864A.

[0388] The portion of the first address encoder logic circuit 854 and / or the second address encoder logic circuit 856 is cache hit-miss translation logic. For example, the first AND gate 864A, the third comparator 870A, and / or the fourth comparator 872A can be an example implementation of cache hit-miss translation logic. In such examples, the second AND gate 864B, the fifth comparator 870B, and / or the sixth comparator 872B can be an example implementation of cache hit-miss translation logic.

[0389] The first AND gate 864A is configured to determine whether to translate a hit (e.g., cache hit) to a miss (e.g., cache miss). For example, while the first read address is being processed during the E2 pipeline stage, a new address (VTAG_WR_SET0) can be written to the victim storage 218 during the E3 pipeline stage. In such examples, the first decoder 860A can translate the new address to a 16-bit value, which can be inverted by the first inverter 862A. The first inverter 862A can transmit the inverted 16-bit value to a first input of the first AND gate 864A. The first AND gate 864A can assert a logic one responsive to the VTAG_WR_SET0 not matching the address in the HIT_DP0, and thus not translate the cache hit to a cache miss. In other examples, the first AND gate 864A can output a logic zero responsive to the VTAG_WR_SET0 matching the address in the HIT_DP0, and thus translate the cache hit to a cache miss because the address requested in the ADP_ADDR_E2_DP0 has been overwritten and is no longer available at the address. Figures 3A-3D

[0390] ​In example operating conditions, the third comparator 870A and the fifth comparator 870B can be configured to convert a cache miss to a cache hit. For example, the third comparator 870A can determine that a first read address in the VCT RAM 800 requested during the E2 pipeline stage (ADP_ADDR_E2_DP0) is written in the E3 pipeline stage, which is represented by VTAG_WR_TAG0. In such examples, the third comparator 870A can assert a logic one in response to ADP_ADDR_E2_DP0 matching VTAG_WR_TAG0, and thus convert a cache miss to a cache hit, and HIT_ADDR0 can be updated with VTAG_WR_SET0, as the data will be available when the ADP_ADDR_E2_DP0 address is read during the E3 pipeline stage.

[0391] In example operating conditions, the fourth comparator 872A and the sixth comparator 872B can be configured to convert a cache miss to a cache hit. For example, the fourth comparator 872A can determine that a first read address in the VCT RAM 800 requested during the E2 pipeline stage (ADP_ADDR_E2_DP0) is written in the E3 pipeline stage through the vector interface 504, which is represented by VTAG_WR_TAG1. In such examples, the fourth comparator 872A can assert a logic one in response to ADP_ADDR_E2_DP0 matching VTAG_WR_TAG1, and thus convert a cache miss to a cache hit, and HIT_ADDR0 can be updated with VTAG_WR_SET1, as the data will be available when the ADP_ADDR_E2_DP0 address is read during the E3 pipeline stage.

[0392] In example operating conditions, the first OR gate 866A and the second OR gate 866B can be configured to generate an output to a corresponding one of the first encoder 868A or the second encoder 868B. For example, the first OR gate 866B can transmit a 16-bit vector representing a cache miss (e.g., a 16-bit value of 0) or a 16-bit vector representing a cache hit (e.g., a 16-bit value of an address of the cache hit). In such examples, the first encoder 868A can encode the 16-bit value from the first OR gate 866A as a 4-bit address, and thus generate HIT_ADDR0. Such example operations can apply to the second OR gate 866B, the second encoder 868B, and / or more generally, to the second address encoder logic 856.

[0393] Example methods, apparatus, systems, and articles of manufacture are described herein for multiple sets of victim caches with dual data paths. Other examples and combinations thereof include the following:

[0394] Example 1 includes a cache system including a storage element including a bank usable to store data, a port usable to receive memory operations in parallel, where each of the memory operations has a respective address, and a plurality of comparators coupled such that each of the comparators is coupled to a respective one of the ports and a respective one of the banks, and usable to determine whether a respective address of a respective memory operation received by the respective port corresponds to the data stored in the respective bank.

[0395] Example 2 includes the cache system of Example 1, further including a victim cache including victim cache data, and the data is tag data corresponding to the victim cache data.

[0396] Example 3 includes the cache system of Example 1, where the memory operations include a first memory operation, the cache system further including a cache including cache data, the data is tag data corresponding to the cache data, and a first one of the plurality of comparators generates a signal in response to detecting a cache hit based on first data associated with the first memory operation corresponding to the data in the storage element.

[0397] Example 4 includes the cache system of Example 1, where the plurality of comparators is a plurality of first comparators, the cache system further including address encoder logic circuitry including a decoder having a decoder input and a decoder output, the decoder input coupled to a first finite state machine associated with a scalar interface of a central processing unit, a plurality of inverters having respective inverter inputs and respective inverter outputs, the inverter inputs coupled to the decoder outputs, a plurality of AND logic gates having respective first inputs and respective second inputs, respective ones of the first inputs coupled to respective ones of the inverter outputs, respective ones of the second inputs coupled to respective ones of outputs of the plurality of first comparators, a plurality of second comparators coupled to respective ones of outputs of the plurality of first comparators and the first finite state machine, and a plurality of third comparators coupled to respective outputs of the plurality of first comparators and a second finite state machine associated with a vector interface of the central processing unit.

[0398] Example 5 includes the cache system of Example 4, where a first one of the plurality of AND logic gates outputs a logic low signal that converts a cache hit to a cache miss in response to a first address associated with the scalar interface matching a second address associated with the cache hit.

[0399] Example 6 includes the cache system of Example 4, wherein a first comparator of the plurality of second comparators is to output a logical high signal to convert a cache miss to a cache hit responsive to a first address associated with the scalar interface matching a second address associated with the cache miss.

[0400] Example 7 includes the cache system of Example 4, wherein a first comparator of the plurality of third comparators is to output a logical high signal to convert a cache miss to a cache hit responsive to a first address associated with the vector interface matching a second address associated with the cache miss.

[0401] Example 8 includes the cache system of Example 4, wherein the address encoder logic circuit includes: a plurality of OR logic gates having a respective third input, a respective fourth input, and a respective fifth input, the third input coupled to a respective one of the outputs of the plurality of AND logic gates, the fourth input coupled to a respective one of the outputs of the plurality of second comparators, the fifth input coupled to a respective one of the outputs of the plurality of third comparators; and an encoder having an encoder input and an encoder output, the encoder input coupled to the outputs of the plurality of OR logic gates, the encoder output coupled to an input of a multiplexer.

[0402] Example 9 includes the cache system of Example 1, wherein the plurality of comparators is a plurality of first comparators, the cache system further including an address encoder logic circuit including: a decoder having a decoder input and a decoder output, the decoder input coupled to a first finite state machine associated with a vector interface of a central processing unit; a plurality of inverters having a respective inverter input and a respective inverter output, the inverter input coupled to the decoder output; a plurality of AND logic gates having a respective first input and a respective second input, a respective one of the first inputs coupled to a respective one of the inverter outputs, a respective one of the second inputs coupled to a respective one of the outputs of the plurality of first comparators; a plurality of second comparators coupled to a respective one of the outputs of the plurality of first comparators and the first finite state machine; and a plurality of third comparators coupled to a respective output of the plurality of first comparators and a second finite state machine associated with the vector interface of the central processing unit.

[0403] Example 10 includes a victim cache system comprising a victim cache storage queue including a first set of data and a victim storage area coupled to the victim cache storage queue, the victim storage area including a second set of data different from the first set of data.

[0404] Example 11 includes the victim cache system of Example 10, wherein at least one of the first data set or the second data set includes 16 data sets.

[0405] Example 12 includes the victim cache system of Example 10, wherein the first data set includes a first data set having 8 addresses, each address having a data width of 1 byte, the first data set configured to store 64 bits.

[0406] Example 13 includes the victim cache system of Example 10, wherein the second data set includes a second data set having 8 addresses, each address having a data width of 1 byte, the second data set configured to store 64 bits.

[0407] Example 14 includes the victim cache system of Example 10, wherein respective ones of the first data set are coupled to respective ones of the second data set.

[0408] Example 15 includes a method of identifying a cache hit in a victim cache, the method comprising receiving a first read address from a first interface of a processor, receiving a second read address from a second interface of the processor, comparing the first read address and the second read address to data sets of a plurality of sets of victim cache tag storage, identifying a cache hit in response to at least one of the first read address or the second read address mapping to a first data set of the data sets, and outputting a cache hit address representing a victim cache address of cache data stored in the victim cache.

[0409] Example 16 includes the method of Example 15, wherein the first interface is a scalar interface and the second interface is a vector interface.

[0410] Example 17 includes the method of Example 15, further comprising, in response to identifying the cache hit, comparing the cache hit address to a first address received from a finite state machine associated with the first interface, the first address representing an address written to the victim cache in a previous pipeline stage, and converting the cache hit to a cache miss in response to the cache hit address matching the first address.

[0411] Example 18 includes the method of example 15, further comprising, in response to identifying the cache hit, comparing the cache hit address to a first address received from a finite state machine associated with the second interface, the first address representing an address written into the victim cache in a previous pipeline stage, and in response to the cache hit address matching the first address, converting the cache hit into a cache miss.

[0412] Example 19 includes the method of example 15, further comprising, in response to identifying a cache miss in response to at least one of the first read address or the second read address not mapping to any of the sets of data, comparing the first read address to a first address received from a finite state machine associated with the first interface, the first address representing an address written into the victim cache in a subsequent pipeline stage, and in response to the first read address matching the first address, converting the cache miss into the cache hit.

[0413] Example 20 includes the method of example 15, further comprising, in response to identifying a cache miss in response to at least one of the first read address or the second read address not mapping to any of the sets of data, comparing the second read address to a first address received from a finite state machine associated with the second interface, the first address representing an address written into the victim cache in a subsequent pipeline stage, and in response to the second read address matching the first address, converting the cache miss into the cache hit.

[0414] Example 21 includes the method of example 15, wherein comparing the first read address and the second read address to the sets of victim cache tag memory is performed substantially in parallel.

[0415] Method and apparatus for allocation in victim cache system

[0416] A data cache architecture including a victim cache system enables a primary cache (e.g., main storage 214) to allocate data to a victim cache (e.g., victim storage 218) when the primary cache needs to create a victim. For example, when an incoming instruction is a read miss, the primary cache needs to make room for the data of the read miss. The primary cache can be a direct mapped cache such that a read miss can only be stored in one location, indicated by the address of the read miss. The primary cache can allocate the data of the read miss location to move to the victim cache when the data is invalid and evict the data from the read miss location to issue to a higher level memory location when the data of the location is clean. For example, the primary cache controller can select a modified (e.g., invalid) line in the main storage to be a victim and select an unmodified (e.g., clean) line in the main storage to be evicted. A line of invalid and / or modified data is data that has been updated by the CPU 102. For example, when a cache line in the main storage 214 only exists in the current state and has been modified from the value in the main memory (e.g., such that a data read in the extended memory 106 is marked or permitted because it is not up to date or valid), the cache line is invalid and / or modified and thus a candidate for allocation (e.g., victimization). The example MESI RAM 300 stores and / or tracks cache line states (e.g., clean, invalid, shared, exclusive, etc.), thereby allowing and / or enabling identification of invalid lines in the main storage 214.

[0417] An allocation policy of the main storage can instruct the primary cache controller to select a victimized modified line because the data of the memory address is not located in a higher level cache or is located in a higher level cache but is stale. Such an allocation policy can instruct the primary cache controller not to allocate / victimize clean and / or shared lines in the main storage because the lines contain data that is already located in a higher level cache (e.g., L2 cache, L3 cache, extended memory, etc.) at the memory address.

[0418] However, such an allocation policy creates latency (e.g., increases the time needed for the CPU to retrieve the requested data) when only invalid and / or modified lines in the Ll cache 110 are allocated. The reason for the latency is the additional clock cycle used to retrieve from a higher level memory. For example, because of the parallel connection of the main storage 214 and the victim storage 218, it takes more time to retrieve data from a higher level memory than from the victim storage 218.

[0419] In the examples described herein, the allocation policy reduces latency of allocating cache lines from a primary cache (e.g., the home storage 214) to a victim cache (e.g., the victim storage 218). For example, due to the architecture of the LI cache 110 (e.g., the parallel connection between the home storage 214 and the victim storage 218), the allocation policy enables the primary cache controller 222 to allocate any cache line (e.g., clean and / or invalid) in the home storage 214 to the victim storage 218. The parallel configuration of the home storage 214 and the victim storage 218 enables the victim storage 218 to act as an extension of the home storage 214. Thus, in addition to providing a location to store victim lines, the victim storage 218 can also provide additional coherency to the home storage 214 by moving any cache line (e.g., clean and / or invalid) from the home storage 214 to the victim storage 214. For example, because the victim storage 218 and the home storage 214 are accessed in parallel (e.g., simultaneously) by the CPU 102, if a clean line is to be accessed and it is allocated to the victim storage 218, latency of accessing a line of clean data does not occur.

[0420] In an example operation, the primary cache controller 222 obtains an instruction (e.g., a memory operation) from the CPU interface 202 (e.g., the scalar interface 502 and / or the vector interface 504). The primary cache controller 222 obtains a result corresponding to the instruction from the primary tag RAM access 204. For example, the primary tag RAM access 204 determines whether an address in the instruction matches an address in the tag RAM 208 and provides a result to the primary cache controller 222. In some examples, the primary cache controller 222 determines that the home storage 214 will victimize and / or allocate data to the victim storage 218 based on the instruction and the result from the primary tag RAM access 204. For example, the primary cache controller 222 determines whether the instruction is a read operation and whether the read operation is a miss (e.g., determined based on the result of the primary tag RAM access 204). If the read operation is a miss, the primary cache controller 222 determines that the home storage 214 needs to allocate a line of data, a way, a block, a slot, etc. for allocation in the victim storage 218.

[0421] In some examples, the primary cache controller 222 allocates a row corresponding to an address of a read miss operation. For example, if a read operation wants to read data from address A but the main storage 214 stores different data at the address location (e.g., address A'), the primary cache controller 222 must evict the data at address A' because the data at address A can only be stored at one location in the main storage 214 (e.g., address A). The primary cache controller 222 identifies a location in the direct-mapped cache (e.g., the main storage 214) that maps to address A' and allocates the data at address A' to the victim storage 218. Thus, the read operation can store the data at address A in the main storage 214.

[0422] Example methods, apparatus, systems, and articles of manufacture for data allocation are described herein. Other examples and combinations thereof include the following:

[0423] Example 1 includes an apparatus comprising a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation specifying an address, determine that the memory operation evicts a first set of data from the first cache storage based on the address, determine that the first set of data is unmodified with respect to an extended memory, and cause the first set of data to be stored in the second cache storage.

[0424] Example 2 includes the apparatus of example 1, wherein the cache controller is to identify a portion of the first cache storage that corresponds to a direct-mapped location of the address.

[0425] Example 3 includes the apparatus of example 1, wherein the cache controller is to allocate the first set of data to the second cache storage to create space for data of a second memory operation.

[0426] Example 4 includes the apparatus of example 1, wherein the cache controller is to receive a second memory operation specifying a second address, determine that the second memory operation evicts a second set of data from the first cache storage based on the second address, determine that the second set of data is modified with respect to the extended memory, and cause the second set of data to be stored in the second cache storage.

[0427] Example 5 includes the apparatus of example 1, wherein the cache controller is to perform a pending transaction of a store queue on the first set of data during the eviction.

[0428] Example 6 includes the apparatus of Example 1, wherein the second cache storage is to provide coherency to the first cache storage while storing the first set of data in the second cache storage.

[0429] Example 7 includes the apparatus of Example 1, wherein the second cache storage is a victim cache storage.

[0430] Example 8 includes a method comprising: receiving a memory operation specifying an address, determining that the memory operation evicts a first set of data from a first cache storage based on the address, determining that the first set of data is unmodified with respect to an extended memory, and causing the first set of data to be stored in a second cache storage.

[0431] Example 9 includes the method of Example 8, further comprising identifying a portion of the first cache storage that corresponds to a direct mapped location of the address.

[0432] Example 10 includes the method of Example 8, further comprising allocating the first set of data to the second cache storage to create space for data of a second memory operation.

[0433] Example 11 includes the method of Example 8, further comprising receiving a second memory operation specifying a second address, determining that the second memory operation evicts a second set of data from the first cache storage based on the second address, determining that the second set of data is modified with respect to the extended memory, and causing the second set of data to be stored in the second cache storage.

[0434] Example 12 includes the method of Example 8, further comprising performing pending transactions of a store queue on the first set of data during the evicting.

[0435] Example 13 includes the method of Example 8, wherein storing the first set of data allocated from the first cache storage comprises providing coherency to the first cache storage.

[0436] Example 14 includes the method of Example 8, wherein the second cache storage is a victim cache storage.

[0437] Example 15 includes a system comprising a central processing unit to output a memory operation specifying an address and a cache coupled to the central processing unit, the cache usable to obtain the memory operation from the central processing unit, the cache further comprising a first cache storage, a second cache storage, and a cache controller to determine, based on the address of the memory operation, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified with respect to an extended memory, and cause the first set of data to be stored in the second cache storage.

[0438] Example 16 includes the system of Example 15, wherein the cache further comprises a first tag random access memory coupled to the central processing unit, the first cache storage, and the cache controller, and a second tag random access memory coupled to the central processing unit, the second cache storage, and the cache controller.

[0439] Example 17 includes the system of Example 15, wherein the cache controller is to determine, based on a second address of a second memory operation, that the second memory operation evicts a second set of data from the first cache storage, determine that the second set of data is modified with respect to the extended memory, and cause the second set of data to be stored in the second cache storage.

[0440] Example 18 includes the system of Example 15, wherein the cache controller is to execute, during the evicting, a pending transaction of a store queue on the first set of data.

[0441] Example 19 includes the system of Example 15, wherein the first cache storage and the second cache storage are connected in parallel to the central processing unit.

[0442] Example 20 includes the system of Example 15, wherein the first cache storage is a direct mapped cache and the second cache storage is a fully associative cache, the direct mapped cache and the fully associative cache coupled in parallel to the central processing unit.

[0443] Method and apparatus for facilitating read-modify-write support in a coherent victim cache with parallel data paths Figure 5

[0444] To facilitate a memory system that is memory coherent, i.e., a memory system in which the corresponding memory bits of each processing element contain the same stored data, some example systems cannot include a victim storage area. The examples described herein overcome this challenge by facilitating a fully coherent memory system in which a victim storage area (e.g., victim storage area 218) can operate in memory coherent operations in the system.

[0445] To provide coherency on the data cache 108, an example scalar interface 502 (e.g., a 64-bit wide interface) and an example vector interface 504 (e.g., a 512-bit wide interface) are included in the victim storage area 218 of the LI cache 110. In this way, the victim storage area 218 of the LI cache 110 is able to service both data paths of the CPU 102.

[0446] In some examples described herein, the snoop address component 506 is used to store the MESI state of each cache line in the victim storage area 218 in the MESI RAM 300. By storing the MESI state of each cache line in the MESI RAM 300, the victim cache system supports coherency.

[0447] Also, the example snoop address component 506 obtains an example snoop request from a higher level memory cache memory (e.g., the L2 data cache 112) and transmits such snoop requests to the tag RAM 210 and the comparison logic 306c. In some examples, the snoop address component 506 triggers an address read instruction to the tag RAM 210. For example, when the L2 data cache 112 is unable to identify the data requested in a read request from the CPU 102, the L2 data cache 112 transmits the snoop address component 506 to a lower level, i.e., the LI data cache 110, to attempt to perform a read request of the memory address in the tag RAM 210. Also, the snoop address component 506 provides the address read to the comparison logic 306c. In the event that a miss is identified (e.g., a read to the tag RAM 210 returns a miss), an appropriate snoop response indicating that the read was unsuccessful is generated and transmitted to the higher level data cache (e.g., the L2 data cache 112) that generated the snoop address component 506.

[0448] Alternatively, in cases where a hit is identified (e.g., a read return hit to the tag RAM 210 is issued), the state of the corresponding row in the MESI RAM 300 is read and the instance address encoder 326c generates an address value for the victim storage 218 to use to obtain the data. Thus, an appropriate response indicating that the read request was successful is generated and transmitted back to the higher level data cache (e.g., the L2 data cache 112) that generated the snoop address component 506 as a snoop response. In the examples described herein, the snoop response includes the data in the victim storage 218 corresponding to the address in the tag RAM 210.

[0449] In example operations, the corresponding storage queue (e.g., the victim cache storage queue 216) can handle write instructions to the address being read via the snoop address. Thus, when the victim storage 218 is servicing a snoop request (e.g., when the snoop request is being processed in response to the snoop address component 506 obtaining the snoop request), the victim cache storage queue 216 forwards data from the victim cache storage queue 216 (e.g., data stored in the latch 402e) to the response multiplexer 508. In this way, any state changes obtained via the vector interface 504 due to the snoop address and any recently updated addresses obtained from the victim cache storage queue 216 are forwarded to the higher level data cache (e.g., the L2 data cache 112).

[0450] In Method and apparatus for eviction in dual data path victim cache system the topology shown in FIG. 6, the coherence pipeline is longer than the victim cache pipeline in order to provide sufficient time for the victim cache controller 224 to properly order potential snoop responses and / or subsequent CPU 102 operations in the event such snoop responses and / or subsequent CPU 102 operations are issued to the higher level memory controller.

[0451] In the examples described herein, in cases where a request tracks a cache line, the victim storage 218 of the Ll data cache 110 is able to issue a tag update to the higher level cache controller. In this way, the victim storage 218 can facilitate tracking of the cache line to distinguish between exclusive and modified cache elements.

[0452] In the examples described herein, the victim storage 218 of the Ll data cache 110 supports global coherence operations by allowing global coherence operations to be processed on fully-associative caches and iterating over the tag RAM 208 based on the set.

[0453] Although the above operations are described in connection with the LI data cache 110, any of the above operations and / or elements can be implemented on any of the L2 data cache 112, the L3 data cache 114, and / or any additional level of data cache in the data cache 108.

[0454] Example methods, apparatus, systems, and articles of manufacture are described herein for facilitating read-modify-write support in a coherent victim cache having parallel data paths. Other examples and combinations thereof include the following:

[0455] Example 1 includes an apparatus comprising: a random access memory configured to be coupled to a central processing unit via a first interface and a second interface, the random access memory configured to obtain a read request indicating a first address read via a snoop interface; an address encoder coupled to the random access memory, the address encoder to generate a second address corresponding to a victim cache based on the first address when the random access memory indicates a hit for the read request; and a multiplexer coupled to the victim cache to transmit a response including data obtained from the second address of the victim cache.

[0456] Example 2 includes the apparatus of example 1, wherein the read request is transmitted through a two-level data cache.

[0457] Example 3 includes the apparatus of example 1, wherein the multiplexer is configured to be coupled to a victim cache way queue, the multiplexer to obtain input data from the victim cache way queue indicating a value to be written to the second address.

[0458] Example 4 includes the apparatus of example 3, wherein the multiplexer is configured to transmit the response including the input data from the victim cache way queue.

[0459] Example 5 includes the apparatus of example 1, wherein the random access memory is a tag random access memory.

[0460] Example 6 includes the apparatus of example 1, wherein the victim cache is a multi-banked memory.

[0461] Example 7 includes the apparatus of example 1, wherein the first interface is a scalar interface and the second interface is a vector interface.

[0462] Example 8 includes the apparatus of example 7, wherein the scalar interface is a 64-bit wide interface and the vector interface is a 512-bit wide interface.

[0463] Example 9 includes a system comprising a controller, a first memory, a second memory configured to obtain a snoop request from the first memory, the second memory to execute a read request of a random access memory in response to the snoop request, generate an address corresponding to a victim cache when the random access memory indicates a hit of the read request, the address to read the victim cache, and transmit a response to the second memory including data obtained from the address of the victim cache.

[0464] Example 10 includes the system of Example 9, wherein the first memory is a level two cache memory and the second memory is a level one cache memory.

[0465] Example 11 includes the system of Example 9, wherein the second memory includes a multiplexer configured to couple to a victim cache way queue, the multiplexer to obtain input data from the victim cache way queue indicating a value of the address of the victim cache to write into the second memory.

[0466] Example 12 includes the system of Example 11, wherein the multiplexer is configured to transmit the response including the input data from the victim cache way queue.

[0467] Example 13 includes the system of Example 9, wherein the second memory is coupled to the controller via a scalar interface and a vector interface, and the second memory is coupled to the first memory via a snoop interface.

[0468] Example 14 includes the system of Example 13, wherein the scalar interface is a 64-bit wide interface and the vector interface is a 512-bit wide interface.

[0469] Example 15 includes the system of Example 13, wherein the controller is a central processing unit.

[0470] Example 16 includes a method comprising obtaining a read request indicating a first address read via a snoop interface, generating a second address corresponding to a victim cache based on the first address when the read request is a hit, and generating a response including data obtained from the second address of the victim cache.

[0471] Example 17 includes the method of Example 16, further comprising transmitting the read request from a level two data cache.

[0472] Example 18 includes the method of Example 16, further comprising obtaining input data from a victim cache way queue indicating a value to write into the second address.

[0473] Example 19 includes the method of example 18, further comprising transmitting the response including the input data from the victim cache storage area queue.

[0474] Example 20 includes the method of example 16, wherein the victim cache is a multi-banked memory.

[0475] Figure 5

[0476] In a victim cache system, when a home cache (e.g., home storage 214) needs to store new data, the home cache sacrifices (e.g., allocates) a cache line to a victim cache (e.g., victim storage 218). When the home cache creates a victim, a replacement policy (e.g., replacement policy component 308) determines where the victim can be stored in the victim cache (e.g., victim storage 218). In some examples, the victim cache is full, thus data needs to be evicted to a higher level cache memory (e.g., L2 cache 112, L3 cache 114, expanded memory 106). When a write miss occurs, the victim cache (e.g., victim storage 218) also evicts data to a higher level cache memory. For example, the victim storage 218 includes a write miss buffer that buffers write miss data. The replacement policy can utilize a fixed scheme to determine which data to evict from the victim cache. For example, eviction schemes such as a first-in-first-out (FIFO) scheme, a random scheme, and a least recently used (LRU) scheme. However, such eviction schemes are not configured to efficiently manage evicting data from the victim cache when there are two or more data paths.

[0477] For example, a FIFO scheme evicts the data block that has been in the victim cache the longest time (e.g., the data in slot 0 if it is the first eviction to occur). In a dual data path victim cache system (e.g., victim cache segment shown in FIG. 2B), the FIFO scheme does not work when both incoming CPU accesses (e.g., instructions) miss and / or are both allocation instructions. In such examples, if both sets from the victim cache are not speculatively locked and read, then an additional stall is created. Figure 6

[0478] ​In different instances, the home storage 214 stores address A and the victim storage 218 stores address B. The CPU 102 sends two requests: the CPU 102 requests to read data at address A' with DP0 and the CPU 102 requests to read data from address B with DP1. The data at address A' is mapped to the same location in the home storage 214 as address A. Thus, the first data path DP0 needs to allocate data in address A to the victim storage 218 (e.g., allocate data at address A' to the home storage 214). In a conventional FIFO scheme, address A would be allocated to slot 0 of the victim storage 218. However, slot 0 is occupied by address B, and the CPU 102 requests to access address B in parallel with the request to allocate data of the read instruction to address A'. Thus, if data path DP0 evicts address B from slot 0, a stall (e.g., cause the CPU 102 to stall for one or more cycles of waiting for memory access) would occur to later retrieve the evicted data from a higher level cache.

[0479] The examples described herein include eviction schemes that efficiently evict data from the victim storage 218 in a dual data path victim cache system. The example eviction schemes are implemented by the replacement policy component 308 of FIGS. 3 and 5. For example, the replacement policy component 308 includes logic that analyzes inputs and produces outputs. For example, the replacement policy component 308 obtains inputs from the hit-miss comparison logic 306a and 306b and determines which location in the victim storage 218 is to be replaced by data from the home storage 214 and / or replaced by data from a write-miss instruction. In the examples described herein, the replacement policy component 308 preserves (e.g., reserves) an entry (e.g., way, set, cache line, etc.) in the victim storage 218 that corresponds to the eviction location. For example, the replacement policy component 308 speculatively locks (e.g., reserves) first and second victim cache lines (e.g., sets) that are dedicated for eviction. The first and second victim cache lines can be locked for a particular data path (e.g., a first victim cache line locked for DP0 and a second victim cache line locked for DP1). The following describes the eviction logic implemented by the replacement policy component 308 in more detail. Figure 6 The eviction logic implemented by the replacement policy component 308 is described in more detail.

[0480] Turning back Figure 6The example first table 602 and the example second table 604 are depicted. The example first table 602 and the second table 604 describe logic of the example replacement policy component 308. The example replacement policy component 308 utilizes LRU values. As used herein, an LRU value corresponds to a way that is the least recently used portion of the victim storage 218. In some examples, the LRU value corresponds to a location in the victim storage 218 that has not been accessed by the first or second data path most recently. In a fully associative cache (e.g., the victim storage 218), an address can map to any "way" in the cache. Thus, a way is a block in the cache that stores data and contains a tag. In some LRU schemes, when the victim cache needs to evict data, the data in the location indicated by the LRU value (e.g., the data in the portion of the victim storage 218 that has not been accessed most recently) is evicted. For example, in a 3-way cache, address A, address B, and address C occupy all three ways (e.g., blocks, slots, etc.). In this example, address A has been accessed most recently by the CPU 102, address B was accessed before address A, and address C was accessed before address B. Thus, address C is the least recently used address and the location of the portion of the address C that is mapped to equals the LRU value.

[0481] Figure 5 The example first table 602 of FIG. 6 includes a first data path scenario 606, a second data path scenario 608, and a third data path scenario 610. The example data path scenarios 606, 608, 610 correspond to validity of transactions (e.g., accesses) on the DP0 and DP1 of FIG. 5. The validity of transactions corresponds to whether the CPU 102 sent valid instructions to the L1 cache 110. Valid instructions on the first data path DP0 and invalid instructions on the second data path DP1 correspond to when the processing core sent instructions on the first data path DP0 and left the second data path DP1 idle. In some examples, the first data path DP0 includes invalid instructions during a particular clock cycle. In some examples, the second data path DP1 includes invalid instructions during a particular clock cycle. Additionally and / or alternatively, both data paths DP0 and DP1 can include valid instructions and / or can include invalid instructions. Figure 5 In the example first table 602 of FIG. 6, the first data path scenario 606 corresponds to when both data paths (DP0, DP1) of FIG. 5 include valid transactions within the same clock cycle (DP0_valid = 1, DP1_valid = 1). In some examples, the replacement policy component 308 obtains results and / or instructions from both data paths DP0, DP1.

[0482] Figures 3A-3D In the example first table 602 of FIG. 6, the second data path scenario 608 corresponds to when the first data path (DP0) of FIG. 5 includes valid transactions within the same clock cycle (DP0_valid = 1) and the second data path (DP1) of FIG. 5 includes invalid transactions within the same clock cycle (DP1_valid = 0). In some examples, the replacement policy component 308 obtains results and / or instructions from the first data path DP0.

[0483] ​In the example first table 602, the second data path scenario 608 corresponds to the first data path (DP0) containing a valid transaction (DP0_valid = 1) and the second data path (DP1) containing an invalid transaction (DP1_valid = 0). In such examples, the replacement policy component 308 determines that the transaction for DP1 contains an invalid instruction.

[0484] In the example first table 602, the third data path scenario 610 corresponds to the first data path (DP0) containing an invalid transaction (DP0_valid = 0) and the second data path (DP1) containing a valid transaction (DP1_valid = 1). In some examples, the replacement policy component 308 determines that the transaction for DP0 contains an invalid instruction.

[0485] The example first data path scenarios 606 in the example first table 602 include an example hit-hit action 612, an example miss-hit action 614, an example hit-miss action 616, and an example miss-miss action 618. The example hit-hit action 612 represents that the address on DP0 and the address on DP1 hit (e.g., match) an address in either of the tag RAMs 208, 210. In other words, the example hit-hit action 612 represents that the address on DP0 and the address on DP1 hit the main storage 214, the victim storage 218, and / or the write-miss cache (described above in connection with the example first table 602). Figure 11AThe miss-hit action 614 indicates that the address on DP0 does not match the addresses in the home storage 214, the victim storage 218, and / or the write miss cache, and the address on DP1 hits the addresses in the home storage 214, the victim storage 218, and / or the write miss cache. In some examples, the miss portion of the miss-hit action 614 indicates that DP0 is to allocate a cache line from the home storage 214 to the victim storage 218, and thus evict data from the victim storage 218 to make room for the cache line of the home storage 214. The hit-miss action 616 indicates that the address on DP0 hits the addresses in the victim storage 218 and / or the write miss cache, and the address on DP1 does not match the addresses in the victim storage 218 and / or the write miss cache. In some examples, the miss portion of the hit-miss action 616 indicates that DP1 is to allocate a cache line from the home storage 214 to the victim storage 218, and thus evict data from the victim storage 218 to make room for the cache line of the home storage 214. The miss-miss action 618 indicates that the addresses on both DP0 and DP1 do not match in the victim storage 218 and / or the write miss cache. In some examples, the miss-miss action 618 indicates that both data paths DP0 and DP1 are to allocate data from the home storage 214 to the victim storage 218. Additionally and / or alternatively, the miss indicates that the write miss is to write data to a write miss buffer in the victim storage 218.

[0486] The example second data path scenario 608 in the example first table 602 includes an example DP0 hit action 620 and an example DP0 miss action 622. In the second data path scenario 608, the first data path DP0 includes a valid transaction and the second data path DP1 includes an invalid transaction. In some examples, the replacement policy component 308 ignores the second data path DP1 because the second data path DP1 does not include an instruction.

[0487] The example third data path scenario 610 in the example first table 602 includes an example DP1 hit action 624 and an example DP1 miss action 626. The example DP1 hit action 624 corresponds to actions taken by the replacement policy component 308 when the address of the second data path DP1 matches an address in the victim storage 218 and / or write miss cache. The example DP1 miss action 624 corresponds to actions taken by the replacement policy component 308 when the address of the second data path DP1 does not match an address in the victim storage 218 and / or write miss cache. Similar to the example DP0 hit action 620 and DP0 miss action 622 under the example second data path scenario 608, the example replacement policy component 308 ignores transactions of the first data path DP0 in the example third data path scenario 610 because the transactions are invalid.

[0488] In the example first table 602, the DP0 hit way indicates a portion of the victim storage 218 and / or write miss cache that should be accessed (e.g., read from, evicted by, written to, etc.) by the first data path DP0 when the instruction is a hit. In the example first table 602, the DP1 hit way is a portion of the victim storage 218 and / or write miss cache that should be accessed by the second data path DP1 when the instruction is a hit.

[0489] In the example first table 602, the variable 'Y' is a variable that indicates a location of a current way selected as an LRU and indicates where the first data path DP0 should remove data from. In some examples, Y is assigned to a DP0 pointer. For example, when DP0 needs to evict a portion of the victim storage 218, then the DP0 pointer points to the location Y (e.g., LRU way) to evict from. In some examples, the replacement policy component 308 stores an indicator of the LRU way of the victim storage 218 to be replaced by DP0. For example, the replacement policy component 308 maintains an indicator that is accessible by the cache controller 220 that indicates that a particular way that has not been recently accessed is available for eviction by the first data path DP0. As used herein, the terms "pointer" and "indicator" are used interchangeably.

[0490] In the example first table 602, the variable 'Y+1' indicates the location of the next LRU way from which the second data path DP1 should remove data. In some examples, "Y+1" is assigned to the DP1 pointer. For example, when the second data path DP1 needs to evict a portion of the victim storage 218, the DP1 pointer points to the location Y+1 (e.g., the next LRU way) to evict. In some examples, the replacement policy component 308 holds an indicator of the LRU way of the victim storage 218 that is to be replaced by DP1. For example, the replacement policy component 308 maintains an indicator that is accessible by the cache controller 220 that indicates that a particular way that has not been recently accessed is available for eviction by the first data path DPO.

[0491] In a first example operation of the replacement policy component 308, both data paths (DPO and DP1) contain valid transactions (e.g., indicated in the first data path scenario 606) and both data paths (DPO and DP1) contain addresses that match addresses in the example victim storage element 218 (e.g., a hit-hit action 612). For example, the comparison logic 306a and 306b compare the addresses of DPO and DP1 to the addresses in the example tag RAM 210 and provide hit results to the replacement policy component 308. Since both data paths are valid and both data paths are hits, the DPO hit way points to the portion (e.g., way) of the victim storage 218 that contains hit / matching data corresponding to the data path DPO and the DP1 hit way points to the way that contains hit / matching data corresponding to the data path DP1. The victim storage 218 responds with the requested data. The location of the LRU way does not increase and remains at location Y.

[0492] In a second example operation of the replacement policy component 308, both data paths (DPO and DP1) contain valid transactions (e.g., indicated in the first data path scenario 606), the first data path DPO is a miss, and the second data path DP1 hits the victim storage 218 (e.g., a miss-hit action 614). For example, the first comparison logic 306a returns a "miss" result to the replacement policy component 308 and the second comparison logic 306b returns a "hit" result to the replacement policy component 308. The DP1 hit way points to the portion (e.g., way) of the victim storage 218 that contains hit / matching data (e.g., the hit way). In some examples, the first data path DPO will evict data from a portion (e.g., way) of the victim storage 218. Accordingly, the DPO pointer points to the location Y of the victim storage 218 that is to be evicted.

[0493] Before eviction occurs, the replacement policy component 308 determines whether the DP1 hitway matches the address (e.g., location Y) of the LRU way. If the DP1 hitway does not have the same location as Y, then the DP0 pointer points to a way (e.g., the LRU way) that has a location equal to location Y. If the DP1 hitway does match the address of the LRU way, then the DP0 pointer points to the location of the DP1 pointer (Y+1) so that DP0 can evict data without colliding with the DP1 hitway.

[0494] In the second example scenario 614, the LRU value and the next LRU value are increased based on which location is evicted. For example, if DP0 evicts data from location Y+1 (e.g., the DP1 hitway matches the location of the DP0 pointer), then the LRU value is increased twice and the next LRU value is increased twice. Otherwise, if DP0 evicts data from location Y (e.g., the DP1 hitway does not match the location of the DP0 pointer), then the LRU value is increased once and the next LRU value is increased once.

[0495] In a third example operation of the replacement policy component 308, both data paths (DP0 and DP1) contain valid transactions (e.g., indicated in the first data path scenario 606), the first data path DP0 is a hit, and the second data path DP1 is a miss (e.g., a hit-miss action 616). For example, the first comparison logic 306a returns a "hit" result to the replacement policy component 308 and the second comparison logic 306b returns a "miss" result to the replacement policy component 308. The DP0 hitway points to a way in the victim storage 218 that contains the hit / matching data. In some examples, the miss causes the second data path DP1 to evict a way to free up space in the victim storage 218. Accordingly, the DP1 pointer points to location Y+1 in the victim storage 218 that will be evicted.

[0496] Before eviction occurs, the replacement policy component 308 determines whether the DP0 hitway matches the address (e.g., location Y+1) of the next LRU way. If the replacement policy component 308 determines that the DP0 hitway matches the address (e.g., location Y+1) of the next LRU way, then the DP1 pointer points to the location of the DP0 pointer (e.g., location Y) so that DP1 can evict data without colliding with the DP0 hitway. If the DP0 hitway does not match the address of the next LRU way, then DP1 evicts data from location Y+1.

[0497] In a third example scenario 616, the LRU value and the next LRU value are increased based on which location is evicted. For example, if DP1 evicts data from location Y (e.g., the DP0 hitway matches the location of the DP1 pointer), the LRU value is increased by one and the next LRU value is increased by one. Otherwise, if DP1 evicts data from location Y+1 (e.g., the DP0 hitway does not match the location of the DP1 pointer), the LRU value is increased by two and the next LRU value is increased by two.

[0498] In a fourth example operation of the replacement policy component 308, both data paths (DP0 and DP1) contain valid transactions (e.g., indicated in the first data path scenario 606) and both data paths are marked as misses (e.g., column 618). For example, when neither of the addresses in data paths DP0 and DP1 are found and / or do not match an address in the tag RAMs 208, 210, the comparison logic 306a and 306b return a "miss" result to the replacement policy component 308. In the fourth operation, both data paths DP0 and DP1 will evict a way in the victim storage 218. Thus, the DP0 pointer points to location Y and the DP1 pointer points to location Y+1.

[0499] When both eviction operations are complete, the LRU value is increased by two (e.g., Y+2) and the next LRU value is increased by two (e.g., (Y+1)+2). In a subsequent operation, if DP0 and DP1 miss, the DP0 hitway points to the new LRU value (e.g., Y+2) and the DP1 hitway points to the next LRU value (e.g., (Y+1)+2).

[0500] In a fifth example operation of the replacement policy component 308, the first data path DP0 is a valid transaction and the second data path DP1 is an invalid transaction (e.g., indicated in the second data path scenario 608). In the fifth example operation, the first data path DP0 is a hit (e.g., indicated in the DP0 hit action 620). For example, the comparison logic 306a returns a "hit" result to the replacement policy component 308. The DP0 hitway points to the way in the victim storage 218 that contains the matching data. The LRU value (Y) remains the same because no data is to be evicted within the clock cycle.

[0501] In a sixth example operation of the replacement policy component 308, the first data path DP0 is a valid transaction and the second data path DP1 is an invalid transaction (e.g., indicated in the second data path scenario 608). In the sixth example operation, the first data path DP0 is a...

Claims

1. A storage device comprising: First storage area; Second storage area; A storage queue coupled to the first storage area and the second storage area, the storage queue being capable of: First memory operation to receive the specified first set of data; Process the first memory operation to store the first set of data in at least one of the first memory area and the second memory area; Receive second memory operation; as well as Before storing the first set of data in at least one of the first and second storage areas, the first set of data is fed back for use in the second memory operation.

2. The storage device according to claim 1, wherein: The second memory operation is a read-modify-write operation, specifying a second set of data; and The storage queue can be used for: Before storing the first set of data in at least one of the first storage area and the second storage area, the first set of data and the second set of data are merged to generate a third set of data; as well as The third set of data is provided for storage in at least one of the first storage area and the second storage area.

3. The storage device according to claim 2, further comprising a third memory operation of receiving an instruction to read the third set of data.

4. The storage device of claim 1, wherein the second storage area is configured as a victim storage area of ​​the first storage area.

5. The storage device of claim 1, wherein the storage queue further comprises a data storage area configured to store a first address value of the first group of data.

6. The storage device of claim 1, wherein the storage queue further comprises an error code correction generator for generating error detection codes.

7. The storage device of claim 6, wherein the error code correction generator generates the error detection code in response to processing the first memory operation.

8. A method for memory operations, comprising: First memory operation to receive the specified first set of data; Process the first memory operation to store the first set of data in at least one of a first storage area and a second storage area; Receive second memory operation; as well as Before storing the first set of data in at least one of the first and second storage areas, the first set of data is transmitted for use in the second memory operation.

9. The method of claim 8, wherein the second memory operation is a read-modify-write operation, and a second set of data is specified, the method further comprising: Before storing the first set of data in at least one of the first and second storage areas, the first set of data and the second set of data are merged to generate a third set of data; and The third set of data is provided for storage in at least one of the first storage area and the second storage area.

10. The method of claim 9, further comprising receiving a third memory operation instructing the reading of the third set of data.

11. The method of claim 8, wherein the second storage area is configured as a victim storage area of ​​the first storage area.

12. The method of claim 8, further comprising storing a first address value for the first set of data.

13. The method of claim 8, further comprising generating an error detection code.

14. The method of claim 13, further comprising generating the error detection code in response to processing the first memory operation.

15. A computing system comprising: A central processing unit configured to transmit first memory operations and second memory operations; A first storage area, which is coupled to the central processing unit; A second storage area is coupled to the central processing unit; A storage queue, coupled to the first storage area, the second storage area, and the central processing unit, is capable of: The first memory operation that receives the specified first group of data; Process the first memory operation to store the first set of data in at least one of the first memory area and the second memory area; Receive the second memory operation; as well as Before storing the first set of data in at least one of the first and second storage areas, the first set of data is fed back for use in the second memory operation.

16. The computing system according to claim 15, wherein: The second memory operation is a read-modify-write operation, specifying a second set of data; and The storage queue can be used for: Before storing the first set of data in at least one of the first storage area and the second storage area, the first set of data and the second set of data are merged to generate a third set of data; as well as The third set of data is provided for storage in at least one of the first storage area and the second storage area.

17. The computing system of claim 16, further comprising a third memory operation for receiving an instruction to read the third set of data.

18. The computing system of claim 15, wherein the second storage area is configured as a victim storage area of ​​the first storage area.

19. The computing system of claim 15, wherein the storage queue further comprises a data storage area configured to store a first address value of the first set of data.

20. The computing system of claim 15, wherein the storage queue further comprises an error code correction generator for generating an error detection code in response to processing the first memory operation.

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