Semiconductor device and automotive electronic control device

Abstract

Provided is a semiconductor device having a current mirror circuit, which is capable of reducing variations in the mirror ratio of the current mirror circuit and suppressing temporal changes in element matching properties.

Description

Technical Field

[0001] The present invention relates to a structure of a semiconductor device constructed using a multilayer wiring technology, and more particularly to an effective technology applicable to a semiconductor device requiring small element matching variations and high reliability. Background Art

[0002] Current mirror circuits, commonly used in analog integrated circuits, convert input current to a desired multiplication factor (mirror ratio) based on the sizes of the MOS transistors on the input and output sides, and output the resulting current. To ensure high-precision operation of semiconductor integrated circuit devices using current mirror circuits, it is necessary to reduce variations in the matching of the transistors that comprise the current mirror circuits and suppress any temporal fluctuations in matching.

[0003] Furthermore, in semiconductor integrated circuit devices, metal wiring that connects elements such as transistors, diodes, resistors, and capacitors is typically formed on these elements via an interlayer insulating film (interlayer oxide film). This metal wiring (wiring pattern) is formed by repeatedly forming metal and insulating films and patterning using photolithography.

[0004] Typically, when forming multi-layer metal wiring, the upper wiring layers farther from the transistors are used for long-distance connections within the chip, power supply lines, and the like. To reduce impedance, these layers are often thicker or wider than the lower wiring layers closer to the transistors. Furthermore, in recent years, in semiconductor devices equipped with power transistors for controlling high currents, copper redistribution (Copper Redistribution) is sometimes used as a further layer above the passivation film of the semiconductor device.

[0005] However, because the metal and insulating films formed on a semiconductor substrate have different linear expansion coefficients from the semiconductor substrate, thermal strain occurs in the semiconductor element due to temperature fluctuations caused by the ambient temperature around the semiconductor element and self-heating. Thermal strain in the wiring patterns surrounding components such as transistors and resistors is a major cause of variations and fluctuations in the electrical characteristics of these components.

[0006] As a technology for reducing the temporal variation of elements caused by wiring patterns, there is, for example, Patent Document 1. Patent Document 1 discloses a technology for reducing the influence of dummy wiring on MOS transistors by defining the arrangement of dummy wiring above a pair of MOS transistors.

[0007] Patent document 1 describes a semiconductor device having a dummy wiring for mechanical chemical polishing averaging arranged on an upper layer of a transistor, wherein the dummy wiring is arranged so as not to overlap with any of the paired transistors when viewed from above, or the portions overlapping with the first transistor and the second transistor are the same in the first transistor and the second transistor.

[0008] Prior art literature

[0009] Patent Literature

[0010] Patent Document 1: Japanese Patent Application Laid-Open No. 2003-100899 Summary of the Invention

[0011] Problems to be solved by the invention

[0012] As mentioned above, wide wiring is sometimes used in upper wiring layers far from transistors. These wiring widths are sometimes wider than the individual transistors that form a pair, and narrower than the entire array of paired transistors. When such wide wiring is placed around paired transistors, in order to maintain a consistent wiring pattern as seen from each transistor, the wide wiring must be routed around the transistor array, increasing chip size.

[0013] In particular, in a current mirror circuit used in an analog-to-digital converter or the like, since the number of transistors included is large, the influence on the chip size is significant.

[0014] Therefore, an object of the present invention is to provide a semiconductor device having a current mirror circuit, which is capable of reducing variations in the mirror ratio of the current mirror circuit and suppressing temporal changes in element matching.

[0015] Technical means to solve the problem

[0016] In order to solve the above-mentioned problems, the present invention comprises: a first semiconductor element group, which is composed of a plurality of semiconductor elements connected in parallel; a second semiconductor element group, which is arranged on the same layer as the first semiconductor element group and is composed of a plurality of semiconductor elements connected in parallel; and a plurality of wirings, which are arranged on the upper layer of the first semiconductor element group and the second semiconductor element group and are wider than the width of each semiconductor element of the first semiconductor element group and the second semiconductor element group. The first semiconductor element group and the second semiconductor element group are paired to form a circuit with a specified pairing accuracy, and the plurality of wirings are arranged in such a manner that a combination of each distance in the planar direction from each semiconductor element of the first semiconductor element group to the wiring at the nearest position in the planar direction is equal to a combination of each distance in the planar direction from each semiconductor element of the second semiconductor element group to the wiring at the nearest position in the planar direction.

[0017] Effects of the Invention

[0018] According to the present invention, in a semiconductor device including a current mirror circuit, a highly reliable semiconductor device capable of reducing variations in the mirror ratio of the current mirror circuit and suppressing temporal changes in element pairing can be realized.

[0019] Other problems, structures, and effects than those described above will become clear from the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a plan view of the semiconductor device according to the first embodiment of the present invention.

[0021] Figure 2 This is a circuit diagram of a semiconductor device according to a first embodiment of the present invention.

[0022] Figure 3A This is a diagram showing a simulation model of thermal strain in wiring.

[0023] Figure 3B Yes Figure 3A Plot of the simulation results of thermal strain of the model.

[0024] Figure 4 yes Figure 1 A partially enlarged view of the semiconductor device shown.

[0025] Figure 5 yes Figure 4 A-A' cross-sectional view.

[0026] Figure 6 It is a plan view of a conventional semiconductor device.

[0027] Figure 7 This is a circuit diagram of a conventional semiconductor device.

[0028] Figure 8 It is a plan view of a semiconductor device according to a second embodiment of the present invention.

[0029] Figure 9 yes Figure 8 BB' cross-section diagram.

[0030] Figure 10 yes Figure 8 A partially enlarged view of the semiconductor device shown.

[0031] Figure 11 yes Figure 10 C-C' cross-section diagram.

[0032] Figure 12 It is a plan view of a semiconductor device according to a third embodiment of the present invention.

[0033] Figure 13 yes Figure 12 D-D' cross-section diagram.

[0034] Figure 14 yes Figure 12 A partially enlarged view of the semiconductor device shown.

[0035] Figure 15 yes Figure 14 E-E' cross-section diagram.

[0036] Figure 16 It is a plan view of a semiconductor device according to a fourth embodiment of the present invention.

[0037] Figure 17 This is a circuit diagram of a semiconductor device according to a fourth embodiment of the present invention.

[0038] Figure 18 yes Figure 16 A partially enlarged view of the semiconductor device shown.

[0039] Figure 19 It is a plan view of a semiconductor device according to a fifth embodiment of the present invention.

[0040] Figure 20 It is a plan view of a semiconductor device according to a sixth embodiment of the present invention.

[0041] Figure 21 This is a circuit diagram of a semiconductor device according to a sixth embodiment of the present invention. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. In the drawings, the same components are given the same reference numerals, and detailed descriptions of the overlapping components will be omitted.

[0043] Example 1

[0044] Reference Figures 1 to 7 , a semiconductor device according to the first embodiment of the present invention is described. Figure 6 as well as Figure 7 These are a plan view and a circuit diagram of a conventional semiconductor device shown as a comparative example to facilitate understanding of the present invention.

[0045] Figure 1 1 is an example showing the positional relationship between the MOS transistors M01 to M74 and the wide wiring 20 constituting the current mirror circuit in the semiconductor device of this embodiment. Figure 1 As shown, a plurality of MOS transistors M01 to M74 are arranged in an array in the X direction, and a plurality of wide wirings 20 are arranged extending in the Y direction perpendicular to the MOS transistors M01 to M74. The width W2 of a wide wiring 20 is approximately four times the width W1 of a MOS transistor.

[0046] Figure 2 express Figure 1 Circuit diagram of the semiconductor device shown. Figure 2The mirror source of the mirror circuit is formed by connecting four MOS transistors M01 to M04 in parallel to the mirror terminal 100. In addition, the mirror target is formed by connecting four MOS transistors M11 to M14, M21 to M24, etc. in parallel to each of the mirror terminals 101 to 107. However, Figure 1 The configuration order of the MOS transistors can also be Figure 2 different.

[0047] exist Figure 1 In FIG. 5 , MOS transistors are dispersedly arranged in parallel, such as M01 to M71, M02 to M72, M03 to M73, and M04 to M74 from the left.

[0048] Furthermore, M01 to M31 are arranged from the left in the order M01, M11, M21, and M31. M02 to M32 are arranged from the left in the order M12, M22, M32, and M02, changing their order one by one. M03 to M43 and M04 to M44 are arranged in the same order. M41 to M71, M42 to M72, M43 to M73, and M44 to M74 are also arranged in the same order.

[0049] Here, use Figure 3A as well as Figure 3B The influence of wiring pattern stress on MOS transistors is described. Figure 3A This is a cross-sectional view of a thermal stress simulation model in which a silicon oxide film 401 as an interlayer oxide film, a polyimide film 500, and a copper wiring 200 are arranged on an SOI substrate composed of a silicon substrate (semiconductor substrate) 300, a silicon oxide film 400, and a silicon (Si) layer 301. In addition, Figure 3B yes Figure 3A Simulation results of the strain amount at the interface 302 between the silicon layer 301 and the silicon oxide film 401.

[0050] like Figure 3B As shown, the thermal strain at the silicon interface 302 is affected by the upper wiring (copper wiring 200) and varies depending on the planar distance from the wiring end. Furthermore, the mobility of electrons and holes within silicon depends on the amount of silicon strain. Thus, the electrical characteristics of semiconductor devices vary depending on their positional relationship with the wiring pattern. Therefore, in semiconductor devices requiring compatibility, the placement and shape of the upper wiring patterns of each device must be considered.

[0051] Next, the detailed positional relationship between the MOS transistor and the wide wiring 20 , which are components of this embodiment, will be described. Figure 4 It is an enlarged representation Figure 1 A plan view of the region of eight MOS transistors M01 to M71 from the left. Figure 5 yes Figure 4A-A' section diagram. Figure 4 as well as Figure 5 In the example, for the MOS transistors M01 to M71 , the pattern of the upper wiring layer 10 close to the MOS transistors is laid out so as to be the same from the perspective of each MOS transistor. The strain applied by these wiring layers 10 to the MOS transistors is the same in each MOS transistor.

[0052] The planar distances from MOS transistors M01, M11, M21, and M31 to the wiring end of wide wiring 20 are set to D2, D1, E1, and E2, respectively. The planar distances from the wiring end of wide wiring 20 are also the same for M41 through M71. Furthermore, due to the presence or absence of overlying wide wiring 20 and the planar distances from the wiring end, M01 through M71 are affected differently by the thermal strain caused by wide wiring 20, which reduces the compatibility of the MOS transistors.

[0053] However, in Figure 2 In the circuit, Figure 1 When the MOS transistor and the wide wiring 20 are arranged as described above, Figure 2 In the group of MOS transistors of the mirror terminals 101 to 107, the combination of the distances in the planar direction from the MOS transistors to the nearest wide wiring 20 is as follows, for example.

[0054] 《Mirror Terminal 100》 (Mirror Source)

[0055] Transistors M01 to M04: distances D2, E2, E1, and D1 to wide wiring 20

[0056] Mirror Terminal 101 (Mirror Target)

[0057] Transistors M11 to M14: distances D1, D2, E2, and E1 to wide wiring 20

[0058] 《Mirror Terminal 102》 (Mirror Target)

[0059] Transistors M21 to M24: distances E1, D1, D2, and E2 from wide wiring 20

[0060] 《Mirror Terminal 103》 (Mirror Target)

[0061] Transistors M31 to M34: distances E2, E1, D1, and D2 from wide wiring 20

[0062] The same is true for mirror terminals 104 to 107. Since they are all combinations of (D1, D2, E1, E2), Figure 2The electrical characteristics of the MOS at each mirror terminal are the same. Therefore, as a current mirror circuit, the matching of the mirror source and each mirror destination can be ensured.

[0063] The present embodiment is configured to include: a circuit requiring matching, which at least comprises: a first semiconductor element group (a group of mirror terminals 100) formed by connecting a plurality of semiconductor elements (MOS transistors M01 to M04) in parallel; and a second semiconductor element group (a group of mirror terminals 101) formed by connecting a plurality of semiconductor elements (MOS transistors M11 to M14) in parallel; and a plurality of wirings formed on the upper layer of each semiconductor element group (100, 101) and having a width wider than one width of the semiconductor element M01, so as to extend from each semiconductor element (M01 to M04) constituting the first semiconductor element group (100) to the second semiconductor element group (101) in the plane direction. A plurality of wide wirings 20 are arranged in such a manner that a combination of respective distances (D2, E2, E1, D1) in the planar direction from the wide wiring 20 at the closest position on the plane is the same as a combination of respective distances (D1, E2, E1, D1) in the planar direction from each semiconductor element (M11 to M14) constituting the second semiconductor element group (101) to the wide wiring 20 at the closest position in the planar direction, thereby making it possible to make the influence of stress received by the wide wiring 20 on the first semiconductor element group (the group of the mirror terminal 100) and the influence of stress received by the wide wiring 20 on the second semiconductor element group (the group of the mirror terminal 101) approximately equal.

[0064] Since the degree of degradation caused by stress can be made equal, the pairing of the first semiconductor element group (the group with mirror terminal 100) and the second semiconductor element group (the group with mirror terminal 101) can be maintained, and aging degradation (temporal change) can be suppressed.

[0065] Furthermore, in this embodiment, a current mirror circuit is cited as an example of a circuit requiring matching properties. However, the present invention is not limited thereto and can be widely applied to other circuits requiring matching properties (matching accuracy).

[0066] Furthermore, although the example of a configuration in which the number of MOS transistors (semiconductor elements) constituting each semiconductor element group is four is given, the present invention is not limited thereto. Similarly, the number of semiconductor element groups constituting a circuit requiring matching is not limited to seven.

[0067] On the other hand, Figure 6 as well as Figure 7 In the conventional semiconductor device shown, the MOS transistors constituting the current mirror circuit are not dispersedly arranged. In this case, since the influence of the wide wiring 20 varies among the MOS transistors M0 to M7, the pairing of the MOS transistors is reduced, and the mirror ratio of the current mirror circuit also varies depending on the mirror target.

[0068] As described above, the semiconductor device of this embodiment includes: a first semiconductor element group (the group with mirror terminal 100) comprising a plurality of semiconductor elements (MOS transistors M01 to M04) connected in parallel; a second semiconductor element group (the group with mirror terminal 101) arranged in the same layer as the first semiconductor element group (the group with mirror terminal 100) and comprising a plurality of semiconductor elements (MOS transistors M11 to M14) connected in parallel; and a plurality of wide-width wirings 20 arranged in an upper layer above the first semiconductor element group (the group with mirror terminal 100) and the second semiconductor element group (the group with mirror terminal 101) and having a width W2 greater than the width W1 of each semiconductor element in the first semiconductor element group (the group with mirror terminal 101) and the second semiconductor element group (the group with mirror terminal 101). The first semiconductor element group (the group with mirror terminal 100) and the second semiconductor element group (the group with mirror terminal 101) are paired to form a circuit with predetermined pairing accuracy. A plurality of wide wirings 20 are arranged so that the combination of the distances in the planar direction from each semiconductor element (MOS transistors M01 to M04) in the first semiconductor element group (the group with mirror terminal 100) to the wide wiring 20 closest to the planar direction is equal to the combination of the distances in the planar direction from each semiconductor element (MOS transistors M11 to M14) in the second semiconductor element group (the group with mirror terminal 101) to the wide wiring 20 closest to the planar direction.

[0069] The above circuit is a current mirror circuit, the first semiconductor element group (the group with mirror terminal 100) is the mirror source of the current mirror circuit, and the second semiconductor element group (the group with mirror terminal 101) is the mirror destination of the current mirror circuit.

[0070] Thus, in a semiconductor device including a current mirror circuit, a highly reliable semiconductor device capable of reducing variations in the mirror ratio of the current mirror circuit and suppressing temporal changes in the matching performance of elements can be realized.

[0071] Furthermore, by mounting the semiconductor device of this embodiment on an in-vehicle electronic control device, the reliability of the in-vehicle electronic control device can be improved.

[0072] Example 2

[0073] Reference Figures 8 to 11 , a semiconductor device according to a second embodiment of the present invention is described. Figure 8 This is an example showing the planar positional relationship among the MOS transistors M01 to M74, the wide wiring 20, and the wide wiring 30 of a wiring layer different from the wide wiring 20, which constitute the current mirror circuit in the semiconductor device of this embodiment. Figure 8 In the embodiment, MOS transistors M01 to M74 and wide wiring 20 are connected to Figure 1In addition, the current mirror circuit of this embodiment is the same as Figure 2 same. Figure 9 express Figure 8 BB' section.

[0074] The following describes the detailed arrangement of the MOS transistor and the wide wiring 20 and 30 of this embodiment. Figure 10 It is an enlarged representation Figure 8 A plan view of the region of eight MOS transistors M01 to M71 from the left, Figure 11 yes Figure 10 C-C' cross-section diagram. Figure 10 as well as Figure 11 The distances D1, D2, E1, and E2 between the MOS transistors M01 to M71 and the wide wiring 20 in the plane direction are the same as those in the first embodiment. Figure 4 、 Figure 5 same.

[0075] like Figure 10 as well as Figure 11 As shown, the distances in the planar direction between the wide wiring 30 and the MOS transistors M01, M11, M21, and M31 are G1, F1, F2, and F3, respectively. The same applies to M41, M51, M61, and M71.

[0076] Through Figure 8 That configuration Figure 9 The MOS transistor of the current mirror circuit, the wide wiring 20 of the upper layer, and the wide wiring 30 of the wiring layer different from the wide wiring 20, Figure 2 In each group of MOS transistors connected to each terminal mirror 101 to 107 in the circuit diagram, the distance in the planar direction from the MOS transistor to the wide wiring 30 is, for example, as follows: all of which are combinations of F1, F2, F3, and G1.

[0077] 《Mirror Terminal 100》 (Mirror Source)

[0078] Transistors M01 to M04: distances G1, F3, F2, and F1 to wide wiring 30

[0079] 《Mirror Terminal 101》(Mirror Target).

[0080] Transistors M11 to M14: distances F1, G1, F3, and F2 to wide wiring 30

[0081] <<Mirror terminal 102>> (mirror target).

[0082] Transistors M21 to M24: distances F2, F1, G1, and F3 to wide wiring 30

[0083] 《Mirror Terminal 103》 (Mirror Target)

[0084] Transistors M31 to M34: distances F3, F2, F1, and G1 to wide wiring 30

[0085] As described above, the combination of the distances in the planar direction from the MOS transistor to the wide wiring 20 and the wide wiring 30 is the same between the terminals of the mirror source (100) and the mirror destination (101 to 107) of the current mirror circuit, so that the influence of the stress of the wide wiring can be made equal on the terminals of the mirror source and the mirror destination, thereby reducing the initial deviation of the mirror ratio of the current mirror circuit and suppressing the degradation (time-dependent change) over time.

[0086] As described above, in the semiconductor device of this embodiment, the plurality of wirings include: a plurality of wide wirings 20 arranged in a first wiring layer; and a plurality of wide wirings 30 arranged in a second wiring layer different from the first wiring layer, with the combination of the distances in the planar direction from each semiconductor element (MOS transistors M01, M11, M21, M31) of the first semiconductor element group (the group of mirror terminal 100) to the wide wiring 20 arranged in the first wiring layer at the nearest position in the planar direction and the distances in the planar direction from each semiconductor element (MOS transistors M41, M51, M61, M71) of the second semiconductor element group (the group of mirror terminal 101) to the wide wiring 20 arranged in the first wiring layer at the nearest position in the planar direction. The plurality of wide wirings 20 of the first wiring layer are arranged so that combinations of distances in the planar direction from each semiconductor element (MOS transistors M01, M11, M21, M31) of the first semiconductor element group (the group having the mirror terminal 100) to the wide wiring 30 arranged in the second wiring layer at the nearest position in the planar direction are equal to combinations of distances in the planar direction from each semiconductor element (MOS transistors M41, M51, M61, M71) of the second semiconductor element group (the group having the mirror terminal 101) to the wide wiring 30 arranged in the second wiring layer at the nearest position in the planar direction.

[0087] Example 3

[0088] Reference Figures 12 to 15 , a semiconductor device according to a third embodiment of the present invention is described. Figure 12 This is an example showing the planar positional relationship among the MOS transistors M01 to M74, the wide wiring 20, and the wide wiring 31 of a wiring layer different from the wide wiring 20, which constitute the current mirror circuit in the semiconductor device of this embodiment. Figure 12 In the embodiment, MOS transistors M01 to M74 and wide wiring 20 are connected to Figure 1In addition, the current mirror circuit of this embodiment is the same as Figure 2 same. Figure 13 express Figure 12 D-D' cross-section diagram.

[0089] In this embodiment, if Figure 13 As shown, wide wiring 31 is arranged on the MOS transistor side (lower layer side) of wide wiring 20 .

[0090] The following describes the detailed arrangement of the MOS transistor and the wide wiring 20 and 31 of this embodiment. Figure 14 It is an enlarged representation Figure 12 A plan view of the region of eight MOS transistors M01 to M71 from the left, Figure 15 yes Figure 14 E-E' section diagram. Figure 14 as well as Figure 15 The distances D1, D2, E1, and E2 between the MOS transistors M01 to M71 and the wide wiring 20 in the plane direction are the same as those in the first embodiment. Figure 4 、 Figure 5 same.

[0091] In addition, the distances between the overlapping area of ​​the wide wiring 20 and the wide wiring 31 and the MOS transistors M01, M11, M21, and M31 in the plane direction are H3, H2, H1, and J1, respectively. Figure 12 、 Figure 13 In this configuration, Figure 2 In the group of MOS transistors connected to the mirror terminals 101 to 107 in the circuit diagram, the distances in the planar direction from the MOS transistors to the overlapping region of the wide wiring 20 and the wide wiring 31 are all combinations of H1, H2, H3, and J1 as described below.

[0092] 《Mirror Terminal 100》 (Mirror Source)

[0093] Transistors M01 to M04: distances to wide wiring 31 H3, J1, H1, H2

[0094] Mirror Terminal 101 (Mirror Target)

[0095] Transistors M11 to M14: distances H2, H3, J1, H1 to wide wiring 31

[0096] 《Mirror Terminal 102》 (Mirror Target)

[0097] Transistors M21 to M24: distances H1, H2, H3, and J1 to wide wiring 31

[0098] 《Mirror Terminal 103》 (Mirror Target)

[0099] Transistors M31 to M34: distances J1, H1, H2, and H3 to wide wiring 31

[0100] As described above, the combination of the distances in the planar direction from the MOS transistor to wide wiring 20 and wide wiring 31 and the combination of the distances in the planar direction from the MOS transistor to the overlap of wide wiring 20 and wide wiring 31 are made the same for each combination of MOS transistors at the mirror source and mirror destination terminals of the current mirror circuit. This makes it possible to make the influence of the stress of the wide wiring equal at the mirror source and the mirror destination, thereby reducing the initial deviation of the mirror ratio of the current mirror circuit and suppressing its degradation over time (change over time).

[0101] As described above, in the semiconductor device of this embodiment, the plurality of wirings include: a plurality of wide wirings 20 arranged in a first wiring layer; and a plurality of wide wirings 31 arranged in a second wiring layer different from the first wiring layer. The plurality of wirings are arranged so that the wide wirings 20 arranged in the first wiring layer and the wide wirings 31 arranged in the second wiring layer overlap, so that the plurality of wirings are arranged from each semiconductor element (MOS transistors M01, M11, M21, and M31) of the first semiconductor element group (the group of mirror terminals 100) to the nearest one arranged in the first wiring layer in the planar direction. The wide wiring 20 arranged in the first wiring layer and the wide wiring 31 arranged in the second wiring layer are arranged so that the combination of the distances in the planar direction from the respective semiconductor elements (MOS transistors M41, M51, M61, and M71) of the second semiconductor element group (the group of mirror terminals 101) to the nearest position in the planar direction at which the wide wiring 20 arranged in the first wiring layer and the wide wiring 31 arranged in the second wiring layer overlap is equal.

[0102] Example 4

[0103] Reference Figures 16 to 18 , a semiconductor device according to a fourth embodiment of the present invention is described. Figure 16 1 is an example showing the positional relationship between the MOS transistors M01 to M84 and the wide wiring 21 in the plane constituting the current mirror circuit in the semiconductor device of this embodiment. Figure 17 express Figure 16 Circuit diagram of the current mirror circuit. Figure 16 and Figure 1Similarly, the array of multiple MOS transistors M01 to M84 is arranged in the X direction, and multiple wide wirings 21 are arranged to extend in the Y direction perpendicular to the MOS transistors M01 to M84. However, in this embodiment, the width W3 of each wide wiring 21 is approximately five times the width W1 of each MOS transistor.

[0104] and Figure 17 The MOS transistors M01 to M04 connected to the mirror terminal 120 of the mirror source are Figure 16 are all arranged in the center of the wiring 21. On the other hand, the MOS transistors M11 to M84 of the mirror target are the same as those in the embodiment 1 ( Figure 1 ) are the same, change the order configuration one by one. Figure 17 In the configuration, the combination of the distances in the plane direction from each mirror target to the nearest mirror source is the same between the mirror terminals of the mirror targets. Therefore, the variation depending on the distance from the mirror source can be reduced.

[0105] Figure 18 It is an enlarged representation Figure 16 A plan view of the region of nine transistors M11 to M81 from the left. The distances in the planar direction from MOS transistors M11, M21, M31, and M41 to the end of wide wiring 21 are D4, D3, E3, and E4, respectively. The same applies to M51 to M81.

[0106] exist Figure 17 In each mirror terminal 121 to 128 of the mirror target, Figure 16 By arranging the MOS transistors and the wide wiring 21 in this manner, the distances from the MOS transistors to the wide wiring 21 in the plane direction are all D3, D4, E3, and E4. This makes the influence of the wide wiring on each mirror target uniform, reducing the variation in the mirror ratio between mirror targets.

[0107] However, the influence of wiring stress on the mirror source is different from that on the mirror target. Therefore, in this embodiment, the MOS transistor sizes of the mirror source and mirror target are adjusted to achieve the necessary mirror ratio, or the mirror ratio is corrected through calibration after the semiconductor integrated circuit device is manufactured.

[0108] Furthermore, long-term fluctuations in the mirror ratio require correction if they occur. However, since the effects of strain caused by wide wiring are uniform between mirrored objects, correction of the mirror ratio does not need to be performed for each mirrored object, simplifying the correction process.

[0109] As described above, in the semiconductor device of this embodiment, the above-mentioned circuit is a current mirror circuit, and further includes a third semiconductor element group (a group with mirror terminal 120) formed by connecting a plurality of semiconductor elements (MOS transistors M01 to M04) in parallel. The first semiconductor element group (a group with mirror terminal 121) and the second semiconductor element group (a group with mirror terminal 122) are mirror targets of the current mirror circuit, and the third semiconductor element group (a group with mirror terminal 120) is a mirror source of the current mirror circuit.

[0110] In addition, there are a plurality of semiconductor element groups (groups of mirror terminals 121 to 128) that serve as mirror targets, and each combination of distances in the planar direction from each semiconductor element in the plurality of semiconductor element groups (groups of mirror terminals 121 to 128) to the wide wiring 21 at the position at which the distance in the planar direction is closest is equal to the combination of distances in the planar direction of the first semiconductor element group (group of mirror terminals 121).

[0111] Example 5

[0112] Reference Figure 19 , a semiconductor device according to a fifth embodiment of the present invention is described. Figure 19 The diagram shows an example of the positional relationship between the MOS transistors M01 to M74, the wide wiring 20, and the dummy wiring 22 on the same wiring layer as the wide wiring 20, which constitute the current mirror circuit in the semiconductor device of this embodiment. Figure 2 same.

[0113] In this embodiment, only two wide wirings 20 are arranged with respect to the array of MOS transistors M01 to M74 constituting the current mirror circuit. Figure 1 A dummy wiring 22 having the same width as the wide wiring 20 is arranged in the same wiring layer as a portion of the location where the wide wiring 20 is arranged. For the same reason as in the first embodiment, the dummy wiring 22 has the effect of making the influence of the stress applied to the MOS transistor by the wide wiring 20 equal between the mirror destination and mirror source terminals.

[0114] like Figure 3B As shown in the stress simulation results, the stress applied to silicon is different at the wiring end and the wiring center, so Figure 19 The dummy wiring 22 needs to extend from the MOS transistor array along the Y direction.

[0115] Example 6

[0116] Reference Figure 20 as well as Figure 21 , a semiconductor device according to a sixth embodiment of the present invention is described. Figure 20This is an example showing the positional relationship between the MOS transistors M01 to M64 and the wide wiring 20 constituting the current mirror circuit in the semiconductor device of this embodiment. Figure 1 ), the array of MOS transistors M01 to M64 is arranged in the X direction, and the wide wiring 20 is extended in the Y direction perpendicular to the MOS transistors M01 to M64. In addition, the width W2 of one wide wiring 20 is about 4 times the width W1 of one MOS transistor. In addition, Figure 21 express Figure 20 Circuit diagram of the current mirror circuit.

[0117] exist Figure 20 In order to adjust the positions of the MOS transistors M01 to M64 and the wide wiring 20, dummy transistors DM1 to DM4 as dummy semiconductor elements are arranged in the MOS transistor array. Figure 1 ) is the same as Figure 21 In the group of MOS transistors having mirror terminals 130 to 136, since the combination of the distances in the planar direction from the MOS transistors to the nearest wide wiring 20 is the same, the influence of the stress of the wide wiring 20 can be made equal at the mirror source and the mirror target, thereby reducing the initial deviation of the mirror ratio of the current mirror circuit and suppressing aging degradation (aging change).

[0118] In addition, the above-described embodiments 1 to 6 are configuration examples of a MOS transistor group and upper-level wiring connected in parallel with the mirror terminal of the current mirror circuit, but in addition to MOS transistors, it can also be a configuration of semiconductor elements such as bipolar transistors and semiconductor resistor elements and their upper-level wiring.

[0119] In addition, the present invention is not limited to the above-described embodiment, and includes various modifications.

[0120] For example, the above-described embodiments are described in detail to facilitate understanding of the present invention and are not necessarily limited to having all of the described configurations. Furthermore, a portion of the configuration of one embodiment may be replaced with a configuration of another embodiment, or a configuration of one embodiment may be added to a configuration of another embodiment. Furthermore, a portion of the configuration of each embodiment may be added, deleted, or replaced with another configuration.

[0121] Explanation of symbols

[0122] M0~M7:MOS transistors

[0123] M01~M84:MOS transistors

[0124] DM1~DM4: dummy transistors

[0125] 10: (Metal) wiring layer

[0126] 20, 21: Wide (metal) wiring

[0127] 22: Dummy wiring (on the same wiring layer as metal wiring 20)

[0128] 30, 31: Wide (metal) wiring (of a different wiring layer from the metal wiring 20)

[0129] W1~W3: Transistor size or metal wiring width

[0130] 100~107: Mirror terminals (current mirror circuit)

[0131] 110-117: Mirror terminals (current mirror circuit)

[0132] 120~128: Mirror terminal (current mirror circuit)

[0133] 130~136: Mirror terminals (current mirror circuit)

[0134] D1 to D4: Distance (in the planar direction from the MOS transistor to the wide metal wiring)

[0135] E1 to E5: Distance (in the planar direction from the MOS transistor to the wide metal wiring)

[0136] F1 to F3: Distance (in the planar direction from the MOS transistor to the wide metal wiring)

[0137] G1: Distance (in the planar direction from the MOS transistor to the wide metal wiring)

[0138] H1 to H3: Distance (in the plane direction from the MOS transistor to the overlap of the wide metal wiring)

[0139] J1: Distance (in the plane direction from the MOS transistor to the overlap of the wide metal wiring)

[0140] 200: Copper wiring

[0141] 300: Silicon substrate (semiconductor substrate)

[0142] 301: Silicon (Si) layer

[0143] 302: Interface (between silicon layer 301 and silicon oxide film 401)

[0144] 400: Silicon oxide film

[0145] 401: Silicon oxide film (interlayer oxide film)

[0146] 500: Polyimide film.

Claims

1. A semiconductor device, characterized in that: have: a first semiconductor element group consisting of a plurality of semiconductor elements connected in parallel; a second semiconductor element group, which is arranged in the same layer as the first semiconductor element group and is composed of a plurality of semiconductor elements connected in parallel; and a plurality of wirings arranged in an upper layer of the first semiconductor element group and the second semiconductor element group, wherein the width of any one of the plurality of wirings is wider than the width of each semiconductor element in the first semiconductor element group and the second semiconductor element group; The first semiconductor element group and the second semiconductor element group are paired to form a circuit with a predetermined pairing accuracy. The multiple wirings are arranged in such a manner that a combination of the planar distances from each semiconductor element of the first semiconductor element group to the wiring at the nearest position in the planar direction is equal to a combination of the planar distances from each semiconductor element of the second semiconductor element group to the wiring at the nearest position in the planar direction.

2. The semiconductor device according to claim 1, wherein The plurality of wirings include a plurality of wirings arranged in a first wiring layer and a plurality of wirings arranged in a second wiring layer different from the first wiring layer. The plurality of wirings of the first wiring layer are arranged so that a combination of the distances in the planar direction from each semiconductor element of the first semiconductor element group to the wiring arranged in the first wiring layer at the nearest position in the planar direction is equal to a combination of the distances in the planar direction from each semiconductor element of the second semiconductor element group to the wiring arranged in the first wiring layer at the nearest position in the planar direction. The multiple wirings of the second wiring layer are arranged in such a manner that a combination of the planar distances from each semiconductor element of the first semiconductor element group to the wiring arranged in the second wiring layer at the nearest position in the planar direction is equal to a combination of the planar distances from each semiconductor element of the second semiconductor element group to the wiring arranged in the second wiring layer at the nearest position in the planar direction.

3. The semiconductor device according to claim 1, wherein The plurality of wirings include a plurality of wirings arranged in a first wiring layer and a plurality of wirings arranged in a second wiring layer different from the first wiring layer. The plurality of wirings are arranged so that wirings arranged in the first wiring layer and wirings arranged in the second wiring layer overlap. The wiring arranged in the first wiring layer and the wiring arranged in the second wiring layer are arranged in the following manner: the combination of the planar distances from each semiconductor element of the first semiconductor element group to the nearest position in the planar direction where the wiring arranged in the first wiring layer and the wiring arranged in the second wiring layer overlap is equal to the combination of the planar distances from each semiconductor element of the second semiconductor element group to the nearest position in the planar direction where the wiring arranged in the first wiring layer and the wiring arranged in the second wiring layer overlap.

4. The semiconductor device according to any one of claims 1 to 3, wherein The circuit is a current mirror circuit, The first semiconductor element group is a mirror source of the current mirror circuit. The second semiconductor element group is a mirror target of the current mirror circuit.

5. The semiconductor device according to any one of claims 1 to 3, wherein The circuit is a current mirror circuit, The semiconductor device further includes a third semiconductor element group formed by connecting a plurality of semiconductor elements in parallel. The first semiconductor element group and the second semiconductor element group are mirror targets of the current mirror circuit. The third semiconductor element group is a mirror source of the current mirror circuit.

6. The semiconductor device according to claim 4, wherein A plurality of semiconductor device groups serving as mirror images are provided. Each combination of distances in the planar direction from each semiconductor element of the plurality of semiconductor element groups to the wiring at the position closest in the planar direction is equal to a combination of distances in the planar direction of the first semiconductor element group.

7. The semiconductor device according to claim 5, wherein A plurality of semiconductor device groups serving as mirror images are provided. Each combination of distances in the planar direction from each semiconductor element of the plurality of semiconductor element groups to the wiring at the position closest in the planar direction is equal to a combination of distances in the planar direction of the first semiconductor element group.

8. The semiconductor device according to any one of claims 1 to 3, wherein: The plurality of wirings include dummy wirings.

9. The semiconductor device according to any one of claims 1 to 3, wherein: The array of the plurality of semiconductor elements includes dummy semiconductor elements.

10. An on-vehicle electronic control device, characterized in that: A semiconductor device according to any one of claims 1 to 9 is provided.

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