Computing devices, integrated circuit chips, board cards, and computing methods

Abstract

The present disclosure discloses a computing device, an integrated circuit chip, a board card and a method for performing an operation operation using the foregoing computing device. Wherein the computing device can be included in a combined processing device, which can also include a general-purpose interconnection interface and other processing devices. The computing device interacts with other processing devices to jointly complete a user-specified computing operation. The combined processing device can also include a storage device connected to the device and other processing devices, respectively, for storing data of the device and other processing devices. The scheme of the present disclosure can improve the operation efficiency of various data processing fields including, for example, the field of artificial intelligence, thereby reducing the overall cost and cost of operation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of data processing. More specifically, the present disclosure relates to a computing device, an integrated circuit chip, a board card and a method of performing a computing operation using the aforementioned computing device. BACKGROUND

[0002] Existing artificial intelligence operations often contain a large amount of data operations, such as convolution operations, image processing, etc. With the increase of data volume, the operation amount and storage amount involved in data operations such as matrix operations will increase sharply due to the increase of data scale. In the existing operation mode, a general-purpose processor such as a central processing unit (“CPU”) or a graphics processing unit (“GPU”) is usually used for operation. However, the general-purpose processor often has a large power consumption overhead due to its general-purpose feature and high redundancy of the used devices, thus limiting its use performance.

[0003] In addition, the existing operation processing circuit usually adopts a fixed hardware architecture. When the data scale is expanded or the data format is changed, not only may it not support certain operations, but also its operation performance may be greatly limited during operation, and even it may not be able to operate. SUMMARY

[0004] In order to at least solve the defects existing in the prior art, the present disclosure provides a solution that supports multiple types of operations, improves operation efficiency, and saves operation cost and overhead. Specifically, the present disclosure provides the aforementioned solution in the following aspects.

[0005] In a first aspect, the present disclosure provides a computing device comprising a control circuit and a plurality of processing circuits, wherein:

[0006] the control circuit is configured to obtain and parse instructions, and send the parsed instructions to one or more processing circuits of the plurality of processing circuits; and

[0007] the plurality of processing circuits are configured to be connected in a one-dimensional or multi-dimensional array structure, and perform multi-threaded operations according to the received parsed instructions.

[0008] In a second aspect, the present disclosure provides an integrated circuit chip comprising the computing device of the aforementioned and later described embodiments.

[0009] In a third aspect, the present disclosure provides a board card comprising the integrated circuit chip of the aforementioned.

[0010] In a fourth aspect, the present disclosure provides a method for performing an operation using a computing device, wherein the computing device comprises a control circuit and a plurality of processing circuits connected in a one-dimensional or multi-dimensional array structure, the method comprising:

[0011] acquiring and parsing instructions using the control circuit, and sending the parsed instructions to one or more processing circuits of the plurality of processing circuits; and

[0012] performing a multi-threaded operation according to the parsed instructions using the one or more processing circuits.

[0013] By using the computing device, integrated circuit chip, board card and method of the present disclosure, the operation limitations under the fixed hardware architecture can be overcome, the running efficiency in data processing and operation in various data processing fields including, for example, the field of artificial intelligence can be improved, and the power consumption overhead and cost of data operation can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0014] The above and other objects, features and advantages of the disclosed example embodiments will become more apparent from the following detailed description read in conjunction with the accompanying drawings. In the drawings, several embodiments of the disclosure are illustrated by way of example and not limitation in which like reference numerals represent similar, but not necessarily identical, elements or components, wherein:

[0015] Figure 1 is a general architecture diagram illustrating a computing device according to an embodiment of the present disclosure;

[0016] Figure 2 is an example specific architecture diagram illustrating a computing device according to an embodiment of the present disclosure;

[0017] Figure 3 is an example structure diagram illustrating a single type processing circuit array of a computing device according to an embodiment of the present disclosure;

[0018] Figure 4 is an example structure diagram illustrating a plurality of type processing circuit arrays of a computing device according to an embodiment of the present disclosure;

[0019] Figure 5a , 5b, 5c and 5d are schematic diagrams illustrating a plurality of connection relationships of a plurality of processing circuits according to an embodiment of the present disclosure;

[0020] Figure 6a , 6b, 6c and 6d are schematic diagrams illustrating another plurality of connection relationships of a plurality of processing circuits according to an embodiment of the present disclosure;

[0021] Figure 7a , 7b, 7c and 7d are schematic diagrams illustrating a plurality of loop structures of a processing circuit according to an embodiment of the present disclosure;

[0022] Figure 8a 8b and 8c are schematic diagrams illustrating various other loop structures of the processing circuit according to embodiments of the present disclosure;

[0023] Figure 9a 9b, 9c and 9d are schematic diagrams illustrating data splicing operations performed by a preprocessing circuit according to an embodiment of the present disclosure;

[0024] Figure 10a 10b and 10c are schematic diagrams illustrating data compression operations performed by the post-processing circuit according to embodiments of the present disclosure;

[0025] Figure 11 This is a simplified flowchart illustrating a method for performing computational operations using a computing device according to an embodiment of this disclosure;

[0026] Figure 12 This is a structural diagram illustrating a combined processing apparatus according to an embodiment of the present disclosure; and

[0027] Figure 13 This is a schematic diagram illustrating the structure of a circuit board according to an embodiment of the present disclosure. Detailed Implementation

[0028] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0029] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0030] Figure 1 This is a general architecture diagram illustrating a computing device 100 according to an embodiment of this disclosure. Figure 1 As shown, the computing device 100 disclosed herein may include a control circuit 102 and a plurality of processing circuits 104. During data processing, the control circuit may be configured to acquire instructions, parse the instructions, and send the parsed instructions to one or more of the plurality of processing circuits.

[0031] According to the embodiments of the present disclosure, the obtained instruction can include one or more operation codes, and each operation code can represent one or more specific operations to be performed by one or more processing circuits. Each operation code can be represented in any suitable form. For example, an operation code can be represented by an English abbreviation such as "ADD" or "MUL" to express that an "addition" or "multiplication" operation is to be performed. Alternatively, an operation code can also be represented by an English abbreviation such as "AM" that does not directly indicate a specific operation from a literal perspective. Depending on the application scenario, an operation code can include or involve different types of operations, such as arithmetic operation, logical operation, comparison operation, or table lookup operation, or any combination of the foregoing. Further, in the present disclosure, each operation code can correspond to one or more micro-instructions obtained in the process of parsing the instruction. Thus, the parsed instruction in the present disclosure can include one or more micro-instructions corresponding to an operation code in the instruction to indicate one or more specific operations to be performed by the processing circuit.

[0032] In one embodiment, in the process of parsing the instruction, the control circuit 102 can be configured to obtain instruction identification information in the instruction, and send the parsed instruction to one or more of the plurality of processing circuits according to the instruction identification information, wherein the instruction identification information identifies one or more processing circuits. Further, depending on the application scenario, the parsed instruction can be a decoded instruction by the control circuit or can also be a parsed instruction without decoding by the control circuit. When the parsed instruction is a parsed instruction without decoding by the control circuit, the processing circuit can include a corresponding decoding circuit to perform decoding on the parsed instruction, for example, to obtain a plurality of micro-instructions.

[0033] In another embodiment, in the process of parsing the instruction, the control circuit can be configured to decode the instruction, and send the parsed instruction to one or more of the plurality of processing circuits according to the decoding result and the operating state of the plurality of processing circuits. In this embodiment, the plurality of processing circuits can all support the same type of non-specific operation. Therefore, in order to improve the utilization rate and operation efficiency of the processing circuit, the parsed instruction can be sent to the processing circuit with low occupancy or in idle state.

[0034] In one or more embodiments, the plurality of processing circuits 104 can be configured to be connected in a one-dimensional or multi-dimensional array structure, and perform multi-threaded operations according to the received resolved instructions. In one embodiment, the plurality of processing circuits can be configured to receive and execute the resolved instructions in a single instruction, multiple thread (“SIMT”) manner. In another embodiment, when the plurality of processing circuits are configured to be connected in a multi-dimensional array structure, the multi-dimensional array can include a two-dimensional array and / or a three-dimensional array (as shown in FIGS. 5 and 6). Further, each processing circuit in the aforementioned one-dimensional or multi-dimensional array can be connected with other processing circuits in a specified direction and a predetermined interval pattern within a certain range. Additionally, the plurality of processing circuits can be connected in series by logic connections to form one or more closed loops (as shown in FIGS. 7 and 8).

[0035] In different application scenarios, the connection manner between the plurality of processing circuits can be a hardwired manner of connection through a hardware structure. Additionally or alternatively, the connection manner between the plurality of processing circuits can also be a logical connection manner configured according to the resolved instructions, such as micro-instructions. Through the aforementioned hardwired manner or logical connection manner, various topologies of processing circuit arrays can be formed to adapt to performing corresponding data processing operations.

[0036] Figure 2 is an example specific architecture diagram illustrating a computing device 200 according to embodiments of the present disclosure. As can be seen from Figure 2 , the computing device 200 not only includes the control circuit 102 and the plurality of processing circuits 104 of the computing device 100 in Figure 1 , but further illustrates the plurality of circuits included in the processing circuits, and additionally a plurality of other devices. Since the functions of the control circuit and the processing circuit have been described in detail above in Figure 1 , the following will not be described again.

[0037] As shown in Figure 2 , the processing circuit 104 can include a logic operation circuit 1041, which can be configured to perform logic operations according to the resolved instructions and received data when performing the multi-threaded operations, such as performing AND, OR, NOT, shift operation, or comparison operation, etc. In addition to being able to perform necessary logic operations, the processing circuit 104 can also include an arithmetic operation circuit 1043, which can be configured to perform arithmetic operation operations, such as addition, subtraction, or multiplication, etc. linear operations.

[0038] In one embodiment, the processing circuit 104 can further include a storage circuit 1042 including a data storage circuit and / or a predicate storage circuit. The data storage circuit can be configured to store at least one of operation data (e.g., pixels) and intermediate operation results of the processing circuit. Further, the predicate storage circuit can be configured to store a predicate storage circuit number and predicate information of each of the processing circuit obtained by the resolved instruction. In a specific storage application, the storage circuit 1042 can be implemented by a register or a static random access memory ("SRAM") or the like according to actual needs.

[0039] In one application scenario, the predicate storage circuit can include a number of 1-bit registers for storing the predicate information. Further, the number of the 1-bit registers can be represented by a binary number of b bits, where b >= log2(a). For example, the predicate storage circuit in the processing circuit can include 32 1-bit registers numbered sequentially from 00000 to 11111. Thus, the processing circuit can read the predicate information in the register with the number "00101" according to the register number "00101" specified in the received resolved instruction.

[0040] In one embodiment, the predicate storage circuit can be configured to update the predicate information according to the resolved instruction. For example, the predicate information can be updated directly according to the configuration information in the resolved instruction, or the configuration information can be obtained according to the configuration information storage address provided in the resolved instruction to update the predicate information. In the process of operation performed by the processing circuit, the predicate storage circuit can also update the predicate information according to the comparison result of each of the processing circuits, which is a form of operation result in the context of the present disclosure. For example, the predicate information can be updated by comparing the input data received by the processing circuit with the storage data in its data storage circuit. When the input data is greater than the storage data, the predicate information of the processing circuit is set to 1. Conversely, when the input data is less than the storage data, the predicate information is set to 0 or maintained unchanged.

[0041] Before performing an operation, each processing circuit can determine whether to perform the operation of the parsed instruction according to the information in the parsed instruction. Further, each processing circuit can be configured to obtain the predicate information corresponding to the predicate storage circuit according to the predicate storage circuit number in the parsed instruction, and determine whether to perform the parsed instruction according to the predicate information. For example, when the value of the predicate information read by the processing circuit according to the predicate storage circuit number specified in the parsed instruction is 1, it means that the processing circuit performs the parsed instruction. For example, the processing circuit can read the data pointed to in the instruction and store the read data in the data storage circuit of the processing circuit. Conversely, when the value of the predicate information read by the processing circuit according to the predicate storage circuit number specified in the parsed instruction is 0, it means that the processing circuit does not perform the parsed instruction.

[0042] In one embodiment, the computing device 200 of the present disclosure can further include a data handling circuit 106, which can include at least one of a pre-handling circuit 1061 and a post-handling circuit 1062. The pre-handling circuit 1061 can be configured to perform a pre-processing operation on operation data before the processing circuit performs an operation (described later in connection with Figure 7b The post-handling circuit 1062 can be configured to perform a post-processing operation on an operation result after the processing circuit performs an operation, for example, to perform a data restoration or data compression operation.

[0043] To implement the transmission and storage of data, the computing device 200 can further include a main storage circuit 108, which can receive and store data from the control circuit as input data of the processing circuit, and can also be used to transmit and store data between multiple processing circuits. In some application scenarios, the main storage circuit 108 can be further divided into at least one of a main storage module 1081 and a main cache module 1082 according to the storage mode or the characteristics of the stored data. The main storage module 1081 can be configured to store data (e.g., input pixels) for processing circuits to perform operations and operation results (e.g., output pixels) after performing operations. The main cache module 1082 can be configured to cache intermediate operation results after performing operations in the multiple processing circuits. In some application scenarios, the main storage circuit not only can perform internal storage, but also supports the function of data interaction with storage devices outside the computing device of the present disclosure, for example, it can exchange data with external storage devices through direct memory access (“DMA”).

[0044] Figure 3 is an example structure diagram illustrating an array of single-type processing circuits of a computing device according to an embodiment of the present disclosure. AsFigure 3 As shown, the computing device shown not only includes Figure 2 As shown, the control circuit 102, the main storage circuit 108, the data handling circuit 106 and the plurality of processing circuits 104 of the same type are shown, and further shown that the plurality of processing circuits of the same type can be arranged through physical connections to form a two-dimensional array, for example, the plurality of processing circuits are arranged to form a two-dimensional array. In view of the foregoing, the functions of the control circuit, the main storage circuit, the data handling circuit and the processing circuit are described in detail, which will not be repeated here. Figure 2 The functions of the control circuit, the main storage circuit, the data handling circuit and the processing circuit are described in detail, which will not be repeated here.

[0045] As mentioned before, the plurality of processing circuits of the present disclosure can be divided into different types for performing different types of data processing operations. For example, the plurality of processing circuits can be divided into a first type of processing circuit and a second type of processing circuit (as shown in Figure 4 In application scenarios, the first type of processing circuit can be suitable for performing at least one of an arithmetic operation and a logical operation, while the second type of processing circuit can be suitable for performing at least one of a comparison operation and a table lookup operation.

[0046] Figure 4 is an example structural diagram showing an array of processing circuits of different types of a computing device according to an embodiment of the present disclosure. As Figure 4 shown, the computing device includes a control circuit 102, a main storage circuit 108 and a plurality of processing circuits 104 of different types. Optionally, the computing device can also include a data handling circuit 106 as shown in Figure 2 and 3 In view of this, Figure 4 The computing device architecture shown is similar to the computing device architecture shown in Figure 2 and Figure 3 Therefore, the technical details of the computing device 200 described in Figure 2 and Figure 3 are also applicable to the computing device shown in Figure 4 .

[0047] As can be seen from Figure 4 , the plurality of processing circuits of the present disclosure can include, for example, a plurality of first type of processing circuits and a plurality of second type of processing circuits (as shown in the figure, the processing circuits with different colors in the background have different types). The plurality of processing circuits can be arranged through physical connections to form a two-dimensional array. It can be understood that Figure 4The arrangement of the two types of processing circuits shown is merely exemplary and not limiting. Those skilled in the art can conceive of other arrangements based on the teachings of this disclosure. For example, multiple first-type processing circuits can be arranged on the left and right sides of the array, while multiple second-type processing circuits can be arranged in the middle region of the array. As another example, multiple first-type processing circuits can be arranged in the middle region of the array, while multiple second-type processing circuits can be arranged around the perimeter of the array. Yet another example is that multiple first-type and second-type processing circuits can be arranged alternately and interspersed within the array. Depending on the computing scenario, the types of processing circuits disclosed herein may not be limited to the two shown in the figures, but may include more types of processing circuits to implement different types of computational operations.

[0048] As shown in the figure, the two-dimensional array has M rows and N columns (denoted as M). N) first-type processing circuits (processing circuit 104 shown in the light-colored background in the figure), where M and N are positive integers greater than 0. The first-type processing circuits can be used to perform arithmetic and logical operations, such as linear operations like addition, subtraction, and multiplication, nonlinear operations like comparison and AND, OR, and NOT, or any combination of the aforementioned operations. Furthermore, in M... The outer perimeter of the N type-1 processing circuit array has two columns on each of its left and right sides, totaling (M). 2+M 2) Two second-type processing circuits, and two rows of total (N) on the lower side of their periphery. There are 2+8) second-type processing circuits, meaning the array of processing circuits has a total of (M) 2+M 2+N (2+8) second-type processing circuits (processing circuit 104 shown in the dark background in the figure). In one embodiment, the second-type processing circuits can be used to perform nonlinear operations on the received data, such as comparison operations, table lookup operations, or shift operations.

[0049] In some application scenarios, the storage circuits used in the first type of processing circuit and the second type of processing circuit can have different storage scales and storage methods. For example, the predicate storage circuit in the first type of processing circuit can use multiple numbered registers to store predicate information. Furthermore, the first type of processing circuit can access the predicate information in the corresponding numbered register according to the register number specified in the received parsed instruction. As another example, the second type of processing circuit can use static random access memory (“SRAM”) to store the predicate information. Specifically, the second type of processing circuit can determine the storage address of the predicate information in the static random access memory (“SRAM”) according to the offset of the location of the predicate information specified in the received parsed instruction, and can perform predetermined read or write operations on the predicate information at that storage address.

[0050] Figure 5a Images 5b, 5c, and 5d are schematic diagrams illustrating various connection relationships of multiple processing circuits according to embodiments of the present disclosure. The multiple processing circuits of the present disclosure can be connected in a one-dimensional or multi-dimensional array topology. When the multiple processing circuits are connected in a multi-dimensional array, the multi-dimensional array can be a two-dimensional array, and the processing circuits located in the two-dimensional array can be connected to one or more other processing circuits in the same row, column, or diagonal in at least one direction, with a predetermined two-dimensional spacing pattern. The predetermined two-dimensional spacing pattern can be associated with the number of processing circuits spaced apart in the connection. Figure 5a to Figure 5c Exemplary topologies of various forms of two-dimensional arrays between multiple processing circuits are shown.

[0051] like Figure 5a As shown, five processing circuits (each represented by a box) are connected to form a simple two-dimensional array. Specifically, with one processing circuit as the center of the two-dimensional array, one processing circuit is connected to each of the four horizontal and vertical directions relative to that processing circuit, thus forming a two-dimensional array with three rows and three columns. Furthermore, since the processing circuit located at the center of the two-dimensional array is directly connected to the processing circuits adjacent to the preceding and following columns in the same row, and to the processing circuits adjacent to the preceding and following rows in the same column, the number of inter-processing circuits (referred to as the "interval number") is 0.

[0052] like Figure 5bAs shown, the four rows and four columns of processing circuits can be connected to form a two-dimensional Torus array. Each processing circuit is connected to the processing circuits in its preceding and following rows and columns, respectively, meaning the number of intervals between adjacent processing circuits is 0. Furthermore, the first processing circuit in each row or column of this two-dimensional Torus array is also connected to the last processing circuit in that row or column, with the number of intervals between the first and last connected processing circuits in each row or column being 2.

[0053] like Figure 5c As shown, the four rows and four columns of processing circuits can also be connected to form a two-dimensional array where the interval between adjacent processing circuits is 0 and the interval between non-adjacent processing circuits is 1. Specifically, in this two-dimensional array, adjacent processing circuits in the same row or column are directly connected, i.e., the interval is 0, while non-adjacent processing circuits in the same row or column are connected to processing circuits with an interval of 1. It can be seen that when multiple processing circuits are connected to form a two-dimensional array, Figure 5b and Figure 5c The processing circuits shown in the same row or column can have different numbers of intervals. Similarly, in some scenarios, processing circuits can be connected with different numbers of intervals in the diagonal direction.

[0054] like Figure 5d As shown, using four such Figure 5b The illustrated two-dimensional Torus array can be arranged into four layers at predetermined intervals and connected to form a three-dimensional Torus array. This three-dimensional Torus array, based on the two-dimensional Torus array, utilizes an interval pattern similar to that between rows and columns for inter-layer connections. For example, firstly, processing circuits in adjacent layers in the same row and column are directly connected, i.e., the interval number is 0. Next, processing circuits in the first and last layers in the same row and column are connected, i.e., the interval number is 2. Ultimately, a four-layer, four-row, four-column three-dimensional Torus array can be formed.

[0055] Through the examples above, those skilled in the art will understand that the connection relationships of other multidimensional arrays of processing circuits can be formed on the basis of a two-dimensional array by adding new dimensions and increasing the number of processing circuits. In some application scenarios, the solutions disclosed herein can also configure logical connections of processing circuits using configuration instructions. In other words, although there may be hardwired connections between processing circuits, the solutions disclosed herein can also selectively connect some processing circuits or selectively bypass some processing circuits through configuration instructions to form one or more logical connections. In some embodiments, the aforementioned logical connections can also be adjusted according to the actual computational needs (e.g., data type conversion). Furthermore, for different computing scenarios, the solutions disclosed herein can configure the connections of processing circuits, including, for example, configuring them as matrices or as one or more closed computational loops.

[0056] Figure 6a Figures 6b, 6c, and 6d are schematic diagrams illustrating various additional connection relationships of multiple processing circuits according to embodiments of the present disclosure. As can be seen from the figures, Figure 6a to Figure 6d Is Figure 5a to Figure 5d This illustrates yet another exemplary connection relationship of a multidimensional array formed by multiple processing circuits. In view of this, combined with... Figure 5a to Figure 5d The described technical details also apply to Figure 6a to Figure 6d The content shown.

[0057] like Figure 6a As shown, the processing circuitry of the two-dimensional array includes a central processing circuit located at the center of the array and three processing circuits connected in four directions (row and column) to the central processing circuit. Therefore, the number of intervals between the central processing circuit and the remaining processing circuits are 0, 1, and 2, respectively. Figure 6b As shown, the processing circuit of the two-dimensional array includes a central processing circuit located at the center of the two-dimensional array, three processing circuits in two opposite directions running parallel to the central processing circuit, and one processing circuit in two opposite directions in the same column as the central processing circuit. Therefore, the number of intervals between the central processing circuit and the processing circuits running parallel to it are 0 and 2, respectively, and the number of intervals between the central processing circuit and the processing circuits in the same column are both 0.

[0058] As mentioned above Figure 5dThe multi-dimensional array of processing circuits can be a three-dimensional array formed by multiple layers. Each layer of the three-dimensional array can include a two-dimensional array of processing circuits arranged along its row direction and column direction. Further, the processing circuits in the three-dimensional array can be connected to one or more other processing circuits in the same row, column, diagonal, or different layer in a predetermined three-dimensional spacing pattern in at least one of the row direction, column direction, diagonal direction, and layer direction. Further, the number of processing circuits spaced apart in the predetermined three-dimensional spacing pattern can be related to the number of layers spaced apart. The connection of the three-dimensional array will be further described below with reference to the following figures. Figure 6c The connection of the three-dimensional array will be further described below with reference to the following figures. Figure 6d The connection of the three-dimensional array will be further described below with reference to the following figures.

[0059] Figure 6c A multi-layer, multi-row, and multi-column three-dimensional array of processing circuits is shown. Take the processing circuit at the lth layer, rth row, and cth column (denoted as (l, r, c)) as an example. The processing circuit is located at the center of the array and is connected to the processing circuit at the previous column (l, r, c-1) and the processing circuit at the next column (l, r, c+1) in the same layer and row, the processing circuit at the previous row (l, r-1, c) and the processing circuit at the next row (l, r+1, c) in the same layer and column, and the processing circuit at the previous layer (l-1, r, c) and the processing circuit at the next layer (l+1, r, c) in the same row and column. Further, the number of processing circuits spaced apart in the row direction, column direction, and layer direction is 0.

[0060] Figure 6dThis diagram illustrates a three-dimensional array where the number of intervals between multiple processing circuits in the row, column, and layer directions is always 1. Taking the processing circuit located at the center (l, r, c) of the array as an example, it is connected to processing circuits at positions (l, r, c-2) and (l, r, c+2) that are one column apart in the same row and at different columns within the same layer, and at positions (l, r-2, c) and (l, r+2, c) that are one row apart in the same column and at different rows within the same layer. Furthermore, it is connected to processing circuits at positions (l-2, r, c) and (l+2, r, c) that are one layer apart in the same row and at different layers within the same column. Similarly, the remaining processing circuits at positions (l, r, c-3) and (l, r, c-1) that are one column apart in the same row and at the same layer are connected to each other, while the processing circuits at positions (l, r, c+1) and (l, r, c+3) are connected to each other. Next, the processing circuits at (l, r-3, c) and (l, r-1, c) on the same layer and column, separated by one row, are connected to each other, and the processing circuits at (l, r+1, c) and (l, r+3, c) are connected to each other. Additionally, the processing circuits at (l-3, r, c) and (l-1, r, c) on the same row and column, separated by one layer, are connected to each other, and the processing circuits at (l+1, r, c) and (l+3, r, c) are connected to each other.

[0061] The above text provides an exemplary description of the connection relationship of a multidimensional array formed by multiple processing circuits. The following text will further illustrate the different loop structures formed by multiple processing circuits in conjunction with Figures 7 and 8.

[0062] Figure 7a Figures 7b, 7c, and 7d are schematic diagrams illustrating various loop structures of the processing circuit according to embodiments of this disclosure. Depending on the application scenario, the multiple processing circuits can be connected not only physically, but also logically, based on received parsed instructions. The multiple processing circuits can be configured to form a closed loop using these logical connections.

[0063] like Figure 7a As shown, the four adjacent processing circuits are sequentially numbered "0, 1, 2, and 3". Then, starting with processing circuit 0, these four processing circuits are connected sequentially in a clockwise direction, and processing circuit 3 is connected to processing circuit 0, so that the four processing circuits are connected in series to form a closed loop (referred to as "loop"). In this loop, the number of intervals between the processing circuits is 0 or 2; for example, the number of intervals between processing circuits 0 and 1 is 0, while the number of intervals between processing circuits 3 and 0 is 2. Furthermore, the physical addresses of the four processing circuits in the loop can be 0-1-2-3, and their logical addresses are also 0-1-2-3. It should be noted that... Figure 7aThe connection order shown is merely exemplary and not restrictive. Those skilled in the art may also connect the four processing circuits in series in a counterclockwise direction to form a closed loop, depending on actual calculation needs.

[0064] In some practical scenarios, when the data bit width supported by a single processing circuit cannot meet the bit width requirements of the processed data, multiple processing circuits can be combined into a processing circuit group to represent a single data point. For example, suppose a processing circuit can process 8-bit data. When 32-bit data needs to be processed, four processing circuits can be combined into a processing circuit group to connect four 8-bit data points to form a 32-bit data point. Furthermore, the aforementioned processing circuit group formed by four 8-bit processing circuits can act as... Figure 7b The diagram shows a processing circuit 104, which can support higher bit-width arithmetic operations.

[0065] from Figure 7b As can be seen from this, the layout of the processing circuit shown is similar to... Figure 7a Similar to what is shown, but Figure 7b The number of intervals between the intermediate processing circuits and Figure 7a different. Figure 7b The diagram shows four processing circuits numbered 0, 1, 2, and 3, connected sequentially in a clockwise direction, starting with processing circuit 0, followed by processing circuit 1, processing circuit 3, and processing circuit 2. Processing circuit 2 is also connected to processing circuit 0, forming a closed loop in series. This loop demonstrates that... Figure 7b The number of intervals between the processing circuits shown is either 0 or 1; for example, the interval between processing circuits 0 and 1 is 0, while the interval between processing circuits 1 and 3 is 1. Furthermore, the physical addresses of the four processing circuits in the closed loop shown can be 0-1-2-3, while the logical addresses are 0-1-3-2. Therefore, when it is necessary to split high-bit-width data to allocate it to different processing circuits, the data order can be rearranged and allocated according to the logical addresses of the processing circuits.

[0066] The above-mentioned splitting and rearranging operations can be performed by combining... Figure 2 The pre-processing circuit described is used for execution. Specifically, this pre-processing circuit can rearrange the input data according to the physical and logical addresses of multiple processing circuits to meet the requirements of data operations. Assume four sequentially arranged processing circuits 0 to 3 as follows... Figure 7a The connections shown, since both their physical and logical addresses are 0-1-2-3, allow the preprocessing circuit to sequentially transmit input data (e.g., pixel data) aa0, aa1, aa2, and aa3 to the corresponding processing circuits. However, when the aforementioned four processing circuits... Figure 7bThe physical addresses of the connected processing circuits remain unchanged as 0-1-2-3, while the logical addresses change to 0-1-3-2. At this time, the front processing circuit needs to rearrange the input data aa0, aa1, aa2 and aa3 to aa0-aa1-aa3-aa2 for transmission to the corresponding processing circuit. Based on the above-mentioned rearrangement of input data, the scheme of the present disclosure can ensure the correctness of the data operation sequence. Similarly, if the sequence of the four operation output results (for example, pixel data) obtained in the foregoing is bb0-bb1-bb3-bb2, the rear processing circuit can be used to adjust the sequence of the operation output results to bb0-bb1-bb2-bb3, so as to ensure the arrangement consistency between the input data and the output result data. Figure 2 The rear processing circuit described above adjusts the sequence of the operation output results to bb0-bb1-bb2-bb3, so as to ensure the arrangement consistency between the input data and the output result data.

[0067] Figure 7c and Figure 7d More processing circuits are shown to be arranged and connected in different ways to form a closed loop. As shown in Figure 7c , 16 processing circuits 104 numbered in the order of 0, 1, …, 15 are sequentially connected and combined every two processing circuits to form a processing circuit group. For example, as shown in the figure, the processing circuit 0 is connected with the processing circuit 1 to form a processing circuit group, and so on. In this way, the processing circuit 14 is connected with the processing circuit 15 to form a processing circuit group, and finally eight processing circuit groups are formed. Further, the eight processing circuit groups can also be connected in a similar manner to the connection of the processing circuits described above, including being connected according to, for example, a predetermined logical address to form a closed loop of a processing circuit group.

[0068] As shown in Figure 7d , a plurality of processing circuits 104 are connected in an irregular or non-uniform manner to form a closed loop. Specifically, in Figure 7d , it is shown that the processing circuits can be spaced apart by a number of 0 or 3 to form a closed loop, for example, the processing circuit 0 can be connected with the processing circuit 1 (spaced apart by a number of 0) and the processing circuit 4 (spaced apart by a number of 3), respectively.

[0069] As described above in combination with Figure 7a , 7b , 7c and 7d, the processing circuits of the present disclosure can be spaced apart by different numbers of processing circuits to be connected into a closed loop. When the total number of processing circuits changes, any intermediate spacing number can be selected for dynamic configuration to be connected into a closed loop. A plurality of processing circuits can also be combined into a processing circuit group and connected into a closed loop of the processing circuit group. In addition, the connection of the plurality of processing circuits can be a hard connection mode constituted by hardware, or can be a soft connection mode configured by software.

[0070] Figure 8a Fig. 8b and Fig. 8c are schematic diagrams showing another plurality of loop structures of processing circuits according to embodiments of the present disclosure. As shown in Fig. 6, a plurality of processing circuits can form a closed loop, and each processing circuit in the closed loop can be configured with a respective logical address. Further, as shown in Fig. 7, the front processing circuit described in conjunction with Fig. 6 can be configured to split the operation data according to the type of the operation data (e.g., 32-bit data, 16-bit data, or 8-bit data) and the logical address, and pass the plurality of sub-data obtained after the splitting to the corresponding processing circuits in the loop for subsequent operations. Figure 2 Fig. 8b and Fig. 8c are schematic diagrams showing another plurality of loop structures of processing circuits according to embodiments of the present disclosure. As shown in Fig. 6, a plurality of processing circuits can form a closed loop, and each processing circuit in the closed loop can be configured with a respective logical address. Further, as shown in Fig. 7, the front processing circuit described in conjunction with Fig. 6 can be configured to split the operation data according to the type of the operation data (e.g., 32-bit data, 16-bit data, or 8-bit data) and the logical address, and pass the plurality of sub-data obtained after the splitting to the corresponding processing circuits in the loop for subsequent operations.

[0071] Figure 8a The upper diagram shows that the four processing circuits form a closed loop, and the physical addresses (which can also be referred to as physical coordinates in the context of the present disclosure) of the four processing circuits in the right-to-left order can be represented as 0-1-2-3. Figure 8a The lower diagram shows that the logical addresses of the four processing circuits in the loop in the right-to-left order are represented as 0-3-1-2. For example, Figure 8a The processing circuit with the logical address “3” shown in the lower diagram has Figure 8a The physical address “1” shown in the upper diagram.

[0072] In some application scenarios, it is assumed that the granularity of the operation data is the lower 128 bits of the input data, for example, the original sequence “15, 14, …, 2, 1, 0” in the diagram (each number corresponds to 8-bit data), and the logical addresses of the 16 8-bit data are numbered from low to high as 0-15. Further, according to the logical address as shown in Figure 8a The lower diagram shows the logical address, and the front processing circuit can encode or arrange data according to different data types according to different logical addresses.

[0073] When the data bit width of the processing circuit is 32 bits, four numbers of logical addresses (3, 2, 1, 0), (7, 6, 5, 4), (11, 10, 9, 8) and (15, 14, 13, 12) can represent the 0th-3rd 32-bit data respectively. The front processing circuit can transmit the 0th 32-bit data to the processing circuit with the logical address of "0" (the corresponding physical address is "0"), transmit the 1st 32-bit data to the processing circuit with the logical address of "1" (the corresponding physical address is "2"), transmit the 2nd 32-bit data to the processing circuit with the logical address of "2" (the corresponding physical address is "3"), and transmit the 3rd 32-bit data to the processing circuit with the logical address of "3" (the corresponding physical address is "1"). Through the rearrangement of the data, the subsequent operation requirements of the processing circuit are met. Therefore, the mapping relationship between the logical address and the physical address of the final data is (15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) -> (11, 10, 9, 8, 7, 6, 5, 4, 15, 14, 13, 12, 3, 2, 1, 0).

[0074] When the data bit width of the processing circuit is 16 bits, eight numbers of logical addresses (1, 0), (3, 2), (5, 4), (7, 6), (9, 8), (11, 10), (13, 12) and (15, 14) can represent the 0th-7th 16-bit data respectively. The front processing circuit can transmit the 0th and 4th 16-bit data to the processing circuit with the logical address of "0" (the corresponding physical address is "0"), transmit the 1st and 5th 16-bit data to the processing circuit with the logical address of "1" (the corresponding physical address is "2"), transmit the 2nd and 6th 16-bit data to the processing circuit with the logical address of "2" (the corresponding physical address is "3"), and transmit the 3rd and 7th 16-bit data to the processing circuit with the logical address of "3" (the corresponding physical address is "1"). Therefore, the mapping relationship between the logical address and the physical address of the final data is (15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) -> (13, 12, 5, 4, 11, 10, 3, 2, 15, 14, 7, 6, 9, 8, 1, 0).

[0075] When the data bit width of the processing circuit is 8 bits, sixteen numbers of logical addresses 0-15 can represent the 0th-15th 8-bit data respectively. According to the above method, the front processing circuit can transmit the 0th and 4th 8-bit data to the processing circuit with the logical address of "0" (the corresponding physical address is "0"), transmit the 1st and 5th 8-bit data to the processing circuit with the logical address of "1" (the corresponding physical address is "2"), transmit the 2nd and 6th 8-bit data to the processing circuit with the logical address of "2" (the corresponding physical address is "3"), transmit the 3rd and 7th 8-bit data to the processing circuit with the logical address of "3" (the corresponding physical address is "1"), transmit the 8th and 12th 8-bit data to the processing circuit with the logical address of "4" (the corresponding physical address is "4"), transmit the 9th and 13th 8-bit data to the processing circuit with the logical address of "5" (the corresponding physical address is "6"), and transmit the 14th and 15th 8-bit data to the processing circuit with the logical address of "6" (the corresponding physical address is "7"). Figure 8aThe connection shown, the front processing circuit can transmit the 0th, 4th, 8th and 12th 8bit data to the processing circuit with logical address "0" (the corresponding physical address is "0"); can transmit the 1st, 5th, 9th and 13th 8bit data to the processing circuit with logical address "1" (the corresponding physical address is "2"); can transmit the 2nd, 6th, 10th and 14th 8bit data to the processing circuit with logical address "2" (the corresponding physical address is "3"); can transmit the 3rd, 7th, 11th and 15th 8bit data to the processing circuit with logical address "3" (the corresponding physical address is "1"). Therefore, the mapping relationship between the logical address and the physical address of the final data is: (15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) -> (14, 19, 6, 2, 13, 9, 5, 1, 15, 11, 7, 3, 12, 8, 4, 0).

[0076] Figure 8b The upper figure shows that eight sequentially numbered processing circuits 0 to 7 are connected to form a closed loop, and the physical addresses of the eight processing circuits are 0-1-2-3-4-5-6-7. Figure 8b The lower figure shows that the logical addresses of the aforementioned eight processing circuits are 0-7-1-6-2-5-3-4. For example, Figure 8b The upper figure shows that the processing circuit with physical address "6" corresponds to Figure 8b The lower figure shows that the logical address is "3".

[0077] Figure 8b The operation shown for different data types, the front processing circuit re-arranges the data and transmits it to the corresponding processing circuit Figure 8a Similarly, the technical solutions described in combination with Figure 8a The technical solutions described are also applicable to Figure 8b The data re-arrangement operation process described above will not be repeated here. Further, Figure 8b The connection relationship of the processing circuits shown is similar to Figure 8a The connection relationship of the processing circuits shown is similar to Figure 8b The eight processing circuits are shown as Figure 8a The number of processing circuits shown is doubled. Therefore, in the application scenario of operating according to different data types, in combination with Figure 8b The granularity of the operation data described can be in combination with Figure 8aThe granularity of the data being manipulated is twice that of the input data described. Therefore, instead of the lower 128 bits of the input data in the previous example, the granularity of the data being manipulated in this example can be the lower 256 bits of the input data, such as the original data sequence "31, 30, ..., 2, 1, 0" shown in the figure, where each number corresponds to an 8-bit ("bit") length.

[0078] For the original data sequence described above, the diagram also shows the data arrangement in the ring-shaped processing circuits when the data bit widths operated by the processing circuits are 32 bits, 16 bits, and 8 bits, respectively. For example, when the data bit width is 32 bits, the 32-bit data in the processing circuit with logical address "1" is (7, 6, 5, 4), and the physical address of this processing circuit is "2". When the data bit width is 16 bits, the two 16-bit data in the processing circuit with logical address "3" are (23, 22, 7, 6), and the physical address of this processing circuit is "6". When the data bit width is 8 bits, the four 8-bit data in the processing circuit with logical address "6" are (30, 22, 14, 6), and the physical address of this processing circuit is "3".

[0079] The above text combined Figure 8a and Figure 8b The multiple single-type processing circuits shown (such as) Figure 3 The first type of processing circuit shown is connected to form a closed loop, and data operations for different data types are described below. Figure 8c The following are several different types of processing circuits (such as...) Figure 4 The first type of processing circuit and the second type of processing circuit shown are connected to form a closed loop, and further descriptions are made for data operations on different data types.

[0080] Figure 8c The diagram above shows twenty multi-type processing circuits, numbered sequentially from 0 to 19, connected to form a closed loop (the numbers shown in the diagram represent the physical addresses of the processing circuits). Sixteen processing circuits numbered 0 to 15 are type 1 processing circuits, and four processing circuits numbered 16 to 19 are type 2 processing circuits. Similarly, the physical address of each of these twenty processing circuits is... Figure 8c The logical addresses of the corresponding processing circuits shown in the diagram below have a mapping relationship.

[0081] Furthermore, when operating on different data types, such as the original sequence of 80 8-bit bytes shown in the diagram, Figure 8cThe results of the operations on the aforementioned raw data are also shown for different data types supported by the processing circuit. For example, when the data bit width of the operation is 32 bits, the 1 32-bit data in the processing circuit with logical address "1" is (7, 6, 5, 4), and the processing circuit corresponds to the physical address "2". When the data bit width of the operation is 16 bits, the 2 16-bit data in the processing circuit with logical address "11" is (63, 62, 23, 22), and the processing circuit corresponds to the physical address "9". When the data bit width of the operation is 8 bits, the 4 8-bit data in the processing circuit with logical address "17" is (77, 57, 37, 17), and the processing circuit corresponds to the physical address "18".

[0082] Figure 9a Figures 9b, 9c, and 9d are schematic diagrams showing data concatenation operations performed by the preceding processing circuit according to embodiments of the present disclosure. As previously described, the present disclosure combines Figure 2 The preceding processing circuit described above can also be configured to select one of a plurality of data concatenation modes according to the parsed instruction to perform a concatenation operation on the two input data. Regarding the plurality of data concatenation modes, in one embodiment, the present disclosure selects one of the plurality of data concatenation modes by dividing and numbering the two data to be concatenated by the smallest data unit, and then extracting different smallest data units of the data based on a specified rule to form different data concatenation modes. For example, the different data concatenation modes can be formed by alternately extracting and placing based on the parity of the number or whether the number is an integer multiple of a specified number. According to different computing scenarios (e.g., different data bit widths), the smallest data unit here can simply be 1 bit or 1 bit of data, or 2 bits, 4 bits, 8 bits, 16 bits, or 32 bits or bit length. Further, when extracting different numbered parts of the two data, the present disclosure can alternately extract by the smallest data unit, or extract by multiples of the smallest data unit, such as alternately extracting two or three smallest data units of the data from the two data as a group to concatenate by group.

[0083] Based on the above description of the data concatenation mode, the data concatenation mode of the present disclosure will be exemplarily described below with specific examples in combination with Figure 9a to Figure 9c In the illustrated figures, the input data is In1 and In2, and when each square in the figure represents a smallest data unit, both of the input data have a bit width length of 8 smallest data units. As previously described, for data of different bit width lengths, the smallest data unit can represent different bits (or bits). For example, for data of a bit width of 8 bits, the smallest data unit represents 1 bit of data, and for data of a bit width of 16 bits, the smallest data unit represents 2 bits of data. For example, for data of a bit width of 32 bits, the smallest data unit represents 4 bits of data.

[0084] like Figure 9a As shown, the two input data sets In1 and In2 to be concatenated each consist of eight smallest data units numbered 1, 2, ..., 8 from right to left. The data concatenation follows an alternating principle: numbers from smallest to largest, In1 before In2, and odd numbers before even numbers. Specifically, when the data width is 8 bits, In1 and In2 each represent an 8-bit data set, and each smallest data unit represents 1 bit of data (i.e., one square represents 1 bit of data). Based on the data width and the aforementioned concatenation principle, the smallest data units numbered 1, 3, 5, and 7 of In1 are first extracted and sequentially arranged in the lower bits. Next, the four odd-numbered smallest data units of In2 are sequentially arranged. Similarly, the smallest data units numbered 2, 4, 6, and 8 of In1 and the four even-numbered smallest data units of In2 are sequentially arranged. Finally, 16 smallest data units are concatenated to form either one 16-bit or two 8-bit new data sets, as shown below. Figure 9a As shown in the second row of squares.

[0085] like Figure 9b As shown, when the data width is 16 bits, data In1 and In2 each represent a 16-bit data unit. In this case, each smallest data unit represents 2 bits of data (i.e., one square represents one 2-bit data unit). Based on the data width and the aforementioned interleaving principle, the smallest data units numbered 1, 2, 5, and 6 of data In1 are first extracted and arranged sequentially in the lower bits. Then, the smallest data units numbered 1, 2, 5, and 6 of data In2 are arranged sequentially. Similarly, the smallest data units numbered 3, 4, 7, and 8 of data In1 and the same as those in data In2 are arranged sequentially to form the final 16 smallest data units, consisting of one 32-bit or two 16-bit new data units, as shown below. Figure 9b As shown in the second row of squares.

[0086] like Figure 9c As shown, when the data width is 32 bits, data In1 and In2 each represent a 32-bit data unit, and each smallest data unit represents 4 bits of data (i.e., one square represents one 4-bit data unit). Based on the data width and the aforementioned interleaving principle, the smallest data units numbered 1, 2, 3, and 4 of data In1, which share the same number as data In2, are first extracted and arranged sequentially in the lower bits. Then, the smallest data units numbered 5, 6, 7, and 8 of data In1, which share the same number as data In2, are extracted and arranged sequentially, thus concatenating them to form a final 16 smallest data units, comprising either one 64-bit or two 32-bit new data units.

[0087] The above combination Figure 9a to Figure 9cExemplary data concatenation manners of the present disclosure are described. However, it can be understood that in some computing scenarios, data concatenation does not involve interleaving as described above, but simply arranging two data while keeping the original data positions unchanged, such as shown in Figure 9d Figure 9d As can be seen from Figure 9a to Figure 9c , the two data In1 and In2 do not perform interleaving as shown in , but simply concatenate the last smallest data unit of In1 and the first smallest data unit of In2, thereby obtaining new data of increased bit width (e.g., doubled). In some scenarios, the scheme of the present disclosure can also concatenate data in groups based on data attributes. For example, neuron data or weight data having the same feature map can be formed into a group, and then arranged to form a continuous part of the concatenated data.

[0088] Figure 10a , 10b and 10c are schematic diagrams showing data compression operations performed by the post-processing circuit according to embodiments of the present disclosure. The compression operation can include filtering data using a mask or compressing data by comparing with a given threshold value. Regarding the data compression operation, it can be divided and numbered by the smallest data unit as described above. Similar to Figure 9a to Figure 9d , the smallest data unit may, for example, be 1-bit data or 2-bit, 4-bit, 8-bit, 16-bit or 32-bit in length. Exemplary descriptions will be made below for different data compression modes. Figure 10a to Figure 10c

[0089] As shown in Figure 10a , the original data is composed of eight squares (i.e., eight smallest data units) numbered in sequence from right to left as 1, 2, …, 8, assuming that each smallest data unit can represent 1-bit data. When performing a data compression operation according to a mask, the post-processing circuit can filter the original data using the mask to perform the data compression operation. In one embodiment, the bit width of the mask corresponds to the number of smallest data units of the original data. For example, the aforementioned original data has eight smallest data units, so the mask has a bit width of eight bits, and the smallest data unit numbered 1 corresponds to the lowest bit of the mask, and the smallest data unit numbered 2 corresponds to the next lowest bit of the mask. In this way, the smallest data unit numbered 8 corresponds to the highest bit of the mask. In one application scenario, when the 8-bit mask is “10010011”, the compression principle can be set to extract the smallest data units in the original data corresponding to the data bits of the mask that are “1”. For example, the smallest data units numbered 1, 2, 5 and 8 correspond to the mask values that are “1”. Thus, the smallest data units numbered 1, 2, 5 and 8 can be extracted and arranged in order from low to high, to form the compressed new data, as shown in​Figure 10a As shown in the second row.

[0090] Figure 10b Showing with Figure 10a Similar raw data, and from Figure 10b As can be seen from the second line, the data sequence after passing through the post-processing circuit maintains its original data arrangement order and content. Therefore, it can be understood that the data compression disclosed herein may also include a disabled mode or an uncompressed mode, so that no compression operation is performed when the data passes through the post-processing circuit.

[0091] like Figure 10c As shown, the original data consists of eight squares arranged sequentially. The number above each square represents its index, numbered 1, 2...8 from right to left, and it is assumed that each smallest data unit can be 8 bits. Furthermore, the number in each square represents the decimal value of that smallest data unit. Taking the smallest data unit numbered 1 as an example, its decimal value is "8", and the corresponding 8-bit data is "00001111". When performing data compression based on a threshold, assuming the threshold is the decimal number "8", the compression principle can be set to extract all smallest data units in the original data that are greater than or equal to the threshold "8". Thus, the smallest data units numbered 1, 4, 7, and 8 can be extracted. Then, all the extracted smallest data units are arranged in ascending order of their numbers to obtain the final data result, as shown below. Figure 10c As shown in the second line of the document.

[0092] Figure 11 This is a simplified flowchart illustrating a method 1100 for performing computational operations using a computing device according to an embodiment of this disclosure, wherein the computing device may have a combination of Figure 1 to Figure 4 The hardware architecture described.

[0093] like Figure 11 As shown, in step 1110, method 1100 can utilize the control circuit to acquire instructions, parse the instructions, and send the parsed instructions to one or more of the plurality of processing circuits. In one embodiment, the control circuit can determine one or more processing circuits to perform the operation based on the instruction identification information in the instructions, and send the parsed instructions to one or more of the plurality of processing circuits to execute the corresponding operation specified by the parsed instructions.

[0094] In one or more embodiments, during the parsing of the instruction, the control circuit can perform a decode operation on the instruction, and send the parsed instruction to one or more of the plurality of processing circuits according to the result of the decode. When the plurality of processing circuits all support the same type of operation that is not specific, the control circuit can send the parsed instruction to the processing circuit that has a low usage or is in an idle state according to the operating state of the plurality of processing circuits. Further, the parsed instruction can also be an unparsed instruction that is not decoded by the control circuit according to different application scenarios. The one or more processing circuits can include a corresponding decode circuit to decode the received parsed instruction, for example, to generate a plurality of micro-instructions, so that the one or more processing circuits can perform subsequent operations according to the micro-instructions.

[0095] Then, the flow can proceed to step 1120, and the method 1100 can use the one or more processing circuits to perform a multi-threaded operation according to the parsed instruction. In one embodiment, the plurality of processing circuits can be configured to receive and execute the parsed instruction in a single instruction, multiple thread (“SIMT”) manner. In another embodiment, the plurality of processing circuits can be connected in a one-dimensional or multi-dimensional array topology, and the plurality of processing circuit arrays connected in series can form one or more closed loops. In yet another embodiment, the plurality of processing circuits can determine whether to perform the operation specified by the parsed instruction according to information (e.g., predicate information) in the received parsed instruction.

[0096] Figure 12 is a structural diagram illustrating a combined processing device 1200 according to an embodiment of the present disclosure. As shown in Figure 12 the combined processing device 1200 includes a computing processing device 1202, an interface device 1204, other processing devices 1206, and a storage device 1208. According to different application scenarios, the computing processing device can include one or more computing devices 1210, which can be configured to perform the operations described herein in connection with Figure 1 to Figure 11 .

[0097] In different embodiments, the computing processing device of the present disclosure can be configured to perform user-specified operations. In an exemplary application, the computing processing device can be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included in the computing processing device can be implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core. When the plurality of computing devices are implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core, the computing processing device of the present disclosure can be considered to have a single-core structure or a homogeneous multi-core structure.

[0098] In exemplary operations, the computing processing device of the present disclosure can interact with other processing devices through the interface device to collectively accomplish user-specified operations. Depending on the implementation, the other processing devices of the present disclosure can include one or more types of processors, including general and / or special purpose processors such as central processing units (CPUs), graphics processing units (GPUs), artificial intelligence processors, etc. These processors can include, but are not limited to, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned previously, only in terms of the computing processing device of the present disclosure, it can be considered to have a single-core structure or a homogeneous multi-core structure. However, when considering the computing processing device and the other processing devices together, both can be considered to form a heterogeneous multi-core structure.

[0099] In one or more embodiments, the other processing devices can serve as an interface for the computing processing device of the present disclosure (which can be embodied as a related operation device for artificial intelligence such as neural network operations) and external data and controls, performing basic controls including but not limited to data transfer, turning on and / or stopping the computing device, etc. In additional embodiments, the other processing devices can also cooperate with the computing processing device to collectively accomplish operation tasks.

[0100] In one or more embodiments, the interface device can be used to transmit data and control instructions between the computing processing device and the other processing devices. For example, the computing processing device can obtain input data from the other processing devices via the interface device and write it to the storage device (or memory) on the computing processing device chip. Further, the computing processing device can obtain control instructions from the other processing devices via the interface device and write them to the control cache on the computing processing device chip. Alternatively or optionally, the interface device can also read data in the storage device of the computing processing device and transmit it to the other processing devices.

[0101] Additionally or optionally, the combined processing apparatus disclosed herein may further include a storage device. As shown in the figures, the storage device is connected to both the computing processing device and the other processing device. In one or more embodiments, the storage device may be used to store data from the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage of the computing processing device or other processing device.

[0102] In some embodiments, this disclosure also discloses a chip (e.g. Figure 13 The chip shown is 1302. In one implementation, the chip is a system-on-chip (SoC) and integrates one or more such... Figure 12 The combined processing unit shown is illustrated. This chip can be connected to external interface devices (such as...). Figure 13 The external interface device 1306 shown is connected to other related components. These related components may be, for example, a camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. In some applications, the chip may integrate other processing units (e.g., video codecs) and / or interface modules (e.g., DRAM interfaces). In some embodiments, this disclosure also discloses a chip package structure that includes the aforementioned chip. In some embodiments, this disclosure also discloses a board that includes the aforementioned chip package structure. The following will be combined with… Figure 13 This board is described in detail.

[0103] Figure 13 This is a schematic diagram illustrating the structure of a board 1300 according to an embodiment of this disclosure. For example... Figure 13 As shown, the board includes a storage device 1304 for storing data, which includes one or more storage cells 1310. This storage device can be connected and transmit data with the controller 1308 and the aforementioned chip 1302 via, for example, a bus. Furthermore, the board also includes an external interface device 1306, configured for data relay or switching between the chip (or a chip in a chip package) and an external device 1312 (e.g., a server or computer). For example, data to be processed can be transferred from the external device to the chip via the external interface device. Alternatively, the calculation results of the chip can be transmitted back to the external device via the external interface device. Depending on the application scenario, the external interface device can have different interface forms; for example, it can adopt a standard PCIe interface.

[0104] In one or more embodiments, the control device in the board card of the present disclosure can be configured to regulate the state of the chip. To this end, in one application scenario, the control device can include a micro controller unit (MCU) for regulating the working state of the chip.

[0105] According to the above description in combination Figure 12 and Figure 13 , those skilled in the art can understand that the present disclosure also discloses an electronic device or apparatus, which can include one or more of the above-mentioned board cards, one or more of the above-mentioned chips, and / or one or more of the above-mentioned combined processing apparatuses.

[0106] According to different application scenarios, the electronic device or apparatus of the present disclosure can include a server, a cloud server, a server cluster, a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a PC device, an Internet of Things terminal, a mobile terminal, a mobile phone, a vehicle recording device, a navigation device, a sensor, a camera, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a visual terminal, an autonomous driving terminal, a vehicle, a household appliance, and / or a medical device. The vehicle includes an airplane, a ship, and / or a vehicle; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, an electric rice cooker, a humidifier, a washing machine, an electric lamp, a gas stove, an exhaust hood; the medical device includes a nuclear magnetic resonance instrument, a B-ultrasound instrument, and / or an electrocardiograph. The electronic device or apparatus of the present disclosure can also be applied to the fields of Internet, Internet of Things, data center, energy, transportation, public management, manufacturing, education, power grid, telecommunications, finance, retail, construction site, medical treatment, etc. Further, the electronic device or apparatus of the present disclosure can also be used in cloud, edge, terminal, etc. application scenarios related to artificial intelligence, big data, and / or cloud computing. In one or more embodiments, the electronic device or apparatus with high computing power according to the present disclosure scheme can be applied to a cloud device (such as a cloud server), while the electronic device or apparatus with low power consumption can be applied to a terminal device and / or an edge device (such as a smart phone or a camera). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or the edge device are compatible with each other, so that according to the hardware information of the terminal device and / or the edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or the edge device, so as to complete the unified management, scheduling and cooperative work of end-cloud integration or cloud-edge integration.

[0107] It should be noted that, for the purpose of clarity, the disclosure describes some methods and embodiments thereof as a series of acts and / or combinations thereof, but those skilled in the art will understand that the present disclosure is not limited to the order of the acts described. Those skilled in the art will understand and appreciate that some steps of the methods can be decided to be executed in other orders or at the same time with other steps. Further, those skilled in the art will understand and appreciate that some of the embodiments described in the disclosure can be considered optional, i.e., the acts or modules involved therein are not necessarily essential for the implementation of one or more of the aspects of the present disclosure. In addition, the disclosure describes some embodiments with different focuses according to different aspects. In view of this, those skilled in the art will understand that the parts not described in detail in some embodiments of the disclosure can also be seen from the relevant description of other embodiments.

[0108] In specific implementation aspects, based on the disclosure and teachings of the present disclosure, those skilled in the art will understand that some of the embodiments disclosed in the present disclosure can also be implemented in other ways not disclosed herein. For example, as for each unit in the electronic device or apparatus embodiments described above, the units are divided herein on the basis of logical functions, and other division manners can also be used in actual implementation. For another example, a plurality of units or components can be combined or integrated into another system, or some features or functions of the units or components can be selectively disabled. As for the connection relationship between different units or components, the connections discussed above in conjunction with the drawings can be direct or indirect coupling between the units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0109] In the present disclosure, the units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units. The aforementioned components or units can be located in the same place or distributed on a plurality of network units. In addition, according to actual needs, some or all of the units can be selected to achieve the purpose of the aspects described in the embodiments of the present disclosure. In addition, in some scenarios, a plurality of units in the embodiments of the present disclosure can be integrated into one unit or each unit physically exists separately.

[0110] In some implementation scenarios, the above-mentioned integrated units can be implemented in the form of software program modules. If implemented in the form of software program modules and sold or used as independent products, the integrated units can be stored in a computer-readable memory. Based on this, when the schemes of the present disclosure are embodied in the form of software products (for example, computer-readable storage media), the software products can be stored in the memory, which can include a number of instructions to make a computer device (for example, a personal computer, a server or a network device, etc.) execute part or all of the steps of the method described in the embodiments of the present disclosure. The aforementioned memory can include, but is not limited to, a U disk, a flash disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0111] In some other implementation scenarios, the above-mentioned integrated units can also be implemented in the form of hardware, that is, specific hardware circuits, which can include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit can include, but is not limited to, physical devices, and the physical devices can include, but are not limited to, transistors or memristors, etc. In view of this, various devices described herein (for example, computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs and ASICs, etc. Further, the aforementioned storage units or storage devices can be any appropriate storage medium (including magnetic storage media or magneto-optical storage media, etc.), which can be, for example, resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), ROM and RAM, etc.

[0112] While several embodiments of the disclosure have been shown and described herein, it is to be understood that the embodiments are merely exemplary. Numerous changes, substitutions and equivalents can occur to those skilled in the art without departing from the spirit and scope of the disclosure. It should be understood that various alternatives to the embodiments of the disclosure described herein can be employed in practicing the disclosure. It is intended that the following claims define the scope of the disclosure and that methods equivalent to those claims recited herein are within the scope and spirit of the disclosure. Therefore, the disclosure is not limited to the specific embodiments described herein, but only by the claims.

Claims

1. A computing apparatus comprising a control circuit and a plurality of processing circuits, wherein: the control circuit is configured to fetch instructions and parse the instructions, and send the parsed instructions to one or more of the plurality of processing circuits; and the plurality of processing circuits are configured to be connected in a one-dimensional or multi-dimensional array structure, and perform multi-threaded operations according to the received parsed instructions, wherein in parsing the instructions, the control circuit is configured to: fetch instruction identification information in the instructions; and send the parsed instructions to one or more of the plurality of processing circuits according to the instruction identification information; or in parsing the instructions, the control circuit is configured to: decode the instructions; and send the parsed instructions to one or more of the plurality of processing circuits according to the results of the decoding and operating states of the plurality of processing circuits. 2.The computing apparatus of claim 1, wherein the plurality of processing circuits are divided into multiple types of processing circuits to perform different types of data processing. 3.The computing apparatus of claim 1, wherein the plurality of processing circuits are divided into a first type of processing circuit and a second type of processing circuit, wherein the first type of processing circuit is adapted to perform at least one of an arithmetic operation and a logic operation, and the second type of processing circuit is adapted to perform at least one of a comparison operation and a table lookup operation. 4.The computing apparatus of claim 1, wherein the multi-dimensional array is a two-dimensional array, and the processing circuits located in the two-dimensional array are connected to the remaining one or more processing circuits in the same row, column or diagonal direction at least one of a row direction, a column direction or a diagonal direction thereof in a predetermined two-dimensional interval pattern, wherein the predetermined two-dimensional interval pattern is associated with a number of processing circuits to be connected in an interval. 5.The computing apparatus of claim 1, wherein the multi-dimensional array is a three-dimensional array composed of multiple layers, wherein each layer comprises a two-dimensional array of multiple processing circuits arranged in a row direction, a column direction and a diagonal direction, wherein: the processing circuits located in the three-dimensional array are connected to the remaining one or more processing circuits in the same row, column, diagonal or different layer at least one of a row direction, a column direction, a diagonal direction and a layer direction thereof in a predetermined three-dimensional interval pattern, wherein the predetermined three-dimensional interval pattern is associated with a number of intervals between the processing circuits to be connected and a number of interval layers. 6.The computing apparatus of claim 4, wherein the plurality of processing circuits are configured to determine whether to be connected by a logical connection according to a parsed designation. 7.The computing apparatus of claim 1, wherein multiple processing circuits are configured to form at least one processing circuit group according to a bit width of received data to process the data. ​ ​ 8.The computing device of claim 7, wherein when a plurality of the processing circuit groups are formed to process data, the plurality of processing circuit groups are connected by logical connections according to the resolved instructions to form one or more closed loops. 9.The computing device of claim 1, wherein each of the processing circuits comprises: a logical operation circuit configured to perform a logical operation according to the resolved instructions and received data when performing the multi-thread operation; and a storage circuit comprising a data storage circuit and a predicate storage circuit, wherein the data storage circuit is configured to store at least one of operation data and intermediate operation results of the processing circuit, and the predicate storage circuit is configured to store a predicate storage circuit number and predicate information of each of the processing circuits obtained using the resolved instructions. 10.The computing device of claim 9, wherein the predicate storage circuit is further configured to: update the predicate information according to the resolved instructions; or update the predicate information according to an operation result of each of the processing circuits. 11.The computing device of claim 9, wherein each of the processing circuits is configured to: obtain the predicate information corresponding to the predicate storage circuit according to the predicate storage circuit number in the resolved instructions; and determine whether to execute the resolved instructions according to the predicate information. 12.The computing device of claim 8, further comprising: a data handling circuit comprising at least one of a pre-handling circuit and a post-handling circuit, wherein the pre-handling circuit is configured to perform a pre-processing operation on operation data before the processing circuit performs an operation, and the post-handling circuit is configured to perform a post-processing operation on an operation result after the processing circuit performs an operation. 13.The computing device of claim 12, wherein each of the plurality of processing circuits in the closed loop is configured with a respective logical address, and the pre-handling circuit is configured to perform at least one of: according to a type of operation data and a logical address, split the operation data into a plurality of sub-data respectively and pass the plurality of sub-data to corresponding processing circuits in the loop for operation respectively; and according to the resolved instructions, select a data concatenation mode from a plurality of data concatenation modes to perform a concatenation operation on two input data. 14.The computing device of claim 13, wherein the post-handling circuit is further configured to perform a compression operation on data, the compression operation comprising filtering data using a mask or filtering by comparison of a given threshold value with a size of data. 15.The computing device of claim 1, wherein the plurality of processing circuits are configured to receive and execute the resolved instructions in a SIMT manner. 16.An integrated circuit chip comprising the computing device of any one of claims 1-15. 17.A board card comprising the integrated circuit chip of claim 16. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 18. A method of performing computing operations using a computing device, wherein the computing device comprises a control circuit and a plurality of processing circuits connected in a one-dimensional or multi-dimensional array structure, the method comprising: acquiring and parsing instructions with the control circuit and sending the parsed instructions to one or more of the plurality of processing circuits; and performing multi-threaded operations with the one or more processing circuits according to the parsed instructions, wherein in parsing the instructions, the method performs the following with the control circuit: acquiring instruction identification information in the instructions; and sending the parsed instructions to one or more of the plurality of processing circuits according to the instruction identification information; or in parsing the instructions, performing the following with the control circuit: decoding the instructions; and sending the parsed instructions to one or more of the plurality of processing circuits according to the results of the decoding and operating states of the plurality of processing circuits.

19. The method of claim 18, comprising dividing the plurality of processing circuits into a plurality of types of processing circuits to perform different types of data processing.

20. The method of claim 18, wherein dividing the plurality of processing circuits into a plurality of types of processing circuits comprises dividing the plurality of processing circuits into a first type of processing circuit and a second type of processing circuit, wherein the first type of processing circuit is adapted to perform at least one of an arithmetic operation and a logical operation, and the second type of processing circuit is adapted to perform at least one of a comparison operation and a table lookup operation.

21. The method of claim 18, wherein the multi-dimensional array is a two-dimensional array, and the method comprises connecting the processing circuits in the two-dimensional array in at least one of a row direction, a column direction, or a diagonal direction with a remaining one or more of the processing circuits in the same row, column, or diagonal at a predetermined two-dimensional spacing pattern, wherein the predetermined two-dimensional spacing pattern is associated with a number of processing circuits to be spaced in the connection.

22. The method of claim 18, wherein the multi-dimensional array is a three-dimensional array composed of a plurality of layers, wherein each layer comprises a two-dimensional array of the processing circuits arranged in a row direction, a column direction, and a diagonal direction, the method comprising: connecting the processing circuits in the three-dimensional array in at least one of the row direction, the column direction, the diagonal direction, and a layer direction with a remaining one or more of the processing circuits in the same row, column, diagonal, or different layer at a predetermined three-dimensional spacing pattern, wherein the predetermined three-dimensional spacing pattern is associated with a number of layers to be spaced and a number of spacings between the processing circuits to be connected.

23. The method of claim 21, wherein whether to connect the plurality of processing circuits by a logical connection is determined according to the parsed instructions.

24. The method of claim 18, wherein a plurality of the processing circuits are formed into at least one processing circuit group to process data according to a bit width of the received data. ​ ​ 25. The method of claim 24, wherein when a plurality of said processing circuit groups are formed to process data, the method comprises connecting said plurality of processing circuit groups by logical connections according to the resolved instructions to form one or more closed loops.

26. The method of claim 18, wherein each said processing circuit comprises a logical operation circuit and a storage circuit, and said storage circuit comprises a data storage circuit and a predicate storage circuit, the method comprising, when performing said multithreading operation, using said logical operation circuit to perform logical operations according to said resolved instructions and received data, and using said data storage circuit to store at least one of operation data and intermediate operation results of said processing circuit, and using said predicate storage circuit to store a predicate storage circuit number and predicate information of each said processing circuit obtained using said resolved instructions.

27. The method of claim 26, further comprising using said predicate storage circuit to perform the following steps: updating said predicate information according to said resolved instructions; or updating said predicate information according to operation results of each said processing circuit.

28. The method of claim 26, further comprising using each said processing circuit to perform the following steps: obtaining said predicate information corresponding to said predicate storage circuit according to said predicate storage circuit number in said resolved instructions; and determining whether to execute said resolved instructions according to said predicate information.

29. The method of claim 25, wherein said computing device further comprises a data handling circuit comprising at least one of a pre-handling circuit and a post-handling circuit, wherein the method further comprises, before said processing circuit performs an operation, using said pre-handling circuit to perform a pre-processing operation on operation data, and after said processing circuit performs an operation, using said post-handling circuit to perform a post-processing operation on operation results.

30. The method of claim 29, comprising configuring each of a plurality of processing circuits in said closed loop with a respective logical address, and using said pre-handling circuit to perform at least one of the following: according to a type of operation data and a logical address, splitting said operation data into a plurality of sub-data respectively and passing said sub-data into corresponding processing circuits in the loop for operation; and selecting a data concatenation mode from a plurality of data concatenation modes according to a resolved instruction to perform a concatenation operation on two input data.

31. The method of claim 30, further comprising using said post-handling circuit to perform a compression operation on data, said compression operation comprising filtering data using a mask or filtering by comparison of a given threshold value with a size of data.

32. The method of any one of claims 18-31, comprising using said plurality of processing circuits to receive and execute said resolved instructions in a SIMT manner.

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