Electronic device and method for operating the same in sleep mode

Abstract

An electronic device and an operating method for its sleep mode. The operating method includes the following steps. Send a sleep command from the first sub-module of the first module to the second sub-module of the first module, the third sub-module and the fourth sub-module of the second module, where the first sub-module includes a first node and a second node, the second sub-module includes a third node and a fourth node, the third sub-module includes a fifth node and a sixth node, and the fourth sub-module includes a seventh node and an eighth node. According to the sleep command, the second sub-module, the third sub-module and the fourth sub-module sequentially execute a sleep program to enter the sleep mode. Send a sleep command from the first node to the second node to cause the second node to execute the sleep program to enter the sleep mode. Send a sleep command from the first node to the first node to cause the first node to execute the sleep program to enter the sleep mode.

Description

Technical Field

[0001] The present invention relates to an electronic device and an operating method thereof, and particularly to an electronic device and an operating method of its sleep mode. Background Art

[0002] Generally, in an electronic device (such as a server system), there are high requirements for the number of cores of a central processing unit (CPU), the memory capacity, and the hard disk capacity. To meet the above requirements, an electronic device will be designed with a complex architecture in which multiple central processing units are interconnected. Therefore, how to effectively implement the sleep function design in an electronic device with a complex structure will become a topic that each manufacturer urgently desires to study. Summary of the Invention

[0003] The present invention provides an electronic device and an operating method of its sleep mode, thereby implementing the sleep function design in an electronic device with a complex structure to increase the convenience in use.

[0004] The present invention provides an operating method of the sleep mode of an electronic device, including the following steps. Send a sleep command from a first sub-module of a first module to a second sub-module of the first module, a third sub-module of a second module, and a fourth sub-module of the second module, where the first sub-module includes a first node and a second node, the second sub-module includes a third node and a fourth node, the third sub-module includes a fifth node and a sixth node, and the fourth sub-module includes a seventh node and an eighth node. According to the sleep command, the second sub-module, the third sub-module, and the fourth sub-module sequentially execute a sleep program to enter the sleep mode. Send a sleep command from the first node to the second node to make the second node execute the sleep program to enter the sleep mode. Send a sleep command from the first node to the first node to make the first node execute the sleep program to enter the sleep mode.

[0005] The present invention also provides an electronic device, which includes a first module and a second module. The first module includes a first sub-module and a second sub-module. The first sub-module includes a first node and a second node. The second node is connected to the first node. The second sub-module includes a third node and a fourth node. The third node is connected to the second node. The fourth node is connected to the third node and the first node. The second module includes a third sub-module and a fourth sub-module. The third sub-module includes a fifth node and a sixth node. The fifth node is connected to the second node. The sixth node is connected to the fifth node and the first node. The fourth sub-module includes a seventh node and an eighth node. The seventh node is connected to the sixth node and the fourth node. The eighth node is connected to the seventh node, the third node and the fifth node. The first sub-module sends a sleep command to the second sub-module, the third sub-module and the fourth sub-module, so that the second sub-module, the third sub-module and the fourth sub-module execute a sleep program in sequence according to the sleep command to enter the sleep mode. The first node sends a sleep command to the second node, so that the second node executes a sleep program to enter the sleep mode. The first node sends a sleep command to the first node, so that the first node executes a sleep program to enter the sleep mode.

[0006] For the electronic device and the operation method of its sleep mode disclosed by the present invention, the first sub-module of the first module sends a sleep command to the second sub-module of the first module, the third sub-module of the second module and the fourth sub-module of the second module, so that the second sub-module, the third sub-module and the fourth sub-module execute a sleep program in sequence according to the sleep command to enter the sleep mode. The first node sends a sleep command to the second node, so that the second node executes a sleep program to enter the sleep mode. The first node sends a sleep command to the first node, so that the first node executes a sleep program to enter the sleep mode. In this way, the sleep function design can be realized in an electronic device with a complex structure, so as to increase the convenience in use. Brief Description of the Drawings

[0007] Figure 1 It is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0008] Figure 2 It is a schematic diagram of a first node according to an embodiment of the present invention.

[0009] Figure 3 It is a schematic diagram of a logic element according to an embodiment of the present invention.

[0010] Figure 4 It is a flowchart of the operation method of the sleep mode of an electronic device according to an embodiment of the present invention.

[0011] Figure 5 For Figure 4 a detailed flowchart of step S404.

[0012] Figure 6 ForFigure 5 Detailed flowchart of step S502 of

[0013] Figure 7 For Figure 5 Detailed flowchart of step S504 of

[0014] Figure 8 For Figure 5 Detailed flowchart of step S506 of

[0015] Figure 9 For Figure 4 Another detailed flowchart of step S404 of

[0016] Figure 10 Flowchart of the operation method of the sleep mode of an electronic device according to another embodiment of the present invention. Detailed implementation manners

[0017] In the following listed embodiments, the same reference numerals will represent the same or similar elements or components.

[0018] Figure 1 Schematic diagram of an electronic device according to an embodiment of the present invention. Please refer to Figure 1 , the electronic device 100 includes a first module 110 and a second module 150. The first module 110 includes a first sub-module 120 and a second sub-module 130. The first sub-module 120 includes a first node N1 and a second node N2. The second node N2 is connected to the first node N1. The second sub-module 130 includes a third node N3 and a fourth node N4. The third node N3 is connected to the second node N2. The fourth node N4 is connected to the third node N3 and the first node N1.

[0019] The second module 150 includes a third sub-module 160 and a fourth sub-module 170. The third sub-module 160 includes a fifth node N5 and a sixth node N6. The fifth node N5 is connected to the second node N2. The sixth node N6 is connected to the fifth node N5 and the first node N1. The fourth sub-module 170 includes a seventh node N7 and an eighth node N8. The seventh node N7 is connected to the sixth node N6 and the fourth node N4. The eighth node N8 is connected to the seventh node N7, the third node N3 and the fifth node N5.

[0020] In this embodiment, the first node N1 and the second node N2, the third node N3 and the fourth node N4, the fifth node N5 and the sixth node N6, and the seventh node N7 and the eighth node N8 are respectively connected through an internal node interconnection (INI) interface 181, for example. That is, the nodes of the same sub-module are connected through the internal interconnection interface 181.

[0021] The first node N1 is connected to the sixth node N6, the second node N2 is connected to the fifth node N5, the third node N3 is connected to the eighth node N8, and the fourth node N4 is connected to the seventh node N7, respectively, for example, through a processor interconnection (P1) interface 182. That is, the nodes of different modules are connected through the processor interconnection interface 182. The first node N1 is connected to the fourth node N4, the second node N2 is connected to the third node N3, the fifth node N5 is connected to the eighth node N8, and the sixth node N6 is connected to the seventh node N7, respectively, for example, through a die interconnection (DI) interface 183. That is, the nodes of different sub-modules of the same module are connected through the die interconnection interface 183.

[0022] In this embodiment, the first node N1 may include a processor 210 and a chipset 220, as Figure 2 shown. In this embodiment, the processor 210 may be a central processing unit (CPU), and the processor 210 may support, for example, 8 cores. The chipset 220 is connected to the processor 210. In addition, the chipset 220 includes a north bridge chip 221 and a south bridge chip 222. The north bridge chip 221 is connected to the processor 210. The south bridge chip 222 is connected to the north bridge chip 221. In addition, the south bridge chip 222 further includes a power management unit (PMU) 223. The power management unit 223 is used to execute the sleep sequence of the node N1 and can be used to control the power off or on of the electronic device 100. Furthermore, the second node N2, the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node may also each include a processor 210 and a chipset 220, as Figure 2 shown.

[0023] In the operation of the sleep mode of the electronic device 100, the first sub-module 120 may execute an operating system (OS) to set the first module 110 and the second module 150 to enter the device power state. For example, the processor 210 of the first node N1 of the first sub-module 120 may execute the operating system to set all the devices of the first module 110 and the second module 150 (i.e., the first node N1, the second node N2, the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node) to enter the device power state, such as the D3 state defined by the advanced configuration and power interface (ACPI) specification.

[0024] Next, the first sub-module 120 can execute the operating system, trigger a system management interrupt (SMI), cause the first sub-module 120 to enter the system management mode (SMM), and execute the system management interrupt handler to configure the second node N2, the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8. For example, the first sub-module 120 can execute the Wbinvd instruction and execute the init EXIPI command to send a transaction layer package (TLP) to the second node N2, the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8.

[0025] In this embodiment, the first node N1 can send transaction layer packages to the second node N2, the fourth node N4, and the sixth node N6. Then, the second node N2 can send transaction layer packages to the third node N3 and the fifth node N5, and the fourth node N4 can send transaction layer packages to the seventh node N7. Thereafter, the third node N3 can send transaction layer packages to the eighth node N8. In this way, the second node N2, the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8 can ignore the SLP# / DPLSP# signals, so that the second node N2, the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8 will not enter the processor power state, such as the C3 state and states above C3 defined by the Advanced Configuration and Power Interface Specification, during the operation in the sleep mode, thereby avoiding misoperations.

[0026] The first sub-module 120 can send a sleep command to the second sub-module 130, the third sub-module 160, and the fourth sub-module 170 according to the instructions of the operating system, so that the second sub-module 130, the third sub-module 160, and the fourth sub-module 170 execute the sleep program in sequence to enter the sleep mode according to the sleep command. For example, the first sub-module 120 can further set the power saving mode of the processor interconnect interface 182 and the chip interconnect interface 183, such as the L23 state defined by the Peripheral Component Interconnect Express (PCIE) specification.

[0027] Next, the first sub-module 120 can query the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8 to confirm that the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8 enter the processor power state. That is to say, the first node N1 of the first sub-module 120 can query a register of the power management unit 223 of the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8 to determine that the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8 enter the C2 state defined by the Advanced Configuration and Power Interface Specification (such as a lower power state). When it is determined that the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8 enter the C2 state, it means that the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8 will no longer execute any processor (CPU) instructions.

[0028] After that, the first sub-module 120 will prohibit sending snoop cycle commands to the second sub-module 130, the third sub-module 160, and the fourth sub-module 170. That is to say, the first node N1 can control the first sub-module 120 to prohibit sending commands to the second sub-module 130, the third sub-module 160, and the fourth sub-module 170 to avoid misoperations of the second sub-module 130, the third sub-module 160, and the fourth sub-module 170 during the operation in the sleep mode.

[0029] Next, according to the sleep command, the second sub-module 130 can send a first signal S1 to the fourth sub-module 170 and the third sub-module 160 can send a second signal S2 to the fourth sub-module, so that the fourth sub-module 170 executes a sleep program to enter the sleep mode and cuts off the connection between the fourth sub-module 170 and the third sub-module 160 and the second sub-module 130. For example, the third node N3 of the second sub-module 130 can send the first signal S1 to the eighth node N8 of the fourth module 170 through the processor interconnect interface 182, and the fifth node N5 of the third sub-module 160 can send the second signal S2 to the eighth node N8 through the chip interconnect interface 183, so that the eighth node N8 executes a sleep program to enter the sleep mode.

[0030] After that, the fourth node N4 of the second sub-module 130 can send the first signal S1 to the seventh node N7 of the fourth sub-module 170 through the processor interconnect 182, and the sixth node N6 of the third sub-module 160 can send the second signal S2 to the seventh node N7 through the chip interface 183, causing the seventh node N7 to execute a sleep program to enter the sleep mode. After the seventh node N7 and the eighth node N8 enter the sleep mode, the fourth sub-module 170 disconnects from the third sub-module 160 and the second sub-module 130. In this embodiment, the eighth node N8 can perform a handshake mechanism with the third node N3 and the fifth node N5, and the seventh node N7 can perform a handshake mechanism with the fourth node N4 and the sixth node N6. That is, after the seventh node N7 and the eighth node N8 enter the sleep mode, the eighth node N8 can provide a disconnection indication signal to the third node N3 and the fifth node N5, and the seventh node N7 can provide a disconnection indication signal to the fourth node N4 and the sixth node N6, to indicate that the fourth sub-module 170 has disconnected from the third sub-module 160 and the second sub-module 130.

[0031] In this embodiment, each of the seventh node N7 and the eighth node N8 may include a logic circuit 310 as Figure 3 shown. The logic circuit 310 receives the first signal S1 and the second signal S2 to generate a sleep enable signal SReady. In this embodiment, the logic circuit 310 is, for example, an AND gate or other suitable logic element, but the embodiments of the present invention are not limited thereto. For example, when the logic circuit 310 receives the first signal S1 and the second signal S2, the logic circuit 310 can generate the sleep enable signal SReady. When the logic circuit 310 does not receive the first signal S1 and the second signal S2, the first signal S1, or the second signal S2, the logic circuit 310 does not generate the sleep enable signal SReady. Then, the sleep enable signal SReady can be transmitted to the power management unit 223 of the south bridge chip 222 of the seventh node N7 and the eighth node N8, and the power management units 223 of the seventh node N7 and the eighth node N8 can execute a sleep program according to the sleep enable signal SReady, causing the seventh node N7 and the eighth node N8 to enter the sleep mode.

[0032] After that, according to the sleep command, the first sub-module 120 can send a third signal to the third sub-module 160, causing the third sub-module 160 to execute a sleep program to enter the sleep mode and disconnecting the third sub-module 160 from the first sub-module 120. For example, the first node N1 of the first sub-module 120 can send the third signal to the sixth node N6 of the third sub-module 160 through the processor interconnect 182, causing the sixth node N6 to execute a sleep program to enter the sleep mode.

[0033] After that, the second node N2 of the first sub-module 120 can send a third signal to the fifth node N5 of the third sub-module 160 through the processor interconnect interface 182, causing the fifth node N5 to execute a sleep program to enter the sleep mode. After the fifth node N5 and the sixth node N6 enter the sleep mode, the third sub-module 160 disconnects from the first sub-module 120. In this embodiment, the sixth node N6 can perform a handshake mechanism with the first node N1 and the fifth node N5 can perform a handshake mechanism with the second node N2. That is to say, after the fifth node N5 and the sixth node N6 enter the sleep mode, the sixth node N6 can provide a disconnection indication signal to the first node N1 and the fifth node N5 can provide a disconnection indication signal to the second node N2 to indicate that the third sub-module 160 has disconnected from the first sub-module 120.

[0034] Next, according to the sleep command, the first sub-module 120 can send a fourth signal to the second sub-module 130, causing the second sub-module 130 to execute a sleep program to enter the sleep mode and disconnecting the second sub-module 130 from the first sub-module 120. For example, the first node N1 of the first sub-module 120 can send a fourth signal to the fourth node N4 of the second sub-module 130 through the chip interconnect interface 183, causing the fourth node N4 to execute a sleep program to enter the sleep mode. After that, according to the sleep command, the second node N2 of the first sub-module 120 can send a fourth signal to the third node N3 of the second sub-module 130 through the chip interconnect interface 183, causing the third node N3 to execute a sleep program to enter the sleep mode. After the third node N3 and the fourth node N4 enter the sleep mode, the second sub-module 130 disconnects from the first sub-module 120. In this embodiment, the fourth node N4 can perform a handshake mechanism with the first node N1 and the third node N3 can perform a handshake mechanism with the second node N2. That is to say, after the third node N3 and the fourth node N4 enter the sleep mode, the fourth node N4 can provide a disconnection indication signal to the first node N1 and the third node N3 can provide a disconnection indication signal to the second node N2 to indicate that the second sub-module 130 has disconnected from the first sub-module 120.

[0035] Next, the first node N1 can query the sleep status registers of the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8 to confirm that the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8 have entered the sleep mode. After the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8 enter the sleep mode, the first node N1 prohibits sending a listening period command to the second node N2 to avoid misoperation of the second node N2 during the sleep mode operation.

[0036] Next, the first node N1 can send a sleep command to the second node N2 to cause the second node N2 to execute a sleep program to enter the sleep mode. For example, the first node N1 can send a sleep command to the second node N2 through the internal node interconnect interface 181 to cause the second node N2 to execute a sleep program to enter the sleep mode. After that, the first node N1 can query the sleep status register of the second node N2 to confirm that the second node N2 has entered the sleep mode.

[0037] Next, the first node N1 can send a sleep command to the first node N1 to cause the first node N1 to execute a sleep program to enter the sleep mode. For example, the first node N1 can send a sleep command to the power management unit 223 of the south bridge chip 222 of the first node N1, and then the power management unit 223 executes the sleep program to cause the first node to enter the sleep mode. In this way, all nodes of the electronic device 100 (such as the first node N1, the second node N2, the third node N3, the fourth node N4, the fifth node N5, the sixth node N6, the seventh node N7, and the eighth node N8) can enter the expected sleep mode, thereby increasing the convenience of use.

[0038] Figure 4 It is a flowchart of an operation method of the sleep mode of an electronic device according to an embodiment of the present invention. In step S402, a sleep command is sent to the second sub-module of the first module, the third sub-module of the second module, and the fourth sub-module of the second module through the first sub-module of the first module, where the first sub-module includes the first node and the second node, the second sub-module includes the third node and the fourth node, the third sub-module includes the fifth node and the sixth node, and the fourth sub-module includes the seventh node and the eighth node.

[0039] In step S404, according to the sleep command, the second sub-module, the third sub-module, and the fourth sub-module sequentially execute a sleep program to enter the sleep mode. In step S406, a sleep command is sent to the second node through the first node to cause the second node to execute a sleep program to enter the sleep mode. In step S408, a sleep command is sent to the first node through the first node to cause the first node to execute a sleep program to enter the sleep mode. In this embodiment, the first node and the second node, the third node and the fourth node, the fifth node and the sixth node, and the seventh node and the eighth node are connected through the internal node interconnect interface respectively, for example. The first node and the sixth node, the second node and the fifth node, the third node and the eighth node, and the fourth node and the seventh node are connected through the processor interconnect interface respectively, for example. The first node and the fourth node, the second node and the third node, the fifth node and the eighth node, and the sixth node and the seventh node are connected through the chip interconnect interface respectively, for example.

[0040] Figure 5For Figure 4 Detailed flowchart of step S404 of

[0041] In step S502, according to the sleep command, the second sub-module sends a first signal to the fourth sub-module and the third sub-module sends a second signal to the fourth sub-module, causing the fourth sub-module to execute a sleep program to enter the sleep mode and disconnecting the fourth sub-module from the third sub-module and the second sub-module.

[0042] Figure 6 For Figure 5 Detailed flowchart of step S502 of

[0043] In step S602, according to the sleep command, the third node of the second sub-module sends a first signal to the eighth node of the fourth sub-module and the fifth node of the third sub-module sends a second signal to the eighth node, causing the eighth node to execute a sleep program to enter the sleep mode.

[0044] Figure 7 For Figure 5 Detailed flowchart of step S504 of

[0045] Figure 8 For Figure 5Detailed flowchart of step S506. In step S802, according to the sleep command, the first node of the first sub-module sends a fourth signal to the fourth node of the second sub-module, causing the fourth node to execute a sleep program to enter the sleep mode. In step S804, according to the sleep command, the second node of the first sub-module sends a fourth signal to the third node of the second sub-module, causing the third node to execute a sleep program to enter the sleep mode. In step S806, the connection between the second sub-module and the first sub-module is cut off.

[0046] Figure 9 For Figure 4 Another detailed flowchart of step S404. In this embodiment, steps S502 - S506 are the same as or similar to Figure 5 steps S504 - S506, and reference can be made to the description of the Figure 5 embodiment, so it will not be elaborated here.

[0047] In step S902, the first sub-module queries the third, fourth, fifth, sixth, seventh, and eighth nodes to confirm that the third, fourth, fifth, sixth, seventh, and eighth nodes enter the processor power state. In step S904, the first sub-module is prohibited from sending listen cycle commands to the second, third, and fourth sub-modules.

[0048] Figure 10 Flowchart of the operation method of the sleep mode of an electronic device according to another embodiment of the present invention. In this embodiment, steps S402 - S408 are the same as or similar to Figure 4 steps S402 - S408, and reference can be made to the description of the Figure 4 embodiment, so it will not be elaborated here. In step S1002, the first sub-module executes the operating system to set the first module and the second module to enter the device power state. In step S1004, the first sub-module executes the operating system to trigger a system management interrupt, causing the first sub-module to enter the system management mode and execute a system management interrupt handler to set the second, third, fourth, fifth, sixth, seventh, and eighth nodes. In step S1006, the first node is prohibited from sending listen cycle commands to the second node.

[0049] It should be noted that Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10The order of the steps is only for illustrative purposes and is not used to limit the order of the steps of the embodiments of the present invention. Moreover, the order of the above steps can be changed by the user according to their needs. Additionally, without departing from the spirit and scope of the present invention, additional steps can be added or fewer steps can be used.

[0050] In summary, for the electronic device and the operation method of its sleep mode disclosed in the present invention, the first sub-module of the first module sends a sleep command to the second sub-module of the first module, the third sub-module of the second module, and the fourth sub-module of the second module, so that the second sub-module, the third sub-module, and the fourth sub-module sequentially execute a sleep program to enter the sleep mode. The first node sends a sleep command to the second node, so that the second node executes a sleep program to enter the sleep mode. The first node sends a sleep command to the first node, so that the first node executes a sleep program to enter the sleep mode. In this way, the sleep function design can be realized in an electronic device with a complex structure, thereby increasing the convenience in use.

[0051] Although the present invention is disclosed as above with embodiments, it is not intended to limit the scope of the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the appended claims.

Claims

1. A method for operating a sleep mode of an electronic device, comprising: Sending a sleep command by a first sub-module of a first module to a second sub-module of the first module, a third sub-module of a second module, and a fourth sub-module of the second module, wherein the first sub-module includes a first node and a second node, the second sub-module includes a third node and a fourth node, the third sub-module includes a fifth node and a sixth node, and the fourth sub-module includes a seventh node and an eighth node; According to the sleep command, the second sub-module, the third sub-module, and the fourth sub-module sequentially execute a sleep program to enter a sleep mode; Sending the sleep command from the first node to the second node, causing the second node to execute the sleep program to enter the sleep mode; and Sending the sleep command from the first node to the first node, causing the first node to execute the sleep program to enter the sleep mode, wherein the step of the second sub-module, the third sub-module, and the fourth sub-module sequentially executing the sleep program to enter the sleep mode according to the sleep command includes: According to the sleep command, the second sub-module sends a first signal to the fourth sub-module and the third sub-module sends a second signal to the fourth sub-module, causing the fourth sub-module to execute the sleep program to enter the sleep mode and disconnecting the fourth sub-module from the third sub-module and the second sub-module; According to the sleep command, the first sub-module sends a third signal to the third sub-module, causing the third sub-module to execute the sleep program to enter the sleep mode and disconnecting the third sub-module from the first sub-module; and According to the sleep command, the first sub-module sends a fourth signal to the second sub-module, causing the second sub-module to execute the sleep program to enter the sleep mode and disconnecting the second sub-module from the first sub-module.

2. The method for operating a sleep mode of an electronic device according to claim 1, further comprising: Executing an operating system by the first sub-module to set the first module and the second module to enter a device power state; And Executing the operating system by the first sub-module to trigger a system management interrupt, causing the first sub-module to enter a system management mode and execute a system management interrupt handler to set the second node, the third node, the fourth node, the fifth node, the sixth node, the seventh node, and the eighth node.

3. The method for operating a sleep mode of an electronic device according to claim 1, wherein the step of the second sub-module sending the first signal to the fourth sub-module and the third sub-module sending the second signal to the fourth sub-module according to the sleep command, causing the fourth sub-module to execute the sleep program to enter the sleep mode and disconnecting the fourth sub-module from the third sub-module and the second sub-module includes: According to the sleep command, the third node of the second sub-module sends the first signal to the eighth node of the fourth sub-module and the fifth node of the third sub-module sends the second signal to the eighth node, causing the eighth node to execute the sleep program to enter the sleep mode; According to the sleep command, the fourth node of the second sub-module sends the first signal to the seventh node of the fourth sub-module, and the sixth node of the third sub-module sends the second signal to the seventh node, causing the seventh node to execute the sleep program to enter the sleep mode; and Cut off the connection between the fourth sub-module and the third sub-module and the second sub-module.

4. The method for operating the sleep mode of the electronic device according to claim 1, wherein according to the sleep command, the first sub-module sends a third signal to the third sub-module, causing the third sub-module to execute the sleep program to enter the sleep mode. The steps of cutting off the connection between the third sub-module and the first sub-module include: According to the sleep command, the first node of the first sub-module sends the third signal to the sixth node of the third sub-module, causing the sixth node to execute the sleep program to enter the sleep mode; According to the sleep command, the second node of the first sub-module sends the third signal to the fifth node of the third sub-module, causing the fifth node to execute the sleep program to enter the sleep mode; and Cut off the connection between the third sub-module and the first sub-module.

5. The method for operating the sleep mode of the electronic device according to claim 1, wherein according to the sleep command, the first sub-module sends a fourth signal to the second sub-module, causing the second sub-module to execute the sleep program to enter the sleep mode. The steps of cutting off the connection between the second sub-module and the first sub-module include: According to the sleep command, the first node of the first sub-module sends the fourth signal to the fourth node of the second sub-module, causing the fourth node to execute the sleep program to enter the sleep mode; According to the sleep command, the second node of the first sub-module sends the fourth signal to the third node of the second sub-module, causing the third node to execute the sleep program to enter the sleep mode; and Cut off the connection between the second sub-module and the first sub-module.

6. The method for operating the sleep mode of the electronic device according to claim 1, wherein the steps of the second sub-module, the third sub-module and the fourth sub-module sequentially executing the sleep program to enter the sleep mode further include: Query the third node, the fourth node, the fifth node, the sixth node, the seventh node and the eighth node through the first sub-module to confirm that the third node, the fourth node, the fifth node, the sixth node, the seventh node and the eighth node enter the processor power state; And Prohibit the first sub-module from sending listening cycle commands to the second sub-module, the third sub-module and the fourth sub-module.

7. The method for operating the sleep mode of the electronic device according to claim 1 further includes: Prohibit the first node from sending listening cycle commands to the second node.

8. The operating method of the sleep mode of the electronic device as claimed in claim 1, wherein the first node is connected to the second node, the third node is connected to the fourth node, the fifth node is connected to the sixth node, and the seventh node is connected to the eighth node respectively through internal node interconnection interfaces; the first node is connected to the sixth node, the second node is connected to the fifth node, the third node is connected to the eighth node, and the fourth node is connected to the seventh node respectively through processor interconnection interfaces; the first node is connected to the fourth node, the second node is connected to the third node, the fifth node is connected to the eighth node, and the sixth node is connected to the seventh node respectively through chip interconnection interfaces.

9. An electronic device, comprising: A first module, comprising: A first sub-module, comprising: A first node; and A second node, connecting the first node; and A second sub-module, comprising: A third node, connecting the second node; and A fourth node, connecting the third node and the first node; and A second module, comprising: A third sub-module, comprising: A fifth node, connecting the second node; and A sixth node, connecting the fifth node and the first node; and A fourth sub-module, comprising: A seventh node, connecting the sixth node and the fourth node; and An eighth node, connecting the seventh node, the third node and the fifth node; Wherein, the first sub-module sends a sleep command to the second sub-module, the third sub-module and the fourth sub-module, so that the second sub-module, the third sub-module and the fourth sub-module execute the sleep program in sequence according to the sleep command to enter the sleep mode. The first node sends the sleep command to the second node, so that the second node executes the sleep program to enter the sleep mode. The first node sends the sleep command to the first node, so that the first node executes the sleep program to enter the sleep mode. According to the sleep command, the second sub-module sends a first signal to the fourth sub-module and the third sub-module sends a second signal to the fourth sub-module, so that the fourth sub-module executes the sleep program to enter the sleep mode and cuts off the connection between the fourth sub-module and the third sub-module and the second sub-module; according to the sleep command, the first sub-module sends a third signal to the third sub-module, so that the third sub-module executes the sleep program to enter the sleep mode and cuts off the connection between the third sub-module and the first sub-module; according to the sleep command, the first sub-module sends a fourth signal to the second sub-module, so that the second sub-module executes the sleep program to enter the sleep mode and cuts off the connection between the second sub-module and the first sub-module.

10. The electronic device as claimed in claim 9, wherein the first sub-module executes an operating system to set the first module and the second module to enter the device power state; the first sub-module executes the operating system to trigger a system management interrupt, so that the first sub-module enters the system management mode and executes a system management interrupt handler to set the second node, the third node, the fourth node, the fifth node, the sixth node, the seventh node and the eighth node.

11. The electronic device according to claim 9, wherein according to the sleep command, the third node of the second sub-module sends the first signal to the eighth node of the fourth sub-module and the fifth node of the third sub-module sends the second signal to the eighth node, so that the eighth node executes the sleep program to enter the sleep mode; according to the sleep command, the fourth node of the second sub-module sends the first signal to the seventh node of the fourth sub-module and the sixth node of the third sub-module sends the second signal to the seventh node, so that the seventh node executes the sleep program to enter the sleep mode; the fourth sub-module cuts off the connection with the third sub-module and the second sub-module.

12. The electronic device according to claim 11, wherein each of the seventh node and the eighth node includes: a logic circuit that receives the first signal and the second signal to generate a sleep enable signal.

13. The electronic device according to claim 9, wherein according to the sleep command, the first node of the first sub-module sends the third signal to the sixth node of the third sub-module, so that the sixth node executes the sleep program to enter the sleep mode; according to the sleep command, the second node of the first sub-module sends the third signal to the fifth node of the third sub-module, so that the fifth node executes the sleep program to enter the sleep mode; the third sub-module cuts off the connection with the first sub-module.

14. The electronic device according to claim 9, wherein according to the sleep command, the first node of the first sub-module sends the fourth signal to the fourth node of the second sub-module, so that the fourth node executes the sleep program to enter the sleep mode; according to the sleep command, the second node of the first sub-module sends the fourth signal to the third node of the second sub-module, so that the third node executes the sleep program to enter the sleep mode; the second sub-module cuts off the connection with the first sub-module.

15. The electronic device according to claim 9, wherein the first sub-module further queries the third node, the fourth node, the fifth node, the sixth node, the seventh node and the eighth node to confirm that the third node, the fourth node, the fifth node, the sixth node, the seventh node and the eighth node enter the processor power state, and prohibits sending listen cycle commands to the second sub-module, the third sub-module and the fourth sub-module.

16. The electronic device according to claim 9, wherein the first node prohibits sending listen cycle commands to the second node.

17. The electronic device according to claim 9, wherein the first node and the second node, the third node and the fourth node, the fifth node and the sixth node, and the seventh node and the eighth node are respectively connected through internal node interconnection interfaces; the first node and the sixth node, the second node and the fifth node, the third node and the eighth node, and the fourth node and the seventh node are respectively connected through processor interconnection interfaces; the first node and the fourth node, the second node and the third node, the fifth node and the eighth node, and the sixth node and the seventh node are respectively connected through chip interconnection interfaces.

Images