Perform a checkpoint operation on the shift register

Abstract

The present disclosure relates to performing checkpoint operations on a shift register. A hardware structure provides a way to perform one or more checkpoint operations on a main shift register. The hardware structure includes an extended shift register having an additional data location for each checkpoint for storing data elements that were most recently shifted onto the main shift register. An update history shift register has a data location for each checkpoint for storing information indicating whether the extended shift register has been updated. Checkpoint generation logic obtains each checkpoint by selecting a subset of the data elements stored in the extended shift register based on the information stored in the update history shift register.

Description

[0001] This application is a divisional application of the application with the application date of July 8, 2016, application number 201610539460.0, and invention title "Checkpoint Operation on Shift Register".

[0002] Background

[0003] As is known to those skilled in the art, a shift register is a data structure for sequentially recording a predetermined number N of data elements. When a new data element is received at the shift register, the existing data elements in the shift register are "shifted" by one data position to make room for the new data element, and the new data element is stored in the first data position of the shift register.

[0004] In the case where the shift register has only N data positions (and thus can store only N data elements), if the shift register already has N data elements when it receives a new data element, the last (or earliest) data element is removed from the shift register to make room for the new data element. The removed data element (and the information associated therewith) is then lost. However, in some cases, it is important to know what the shift register looked like before it was updated or before a certain event occurred. In these cases, a copy or snapshot of the shift register is obtained and stored before the shift register is updated or before the event occurs. This process of obtaining and storing a snapshot of the shift register is referred to as checkpointing the shift register.

[0005] The embodiments described below are provided only as examples and are not limitations of implementations that solve any or all of the disadvantages of known methods for checkpointing a shift register.

[0006] Overview

[0007] This overview is provided to introduce a series of concepts in a simplified form, which are further described in the detailed description below. This overview is not intended to identify the key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0008] This document describes methods and hardware architectures for performing checkpoint operations on a main shift register one or more times. The hardware architecture includes an extended shift register for storing data elements that have most recently been shifted onto the main shift register, the extended shift register having additional data positions for each checkpoint. An update history shift register has data position information for each checkpoint, the data position information for each checkpoint being used to store information indicating whether the extended shift register is updated at a particular clock cycle. Checkpoint generation logic obtains each checkpoint by selecting a subset of the data elements stored in the extended shift register based on the information stored in the update history shift register.

[0009] A first aspect provides a hardware architecture configured to obtain one or more checkpoints of a main shift register having a predetermined number of data positions. The hardware architecture includes an extended shift register having data positions for each data position of the main shift register and additional data positions for each checkpoint. The data positions of the extended shift register store data elements that have most recently been shifted onto the main shift register. An update history shift register has data positions for each checkpoint, and each data position of the update history register stores information indicating whether the extended shift register is updated at the same clock cycle as a particular checkpoint trigger event. Checkpoint generation logic obtains each checkpoint by selecting a subset of the data positions of the extended shift register based on the information stored in the update history shift register.

[0010] A second aspect provides a method for obtaining one or more checkpoints of a main shift register having a predetermined number of data positions. The method includes storing a predetermined number of data elements that have most recently been shifted onto the main shift register in a plurality of data positions of an extended shift register. The method stores additional data elements for each checkpoint in additional data positions of the extended shift register. Information indicating whether the extended shift register is updated at the same clock cycle as a particular checkpoint trigger event is stored in a data position of an update history shift register. The method obtains each checkpoint by selecting a subset of the data positions of the extended shift register based on the information stored in the update history shift register.

[0011] Embodiments of the present disclosure relate to the following aspects:

[0012] 1) A hardware architecture configured to obtain one or more checkpoints of a main shift register, the checkpoints being triggered by trigger events, the hardware architecture including:

[0013] An extended shift register having a plurality of data positions for storing data elements, the plurality of data positions including a first subset representing the data positions of the main shift register and additional data positions for each checkpoint;

[0014] An update history shift register having data positions for each checkpoint, each data position of the update history shift register storing information indicating whether the extended shift register was updated in the same clock cycle as a particular checkpoint trigger event; and

[0015] Checkpoint generation logic configured to obtain each checkpoint by selecting a subset of the plurality of data positions of the extended shift register based on the information stored in the update history shift register.

[0016] 2) The hardware structure according to 1), wherein the selected subset of the plurality of data positions of the extended shift register for a particular checkpoint can be offset from the first subset of data positions by zero, one data position, or more than one data position.

[0017] 3) The hardware structure according to 2), wherein the checkpoint generation logic is configured to determine the offset from the first subset of data positions for a particular checkpoint by evaluating the information stored in a plurality of relevant data positions of the update history shift register.

[0018] 4) The hardware structure according to 3), wherein each checkpoint represents the main shift register prior to a plurality of checkpoint trigger events, and the number of relevant data positions for a particular checkpoint is equal to the number of checkpoint trigger events for that checkpoint.

[0019] 5) The hardware structure according to 3), wherein the offset is equal to the count of the relevant data positions of the update history shift register that include information indicating that the extended shift register was updated.

[0020] 6) The hardware structure according to any one of 2) to 5), wherein the checkpoint generation logic is configured to obtain a first checkpoint representing the main shift register prior to the most recent checkpoint trigger event by: determining in the checkpoint generation logic whether a first data position of the update history shift register includes information indicating that the extended shift register was updated; in response to determining that the first data position of the update history shift register does not include information indicating that the extended shift register was updated, selecting in the checkpoint generation logic the first subset of data positions of the extended shift register; and in response to determining that the first data position of the update history shift register includes information indicating that the extended shift register was updated, selecting in the checkpoint generation logic a subset of the plurality of data positions of the extended shift register that is offset from the first subset of data positions by one data position.

[0021] 7) The hardware structure according to any one of 2) to 5), wherein the number of checkpoints is at least two, and the checkpoint generation logic is configured to obtain a second checkpoint representing the main shift register before the two most recent checkpoint trigger events by the following operations: counting in the checkpoint generation logic the number of the first two data positions of the update history shift register including information indicating that the extended shift register is updated; and selecting in the checkpoint generation logic a subset of the plurality of data positions of the extended shift register that is offset from the first subset of data positions by the count of the first two data positions of the update history shift register.

[0022] 8) The hardware structure according to any one of 1) to 5), further comprising update logic configured to, in each clock cycle: determine in the update logic whether a checkpoint trigger event occurs; in response to determining that a checkpoint trigger event has occurred, determine in the update logic whether the extended shift register is updated in the current clock cycle; in response to determining that the extended shift register is updated in the current clock cycle, shift in the update logic information indicating that the extended shift register has been updated onto the update history shift register; and in response to determining that the extended shift register is not updated in the current clock cycle, shift in the update logic information indicating that the extended shift register has not been updated onto the update history shift register.

[0023] 9) The hardware structure according to any one of 1) to 5), further comprising: a recovery buffer having a plurality of data positions, each data position storing a copy of a data element of the extended shift register and a copy of information of the update history shift register at a specific time point; and recovery logic configured to, in response to receiving an indication that recovery is to be performed, restore the extended shift register and the update history shift register to a specific time point using the copies stored in the recovery buffer.

[0024] 10. A method for obtaining one or more checkpoints of a main shift register, the checkpoints being triggered by trigger events, the method comprising:

[0025] Storing data elements in a plurality of data positions of an extended shift register, the plurality of data positions including a first subset representing data positions of the main shift register and additional data positions for each checkpoint;

[0026] Storing information indicating whether the extended shift register is updated in the same clock cycle as a specific checkpoint trigger event in a data position of an update history shift register; and

[0027] Each checkpoint is obtained in the hardware logic by selecting a subset of the plurality of data positions of the expansion shift register based on information stored in the update history shift register.

[0028] As will be apparent to the person skilled in the art, the preferred features may be combined as appropriate and may be combined with any aspect of the invention.

[0029] Brief Description of the Drawings

[0030] By way of example, embodiments of the present invention will be described with reference to the following drawings, in which:

[0031] Figure 1(A)-1(D) is a schematic diagram showing an example global history register (GHR);

[0032] Figure 2 is using Figure 1(A)-1(D) of the GHR example three-stage instruction fetch unit pipeline block diagram;

[0033] Figure 3 is a schematic diagram showing the Figure 1(A)-1(D) after the non-branch instruction is sent to the execution unit for checkpoint operation of the GHR;

[0034] Figure 4 is a schematic diagram showing the Figure 1(A)-1(D) after the branch instruction is sent to the execution unit for checkpoint operation of the GHR;

[0035] Figure 5(A)-5(C) is a schematic diagram showing an example recovery buffer;

[0036] Figure 6 is a schematic diagram showing an expansion shift register and an update history shift register;

[0037] Figure 7 is for updating Figure 6 example method flowchart of the expansion shift register and the update history shift register;

[0038] Figure 8(A)-8(D) is showing the use of Figure 7 method to update Figure 6 schematic diagram of the expansion shift register and the update history shift register;

[0039] Figure 9 is for Figure 6 example method flowchart of obtaining the first checkpoint from the expansion shift register and the update history shift register;

[0040] Figure 10 is for Figure 6Flowchart of an example method for obtaining a second checkpoint from an extended shift register and an update history shift register;

[0041] Figure 11 is for obtaining from Figure 6 Flowchart of an example method for obtaining a third checkpoint from an extended shift register and an update history shift register;

[0042] Figure 12 is according to Figures 9 to 11 Schematic diagram of a checkpoint obtained from an example extended shift register and an example update history shift register according to the method;

[0043] Figure 13(A)-13(C) is for restoring Figure 6 Schematic diagram of an example recovery buffer for an extended shift register and an update history shift register;

[0044] Figure 14 Block diagram of an example hardware structure for performing a checkpoint operation on a shift register;

[0045] Figure 15 Schematic diagram of a circular buffer and an update history shift register;

[0046] Figures 16(A) and 16(B) are schematic diagrams showing the update of the circular buffer and the update history shift register after a non-branch instruction is sent to the execution unit;

[0047] Figures 17(A) and 17(B) are schematic diagrams showing the update of the circular buffer and the update history shift register after a branch instruction is sent to the execution unit;

[0048] Figures 18(A) and 18(B) are schematic diagrams showing the update of the circular buffer and the update history shift register after a branch instruction is sent to the execution unit;

[0049] Figure 19 is for obtaining from Figure 15 Flowchart of an example method for obtaining a first checkpoint from a circular buffer and an update history shift register;

[0050] Figure 20 is for obtaining from Figure 15 Flowchart of an example method for obtaining a second checkpoint from a circular buffer and an update history shift register;

[0051] Figure 21 is for obtaining from Figure 15 Flowchart of an example method for obtaining a third checkpoint from a circular buffer and an update history shift register;

[0052] Figure 22 is according to Figures 19 to 21Schematic diagram of a checkpoint obtained from an example circular buffer and an example update history shift register;

[0053] Figure 23(A)-23(C) for recovery Figure 15 Schematic diagram of a first example recovery buffer for the update history shift register and pointer to be recovered;

[0054] Figure 24(A)-24(C) Shows an update Figure 15 Schematic diagram of the pointer to be updated in response to a conditional branch instruction being issued to an execution unit for execution;

[0055] Figure 25(A)-25(C) for recovery Figure 15 Schematic diagram of a second example recovery buffer for the update history shift register and pointer to be recovered;

[0056] Figure 26(A)-26(B) Shows the use of Figure 25(A)-25(C) The recovery buffer to recover Figure 15 Schematic diagram of the update history and pointer; and

[0057] Figure 27 Block diagram of an example hardware structure for checkpointing a shift register.

[0058] Common reference numerals are used throughout the drawings to indicate like features.

[0059] Detailed description

[0060] The embodiments of the present invention are described below only by way of example. These examples represent various ways of implementing the present invention, which are currently known to the applicant, but they are not the only ways in which the present invention can be implemented. This description sets forth the functions of the examples and the order of steps for constructing and operating the examples. However, the same or equivalent functions and orders can be implemented by different examples.

[0061] An improved method for checkpointing a main shift register is described herein, which uses a small update history shift register to keep track of changes to the main shift register. Shift registers can be used in a processor for various purposes. For example, a shift register can be used to store the history of the results (e.g., taken or not taken) of the N most recent conditional branch instructions. Such a shift register is often referred to as a global history register (GHR). The improved checkpointing method will be described with reference to the GHR, however, it will be apparent to those skilled in the art that the GHR is merely an example shift register and the improved checkpointing method can be applied to various shift registers.

[0062] Now referring to Figure 1(A)-1(D)。In this example, GHR102 includes eight data positions (numbered 0 to 7), 104 to 118, for storing an ordered list of data elements. In this case, each data element is the predicted result (taken / not taken) of a conditional branch instruction, such that GHR 102 stores an ordered list of the eight most recent predicted results (taken / not taken) of conditional branch instructions. It will be apparent to those skilled in the art that other shift registers and GHRs may have more or fewer data positions.

[0063] In this example, the least significant data position 104 stores the most recent predicted result of the conditional branch instruction, while the most significant data position 118 stores the earliest predicted result of the conditional branch instruction. However, it will be apparent to those skilled in the art that the data within the GHR may be arranged in another way (e.g., the most significant data position may store the most recent predicted result of the conditional branch instruction).

[0064] In Figure 1(A)-1(D) the example, each data position 104 to 108 includes a single bit for storing the predicted result ("1" or "0") of the conditional branch instruction. In particular, in this example, a one ("1") is used to indicate that the branch is predicted to be taken, while a zero (0) is used to indicate that the branch is predicted not to be taken. However, it will be apparent to those skilled in the art that other shift registers and GHRs may have a different number of bits per data position, depending on the type of data being stored.

[0065] As with any shift register, when GHR 102 receives a new data element (e.g., a bit) to be inserted into GHR 102, the existing data elements (e.g., bits) in GHR 102 are "shifted" one data position (e.g., bit), and the new data element is stored in the first data position. In particular, in Figures 1(A) to 1(D) when GHR 102 receives a new data element to be inserted into GHR 102, the data elements in the first seven data positions 104 to 116 are shifted one data position each to the next seven data positions 106 to 118, and the new data element is inserted into the first data position 104 (while any data stored in the last data position 118 will be shifted out of GHR 102).

[0066] This is in Figures 1(A) to 1(D)Shown in. For example, if the GHR 102 is initially set to all zeros as shown in FIG. 1(A), when the GHR 102 receives a new data element (the prediction result of "1"), in FIG. 1(B), the data "0000000" at the first seven data positions 104 to 116 are respectively shifted by one data position to the next seven data positions 106 to 118 and the new data element (e.g., the new prediction result of "1") is placed at the first data position 104, such that the GHR 102 contains the data "00000001". If the GHR 102 subsequently receives a "0" to be inserted into the GHR 102, then the data at the first seven data positions 104 to 116 are similarly shifted by one data position and the new data element "0" is inserted at the first data position 104, such that the GHR contains the data "00000010", as shown in FIG. 1(C). Similarly, if the GHR 102 subsequently receives a "1" to be inserted into the GHR 102, then the data in the GHR 102 are again shifted by one data position and the new data element "1" is inserted at the first data position 104, such that the GHR contains the data "00000101", as shown in FIG. 1(D).

[0067] As described above, in some cases, it is important to know what the shift register looks like before it is updated or before a certain event. For example, in the case where the shift register is the GHR, it is important to know what the GHR looks like before the instruction is sent to the execution unit for execution. In these cases, a copy or snapshot of the shift register is obtained and stored before the update or before a certain event occurs to preserve a picture of what the shift register looks like. This process of obtaining and storing a snapshot of the shift register is referred to as checkpointing the shift register. Accordingly, the event that triggers the checkpointing of the shift register (e.g., sending the instruction to the execution unit for execution) will be referred to herein as the checkpoint trigger event.

[0068] For example, as Figure 2 shown, the instruction fetch unit (IFU) 202 of a multi-threaded processor can implement a pipelined (i.e., multi-cycle or multi-stage) process 204 for obtaining instructions from the instruction cache (i-cache) and using the GHR 102 to predict the result of a conditional branch instruction. In particular, in Figure 2In the example, the pipelined process 204 includes three stages - a fetch stage 206, a cache stage 208, and a select stage 210; and both the fetch stage 206 and the cache stage 208 use the GHR 102. For example, in the fetch stage 206, the GHR 102 can be used to generate an index for the jump register cache (JRC), and during the cache stage 208, the GHR 102 can be used to generate an index for the branch history table (BHT). At the end of the process 204, the GHR 102 is updated by the update logic 211 to include the predicted result of any conditional branch instruction.

[0069] For the prediction method to work correctly, the GHR value read by any stage in the pipelined process 204 must be invariant, meaning that regardless of what happens in the pipeline (e.g., different threads are fetched), the GHR value must match the best-case IFU performance (e.g., one thread is fetched, there are no gaps in the fetch, etc.). However, since the GHR 102 is updated and read in different cycles, this is not always the case.

[0070] For example, since the processor is multi-threaded in this example, instructions from multiple threads can be interleaved in the pipelined process 204. Thus, if in clock cycle A, the first instruction related to the first thread is in the fetch stage 206, the second instruction related to the first thread is in the cache stage 208, and a conditional branch instruction related to the second thread is in the select stage 210; in clock cycle A+1, the GHR 102 will be updated to include the predicted result of the conditional branch instruction related to the second thread, and the cache stage 208 will read the updated GHR 102. However, the predicted result of the second stage included in the updated GHR 102 is not relevant to the prediction of the result of the first or second instruction related to the first thread.

[0071] Accordingly, to ensure that the prediction method works correctly, the GHR 102 is checkpointed multiple times so that different stages of the pipelined process 204 can use different versions of the GHR as appropriate. Different versions of the GHR can be snapshots of the GHR before one or more checkpoint trigger events. In this example, the GHR is checkpointed whenever the IFU sends an instruction to the execution unit for execution, so the checkpoint trigger event is sending an instruction to the execution unit for execution, however in other examples, other checkpoint trigger events can be used. In this example, the GHR is checkpointed three times, but in other examples, the GHR or other shift registers can be checkpointed fewer or more times. The result of each checkpoint can be stored in separate checkpoint registers 212, 214, 216.

[0072] Now refer to Figure 3and Figure 4 . In these examples, the GHR 102 is checkpointed three times, and the results of each checkpoint are stored in separate eight-bit checkpoint registers 212, 214, 216. The first checkpoint register 212 stores the GHR when the GHR was before a checkpoint trigger event (e.g., before the most recent instruction was sent to the execution unit for execution); the second checkpoint register 214 stores the GHR when the GHR was before two checkpoint trigger events (e.g., before the two most recent instructions were sent to the execution unit for execution); and the third checkpoint register 216 stores the GHR when the GHR was before three checkpoint trigger events (e.g., before the three most recent instructions were sent to the execution unit for execution).

[0073] When a checkpoint trigger event occurs (e.g., an instruction is sent to the execution unit for execution), the data in the GHR 102, the first checkpoint register 212, and the second checkpoint register 214 are respectively copied to the first, second, and third checkpoint registers 212, 214, and 216. Specifically, the data in the second checkpoint register 214 is copied to the third checkpoint register 216, as indicated at 302; the data in the first checkpoint register 212 is copied to the second checkpoint register 214, as indicated at 304; the data in the GHR 102 is copied to the first checkpoint register 212, as indicated at 306; and when the instruction sent to the execution unit is a conditional branch instruction, the GHR 102 is updated to include the predicted result of the conditional branch instruction, otherwise no change is made to the GHR 102. For example, in Figure 3 the example, the instruction sent to the execution unit (EXU) is not a conditional branch instruction, so in clock cycle A + 1, the GHR 102 remains the same as in clock cycle A. In contrast, in Figure 4 the example, the instruction sent to the execution unit (EXU) is a conditional branch instruction and the branch is predicted to be taken, so a "1" is shifted onto the GHR102 in clock cycle A + 1.

[0074] Referring back Figure 2 , when a misprediction occurs, the IFU 202 restores the GHR 102 and the checkpoint registers 212, 214, and 216 to what they were before the mispredicted instruction was sent to the execution unit. To be able to restore the checkpoint registers 212, 214, and 216 after a misprediction, for each uncompleted or in-flight conditional branch instruction (i.e., a conditional branch instruction that has been predicted but not yet executed), the IFU 202 stores a copy of the data in the checkpoint registers 212, 214, and 216 in the restore buffer 218.

[0075] Now referring toFigure 5(A)-5(C) 。In Figure 5(A)-5(C) the example of Figure 5(A)-5(C) , the recovery buffer 218 is implemented as a FIFO (first-in-first-out) circular buffer including a plurality of data positions 5020 to 5024, where each data position is used to store copies of three checkpoint registers for a specific conditional branch instruction; the read pointer 504 points to the data position 5020 to 5024 containing the checkpoint register value of the earliest outstanding or unfinished conditional branch instruction (i.e., the conditional branch instruction predicted the longest time ago); and the write pointer 506 points to the next data position 5020 to 5024 to be written.

[0076] In some cases, when the IFU 202 makes a conditional branch prediction, the data in the checkpoint registers 212, 214, and 216 is pushed onto the recovery buffer 218. In particular, the data in the checkpoint registers 212, 214, and 216 is written to the data position of the recovery buffer 218 indicated by the write pointer 506, and then the write pointer 506 is incremented to point to the next data position. For example, if the recovery buffer 218 has five data positions 5020 to 5024 and the read pointer 504 points to the first data position 5020 while the write pointer 506 points to the fourth data position 5023, as shown in FIG. 5(A), then when the IFU 202 makes a branch prediction for the conditional branch instruction D, the data in the checkpoint registers 212, 214, and 216, which are referred to as checkpoint 1-D, checkpoint 2-D, and checkpoint 3-D, is stored in the fourth data position 5023, as shown in FIG. 5(B), and the write pointer 506 is incremented to point to the fifth data position 5024.

[0077] When the IFU 202 receives information indicating that a branch instruction has been executed from an execution unit (EXU) (e.g., via the recovery logic 220), the data in the data positions 5020 to 5024 pointed to by the read pointer 504 pops out of the recovery buffer 218. In particular, the read pointer 504 is incremented to point to the next data position 5020 to 5024. For example, if the recovery buffer 218 has five data positions 5020 to 5024 and the read pointer 504 points to the first data position 5020 while the write pointer 506 points to the fifth data position 5024, as shown in FIG. 5(B), when the IFU 202 receives information indicating that the branch instruction A has been executed from the EXU, then the read pointer 504 is incremented to point to the second data position 5021, as shown in FIG. 5(C).

[0078] If the IFU 202 receives an indication that a misprediction has occurred, the IFU 202 replaces the data in the checkpoint registers 212, 214, and 216 with the data from the top data position (the data position pointed to by the read pointer 504), and then invalidates the entries in the recovery buffer 218.

[0079] The number of data positions in the recovery buffer 218 generally equals the maximum number of conditional branch instructions that may be outstanding or in flight at any given time (i.e., conditional branch instructions that have been predicted but not yet executed), such that the IFU 202 can restore the checkpoint register to an appropriate state in the event that any outstanding conditional branch instruction is mispredicted. Accordingly, the number of bits required for the recovery buffer 218 equals N*M*C, where N is the number of bits in the GHR (and thus the number of bits in each checkpoint register), M is the number of entries in the recovery buffer 218, and C is the number of checkpoint registers. Thus, in the case where N equals 8, M equals 16, and C equals 3, the recovery buffer 218 requires 384 bits.

[0080] Due to the fairly large amount of copying of information between the shift register (e.g., GHR) and the checkpoint register, checkpointing the shift register by storing a copy of the shift register after multiple checkpoint trigger events is inefficient. Specifically, in the clock cycle in which a checkpoint trigger event occurs but the shift register is not updated (e.g., when an instruction is sent to the execution unit for execution but the instruction is not a conditional branch instruction), the first checkpoint will equal the shift register. Even in the clock cycle in which a checkpoint trigger event occurs and the shift register (e.g., GHR 102) is updated (e.g., when a conditional branch instruction is sent to the execution unit for execution), the first checkpoint will differ from the shift register (e.g., GHR 102) by only one data element (e.g., bit).

[0081] Accordingly, the present disclosure provides efficient methods and systems for checkpointing a shift register (e.g., GHR) using the copying between the shift register and the checkpoint. In these methods, the primary shift register is extended to record a longer history, and a record of updates to the primary shift register is maintained in a separate update history shift register and used to determine which bits of the extended shift register describe the current state of the primary shift register and any checkpoint state of the primary shift register.

[0082] Figures 6 - 12 Describe a first embodiment for checkpointing the primary shift register. In this embodiment, rather than storing a full copy of the primary shift register for each checkpoint, as described above with reference to Figures 2 - 5(C) the primary shift register is extended to include additional or extra data positions (e.g., bits) for each checkpoint, and a record of whether an update was made to the primary shift register for each of the C previous checkpoint trigger events is maintained in a separate update history shift register, where C is the number of checkpoints. The current state of the primary shift register and the checkpoint can then be identified from the extended shift register and the update history shift register.

[0083] Figure 6 An example structure of the extended shift register 602 and the update history shift register 604 is shown. In this example, the main shift register is the GHR, but it will be apparent to those skilled in the art that the methods and principles described herein can equally be applied to checkpoint operations on other shift registers.

[0084] The extended shift register 602 includes N + C data positions 606 to 626, where N is the number of data positions in the main shift register, and C is the number of checkpoints. Accordingly, the extended shift register 602 includes data positions 606 to 620 for each data position in the main shift register and additional data positions 622 to 626 for each checkpoint. The extended shift register 602 is updated as described above with respect to Figures 1(A) to 1(D) the same. In particular, when a new data element is received at the extended shift register 602, the data elements in the extended shift register 602 are shifted by one data position, and the new data element is inserted into the first data position. For example, if a new data element arrives, the data elements at data positions 606 to 624 are shifted to data positions 608 to 626 respectively, and the new data element is inserted into the first data position 606.

[0085] The data positions 606 to 626 of the extended shift register 602 are divided into two subsets 628 and 630. The first subset 628 includes N data positions that hold the most recent data elements (i.e., the data elements most recently added to the main shift register) and represents the current state of the main shift register (e.g., the GHR). The second subset 630 includes C data positions that hold the earliest data elements and is combined with the update history shift register 604 to be used to identify the checkpoints of the main shift register.

[0086] For example, in the case where the main shift register is an 8-bit GHR (N = 8) that is to be checkpointed three times (C = 3), the extended shift register 602 includes 11 bits that represent 11 most recently predicted conditional branch results. The first subset 628 of the data positions of the extended shift register 602 includes 8 most recently predicted conditional branch results, and the second subset 630 of the data positions of the extended shift register 602 includes 3 earliest predicted conditional branch results (i.e., the results predicted the longest time ago).

[0087] The update history shift register 604 is a shift register including C data positions 632 to 636, where C is the number of checkpoints. Each data position includes information indicating whether the extended shift register 602 was updated prior to a certain number of checkpoint trigger events. In particular, the first data position 632 includes information indicating whether the extended shift register 602 was updated after the last checkpoint trigger event; the second data position 634 includes information indicating whether the extended shift register 602 was updated two checkpoint trigger events prior; and so on.

[0088] For example, in the case where the main shift register is a GHR that is to be checkpointed three times (C = 3), the update history shift register 604 includes three bits indicating which of the last three instructions sent to the execution unit were branch instructions. In particular, the first bit 632 indicates whether the last instruction sent to the execution unit for execution was a conditional branch instruction (and thus the result was predicted and the extended shift register 602 was updated); the second bit 634 indicates whether the second-to-last instruction sent to the execution unit for execution was a conditional branch instruction (and thus the result was predicted and the extended shift register 602 was updated); and the third bit 636 indicates whether the third-to-last instruction sent to the execution unit for execution was a conditional branch instruction (and thus the result was predicted and the extended shift register 602 was updated).

[0089] Figure 7 An example method 700 for updating the extended shift register 602 and the update history shift register 604 that can be performed by update logic (not shown) each clock cycle is shown. Method 700 begins at block 701, where the update logic determines whether a checkpoint trigger event has occurred. In the case where the main shift register is a GHR, the checkpoint trigger event can be when an instruction is sent to the execution unit for execution. However, it will be apparent to those skilled in the art that other checkpoint trigger events can be used depending on the purpose and use of the shift register. If it is determined that the checkpoint trigger event has occurred, then method 700 proceeds to block 702. However, if it is determined that the checkpoint trigger event has not occurred, then method 700 ends.

[0090] At block 702, the update logic determines whether the extended shift register was updated during the current clock cycle. This can include determining whether there is a new data element shifted onto the extended shift register 602. In the case where the main shift register is a GHR, then determining whether the extended shift register was updated can include determining whether the result of a conditional branch instruction was predicted (i.e., whether the instruction sent to the instruction unit was a conditional branch instruction).

[0091] If it is determined that the extended shift register 602 is not updated in the current clock cycle, the method proceeds to block 704, where data is shifted onto the update history shift register 604 to indicate that the extended shift register 602 is not updated. In some cases, a "0" indicates that the extended shift register 602 is not updated, while a "1" indicates that the extended shift register 602 is updated. In these cases, at block 704, a "0" is shifted onto the update history shift register 604. No change is made to the extended shift register 602. For example, if the main shift register is the GHR and the extended shift register 602 and the update history shift register 604 are as shown in FIG. 8(A), then if no branch is predicted in the current clock cycle (and thus there is no update to the extended shift register 602), a "0" is shifted onto the update history shift register 604, as shown in FIG. 8(B). In particular, the data elements / information in bits 0 and 1 of the update history shift register 604 are shifted to bits 1 and 2 respectively, and a "0" is inserted in bit 0.

[0092] However, if it is determined that the extended shift register 602 is updated in the current clock cycle, method 700 proceeds to blocks 706 and 708, where data is shifted onto the update history shift register 604 to indicate that the extended shift register is updated, and the extended shift register 602 is updated to include a new data element (e.g., the prediction result of a conditional branch instruction). In some cases, a "0" indicates that the extended shift register is not updated, while a "1" indicates that the extended shift register is updated. In these cases, at block 706, a "1" is shifted onto the update history shift register 604. For example, if the main shift register is the GHR and the extended shift register 602 and the update history shift register 604 are as shown in FIG. 8(B), and the branch is predicted to be not taken, then a "1" is shifted onto the update history shift register 604 and a "0" is shifted onto the extended shift register 602, as shown in FIG. 8(C). Similarly, if the main shift register is the GHR and the extended shift register 602 and the update history shift register 604 are as shown in FIG. 8(C), and the branch is predicted to be taken, then a "1" is shifted onto the update history shift register 604 and a "1" is shifted onto the extended shift register 602, as shown in FIG. 8(D).

[0093] As mentioned above, checkpoints of the main shift register (e.g., the GHR) can be obtained from the update history shift register 604 and the extended shift register 602. In particular, checkpoint generation logic (not shown) is configured to obtain each checkpoint by selecting a subset of data locations 606 to 626 in the extended shift register 602 based on the information stored in the update history shift register 604.

[0094] For example, the checkpoint generation logic can be configured to select a first subset 628 of the slave data positions of the data positions 606 to 626 that is either not offset, offset by one or more than one data position, based on the information stored in the update history shift register 604. The offset for a particular checkpoint is based on the number of relevant data positions (e.g., bits) of the update history shift register 604 that indicate an update to the extended shift register 602 in the corresponding clock cycle.

[0095] The relevant data positions (e.g., bits) of the update history shift register 604 for a checkpoint are based on the level or number of the checkpoint. In particular, the relevant data positions (e.g., bits) of the update history shift register 604 for a checkpoint are the data positions (e.g., bits) up to and including the level of the checkpoint. As described above, each checkpoint represents the data elements or values of the master shift register (e.g., GHR) prior to a predetermined number of checkpoint trigger events. The level or number of a checkpoint is equal to the predetermined number of checkpoint trigger events. For example, checkpoint 1 represents the value or data element of the master shift register (e.g., GHR) prior to one checkpoint trigger event, so checkpoint 1 is a level 1 checkpoint; and checkpoint 3 represents the value or data element of the master shift register (e.g., GHR) prior to three checkpoint trigger events, so checkpoint 3 is a level 3 checkpoint.

[0096] Accordingly, the offset for a particular checkpoint is based on the number of data positions (e.g., bits) of the update history shift register 604 up to and including the level of the checkpoint. For example, for a level 1 checkpoint (e.g., checkpoint 1), only the first data position of the update history shift register 604 is relevant, and for a level 2 checkpoint (e.g., checkpoint 2), only the first two data positions of the update history shift register 604 are relevant. Thus, for a level 1 checkpoint (e.g., checkpoint 1), the offset is determined from the information in the first data position 632 of the update history shift register 604; and for a level 2 checkpoint (e.g., checkpoint 2), the offset is determined from the information in the first two bits of the update history shift register 604.

[0097] The offset thus equals the number or count of relevant data positions of the update history shift register 604 that indicate that the extended shift register 602 was updated in the same clock cycle as the corresponding checkpoint trigger event. For example, if only one relevant position of the update history shift register 604 includes information indicating that the extended shift register 602 was updated (e.g., set to "1") in the same clock cycle as the corresponding checkpoint trigger event, then the subset of data positions of the checkpoint has moved one data position relative to the first subset 628 of data positions, such that the checkpoint includes the first data position in the second subset 630 of data positions and N - 1 data positions from the first subset 628 of data positions; and if only two relevant data positions of the update history shift register 604 include information indicating that the extended shift register 602 was updated in the same clock cycle as the corresponding checkpoint trigger event, then the subset of data positions of the checkpoint has moved two data positions relative to the first subset 629 of data positions, such that the checkpoint includes the first two data positions from the second subset 630 of data positions and N - 2 data positions from the first subset 628 of data positions.

[0098] Figures 9 - 11 illustrates an example method for using these principles to generate first, second, and third checkpoints from the extended shift register 602 and the update history shift register 604, as further shown in Figure 12 As shown. In particular, Figure 9 illustrates an example method for generating checkpoint 1 from the extended shift register 602 and the update history shift register 604 described above. Since checkpoint 1 is a level 1 checkpoint, it is only the first bit (bit 0 or data position 632) of the update history shift register 604 that is relevant when determining the offset.

[0099] Method 900 begins at block 902, where it is determined whether the first bit (bit 0 or data position 632) of the update history shift register 604 is set. In the case where "1" is used to indicate that the extended shift register 602 was updated, then determining whether the first bit of the update history shift register 604 is set may include determining whether the first bit is set to 1.

[0100] If it is determined that the first bit of the update history shift register 604 is not set, the method 900 proceeds to block 904, where checkpoint 1 is set to data positions 0 to N-1 (the first subset 628 of data positions) of the extended shift register 602. If, however, it is determined that the first bit of the update history shift register 604 is set, the method 900 proceeds to block 906, where checkpoint 1 is set to data positions 1 to N (the first data position from the second subset 630 + the next N-1 data positions of the first subset 628) of the extended shift register 602. Accordingly, in this case, checkpoint 1 is offset by one data position from the first subset of data positions.

[0101] For example, if the main shift register is an 8-bit GHR (N=8) that will be checkpointed 3 times (C=3) and the extended shift register 602 and the updated history shift register 604 are as follows: Figure 12 As shown, according to Figure 9 900, checkpoint 1 (indicated by numeral 1202) will be equal to the first 8 bits (bits 0 through 7) of the extended shift register 602 because the first bit of the update history shift register 604 is not set.

[0102] Figure 10 An example method 1000 is shown for generating a checkpoint 2 from the extended shift register 602 and the update history shift register 604 described above. The method 1000 begins at block 1002, where it is determined whether the first two bits of the update history shift register 604 are both set. If it is determined that the first two bits of the update history shift register 604 are both set, the method 1000 proceeds to block 1004, where a checkpoint 2 is generated from the data elements at data positions 2 to N+1. Accordingly, in this case, the checkpoint 2 is offset from the first subset 628 of data positions by two data positions.

[0103] However, if it is determined that neither of the first two bits of the update history shift register is set, the method 1000 proceeds to block 1006, where it is determined whether one of the first two bits of the update history shift register 604 is set. If it is determined that one of the first two bits of the update history shift register is set, the method 1000 proceeds to block 1008, where a checkpoint 2 is generated from the data elements at data positions 1 through N. Accordingly, in this case, the checkpoint 2 is offset from the first subset 628 of data positions by one data position.

[0104] However, if it is determined that neither of the first two bits of the update history shift register 604 is set, method 1000 proceeds to block 1010, where checkpoint 2 is generated from the data elements at data positions 0 to N-1 (i.e., the first subset 628 of data positions). Accordingly, in this case, checkpoint 2 is offset by zero data positions from the first subset 628 of data positions.

[0105] For example, if the main shift register is an 8-bit GHR (N = 8) that is to be checkpointed 3 times (C = 3) and the extended shift register 602 and the update history shift register 604 are as Figure 12 shown, then according to Figure 10 method 1000, checkpoint 2 (indicated by the number 1204) will be equal to bits 1 to 8 of the extended shift register 602 because only one of the first two bits of the update history shift register 604 is set.

[0106] Figure 11 FIG. 11 shows an example method 1100 for generating checkpoint 3 from the extended shift register 602 and the update history shift register 604 described above. Method 1100 begins at block 1102, where it is determined whether all of the first three bits of the update history shift register are set. If it is determined that all of the first three bits of the update history shift register are set, method 1100 proceeds to block 1104, where checkpoint 3 is generated from the data elements at data positions 3 to N+2. Accordingly, in this case, checkpoint 3 is offset by three data positions from the first subset 628 of data positions.

[0107] However, if it is determined that not all of the first three bits of the update history shift register 604 are set, method 1100 proceeds to block 1106, where it is determined whether two of the first three bits of the update history shift register are set. If it is determined that two of the first three bits of the update history shift register 604 are set, method 1100 proceeds to block 1108, where checkpoint 3 is generated from the data elements at data positions 2 to N+1. Accordingly, in this case, checkpoint 3 is offset by two data positions from the first subset 628 of data positions.

[0108] However, if it is determined that fewer than two of the first three bits of the update history shift register 604 are set, method 1100 proceeds to block 1110, where it is determined whether one of the first three bits of the update history shift register 604 is set. If it is determined that one of the first three bits of the update history shift register 604 is set, method 1100 proceeds to block 1112, where checkpoint 3 is generated from the data elements at data positions 1 to N. Accordingly, in this case, checkpoint 3 is offset by one data position from the first subset 628 of data positions.

[0109] However, if it is determined that none of the first three bits of the update history shift register 604 are set, method 1100 proceeds to block 1114, where checkpoint 3 is generated from the data elements at data positions 0 to N-1 (i.e., the first subset 628 of data positions). Accordingly, in this case, checkpoint 3 is offset by zero data positions from the first subset 628 of data positions.

[0110] For example, if the main shift register is an 8-bit GHR (N = 8) that is to be checkpointed 3 times (C = 3) and the extended shift register 602 and the update history shift register 604 are as Figure 12 shown, then according to Figure 11 method 1100, checkpoint 3 (indicated by the number 1206) will be equal to bits 1 to 8 of the extended shift register 602 because only one of the first two bits of the update history shift register 604 is set.

[0111] When the extended shift register 602 and the update history shift register 604 are used to checkpoint a main shift register (e.g., GHR), then in order to be able to restore the checkpoint to a previous time point (e.g., after a branch misprediction), instead of storing copies of all checkpoints in the restore buffer as described above with respect to Figure 5(A)-5(C) , only the update history shift register 604 and the extended shift register 602 for each relevant time point (e.g., before a conditional branch instruction is issued to the execution unit) are stored in the restore buffer.

[0112] Now referring to Figure 13(A)-13(C) which shows an example restore buffer 1300, the example restore buffer 1300 is used to store the update history shift register 604 and the extended shift register 602 at a particular time point (e.g., before a conditional branch instruction is sent to the execution unit for execution) to allow the main shift register (e.g., GHR) and the checkpoint to be restored to that time point (e.g., after a misprediction of a conditional branch instruction). Like Figure 5(A)-5(C) restore buffer 218, restore buffer 1300 is implemented as a FIFO circular buffer including data positions 13020 to 13024, where each data position is used to store a copy of the update history shift register 604 and the extended shift register 602 at a particular time point (e.g., before a conditional branch instruction is issued to the execution unit); a read pointer 1304 pointing to the data positions 13020 to 13024 containing the update history shift register 604 and the extended shift register 602 for the earliest time point (e.g., corresponding to the time point before the earliest outstanding conditional branch instruction is issued to the execution unit); and a write pointer 1306 pointing to the next data position 13020 to 13024 to be written.

[0113] Whenever an update trigger event occurs (e.g., the result of predicting a conditional branch instruction by the IFU 202), the update logic (not shown) pushes the information in the update history shift register 604 and the data elements in the extended shift register 602 onto the recovery buffer 1300. In particular, the information in the update history shift register 604 and the data elements stored in the extended shift register 602 are written to the data location indicated by the write pointer 1306, and then the write pointer 1306 is incremented to point to the next data location. For example, if the recovery buffer 1300 is as shown in FIG. 13(A), when an update trigger event occurs (e.g., the result of predicting conditional branch instruction D by the IFU 202), then the information in the update history shift register 604 and the data elements stored in the extended shift register 602 are stored at the data location pointed to by the write pointer 1306, and then the write pointer 1306 is incremented to point to the next data location, as shown in FIG. 13(B).

[0114] Whenever the update logic (not shown) receives a removal trigger (e.g., information from the execution unit (EXU) indicating that a branch instruction has been executed), the update logic pops the data elements in the data locations 13020 to 13024 pointed to by the read pointer 1304 from the recovery buffer 1300. This can be done by incrementing the read pointer 1304 to point to the next data locations 13020 to 13024. For example, if the recovery buffer 1300 is as shown in FIG. 13(B), when a removal trigger is received (e.g., information from the EXU indicating that branch instruction A has been executed), then the read pointer 1304 is incremented to point to the next data location, as shown in FIG. 13(C).

[0115] If the recovery logic (not shown) receives a recovery trigger (e.g., an indication that a misprediction has occurred), then the recovery logic replaces the information in the update history shift register 604 and the data elements in the extended shift register 602 with the data from the top data location (the data location pointed to by the read pointer 1304), and then invalidates the entries in the recovery buffer 1300.

[0116] In this example, each data location in the recovery buffer 1300 has C bits (for the update history shift register) + N + C bits (for the extended shift register). In the case where there are M data locations in the recovery buffer, the total number of bits in the recovery buffer is M * (2C + N). So in the case where C is 3, N is 8, and M is 16, the total number of bits in the recovery buffer 1300 is 224. Accordingly, compared with using the checkpoint operation method described above with respect to FIGS. 1 to 5(C), using the update history shift register and the extended shift register to perform checkpoint operation on the shift register provides a significant cost savings in terms of the storage of the recovery buffer 1300.

[0117] It will be apparent to those skilled in the art that the structure of the recovery buffer 1300 in Figure 13(A)-13(C) is merely an example, and the recovery buffer can take other forms (e.g., recovery can be implemented as an indexed buffer or a table).

[0118] Now refer to Figures 6 to 13(C) showing an example hardware structure 1400 for implementing the shift register checkpoint method described above with respect to Figure 14 . The hardware structure includes the extended shift register 602, the update history shift register 604, and the recovery buffer 1300 described above.

[0119] The hardware structure further includes update logic 1402 for updating the extended shift register 602, the update history shift register 604, and the recovery buffer 1300 as described above. In particular, the update logic is configured to receive new data elements of the main shift register (e.g., GHR) and update the extended shift register 602, the update history shift register 604, and the recovery buffer 1300 accordingly, as described with respect to Figure 7 , 8, and 13. For example, in the case where the shift register being checkpointed is the GHR, the new data element to be added to the GHR can be the predicted result of a conditional branch instruction.

[0120] The hardware structure 1400 further includes checkpoint generation logic 1404 for generating a checkpoint of the extended shift register 602 and the update history shift register 604 and / or the main shift register as described above with respect to Figures 9 - 11 . For example, the checkpoint generation logic 1404 can be configured to implement one or more methods described with respect to Figures 9 to 11 .

[0121] The hardware structure 1400 may further include recovery logic 1406 for replacing the information in the extended shift register 602 and the update history shift register 604 with the information stored in the recovery buffer 1300 when a recovery trigger event (e.g., misprediction of a conditional branch instruction) occurs, as described above with respect toFigure 13(A)-13(C) as described above

[0122] Figures 15 to 26(B) Describe a second embodiment for checkpointing a shift register. The second embodiment uses an update history shift register to save a track of which of the previous C checkpoint trigger events also resulted in an update to the main shift register, similar to the first embodiment (as described above with respect to Figures 6 to 14 as described). And an extended shift register. However, instead of the extended shift register including an additional data location (e.g., bit) for each checkpoint, the extended shift register is implemented as a circular buffer having M + C additional data locations, where M is the number of different snapshots of the shift register and checkpoints that can be restored (e.g., the number of conditional branch instructions that can be outstanding or in-flight at any given time). Accordingly, in a scenario where there can be at most 13 conditional branch instructions outstanding or in-flight (M = 13) and three checkpoints (C = 3) at any given time, the circular buffer 16 includes 16 additional data locations.

[0123] Figure 15 Illustrate an example update history shift register 1504 and circular buffer 1502 for checkpointing a main shift register. Figure 15 The update history shift register 1504 is the same as the update history shift register 604 described above with respect to Figures 6 to 13(C) as described. In particular, it has bits 1506 to 1510 for each checkpoint; and in each clock cycle when a checkpoint trigger event occurs, information (e.g., "1" or "0") is pushed onto the update history shift register 1504 indicating whether the circular buffer 1502 was updated during that clock cycle. When the checkpoint trigger event does not occur in each clock cycle, the update history shift register 1504 is not updated during the clock cycles when the checkpoint trigger event does not occur.

[0124] The circular buffer 1502 includes M + C + N data locations 1512 - 1558 for saving the M + C + N most recent data elements (e.g., most recently predicted branch instruction results) added to the shift register. As described above, M is the number of different snapshots of the main shift register and checkpoints that can be restored (e.g., the maximum number of branch instructions that can be outstanding or in-flight at any given time), C is the number of checkpoints, and N is the size of the main shift register being checkpointed.

[0125] The next data location to be written to the circular buffer 1502 is identified by a top pointer 1560. In particular, the top pointer 1560 includes a plurality of bits 1562 to 1570 that together form an index identifying a particular data location 1512 to 1558 of the circular buffer 1502. For example, inFigure 15 In this case, the index formed by bits 1562 to 1570 of the top pointer 1560 is binary "00011", which is equivalent to the decimal value 3. Thus, the top pointer 1560 points to data location 3 (identified as the number 1518). When a new data element is received for insertion into the shift register, the data element is added to the data location identified by the top pointer 1560, and then the top pointer 1560 is decremented.

[0126] Figure 16(A)-18(B) Examples are shown of how the update history shift register 1504 and the circular buffer 1502 can be updated after a checkpoint trigger event occurs (e.g., when an instruction is sent to the execution unit for execution). In these examples, the main shift register is an 8-bit GHR (N = 8) that is checkpointed three times (C = 3); the GHR is updated with a "1" when a branch is predicted to be taken and with a "0" when a branch is predicted not to be taken; and the update history shift register 1504 is updated with a "1" when a conditional branch instruction is sent to the execution unit (and thus a branch is predicted) and with a "0" when an unconditional branch instruction is sent to the execution unit (and thus no branch is predicted).

[0127] FIG. 16(A) shows the update history shift register 1504 and the circular buffer 1502 when the IFU 202 sends a non-branch instruction to the execution unit for execution. This causes a "0" to be pushed onto the update history shift register 1504 as shown in FIG. 16(B) to indicate that the circular buffer 1502 is not updated for this instruction. The circular buffer 1502 and the top pointer are not updated.

[0128] FIG. 17(A) shows the update history shift register 1504 and the circular buffer 1502 when the IFU 202 sends a conditional branch instruction predicted to not be taken to the execution unit for execution. This causes a "1" to be pushed onto the update history shift register 1504 to indicate that the circular buffer 1502 is updated in this clock cycle; a "0" is inserted into data location 3 of the circular buffer 1502 to indicate that the branch is predicted not to be taken; and the top pointer 1560 is decremented to "00010" (2), as shown in FIG. 17(B).

[0129] FIG. 18(A) shows the update history shift register 1504 and the circular buffer 1502 when the IFU 202 sends a conditional branch instruction predicted to be taken to the execution unit for execution. This causes a "1" to be pushed onto the update history shift register to indicate that the circular buffer 1502 is updated in this clock cycle; a "1" is to be inserted into data location 3 of the circular buffer 1502 to indicate that the branch is predicted to be taken; and the top pointer 1560 is decremented to "00010" (2), as shown in FIG. 18(B).

[0130] Refer back Figure 15 , in addition to indicating the next data position to be written in the circular buffer, the top pointer 1560 also identifies the active data positions A1 to A of the circular buffer 11 . The active data positions A1 to A 11 are the data positions of the circular buffer from which the current values of the main shift register and the checkpoint can be determined. The active data positions A1 to A 11 are typically N + C data positions before the data position indicated or pointed to by the top pointer 1560. In particular, if the data position indicated or pointed to by the top pointer is Y, the active data positions are data positions Y + 1 to Y + N + 3. For example, when the top pointer points to data position 3 (indicated by reference numeral 1420), N = 8 and C = 3, then the active data positions A1 to A 11 are data positions 4 to 14 (indicated by reference numerals 1520 to 1540).

[0131] The active data positions A1 to A 11 can be understood as being similar to the data positions 606 to 626 of the extended shift register 602 described above with respect to Figures 6 to 13(C) . In particular, like the data positions 606 to 626 of the extended shift register 602, the active data positions A1 to A 11 are divided into two subsets 1572 and 1574. The first subset 1572 is the N active data positions A1 to A8 that hold the latest data elements (i.e., the data elements most recently added to the circular buffer) and represent the current state of the main shift register (e.g., GHR). The second subset 1574 is the next C data positions that hold the next C latest data elements

[0132] For example, in the case where the main shift register is an 8-bit GHR (N = 8) that is to be checkpointed three times (C = 3), there are 11 active data positions A1 to A 11 that represent 11 most recently predicted branch outcomes. The first subset 1572 of the active data positions includes 8 most recently predicted branch outcomes, and the second subset 1574 of the active data positions includes 3 next most recently predicted outcomes

[0133] Accordingly, in the same way as Figures 6 to 13(C) the update history shift register 604 is used to identify the current checkpoint value from the data positions 606 to 626 of the extended shift register 602 of Figures 6 to 14 , the update history shift register 1504 can be used to identify from the active data positions A1 to A 11Identify the current checkpoint value. In particular, the update history shift register 1504 identifies and / or selects the active data locations A1 to A that provide the current value of each checkpoint 11 .

[0134] For example, the checkpoint generation logic can be configured to select, based on the information stored in the update history shift register 1504, the active data locations A1 to A that are not offset, offset by one or more data locations, from a first subset 1572 of the active data locations 11 The subset for a particular checkpoint is based on the number of relevant data locations (e.g., bits) of the update history shift register 604 that indicate an update to the circular buffer 1502 in the same clock cycle as the corresponding checkpoint trigger event.

[0135] As described above with respect to Figures 6 to 13(C) The relevant data locations (e.g., bits) of the update history shift register 1504 with respect to a checkpoint are based on the level or number of the checkpoint. In particular, the relevant data locations (e.g., bits) of the update history shift register 1504 with respect to a checkpoint are the data locations (e.g., bits) up to and including the level of the checkpoint. As described above, each checkpoint represents the data elements or values of the main shift register (e.g., GHR) a predetermined number of checkpoint trigger events ago. The level or number of a checkpoint is equal to the predetermined number of checkpoint trigger events. For example, checkpoint 1 represents the value or data element of the main shift register (e.g., GHR) one checkpoint trigger event ago, so checkpoint 1 is a level 1 checkpoint; and checkpoint 3 represents the value or data element of the main shift register (e.g., GHR) three checkpoint trigger events ago, so checkpoint 3 is a level 3 checkpoint.

[0136] Accordingly, the offset for a particular checkpoint is based on the number of data locations (e.g., bits) of the update history shift register 1504 up to and including the level of the checkpoint. For example, for a level 1 checkpoint (e.g., checkpoint 1), only the first data location of the update history shift register 1504 is relevant, and for a level 2 checkpoint (e.g., checkpoint 2), only the first two data locations of the update history shift register 1504 are relevant. Thus for a level 1 checkpoint (e.g., checkpoint 1), the offset is determined from the information in the first data location 1506 of the update history shift register 1504; and for a level 2 checkpoint (e.g., checkpoint 2), the offset is determined from the information in the first two data locations of the update history shift register 1504.

[0137] The offset is then equal to the number or count of the relevant data positions of the update history shift register 1504 that includes information indicating that the circular buffer 1502 was updated (e.g., set to "1") in the clock cycle of the corresponding checkpoint trigger event, and then a subset of the active data positions with respect to the checkpoint is shifted by one data position relative to the first subset 1572 of the active data positions, such that the checkpoint includes the first data position in the second subset 1574 of the active data positions and N - 1 data positions from the first subset 1572 of the active data positions; and if only two relevant data positions of the update history shift register 1504 include information indicating that the circular buffer 1502 was updated (e.g., set to "1") in the clock cycle of the corresponding checkpoint trigger event, then the subset of the active data positions of the checkpoint is shifted by two data positions relative to the first subset 1572 of the active data positions, such that the checkpoint includes the first two data positions from the second subset 1574 of the active data positions and N - 2 data positions from the first subset 1572 of the active data positions.

[0138] Figures 19 - 21 Illustrates an example method for generating first, second, and third checkpoints from the circular buffer 1502 and the update history shift register 1504 using the principles described above with respect to the extended shift register 602 and the update history shift register 604. In particular, Figure 19 Illustrates an example method 1900 for generating checkpoint 1 from the circular buffer 1502 and the update history shift register 1504 described above. Since checkpoint 1 is a level 1 checkpoint, it is simply the first bit (bit 0 or data position 1506) of the update history shift register 1504 used to determine the update history of the relevant bits from the circular buffer 1502.

[0139] Method 1900 begins at block 1902, where it is determined whether the first bit (bit 0 or data position 1506) of the update history shift register 1504 is set. Where "1" is used to indicate that the circular buffer 1502 was updated in the clock cycle of the corresponding checkpoint trigger event, determining whether the first bit of the update history shift register 1504 is set may include determining whether the first bit is set to 1.

[0140] If it is determined that the first bit of the update history shift register 1504 is not set, then method 1900 proceeds to block 1904, where checkpoint 1 is set to the data elements in the active data positions A1 to A N (the first subset 1572 of the active data positions). However, if it is determined that the first bit of the update history shift register 1504 is set, then method 1900 proceeds to block 1906, where checkpoint 1 is set to the data elements in the active data positions A2 to A N+1Data elements in (the first active data position from the second subset 1574 + the next N - 1 active data positions of the first subset 1572). Accordingly, in this case, checkpoint 1 is offset from the first subset of active data positions by one data position.

[0141] For example, if the main shift register is an 8 - bit GHR (N = 8) to be checkpointed 3 times (C = 3) and the circular buffer 1502 and the update history shift register 1504 are as Figure 22 shown, then according to Figure 19 Method 1900, checkpoint 1 (indicated by the number 2202) will be equal to the data in the active data bits A2 to A9 of the circular buffer 1502 because the first bit of the update history shift register 1504 is set.

[0142] Figure 20 Figure 2000 shows an example method for generating checkpoint 2 from the circular buffer 1502 and the update history shift register 1504 described above. Method 2000 starts at block 2002, where it is determined whether the first two bits of the update history shift register 1504 are both set. If it is determined that the first two bits of the update history shift register 1504 are both set, then method 2000 proceeds to block 2004, where checkpoint 2 is generated from the data elements at the active data positions A3 to A N+2 above. Accordingly, in this case, checkpoint 2 is offset from the first subset of active data positions by two data positions.

[0143] However, if it is determined that neither of the first two bits of the update history shift register 1504 is set, then method 2000 proceeds to block 2006, where it is determined whether one of the first two bits of the update history shift register is set. If it is determined that one of the first two bits of the update history shift register is set, then method 2000 proceeds to block 2008, where checkpoint 2 is generated from the data elements at the active data positions A2 to A N+1 above. Accordingly, in this case, checkpoint 2 is offset from the first subset of active data positions by one data position.

[0144] However, if it is determined that none of the first two bits of the update history shift register 1504 is set, then method 2000 proceeds to block 2010, where checkpoint 2 is generated from the data elements at the active data positions A1 to A N (i.e., the first subset 1572 of data positions). Accordingly, in this case, checkpoint 2 is offset from the first subset of active data positions by zero data positions.

[0145] For example, if the main shift register is an 8-bit GHR (N = 8) that is to be checkpointed 3 times (C = 3) and the circular buffer 1502 and the update history shift register 1504 are as Figure 22 shown, then according to Figure 20 method 2000, checkpoint 2 (indicated by the number 2204) will be equal to the active data positions A2 to A9 of the circular buffer 1502 because only one of the first two bits of the update history shift register 1504 is set.

[0146] Figure 21 FIG. shows an example method 2100 for generating checkpoint 3 from the circular buffer 1502 and the update history shift register 1504 described above. Method 2100 begins at block 2102, where it is determined whether all of the first three bits of the update history shift register 1504 are set. If it is determined that all of the first three bits of the update history shift register 1504 are set, then method 2100 proceeds to block 2104, where checkpoint 3 is generated from the data elements at the active data positions A4 to A N+3 above. Accordingly, in this case, checkpoint 3 is offset by three data positions from the first subset 1572 of the active data positions.

[0147] However, if it is determined that not all of the first three bits of the update history shift register 1504 are set, then method 2100 proceeds to block 2106, where it is determined whether two of the first three bits of the update history shift register 1504 are set. If it is determined that two of the first three bits of the update history shift register 1504 are set, then method 2100 proceeds to block 2108, where checkpoint 3 is generated from the data elements at the active data positions A3 to A N+2 above. Accordingly, in this case, checkpoint 3 is offset by two data positions from the first subset 1572 of the active data positions.

[0148] However, if it is determined that fewer than two of the first three bits of the update history shift register 1504 are set, then method 2100 proceeds to block 2110, where it is determined whether one of the first three bits of the update history shift register 1504 is set. If it is determined that one of the first three bits of the update history shift register 1504 is set, then method 2100 proceeds to block 2112, where checkpoint 3 is generated from the data elements at the active data positions A2 to A N+1 above. Accordingly, in this case, checkpoint 3 is offset by one data position from the first subset 1572 of the active data positions.

[0149] However, if it is determined that none of the first three bits of the update history shift register 1504 is set, then method 2100 proceeds to block 2114, where checkpoint 3 is generated from the data elements at the active data positions A1 to AN Checkpoint 3 is generated for data elements on (i.e., the first subset 1572 of the active data location).

[0150] For example, as Figure 22 shown, if the main shift register is an 8-bit GHR (N = 8) to be checkpointed 3 times (C = 3) and the circular buffer 1502 and the update history shift register 1504 are as shown, then according to Figure 21 method 2100, checkpoint 3 (indicated by the number 2206) will be generated from bits A3 to A of the circular buffer 1502 10 , because only two of the first three bits of the update history shift register 1504 are set.

[0151] As described above with respect to Figures 15 to 22 using the circular buffer 1502 and the update history shift register 1504 to perform checkpoint operations on the main shift register (e.g., GHR) significantly reduces the amount of data that needs to be stored to be able to restore the main shift register (e.g., GHR) and the checkpoint to a previous time point (e.g., after a misprediction of a conditional branch instruction). Specifically, instead of storing copies of all checkpoints in the restore buffer at each relevant time point (e.g., before each uncompleted conditional branch instruction is issued to the execution unit) as described above with respect to Figure 5(A)-5(C) , only the update history shift register 1504 and the top pointer 1560 for each relevant time point (e.g., before each uncompleted conditional branch instruction is issued to the execution unit) are stored in the restore buffer. Since the circular buffer 1502 contains N + M + C predicted results, it contains sufficient predicted results: for any uncompleted conditional branch instruction, the main shift register (e.g., GHR) and the relevant checkpoint can be restored from the current circular buffer 1502 itself and there is no need to store a copy of the circular buffer 1502.

[0152] Figure 23(A)-23(C)Shows a first example of a recovery buffer 2300 for restoring a main shift register and a checkpoint to a previous point in time. In this example, the recovery buffer 2300 is configured to store information in the updated history shift register 1504 and the value of the top pointer 1560 for a relevant point in time (e.g., before a conditional branch instruction is sent to the execution unit for execution). Similar to the recovery buffers 218 and 1300 of FIGS. 5(A)-(C) and 13(A)-(C), the recovery buffer 2300 is implemented as a FIFO circular buffer having a plurality of data locations 23020 to 23024, where each data location is used to store a copy of the information in the updated history shift register 1504 and the top pointer 1560 for a specific point in time (e.g., before a conditional branch instruction is sent to the execution unit for execution); a read pointer 2304 pointing to the data location 23020 to 23024 containing the information in the updated history shift register and the value of the top pointer for the earliest relevant point in time (e.g., before the earliest pending conditional branch instruction is sent to the execution unit for execution); and a write pointer 2306 pointing to the next data location 23020 to 23024 to be written.

[0153] Whenever an update trigger event occurs (e.g., a conditional branch instruction is issued to the execution unit), the information in the updated history shift register 1504 and the value of the top pointer 1560 are pushed onto the recovery buffer 2300. In particular, the information in the updated history shift register 1504 and the value of the top pointer 1560 are written to the data location indicated by the write pointer 2306, and then the write pointer 2306 is incremented to point to the next data location. For example, if the recovery buffer 2300 is as shown in FIG. 23(A), when an update trigger event occurs (e.g., conditional branch instruction D is sent to the execution unit for execution), then the information in the updated history shift register 1504 and the value of the top pointer 1560 are stored in the data location pointed to by the write pointer 2306, and then the write pointer 2306 is incremented to point to the next data location, as shown in FIG. 23(B).

[0154] Whenever a removal trigger event occurs (e.g., information indicating that a conditional branch instruction has been executed is received from the execution unit (EXU)), the data element in the data location 23020 to 23024 pointed to by the read pointer 2304 is popped from the recovery buffer 2300. This can be done by incrementing the read pointer 2304 to point to the next data location 23020 to 23024. For example, if the recovery buffer 2300 is as shown in FIG. 23(B), when a removal trigger event occurs (e.g., information indicating that branch instruction A has been executed is received from the EXU), then the read pointer 2304 is incremented to point to the next data location, as shown in FIG. 23(C).

[0155] When a recovery trigger event occurs (e.g., an indication that a misprediction has occurred is received), the information in the update history shift register 1504 and the value of the top pointer 1560 are replaced with data from the top data location (the data location pointed to by the read pointer 2304), and the entries in the recovery buffer 2300 are invalidated. This causes the active data locations of the circular buffer 1502 to change, such that different sets of data locations of the circular buffer 1502 are used to determine the current values of the main shift register (e.g., the GHR) and the checkpoint. In other words, it moves the active data locations back to what they were at a previous time point (e.g., before a conditional branch instruction was issued to the execution unit for execution).

[0156] In this example, each data location in the recovery buffer 2300 has C bits (for the update history shift register) + K bits (for the top pointer). In the case where there are M data locations in the recovery buffer, the total number of bits in the recovery buffer is then M * (C + K). So in the case where C is 3, K is 5, and M is 16, the total number of bits to implement the recovery buffer 2300 is 128. Accordingly, compared to checkpointing the shift register using the method described above with respect to FIGS. 1 to 5(C) or the method described above with respect to Figures 6 to 13(C) the method described above, this provides a significant cost savings in terms of the storage of the recovery buffer 2300.

[0157] In other examples, instead of storing the value of the top pointer 1560 in the recovery buffer at a specific time point, information that enables the top pointer 1560 to be restored to a specific time point can be stored in the recovery buffer. As described above, the top pointer 1560 is adjusted (e.g., decremented) whenever a new element is added to the circular buffer 1502. For example, in the case where the main shift register is the GHR, whenever the result of a conditional branch instruction is predicted (e.g., whenever a conditional branch instruction is sent to the execution unit for execution), a new element will be added to the circular buffer 1502 (and thus the top pointer 1560 is updated). Accordingly, if the number of circular buffer updates (e.g., conditional branch instructions sent to the execution unit) that have occurred since a specific time point is known, the top pointer at that specific time can be generated by adjusting (e.g., incrementing) the top pointer 1560 by that number. For example, if two new elements are added to the circular buffer after a specific time point (e.g., after a specific instruction is sent to the execution unit), the top pointer has been decremented twice since that time point. Accordingly, the top pointer can be restored to that specific time point by incrementing the top pointer by two.

[0158] Using Figure 24(A)-24(C)This concept is illustrated by an example. In this example, the main shift register is the GHR that is updated after a conditional branch instruction (for which a prediction of whether the branch is taken or not is made) is sent to the execution unit for execution. As shown in FIG. 24(A), the updated history shift register 1504 is equal to "001", the top pointer 1560 is equal to "00011" (3), and the circular buffer 1502 is equal to "010100000100101100011101", meaning that the active data positions A0 to A 11 of the circular buffer 1502 are data positions 4 to 14.

[0159] If the IFU 202 subsequently sends a conditional branch instruction (instruction X) for which the branch is predicted to be taken to the execution unit for execution, then a "1" is pushed onto the updated history shift register 1504 to indicate that the circular buffer 1502 is updated in this clock cycle; a "1" is inserted into data position 3 of the circular buffer 1502 to indicate that the branch is predicted to be taken; and the top pointer 1560 is decremented by 1 to "00010" (2), as shown in FIG. 24(B).

[0160] If the IFU 202 subsequently sends a conditional branch instruction (instruction X+1) for which the branch is predicted not to be taken to the execution unit for execution, then a "1" is pushed onto the updated history shift register 1504 to indicate that the circular buffer 1502 is updated in this clock cycle; a "0" is inserted into data position 2 of the circular buffer 1502 to indicate that the branch is predicted not to be taken; and the top pointer 1560 is decremented by 1 to "00001" (1), as shown in FIG. 24(C).

[0161] If it is then determined that instruction X is mispredicted, the updated history shift register 1504 and the top pointer 1560 are restored to the time point before instruction X was sent to the execution unit for execution (i.e., the time point shown in FIG. 24(A)). Since two conditional branch instructions (instruction X and instruction X+1) have been sent to the execution unit since the time point shown in FIG. 24(A), the circular buffer 1502 has been updated twice and thus the top pointer 1560 has been decremented twice. The top pointer 1560 can thus be restored to the time point shown in FIG. 24(A) by incrementing the top pointer 1560 of "00001" (1) in FIG. 24(C) by 2 to set the top pointer 1560 back to "00011" (3). Accordingly, the top pointer 1560 can be restored to a specific time point by keeping track of the number of times the circular buffer is updated after that time point.

[0162] Figure 25(A)-25(C)Shows a second example of a recovery buffer 2500 for restoring a main shift register and a checkpoint to a previous point in time. In this example, the recovery buffer 2500 is configured to store the information in the update history shift register 1504 and an indication of whether the circular buffer 1502 was updated during that clock cycle at a specific point in time (e.g., before a control transfer instruction (CTI) - an instruction that changes the direction of a program (e.g., a branch instruction, a jump instruction) - is sent to the execution unit for execution). The indication of whether the circular buffer 1502 was updated may also be referred to herein as a circular buffer update indication. In the case where the main shift register is the GHR, the indication of whether the circular buffer 1502 was updated is set to indicate that the circular buffer 1502 was updated when a conditional branch instruction was sent to the execution unit (and thus a prediction of whether the branch was taken was made).

[0163] Similar to the recovery buffers 218, 1300, and 2300 of FIGS. 5(A)-(C), 13(A)-(C), and 23(A)-(C), Figure 25(A)-25(C) the recovery buffer 2500 is implemented as a FIFO circular buffer having a plurality of data locations 25020 to 25024, where each data location is for storing a copy of the information in the update history shift register 1504 at a specific point in time (e.g., before a control transfer instruction (CTI) such as a conditional branch instruction or a direct branch instruction is sent to the execution unit for execution) and an indication of whether the circular buffer was updated (e.g., whether the instruction sent to the execution unit was a conditional branch instruction); a read pointer 2504 pointing to the data location 25020 to 25024 that contains the information in the update history shift register and the circular buffer update indication for the earliest relevant point in time (e.g., before the earliest outstanding control transfer instruction is sent to the execution unit for execution); and a write pointer 2506 pointing to the next data location 25020 to 25024 to be written to.

[0164] Whenever an update trigger event occurs (e.g., a control transfer instruction, such as a conditional branch instruction or a jump instruction, is sent to the execution unit for execution), information in the update history shift register 1504 and an indication of whether the circular buffer 1502 is updated (e.g., whether the control transfer instruction is a conditional branch instruction) are pushed onto the recovery buffer 2500. In particular, when information in the update history shift register 1504 and an indication of whether the circular buffer 1502 is updated are written to the data location indicated by the write pointer 2506, the write pointer 2506 is incremented to point to the next data location. For example, if the recovery buffer 2500 is as shown in FIG. 25(A), when an update trigger event occurs (e.g., conditional branch instruction D is sent to the execution unit for execution), information in the update history shift register 1504 and an indication of whether the circular buffer is updated are stored at the data location pointed to by the write pointer 2506, and then the write pointer 2506 is incremented to point to the next data location, as shown in FIG. 25(B).

[0165] In some cases, the indication of whether the circular buffer is updated is a single bit, which is set to "1" if the circular buffer is updated and set to "0" if the circular buffer is not updated. For example, if a conditional branch instruction is sent to the execution unit for execution (which causes an update to the circular buffer due to a branch prediction being made), then information in the update history shift register 1504 and "1" are stored at the data location pointed to by the write pointer 2506. However, if a jump instruction is sent to the execution unit for execution (which is a CTI that does not cause an update to the circular buffer due to no branch prediction being made), then information in the update history shift register 1504 and "0" are stored at the data location pointed to by the write pointer 2506.

[0166] Whenever a removal trigger event occurs (e.g., information indicating that a control transfer instruction has been executed is received from the execution unit (EXU)), data elements in the data locations 25020 to 25024 pointed to by the read pointer 2504 are popped from the recovery buffer 2500. This can be done by incrementing the read pointer 2504 to point to the next data locations 25020 to 25024. For example, if the recovery buffer 2500 is as shown in FIG. 25(B), when a removal trigger event occurs (e.g., information indicating that control transfer instruction A has been executed is received from the EXU), then the read pointer 2504 is incremented to point to the next data location, as shown in FIG. 25(C).

[0167] When a recovery trigger event occurs (e.g., an indication that a misprediction has occurred is received), the information in the update history register 1504 and the value of the top pointer 1560 are replaced based on data from the top data location (the data location pointed to by the read pointer 2504), and the entries in the recovery buffer 2500 are invalidated. In particular, the information in the update history register 1504 is replaced with the update history register information in the top data location of the recovery buffer; and the number of data locations in the recovery buffer 2500 that indicate a branch prediction has been made is counted, and this count is used to update the top pointer 1560 (e.g., the top pointer may be incremented by this count).

[0168] This change to the top pointer 1560 causes the active data locations of the circular buffer 1502 to change, such that a different set of data locations of the circular buffer 1502 are used to determine the current values of the main shift register (e.g., GHR) and the checkpoint. In other words, it moves the active data locations back to what they were at the previous time point (e.g., before the mispredicted instruction was issued to the execution unit for execution). Reference will be made to Figure 26(A)-26(B) the example that depicts the circular buffer 1502, the top pointer 1560, the update history register 1504, and the recovery buffer 2500 after a recovery event.

[0169] In this example recovery buffer 2500, each data location in the recovery buffer 2500 has C bits (for the update history register) + 1 bit (for the circular buffer update indicator). In the case where there are M data locations in the recovery buffer, the total number of bits of the recovery buffer 2500 is then M*(C + 1). So in the case where C is 3 and M is 16, the total number of bits to implement the recovery buffer 2500 is only 64.

[0170] Figure 26(A)-26(B) An example that depicts the circular buffer 1502, the top pointer 1560, the update history register 1504, and the recovery buffer 2500 after a recovery event is shown. In particular, in FIG. 26(A), the update history register 1504 is equal to "001", the top pointer 1560 is equal to "00011" (3), and the circular buffer 1502 is equal to "010100000100101100011101", meaning that the active data locations A0 to A 11 are data locations 4 to 14.

[0171] If a recovery event (e.g., a misprediction of instruction X) subsequently occurs, the history shift register 1504 and the top pointer 1560 are updated as shown in Figure 26(B) based on the information in the recovery buffer 2500 to restore them to what they were before instruction X was sent to the execution unit for execution. In particular, the information in the history shift register 1504 is replaced with the updated history shift register information at the top data location (the data location pointed to by the read pointer 2502). In the example of Figure 26(A), the information in the history shift register at the top data location 25020 is "101", so after the recovery event, the history shift register 1504 is set to "101", as shown in Figure 26(B).

[0172] The number of loop buffer update indicators is also counted and used to restore the top pointer 1560 to its value before instruction X was sent to the execution unit for execution. In Figure 26(A)-26(B) 's example, the recovery buffer has two data locations (25020 and 25022) where the loop buffer update indicators are set, indicating that two branch predictions (and thus two updates to the loop buffer 1502) have been made since instruction X was issued to the execution unit for execution. Accordingly, the top pointer 1560 is restored to its value before instruction X was issued to the execution unit for execution by adding two to the top pointer 1560. In particular, before the recovery event, the top pointer was "00011", so to restore the top pointer 1560 to its value before instruction X was issued to the execution unit for execution, the top pointer value "00011" is incremented by two to "00101" (5).

[0173] As can be seen from Figure 26(A)-26(B) , this changes the active data locations of the loop buffer from data locations 4 to 14 back to data locations 6 to 16.

[0174] Once the history shift register 1504 and the top pointer 1560 are restored, the data in the recovery buffer 2500 is invalidated. This may involve setting the write pointer 2506 and the read pointer 1504 to point to the same data location indicating that the recovery buffer 1500 is empty.

[0175] Figure 27 Illustrates an example hardware structure 2700 for implementing the shift register checkpoint operation method described above with respect to Figures 15 to 26(B) The hardware structure 2700 includes the loop buffer 1502, the history shift register 1504, and the top pointer 1560 described above. The hardware structure 2700 also includes a recovery buffer 2702, which can be, for example, Figure 23(A)-23(C) 's recovery buffer 2300 or Figure 25(A)-25(C) 's recovery buffer 2500.

[0176] The hardware structure further includes update logic 2704 for updating the circular buffer 1502, update history shift register 1504, top pointer 1560, and recovery buffer 2702 as described above. In particular, the update logic 2704 is configured to receive new data elements of the main shift register (e.g., GHR) and update the circular buffer 1502, update history shift register 1504, top pointer 1560, and recovery buffer 2702 accordingly as described with respect to Figure 16(A)-18(B) and Figure 23(A)-26(B) above. For example, in the case where the shift register being checkpointed is the GHR, the new data element to be added to the GHR can be the predicted result of a conditional branch instruction.

[0177] The hardware structure further includes checkpoint generation logic 2706 for generating checkpoints from the circular buffer 1502, update history shift register 1504, and top pointer 1560 as described above with respect to Figures 19 - 22 above and / or for the main shift register. For example, the checkpoint generation logic 2706 can be configured to implement one or more of the methods described with respect to Figures 19 to 21 above.

[0178] The hardware structure 2700 may further include recovery logic 2708 for restoring the update history shift register 1504 and top pointer 1560 to a previous time point based on information stored in the recovery buffer 2702 when notified of a recovery trigger event (e.g., misprediction of a conditional branch instruction), as described above with respect to Figure 23(A)-26(B) above.

[0179] For example, in the case where the recovery buffer 2702 is configured to store copies of the update history shift register 1504 and top pointer 1560 at a specific time point (e.g., as described with respect to Figure 23(A)-23(C) above), when the recovery trigger event is notified to the recovery logic 2708, the recovery logic 2708 can be configured to replace the update history shift register 1504 and top pointer 1560 with the values stored in the recovery buffer 2702. However, in the case where the recovery buffer 2702 is configured to store a copy of the update history shift register 1504 and information indicating whether the circular buffer 1502 has been updated (e.g., as described with respect to Figure 24(A)-26(B) above), when the recovery trigger event is notified to the recovery logic 2708, the recovery logic 2708 can be configured to replace the update history shift register 1504 with the update history shift register data stored in the recovery buffer 2702 and update the value of the top pointer 1560 based on the information indicating whether the circular buffer 1502 has been updated.

[0180] A first additional example provides a hardware structure configured to obtain one or more checkpoints of a main shift register having a predetermined number of data positions. The hardware structure includes: an extended shift register including the data positions of each data position of the main shift register and the additional data positions of each checkpoint, where the data positions of the extended shift register store data elements most recently shifted onto the main shift register; an update history shift register including the data positions of each checkpoint, where each data position of the update history register stores information indicating whether the extended shift register was updated in the same clock cycle as a particular checkpoint trigger event; and checkpoint generation logic configured to obtain each checkpoint by selecting a subset of the data positions of the extended shift register based on the information stored in the update history shift register.

[0181] A second additional example provides a method for obtaining one or more checkpoints of a main shift register having a predetermined number of data positions. The method includes: storing a predetermined number of data elements most recently shifted onto the main shift register in a plurality of data positions of an extended shift register; storing additional data elements for each checkpoint in additional data positions of the extended shift register; storing information indicating whether the extended shift register was updated in the same clock cycle as a particular checkpoint trigger event in a data position of an update history shift register; and obtaining each checkpoint by selecting a subset of the data positions of the extended shift register based on the information stored in the update history shift register.

[0182] A third additional example provides a hardware structure configured to obtain one or more checkpoints of a main shift register having a predetermined number of data positions and being restorable to multiple time points. The hardware structure includes: a circular buffer including the data positions of each data position of the main shift register, the additional data positions of each checkpoint, and the additional data positions of each of the multiple time points, where the data positions of the circular buffer store data elements most recently shifted onto the main shift register; a pointer configured to identify a plurality of active data positions of the circular buffer, the active data positions including a subset of the data positions of the circular buffer storing data elements most recently written to the circular buffer; an update history shift register having the data positions of each checkpoint, where the data positions of the update history register store information indicating whether the circular buffer was updated in the same clock cycle as a particular checkpoint trigger event; and checkpoint generation logic configured to obtain each checkpoint by selecting a subset of the active data positions based on the information stored in the update history shift register.

[0183] A fourth additional example provides a method of obtaining one or more checkpoints of a master shift register having a predetermined number of data positions and being restorable to multiple time periods, the method comprising: storing a predetermined number of data elements most recently shifted onto the master shift register at multiple data positions of a circular buffer; storing additional data positions of each checkpoint at additional data positions of the circular buffer; storing additional data elements during each of the multiple time periods at additional data positions of the circular buffer; storing an index to the circular buffer into a pointer, the index identifying an active data position of the circular buffer; storing information indicating whether the circular buffer was updated in the same clock cycle as a particular checkpoint trigger event at a data position of an update history shift register; and obtaining each checkpoint by selecting a subset of the active data positions based on the information stored in the update history shift register.

[0184] A fifth additional example provides a hardware structure configured to restore a master shift register and one or more checkpoints to a previous time point, the hardware structure comprising: a circular buffer including multiple data positions; a pointer configured to identify a set of active data positions from the data positions of the circular buffer; an update history shift register including information indicating whether the circular buffer was updated in the same cycle as each of one or more checkpoint trigger events; checkpoint generation logic configured to generate one or more checkpoints of the master shift register from the active data positions based on the information stored in the update history shift register; a restore buffer storing a copy of the information including the update history shift register and an indication of whether the circular buffer was updated in the corresponding cycle for one or more time points; and restore logic configured to restore the update history shift register and the pointer to a particular time point based on the data stored in the restore buffer in response to receiving an indication that a restore is to be performed.

[0185] A sixth additional example provides a method for restoring a main shift register and one or more checkpoints to a previous point in time, the method comprising: storing a predetermined number of data elements most recently shifted onto the main shift register at a plurality of data positions in a circular buffer; storing an index to the circular buffer in a pointer, the index identifying a set of active data positions from the plurality of data positions in the circular buffer; storing information indicating whether the circular buffer was updated in the same clock cycle as a checkpoint trigger event at a data position in an update history shift register; obtaining each checkpoint by selecting a subset of the active data positions based on the information stored in the update history shift register; storing in a recovery buffer data including a copy of the information in the update history shift register and an indication of whether the circular buffer was updated in the corresponding cycle for one or more points in time; and in response to receiving an indication that a recovery is to be performed at a recovery logic, restoring the update history shift register and the pointer to a particular point in time based on the data stored in the recovery buffer.

[0186] A seventh additional example provides a hardware structure configured to obtain one or more checkpoints of a main shift register having a predetermined number of data positions and being restorable to multiple points in time, the checkpoints being triggered by trigger events, the hardware structure comprising: a circular buffer having a plurality of data positions for storing data elements, the plurality of data positions including data positions for each data position of the main shift register, additional data positions for each checkpoint, and additional data positions for each of the multiple points in time; a pointer configured to identify a plurality of active data positions from the plurality of data positions in the circular buffer, the active data positions including a first subset of the plurality of data positions in the circular buffer representing the main shift register and the additional data positions for each checkpoint; an update history shift register having data positions for each checkpoint, the data positions in the update history register storing information indicating whether the circular buffer was updated in the same clock cycle as a particular checkpoint trigger event; and checkpoint generation logic configured to obtain each checkpoint by selecting a subset of the plurality of active data positions based on the information stored in the update history shift register.

[0187] In the seventh additional example, a selected subset of the plurality of active data positions for a particular checkpoint may be offset from the first subset of data positions by zero, one, or more than one data position.

[0188] The checkpoint generation logic may be configured to determine an offset from the first subset of data positions for a particular checkpoint by evaluating information stored in a plurality of associated data positions in the update history shift register.

[0189] Each checkpoint may represent the main shift register prior to a plurality of checkpoint trigger events; and the number of relevant data positions of the update history shift register for a particular checkpoint is equal to the number of checkpoint trigger events for that checkpoint.

[0190] The offset may be equal to a count of relevant data positions of the update history shift register including information indicating that the circular buffer has been updated.

[0191] The checkpoint generation logic may be configured to obtain a first checkpoint representing the main shift register prior to the most recent checkpoint trigger event by: determining in the checkpoint generation logic whether a first data position of the update history shift register includes information indicating that the circular buffer has been updated; in response to determining that the first data position of the update history shift register includes information indicating that the circular buffer has not been updated, selecting a first subset of data positions of the circular buffer in the checkpoint generation logic; and in response to determining in the checkpoint generation logic that the first data position of the update history shift register includes information indicating that the circular buffer has been updated, selecting a subset of a plurality of active data positions offset by one data position from the first subset of data positions in the checkpoint generation logic.

[0192] In the case where the number of checkpoints is at least two, the checkpoint generation logic may be configured to obtain a second checkpoint representing the main shift register prior to the two most recent checkpoint trigger events by: counting the number of the first two data positions of the update history shift register including information indicating that the circular buffer has been updated; and selecting a subset of a plurality of active data positions offset by the count from the first subset of data positions.

[0193] The seventh additional example may further include update logic configured to, in each clock cycle: determine in the update logic whether a checkpoint trigger event occurs; in response to determining that a checkpoint trigger event has occurred, determine in the update logic whether the circular buffer is updated in the current clock cycle; in response to determining that the circular buffer is updated in the current clock cycle, shift information indicating that the circular buffer has been updated onto the update history shift register; and in response to determining that the circular buffer is not updated in the current clock cycle, shift information indicating that the circular buffer has not been updated onto the update history shift register.

[0194] The seventh additional example may further include a recovery buffer having a plurality of data positions, each data position of the recovery buffer storing a copy of the information of the update history shift register and a copy of a pointer at a particular point in time.

[0195] The seventh additional example may further include recovery logic configured to, in response to receiving an indication that recovery is to be performed, restore the update history shift register and the pointer to a particular point in time using the copies stored in the recovery buffer.

[0196] The main shift register may be a global history register, and each data element of the global history register indicates the prediction result of a conditional branch instruction; and the indication that recovery is to be performed is an indication that the conditional branch instruction has been mispredicted.

[0197] The main shift register may be a global history register, and each data element of the global history register indicates the prediction result of a conditional branch instruction.

[0198] There may be a processor with a hardware structure including a seventh additional example.

[0199] There may be an instruction fetch unit with a hardware structure including a seventh additional example.

[0200] An eighth additional example provides a method of obtaining one or more checkpoints of a main shift register having a predetermined number of data positions and recoverable to multiple time periods, the checkpoints being triggered by trigger events, the method including: storing data elements at multiple data positions of a circular buffer; the multiple data positions including the data positions of each data position of the main shift register, additional data positions of each checkpoint, and additional data positions of each of the multiple time points; storing an index to the circular buffer into a pointer, the index identifying multiple active data positions of the multiple data positions of the circular buffer, the multiple active data positions including a first subset of the multiple data positions of the circular buffer representing the main shift register and the additional data positions of each checkpoint; storing information indicating whether the circular buffer is updated in the same clock cycle as a particular checkpoint trigger event at a data position of an update history shift register; and obtaining each checkpoint by selecting a subset of the multiple active data positions using hardware logic based on the information stored in the update history shift register.

[0201] The selected subset of the multiple active data positions of a particular checkpoint may be offset from the first subset of data positions by zero, one, or more than one data position.

[0202] The offset from the first subset of data positions of a particular checkpoint may be determined by hardware logic that evaluates information stored in multiple relevant data positions of the update history shift register.

[0203] Each checkpoint may represent the main shift register prior to multiple checkpoint trigger events; and the number of relevant data positions of the update history shift register for a particular checkpoint may be equal to the number of checkpoint trigger events for that checkpoint.

[0204] The offset may be equal to the count of relevant data positions of the update history shift register including information indicating that the circular buffer has been updated.

[0205] The eighth additional example may also include storing a copy of the information of the update history shift register and a copy of the pointer at the data location in the recovery buffer at a specific point in time.

[0206] The methods described herein may be executed by a computer configured with software in a machine-readable form stored on a tangible storage medium, e.g., in the form of a computer program including computer-readable program code for configuring the computer to execute the components of the method, or in the form of a computer program including computer program code modules suitable for performing all steps of any method described herein when the program runs on a computer, and wherein the computer program may be embodied on a computer-readable storage medium. Examples of tangible (or non-transitory) storage media include magnetic disks, thumb drives, memory cards, etc., and do not include propagated signals. The software may be suitable for execution on a parallel processor or a serial processor such that the method steps may be performed in any suitable order or simultaneously.

[0207] The terms "processor" and "computer" are used herein to refer to any device or portion thereof having processing capabilities such that it can execute instructions. The term "processor" may include, for example, a central processing unit (CPU), a graphics processing unit (GPU or VPU), a physics processing unit (PPU), a radio processing unit (RPU), a digital signal processor (DSP), a general-purpose processor (e.g., a general-purpose GPU), a microprocessor, any processing unit designed to accelerate tasks outside of the CPU, etc. Those skilled in the art will recognize that such processing capabilities are incorporated into many different devices, and thus the term "computer" includes set-top boxes, media players, digital radio devices, PCs, servers, mobile phones, personal digital assistants, and many other devices.

[0208] Those skilled in the art will recognize that storage devices for storing program instructions may be distributed across a network. For example, a remote computer may store examples of processes described as software. A local or terminal computer may access the remote computer and download a portion or all of the software to run the program. Alternatively, the local computer may download several software as needed or execute some software instructions at the local terminal and some software instructions at the remote computer (or computer network). Those skilled in the art will also recognize that all or a portion of the software instructions may be implemented by dedicated circuitry (e.g., DSP, programmable logic array, etc.) using conventional techniques known to those skilled in the art.

[0209] The methods described herein can be performed by a computer configured with software in a machine-readable form stored on a tangible storage medium, e.g., in the form of a computer program including computer-readable program code for configuring the computer to perform the methods, or in the form of a computer program including computer program code modules adapted to perform all steps of any method described herein when the program is run on a computer, and wherein the computer program can be embodied on a computer-readable storage medium. Examples of tangible (or non-transitory) storage media include magnetic disks, thumb drives, memory cards, etc., and do not include propagated signals. The software can be adapted to be executed on a parallel processor or a serial processor such that the method steps can be performed in any suitable order or simultaneously.

[0210] The hardware components described herein can be produced by a non-transitory computer-readable storage medium encoded with computer-readable program code.

[0211] Software is also contemplated that “describes” or defines the configuration of hardware implementing the modules, functions, components, or logic described above, e.g., HDL (Hardware Description Language) software, such as that used for designing integrated circuits or for configuring programmable chips, to implement the desired functionality. That is, a computer-readable storage medium can be provided having stored thereon computer-readable program code for producing a processing unit configured to perform any method described herein or for producing a processing unit including any apparatus described herein. That is, a computer system can be configured to produce a representation of a digital circuit from a definition of circuit elements and data defining rules for combining those circuit elements, where the non-transitory computer-readable storage medium can have processor-executable instructions stored thereon that, when executed at such a computer system, cause the computer system to produce a processing unit as described herein. For example, the non-transitory computer-readable storage medium can have computer-readable instructions stored thereon that, when processed at a computer system for producing a representation of an integrated circuit, cause the computer system to produce a representation of a processor of a receiver as described in the examples herein or to produce a representation of a processor configured to perform a method as described in the examples herein. The representation of the processor can be the processor itself or a representation of the processor (e.g., a mask) that can be used to produce the processor.

[0212] The memory storing machine-executable data used in implementing the disclosed aspects can be a non-transitory medium. The non-transitory medium can be volatile or non-volatile. Examples of volatile non-transitory media include semiconductor-based memories such as SRAM or DRAM. Examples of technologies that can be used to implement non-volatile memory include optical and magnetic memory technologies, flash memory, phase change memory, persistent RAM.

[0213] A particular reference to "logic" refers to a structure that performs one or more functions. Examples of logic include circuits arranged to perform those functions. For example, such a circuit may include transistors and / or other hardware elements available in a manufacturing process. As an example, such transistors and / or other elements may be used to form a circuit or structure that implements and / or includes a memory such as a register, a trigger circuit or a latch, a logic operation unit such as a Boolean operation, a mathematical operation unit such as an adder, a multiplier or a shifter, and an interconnection structure. Such elements may be provided as custom circuits or standard cell libraries, macros, or at other levels of abstraction. Such elements may be interconnected in a particular arrangement. Logic may include circuits with fixed functions, and the circuits may be programmed to perform one or more functions; such programming may be provided from a firmware or software update or control mechanism. Logic identified as performing one function may also include logic that implements component functions or sub-processes. In an example, hardware logic has a circuit that implements a fixed function operation or multiple operations, a state machine, or a process.

[0214] As will be apparent to those skilled in the art, any range or device value given herein may be extended or altered without losing the desired effect.

[0215] It will be understood that the benefits and advantages described above may relate to one embodiment or may relate to several embodiments. Embodiments are not limited to those embodiments that solve any or all of the stated problems or have any or all of the stated benefits and advantages.

[0216] Any reference to an item refers to one or more of those items. The term "comprising" is used herein to mean including the identified method blocks or elements, but such blocks or elements do not comprise an exclusive list, and a device may include additional blocks or elements, and a method may include additional operations or elements. In addition, the blocks, elements, and operations themselves are not implicitly closed.

[0217] The steps of the methods described herein may be performed in any suitable order or simultaneously when appropriate. The arrows between the boxes in the figures illustrate an example order of method steps, but are not intended to exclude other orders or the execution of multiple steps in parallel. In addition, individual blocks may be removed from any method without departing from the spirit and scope of the subject matter described herein. Aspects of any of the examples described above may be combined with aspects of any of the other examples described to form additional examples without losing the desired effect. Where elements in the figures are shown as being connected by arrows, it is to be understood that these arrows illustrate only one example flow of communication (including data and control messages) between the elements. The flow between the elements may be in either direction or in both directions.

[0218] It will be understood that the foregoing description of the preferred embodiments is given by way of example only, and that various modifications may be made by those skilled in the art. Although the various embodiments have been described above in a certain degree of detail or with reference to one or more separate embodiments, those skilled in the art may make many variations to the disclosed embodiments without departing from the spirit or scope of the invention.

Claims

1. A hardware structure for restoring a main shift register and one or more checkpoints to a previous point in time, the hardware structure comprising: An extended shift register implemented as a circular buffer, the circular buffer including a plurality of data positions; A pointer configured to identify a set of active data positions from the data positions of the circular buffer; An update history shift register including information indicating whether the circular buffer was updated in the same cycle as each of one or more checkpoint trigger events; Checkpoint generation logic configured to generate one or more checkpoints of the main shift register from the active data positions of the extended shift register implemented as the circular buffer based on the information stored in the update history shift register; A restore buffer storing data including a copy of the information of the update history shift register and an indication of whether the circular buffer was updated in a corresponding cycle for one or more points in time; And Restore logic configured to, in response to receiving an indication that a restore is to be performed, restore the update history shift register and the pointer to a specific point in time based on the data stored in the restore buffer.

2. The hardware structure of claim 1, wherein the restore logic is configured to restore the pointer to a specific point in time by: identifying the number of indications in the restore buffer that the circular buffer was updated in a corresponding cycle, the indications indicating that the circular buffer was updated in the corresponding cycle; and adjusting the pointer by that number.

3. The hardware structure of claim 1, wherein the indication of whether the circular buffer was updated in a corresponding cycle is a single bit.

4. The hardware structure of claim 2, wherein the indication of whether the circular buffer was updated in a corresponding cycle is a single bit.

5. The hardware structure of claim 1, wherein each data position of the circular buffer includes information indicating a prediction result of a conditional branch instruction; and the indication of whether the circular buffer was updated in a corresponding cycle indicates that the circular buffer was updated in the corresponding cycle when the result of the conditional branch instruction was predicted in the corresponding cycle.

6. The hardware structure of any one of claims 1-5, wherein the checkpoint generation logic is configured to generate each of the one or more checkpoints by selecting a subset of the active data positions based on the information in the update history shift register.

7. The hardware structure of claim 6, wherein the active data positions include a first subset of active data positions corresponding to the main shift register; and the subset of the active data positions for a particular checkpoint is not offset, offset by one data position, or offset by more than one data position from the first subset of the active data positions.

8. The hardware structure according to claim 7, wherein the update history shift register includes one data position for each checkpoint, and the one data position includes information indicating whether the circular buffer is updated in the same cycle as the checkpoint trigger event; and the checkpoint generation logic is configured to determine an offset of the first subset of active data positions from a specific checkpoint by evaluating information stored in a plurality of relevant data positions of the update history shift register.

9. The hardware structure according to claim 8, wherein each checkpoint represents the main shift register before a plurality of checkpoint trigger events; and the number of relevant data positions of the update history shift register for a specific checkpoint is equal to the number of checkpoint trigger events for that specific checkpoint.

10. The hardware structure according to claim 8, wherein the offset is equal to a count of the plurality of relevant data positions of the update history shift register that include information indicating that the circular buffer is updated.

11. The hardware structure according to claim 9, wherein the offset is equal to a count of the plurality of relevant data positions of the update history shift register that include information indicating that the circular buffer is updated.

12. The hardware structure according to any one of claims 8-11, wherein the checkpoint generation logic is configured to obtain a first checkpoint representing the main shift register before the most recent checkpoint trigger event by: determining whether a first data position of the update history shift register includes information indicating that the circular buffer is updated; in response to determining that the first data position of the update history shift register includes information indicating that the circular buffer is not updated, selecting the first subset of active data positions of the circular buffer; and in response to determining that the first data position of the update history shift register includes information indicating that the circular buffer is updated, selecting a subset of the active data positions that is offset by one data position from the first subset of active data positions.

13. The hardware structure according to any one of claims 8-11, wherein the number of checkpoints is at least two, and the checkpoint generation logic is configured to obtain a second checkpoint representing the main shift register before the two most recent checkpoint trigger events by: counting the number of the first two data positions of the update history shift register that include information indicating that the circular buffer is updated; and selecting a subset of the active data positions that is offset by the counted data positions from the first subset of active data positions.

14. The hardware structure according to any one of claims 1-11, further comprising update logic, the update logic being configured to, in each clock cycle: determine whether a checkpoint trigger event occurs; in response to determining that a checkpoint trigger event has occurred, determine whether the circular buffer is updated in the current clock cycle; In response to determining that the circular buffer is updated in the current clock cycle, move the information indicating that the circular buffer has been updated onto the update history shift register; and In response to determining that the circular buffer is not updated in the current clock cycle, move the information indicating that the circular buffer has not been updated onto the update history shift register.

15. The hardware structure according to any one of claims 1-11, wherein, An indication that a resume to be executed is a misprediction of a conditional branch instruction.

16. A method for restoring a main shift register and one or more checkpoints to a previous time point, the method comprising: Storing a predetermined number of data elements most recently moved onto the main shift register at a plurality of data positions of an extended shift register implemented as a circular buffer; Storing an index to the circular buffer into a pointer, the index identifying a set of active data positions from the plurality of data positions of the circular buffer; Storing information indicating whether the circular buffer is updated in the same clock cycle as a checkpoint trigger event at a data position of an update history shift register; Obtaining each checkpoint by selecting a subset of the active data positions of the extended shift register implemented as the circular buffer based on the information stored in the update history shift register; Storing in a restore buffer data including a copy of the information of the update history shift register and an indication of whether the circular buffer is updated in the corresponding cycle for one or more time points; And In response to receiving an indication that a restore is to be executed at a restore logic, restoring the update history shift register and the pointer to a specific time point based on the data stored in the restore buffer.

17. The method according to claim 16, wherein restoring the pointer to a specific point in time comprises: Identifying the number of indications in the restore buffer that the circular buffer is updated in the corresponding cycle, the indications indicating that the circular buffer is updated in the corresponding cycle; and adjusting the pointer by that number.

18. The method of claim 16 or 17, wherein the active data positions include a first subset of active data positions corresponding to the main shift register; and the selected subset of the active data positions for a particular checkpoint is not offset from, offset by one data position, or offset by more than one data position from the first subset of active data positions.

19. The method of claim 18, wherein obtaining a first checkpoint representing the data elements before the most recent checkpoint trigger event comprises: Determining whether a first data position of the update history shift register includes information indicating that the circular buffer is updated; In response to determining that the first data position of the update history shift register includes information indicating that the circular buffer is not updated, selecting the first subset of the active data positions of the circular buffer; And In response to determining that the first data position of the update history shift register includes information indicating that the circular buffer is updated, selecting the subset of the active data positions offset by one data position from the first subset of active data positions.

20. The method according to claim 18, wherein the number of checkpoints is at least two, and obtaining a second checkpoint representative of the master shift register before events are triggered at two nearest checkpoints comprises: counting a number of the first two data positions of the update history shift register that include information indicating that the circular buffer has been updated; and selecting a subset of the active data positions that is offset from the first subset of the active data positions by the counted data positions.

21. The method according to claim 16, further comprising, in each clock cycle: determining whether a checkpoint trigger event occurs; in response to determining that a checkpoint trigger event has occurred, determining whether the circular buffer is updated in the current clock cycle; in response to determining that the circular buffer is updated in the current clock cycle, shifting information indicating that the circular buffer has been updated onto the update history shift register; and in response to determining that the circular buffer is not updated in the current clock cycle, shifting information indicating that the circular buffer has not been updated onto the update history shift register.

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