A multi-objective optimization method for high voltage silicon carbide modules

Abstract

The present application relates to the technical field of electronic power devices, in particular to a multi-objective optimization method for high-voltage silicon carbide modules, which can improve the defects of single optimization target design method not considering other performance indicators, realize the overall performance of high-voltage SiC modules, by establishing a finite element model to model the internal electric field intensity peak, parasitic capacitance and solder layer thermal stress of the module, multi-objective weighted optimization, and selecting the optimal parameters. After adopting the above method, the relationship model between the performance parameters and the optimized size parameters obtained in the optimization design of the present application can be used to analyze the influence trend and degree of each design parameter on each target parameter; in addition, the reliability of the final scheme and the effectiveness of the design method are verified by simulation and experiment: the optimal scheme selected by the present application to balance each optimization target needs to be verified by simulation and experiment, so as to prove the feasibility of the method and the performance advantage of the module.

Description

Technical Field

[0001] This invention relates to the field of electronic power device technology, and in particular to a multi-objective optimization method for high-voltage silicon carbide modules. Background Technology

[0002] In recent years, with the development of technologies such as rail transit, pulsed power, high-voltage direct current transmission, and new energy power generation, the demand for high-voltage power semiconductor modules has been increasing. Wide-bandgap semiconductor material SiC is an excellent choice, as its chips offer advantages such as high blocking voltage, low switching losses, and fast switching speeds. Its application in solid-state transformers, converters, and other equipment can significantly reduce their size and improve their efficiency and power density, attracting increasing attention from academic and industrial communities both domestically and internationally.

[0003] like Figure 2 As shown, innovation in packaging technology is essential for SiC chips to fully realize their advantages, such as high voltage. The main packaging issues for high-voltage SiC modules are insulation breakdown, parasitic parameters, and thermal management. Currently, researchers have proposed many optimization methods for these issues in the design of high-voltage power semiconductor modules, but most of them only address one aspect and do not consider the various contradictions inherent in actual high-voltage applications. Summary of the Invention

[0004] The technical problem this invention aims to solve is to provide an optimization method that can guarantee the overall performance of high-voltage SiC modules.

[0005] To address the aforementioned technical problems, the present invention includes a multi-objective optimization method for high-voltage silicon carbide modules, characterized by comprising the following steps:

[0006] Step S1: Determine the initial parameters of the module;

[0007] Step S2: Establish an electric field finite element model for the copper-clad ceramic plate within the module, and optimize the parameters of the copper-clad ceramic plate that are only related to the electric field distribution.

[0008] Step S3: Establish a model of the relationship between peak electric field intensity, parasitic capacitance, and thermal stress of solder layer and dimensional parameters using the electric, thermal, and mechanical finite element method;

[0009] Step S4: Based on the above relationship model, use the weighted optimization method to select the optimal parameters to optimize the overall performance of the module;

[0010] Step S5: Design the module power terminals and housing to achieve a trade-off between parasitic inductance and external insulation performance;

[0011] Step S6: Verify the effectiveness of the design method using simulation;

[0012] Step S7: Experimentally verify the module performance. If it meets the requirements, it is the optimal solution; if it does not meet the operating conditions, return to step S1.

[0013] Preferably, the initial parameters in step S1 include the copper-clad ceramic plate material and the relevant dimensional parameters of the copper-clad ceramic plate.

[0014] Preferably, the optimized dimensional parameters in step S2 include the spacing between the metal layers on the copper-clad ceramic plate and the distance between the upper metal layer and the edge of the ceramic layer on the copper-clad ceramic plate.

[0015] Preferably, the dimensional parameters in step S3 include the shape of the lower metal layer of the copper-clad ceramic plate and the thickness of the upper and lower metal layers and ceramic layer of the copper-clad ceramic plate.

[0016] Preferably, the optimization objectives in step S4 include the peak electric field strength, parasitic capacitance, and thermal stress of the solder layer, which are quantitative indicators. The mathematical model expression for the weighted design method is as follows:

[0017]

[0018] 0.1mm ≤ h1 = h3 ≤ 0.3mm;

[0019] 0.6mm≤h2≤1.0mm;

[0020] 0mm≤x≤15.6mm;

[0021] w1+w2+w3+w4=1;

[0022] The objective function is a weighted sum of standardized parameters to obtain the final index, denoted by F, where a smaller value indicates better module performance. h1, h2, and h3 are the thicknesses of the upper metal layer, ceramic layer, lower metal layer, and solder layer between the copper-clad ceramic board and the substrate, respectively. x is the quantified dimensional parameter of the shape of the lower metal layer of the copper-clad ceramic board. CS and Cd are the parasitic capacitances to ground of the source and drain of the copper-clad ceramic board, respectively. Emax is the peak electric field strength of the copper-clad ceramic board. σ is the average thermal stress of the solder layer between the copper-clad ceramic board and the substrate. The weighting factor wi is expressed as a percentage, and the specific value of wi can be selected according to different application scenarios.

[0023] Preferably, in step S4, different size parameters are substituted into the corresponding quantitative performance index calculation model, and then the index F representing the overall performance of the module is calculated by weighting, and the optimal parameter is selected as the subsequent verification parameter.

[0024] Preferably, the length of the power terminal and the shape of the housing are mainly compromised in S5.

[0025] By using the above method, the present invention has the following advantages:

[0026] (1) More comprehensive optimization objectives: The optimization design proposed in this invention needs to comprehensively consider parasitic parameters, module life, and insulation performance, and make multi-objective optimization selections for the quantitative indicators of the three, such as peak electric field strength, parasitic capacitance, and thermal stress of solder layer.

[0027] (2) Combining the relationship model to support theoretical analysis: The relationship model between the performance parameters and the optimized size parameters obtained in the optimization design proposed in this invention can be used to analyze the influence trend and degree of each design parameter on each target parameter;

[0028] (3) Verify the reliability of the final solution and the effectiveness of the design method by combining simulation and experiment: The optimal solution selected by this invention that balances various optimization objectives needs to be verified by simulation and experiment in order to prove the feasibility of this method and the performance advantages of the module. Attached Figure Description

[0029] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0030] Figure 1 This is a flowchart of the present invention;

[0031] Figure 2 This is a schematic diagram of the DBC under-metal layer layout in the module, designed according to traditional methods.

[0032] Figure 3 This is a schematic diagram of the preliminary optimized metal layer layout under DBC in an embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of the weighted optimization results of the present invention;

[0034] Figure 5 This is a schematic diagram of the optimal metal layer layout under DBC after weighted optimization according to the present invention;

[0035] Figure 6 This is an exploded view of the high-voltage SiC module after the multi-objective design of this invention.

[0036] In the diagram: 1 is the outer casing, 2 is the terminal, 3 is the copper-clad ceramic plate, 4 is the substrate, and 5 is the SiC chip. Detailed Implementation

[0037] The purpose of this invention is to provide a multi-objective optimization design method for high-voltage silicon carbide (SiC) modules. A finite element model is established to model the peak electric field intensity, parasitic capacitance, and thermal stress of the solder layer inside the module. Multi-objective weighted optimization is performed to select the optimal parameters. This method can improve the shortcomings of single-objective optimization design methods that do not consider other performance indicators, and achieve better overall performance of high-voltage SiC modules.

[0038] like Figure 1As shown, this embodiment provides a multi-objective optimization design method for high-voltage silicon carbide (SiC) modules, which includes the following steps:

[0039] Step S1: Determine the initial parameters of the module, including dimensional parameters such as the material of each layer of DBC, DBC thickness, and spacing;

[0040] Step S2: Establish an electric field finite element model for the copper-clad ceramic plate (DBC) inside the module, and optimize the parameters of the DBC that are only related to the electric field distribution;

[0041] Step S3: Establish a model of the relationship between peak electric field intensity, parasitic capacitance, and thermal stress of solder layer and dimensional parameters using the electric, thermal, and mechanical finite element method;

[0042] Step S4: Based on the above relationship model, use the weighted optimization method to select the optimal parameters to optimize the overall performance of the module;

[0043] Step S5: Design the module power terminals and housing to achieve a trade-off between parasitic inductance and external insulation performance;

[0044] Step S6: Verify the effectiveness of the design method using simulation;

[0045] Step S7: Experimentally verify the module performance. If it meets the requirements, it is the optimal solution; if it does not meet the operating conditions, return to step S1.

[0046] The specific steps are described below:

[0047] In step S1, the ceramic layer in the DBC is made of alumina, and the upper and lower metal layers are made of copper. The thickness of the DBC ceramic layer is 1 mm, and the thickness of the copper layer is 0.3 mm.

[0048] The optimized size parameters in step S2 are parameters that are only related to the electric field, specifically including the spacing between the copper layers on the DBC and the distance between the copper layer and the edge of the DBC ceramic layer. Finally, the optimal parameters are selected through the electric field finite element model to minimize the peak value of the electric field intensity.

[0049] The dimensional parameters in step S3 include the shape of the lower copper layer of the DBC (where the shape of the lower copper layer is quantified as follows). Figure 3 The thickness of the upper and lower copper and ceramic layers of the DBC, along with x), will affect the peak electric field strength, parasitic capacitance, and thermal stress of the solder layer. Therefore, a corresponding relationship model is established by setting up an electric, thermal, and mechanical finite element model. Figure 3 The middle part represents the result of optimizing only the shape of the lower copper layer to reduce parasitic capacitance, and is denoted as the initial optimization.

[0050] The optimization objectives in step S4 include the peak electric field strength, parasitic capacitance, and thermal stress of the solder layer, which reflect quantitative indicators. After standardization, these are weighted to obtain the index F characterizing the overall performance. The mathematical model expression of the weighted design method is as follows:

[0051]

[0052] 0.1mm ≤ h1 = h3 ≤ 0.3mm;

[0053] 0.6mm≤h2≤1.0mm;

[0054] 0mm≤x≤15.6mm;

[0055] w1+w2+w3+w4=1;

[0056] The objective function, denoted by F, is a weighted sum of standardized parameters to obtain the final index, with a smaller F indicating better module performance. h1, h2, and h3 represent the thicknesses of the upper metal layer, ceramic layer, lower metal layer, and solder layer between the copper-clad ceramic board and the substrate, respectively. x is the quantified dimensional parameter of the shape of the lower metal layer of the copper-clad ceramic board. CS and Cd are the parasitic capacitances to ground of the source and drain of the copper-clad ceramic board, respectively. Emax is the peak electric field strength of the copper-clad ceramic board. σ is the average thermal stress of the solder layer between the copper-clad ceramic board and the substrate. The weighting factor wi is expressed as a percentage, and its specific value can be selected according to different application scenarios. For example, when there are no special requirements for the application scenario, w1 + w2 = w3 = w4 = 33.33%, and w1 = w2. When operating at high frequencies, due to the high dv / dt of the SiC module, the requirements for parasitic capacitance are higher, so w1 and w2 can be larger. If the insulation performance of the module under high-voltage conditions is more important, then w4 can be larger.

[0057] In step S4, different size parameters h1, h2, h3, and x are substituted into the corresponding quantitative performance index calculation model, and then the index F characterizing the overall performance of the module is obtained by weighted calculation. This addresses the overall parameter design problem in high-voltage module application modules, so w1 + w2 = w3 = w4 = 33.33%, and w1 = w2 = 16.67%. The result is as follows: Figure 4 As shown, the optimal parameters were selected as the subsequent verification parameters, and the results are as follows. Figure 5 As shown in the figure, the distribution pattern is clear from the F distribution: as h1 = h3, h2, and x increase, the color becomes darker and the F value decreases. The overall performance after DBC compromise shows an upward trend. Among them, the copper layer thickness h1 = h3 has a relatively small impact, while the ceramic layer thickness h2 and the quantitative index of the lower copper layer shape x have a more significant impact on the overall performance F. Combining the data and the graph, we can see that when h1 = h3 = 0.26 mm, h2 = 1.0 mm, and x = 14.0 mm, F is the smallest, that is, the overall performance is optimal.

[0058] The S5 design primarily compromises on the length of the power terminals and the shape of the housing. The SiC chip 5 is mounted on the copper-clad ceramic substrate 3 (DBC), ensuring that the creepage distance between the terminals 2 extending from the module housing 1 and the module substrate 4 meets requirements while reducing parasitic inductance. Figure 6 As shown.

[0059] The simulation verification represented in step S6 includes the verification of four performance indicators: CS, Cd, Emax, and σ. The simulation results are shown below.

[0060] Table 1 Performance comparison before and after optimization

[0061]

[0062] After multi-objective weighted optimization, the DBC achieves the minimum F-value, indicating optimal overall performance. Compared to traditional DBC designs, the weighted optimization significantly reduces the average electric field strength and parasitic capacitance, while slightly increasing the peak temperature and average thermal stress of the solder layer. This demonstrates that the module's performance achieves a trade-off, sacrificing some module lifespan to improve insulation performance and reduce parasitic capacitance parameters. This approach offers advantages for high-voltage and high-frequency applications without being as extreme as the initial optimization, which excessively sacrifices module lifespan for parasitic capacitance, potentially impacting insulation performance and overall performance. Through this invention's multi-objective weighted optimization, the electric field strength is reduced and insulation performance enhanced without increasing the ceramic layer thickness, a superior approach compared to conventional empirical selection. Furthermore, the parasitic capacitance to ground of the gate and Kelvin is reduced from 4.9 pF to approximately 2.7 pF, a reduction of nearly 44.9%.

[0063] By employing this multi-objective optimization design method, multiple performance indicators of high-voltage SiC modules can be designed, thereby optimizing the overall performance of the module and greatly improving the limitations of single-objective optimization design methods. For different operating conditions or situations where a particular performance parameter is of paramount importance, the multi-objective optimization design method proposed in this invention can improve other performance characteristics by sacrificing some parameters that are less important under those conditions.

[0064] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and various changes or modifications can be made to these embodiments without departing from the principles and essence of the present invention. The scope of protection of the present invention is defined only by the appended claims.

Claims

1. A multi-objective optimization method for high voltage silicon carbide modules, characterized in that, The method comprises the following steps, Step S1: determining module initial parameters; Step S2: establishing an electric field finite element model for the copper-clad ceramic plate in the module, and optimizing parameters related to electric field distribution of the copper-clad ceramic plate; Step S3: establishing a relationship model of electric field intensity peak value, parasitic capacitance and solder layer thermal stress and size parameters by means of electric, thermal and force finite element methods; Step S4: establishing an optimal parameter selection by means of a weighted optimization method according to the relationship model, so that the overall performance of the module is optimal; Step S5: designing a module power terminal and a shell to achieve a compromise between parasitic inductance and external insulation performance; Step S6: verifying the effectiveness of the design method by means of simulation; Step S7: verifying the performance of the module by experiment, and if the performance meets the requirements, the optimal scheme is obtained; if the performance does not meet the requirements, the process returns to step S1； The optimization target in the step S4 includes the quantified indicators of electric field intensity peak value, parasitic capacitance and solder layer thermal stress, and the mathematical model expression of the weighted design method is as follows: ； 0.1mm≤h1=h3 ≤0.3mm; 0.6mm≤h2 ≤1.0mm; 0mm≤x≤15.6mm; w1+w2+w3+w4=1; wherein the objective function is a weighted sum of the normalized parameters to obtain the final indicator, which is represented by F, and the smaller the value is, the better the performance of the module is; h1, h2 and h3 are the thicknesses of the upper metal layer, the ceramic layer and the lower metal layer respectively; x is a quantified size parameter of the shape of the lower metal layer of the copper-clad ceramic plate; CS and Cd are the parasitic capacitances of the source and the drain of the copper-clad ceramic plate to the ground respectively; Emax is the electric field intensity peak value of the copper-clad ceramic plate; sigma is the average thermal stress of the solder layer between the copper-clad ceramic plate and the substrate; the weighted factor wi is expressed by percentage, and the specific value of wi can be selected according to different application scenarios.

2. A multi-objective optimization method for high voltage silicon carbide modules according to claim 1, characterized in that: The initial parameters in the step S1 include the material of the copper-clad ceramic plate and the size parameters related to the copper-clad ceramic plate.

3. A multi-objective optimization method for high voltage silicon carbide modules according to claim 1, characterized in that: The size parameters optimized in the step S2 include the distance between the upper metal layers of the copper-clad ceramic plate and the distance between the upper metal layer and the edge of the ceramic layer of the copper-clad ceramic plate.

4. A multi-objective optimization method for high voltage silicon carbide modules as defined in claim 1, characterized in that: The size parameters in the step S3 include the shape of the lower metal layer of the copper-clad ceramic plate and the thicknesses of the upper and lower metal layers and the ceramic layer of the copper-clad ceramic plate.

5. A multi-objective optimization method for high voltage silicon carbide modules as defined in claim 1, characterized in that: In the step S4, different size parameters are brought into the corresponding quantified performance indicator calculation model, and then the indicator F representing the overall performance of the module is obtained by weighted summation, and the optimal parameter is selected as the subsequent verification parameter.

6. A multi-objective optimization method for high voltage silicon carbide modules as defined in claim 1, characterized in that: In the step S5, the length of the power terminal and the shape of the shell are mainly compromised, so that the creepage distance between the external terminal of the module and the substrate of the module meets the requirements, and the parasitic inductance is reduced as much as possible.

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