Memory device and method of operating the same

Abstract

The present invention discloses a memory device, comprising a well, a polysilicon layer, a sidewall, a dielectric layer, an alignment layer and an active region. The polysilicon layer and the sidewall are formed above the well. The dielectric layer is formed and completely covers the polysilicon layer and the sidewall. The alignment layer is formed on the dielectric layer to receive the alignment layer voltage and is substantially aligned with the dielectric layer in the projection direction. The active region is formed on the well. The dielectric layer is thicker than the alignment layer. The area of ​​the first overlapping region of the polysilicon layer and the active region is smaller than the area of ​​the second overlapping region of the first polysilicon layer and the dielectric layer excluding the first overlapping region.

Description

Technical Field

[0001] The present invention relates to a memory device and a method for operating the memory device, in particular to a memory device including an alignment layer and a method for operating the memory device including the alignment layer. Background Art

[0002] As the demand for data storage increases, the importance of memory devices also increases. A common requirement for memory devices includes reducing the size of the device so that more memory cells can be arranged in a limited area. However, based on current technology, at least two wells must be used in a memory device. For example, a current non-volatile memory device may have a select gate and a floating gate, wherein the select gate may be formed on a first well, and two portions of the floating gate may be formed on the first well and the second well, respectively. Since at least two wells must be used to construct a memory device, reducing the size of the memory is a difficult challenge. Summary of the invention

[0003] A memory device comprises a well, a polysilicon layer, a sidewall, a dielectric layer, an alignment layer and an active region. The polysilicon layer and the sidewall are formed above the well. The dielectric layer is formed and completely covers the polysilicon layer and the sidewall. The alignment layer is formed on the dielectric layer to receive an alignment layer voltage and is substantially aligned with the dielectric layer in a projection direction. The active region is formed on the well. The dielectric layer is thicker than the alignment layer. The area of ​​a first overlapping region of the polysilicon layer and the active region is smaller than the area of ​​a second overlapping region of the first polysilicon layer and the dielectric layer excluding the first overlapping region.

[0004] A method for operating a memory device. The memory device includes a well, a first polysilicon layer, a sidewall, a second polysilicon layer, a dielectric layer, an alignment layer, a first active region, and a second active region. The first polysilicon layer and the sidewall are formed above the well. The second polysilicon layer is formed above the well. The dielectric layer is formed and completely covers the first polysilicon layer and the sidewall. The alignment layer is formed on the dielectric layer and is substantially aligned with the dielectric layer in a projection direction. The first active region is formed on the well. The second active region is formed on the well and below the first polysilicon layer and the second polysilicon layer. The method includes applying a first voltage to a doped region of the first active region and applying a second voltage to a first doped region and a second doped region of the second active region when the memory device performs an erase operation. The first voltage is higher than the second voltage, and the voltage difference between the first voltage and the second voltage is less than a preset voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 1 is a top view of a memory device in an embodiment.

[0006] Figure 2 for Figure 1 A cross-sectional view of the memory device along the cutting line 2-2'.

[0007] Figure 3 for Figure 1 A cross-sectional view of the memory device along the cutting line 3-3'.

[0008] Figure 4 for Figure 1 A schematic diagram of a memory device performing an erase operation.

[0009] Figure 5 for Figure 1 A schematic diagram of a memory device performing a programming operation.

[0010] Figure 6 for Figure 1 A schematic diagram of a memory device performing a soft programming operation.

[0011] Figure 7 for Figure 1 A schematic diagram of a memory device performing a read operation.

[0012] The reference numerals are described as follows:

[0013] 100 Memory device

[0014] 102 Substrate

[0015] 105 Trap

[0016] 110,120 Polysilicon layer

[0017] 1101 Sidewall

[0018] 1201 Part

[0019] 151,152 Active Zone

[0020] 151a, 152a, 152b, 152c doping regions

[0021] 175 Dielectric layer

[0022] 180 Alignment Layer

[0023] 2-2',3-3' tangent

[0024] 252a, 252b Conductive contacts

[0025] 310,320 Trench isolation layer

[0026] 350 unit channels

[0027] A1,A2,A3 overlapping area

[0028] D1 Projection direction

[0029] V1 to V19 Voltage

[0030] VAL Alignment layer voltage

[0031] VBL bit line voltage

[0032] VEL Erase line voltage

[0033] VSL Source line voltage

[0034] VWL Word line voltage DETAILED DESCRIPTION

[0035] In order to reduce the size of the memory device, the embodiment provides a solution as described below. Herein, when describing that element A (hereinafter referred to as A) is disposed or formed on element B (hereinafter referred to as B), it means that A can be disposed or formed on the surface of B, or A can be partially or completely embedded in B. When describing that A is placed or formed in B, it means that A can be embedded in B. Herein, "polysilicon" (poly) can be polycrystalline silicon (polycrystalline silicon). Herein, when describing that a first value (hereinafter referred to as X) is substantially equal to a second value (hereinafter referred to as Y), the difference between X and Y is not greater than 15% of each of X and Y.

[0036] Figure 1 FIG. 1 is a top view of a layout of a memory device 100 in an embodiment. Figure 2 for Figure 1 A cross-sectional view of the memory device 100 along the cutting line 2 - 2 ′. Figure 3 for Figure 1 A cross-sectional view of the memory device 100 along the cutting line 3 - 3 ′.

[0037] Figure 1 The memory device 100 includes four memory devices with a related layout and symmetrical structure. Figure 1 Herein, since the structures and operation principles of other memory devices are similar, only the memory device 100 is described.

[0038] like Figures 1 to 3 As shown, the memory device 100 may include a well 105 , a polysilicon layer 110 , another polysilicon layer 120 , a sidewall (spacer) 1101 , a dielectric layer 175 , an alignment layer 180 , an active region 151 , and another active region 152 .

[0039] Well 105 may be formed on substrate 102. For example, well 105 may be an n-type well. Polysilicon layer 110 and sidewall 1101 may be formed above well 105. Dielectric layer 175 may be formed above polysilicon layer 110 and sidewall 1101, and dielectric 175 completely covers polysilicon layer 110 and sidewall 1101. Sidewall 1101 may have one or two layers, one layer of sidewall may be composed of oxide layer, and the second layer of sidewall may be composed of oxide layer and nitride layer. Figure 2 The sidewall of the second layer is taken as an example. The alignment layer 180 can be formed on the dielectric layer 175 to receive the alignment layer voltage VAL and is substantially aligned with the dielectric layer 175 in the projection direction D1. In other words, the alignment layer 180 and the dielectric layer 175 can cover the same area. The projection direction D1 can be an upward viewing direction. The alignment layer 180 can be a polysilicon layer formed using the same mask used to form the dielectric layer 175. The dielectric layer 175 can be a resist protection oxide (RPO) layer or a silicide blocking layer (SAB) layer. The active region 151 can be formed on the well 105. The area of ​​the overlapping region A1 of the polysilicon layer 110 and the active region 151 can be smaller than the area of ​​the overlapping region A2 of the polysilicon layer 110 and the dielectric layer 175 except the overlapping region A1. In addition, the area of ​​the overlapping region A1 between the polysilicon layer 110 and the active region 151 is smaller than the area of ​​the overlapping region A3 between the polysilicon layer 110 and the active region 152 .

[0040] The active region 152 may be formed on the well 105, the polysilicon layer 110 may be formed above the active region 152, and the polysilicon layer 120 may be formed above the well 105 and the active region 152. Figure 1 and Figure 2 As shown, the dielectric layer 175 and the alignment layer 180 may overlap the portion 1201 of the polysilicon layer 120. According to an embodiment, the dielectric layer 175 and the alignment layer 180 may not overlap the polysilicon layer 120, but if the dielectric layer 175 and the alignment layer 180 extend appropriately, it helps stabilize the structure. By overlapping the dielectric layer 175 and the alignment layer 180 with the polysilicon layer 120, reliability can be improved without increasing the area of ​​the memory device.

[0041] The dielectric layer 175 may be thicker than the alignment layer 180 to avoid electrical shorting between the alignment layer 180 and the polysilicon layer 110. The polysilicon layer 110 and the polysilicon layer 120 may both be thicker than the dielectric layer 175. For example, the thickness of the polysilicon layer 110 and the polysilicon layer 120 may be 220 nanometers (nm), the thickness of the dielectric layer 175 may be 100 nm, and the thickness of the alignment layer 180 may be 30 to 40 nm, which are examples only and do not limit the scope of the embodiment.

[0042] like Figures 1 to 3 As shown, the active region 151 may include a doped region 151a of a first conductivity type, and the active region 152 may include a doped region 152a and a doped region 152b of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. For example, the first conductivity type may be N+ type, and the second conductivity type may be P+ type. Figure 2 As shown, the active region 152 may further include a doped region 152 c , and the doped region 152 c may not be used to receive an external voltage.

[0043] like Figure 3 As shown, two trench isolation layers 310 and 320 may be formed on the well 105 below the polysilicon layer 110 (floating gate layer), and a cell channel 350 may be located between the trench isolation layers 310 and 320. The trench isolation layers 310 and 320 may be used to reduce electrical interference and prevent leakage current, and the trench isolation layers 310 and 320 may be shallow trench isolations (STIs).

[0044] In the above structure, the polysilicon layer 110 and the polysilicon layer 120 may be respectively the floating gate layer and the select gate layer of the memory device 100. With respect to the structure and operating voltage of the memory device 100, the polysilicon layer 120 may be coupled to the word line and used to receive the word line voltage VWL, the doped region 151a of the active region 151 may be coupled to the erase line and used to receive the erase line voltage VEL, the doped region 152a of the active region 152 may be coupled to the source line and used to receive the source line voltage VSL, and the doped region 152b of the active region 152 may be coupled to the bit line and used to receive the bit voltage VBL.

[0045] Figure 2 In the embodiment, a conductive contact 252a can be electrically connected to the doped region 152a to transmit a source line voltage VSL, and a conductive contact 252b can be electrically connected to the doped region 152b to transmit a bit line voltage VBL. Figure 1 The small squares can be conductive contacts for applying voltage.

[0046] Regarding the size of the memory device 100, since the memory device 100 includes the alignment layer 180, the above-mentioned alignment layer voltage VAL can be applied to the alignment layer 180. When performing an erase operation, the alignment layer voltage VAL can be set to a predetermined voltage (e.g., a zero voltage or a negative voltage), and the voltage difference between the floating gate layer (e.g., the polysilicon layer 110) and the doped region 152b can cause the electrons stored in the floating gate to be pulled out. Therefore, it is no longer necessary to use an active region formed in the second well (different from the well 105) to apply an erase line voltage. In other words, according to an embodiment, only one well is used instead of two wells. Therefore, the size of the memory device can be effectively reduced, and the related operations are described as follows.

[0047] The operating voltages applied to the memory device 100 may be as described in Table 1 below. The erase line voltage VEL, source line voltage VSL, bit line voltage VBL, word line voltage VWL, and alignment layer voltage VAL mentioned in Table 1 may be as described above and Figures 1 to 3 As described above, any two of the erase operation, soft program operation, program operation and read operation are not performed at the same time, and only one operation is performed at one time.

[0048]

[0049] (In Table 1, the voltage and time in brackets are for example only, and the embodiments are not limited thereto)

[0050] The above erase operation, program operation, soft program operation and read operation can be as follows: Figures 4 to 7 The invention relates to a method for performing an erase operation, a program operation, a soft program operation and a read operation.

[0051] (1) Erase operation:

[0052] Figure 4 for Figure 1 Schematic diagram of a memory device 100 performing an erase operation. According to an embodiment, the erase operation may be performed using Fowler-Nordheim (FN) tunneling, such as Figures 1 to 4 As shown in Table 1, when the memory device 100 performs an erase operation, the erase line voltage VEL, the source line voltage VSL, the bit line voltage VBL, the word line voltage VWL and the alignment layer voltage VAL may be respectively voltage V1, voltage V2, voltage V2, voltage V4 and voltage V3 as shown in Table 1. Voltage V1 may be higher than voltage V2, and the voltage difference between voltage V1 and voltage V2 may be less than a preset voltage. For example, the preset voltage may be a junction breakdown voltage to avoid junction breakdown. Voltage V3 may be lower than or equal to zero voltage. Voltage V2 and voltage V4 may be lower than voltage V1. Voltage V2 may selectively be substantially equal to voltage V4.

[0053] like Figure 1As shown, the erase line voltage VEL (e.g., voltage V1) can be set higher to pull up the voltage level of the floating gate layer (e.g., polysilicon layer 110) through the coupling effect; and the alignment layer voltage VAL (e.g., voltage V3) can be set lower to pull down the voltage level of the floating gate layer through the coupling effect. Because the area of ​​the overlapping region A1 between the polysilicon layer 110 and the active region 151 is smaller than the area of ​​the overlapping region A2 between the polysilicon layer 110 and the dielectric layer 175 except the overlapping region A1, the influence of the alignment layer 180 on the floating gate layer (e.g., polysilicon layer 110) can be greater than the influence of the active region 151 on the floating gate layer. For example, if the ratio of overlapping area A1 and overlapping area A2 minus overlapping area A1 is 5 to 95, the erase voltage VEL (for example, voltage V1) is 16 volts, and the alignment layer voltage VAL (for example, voltage V3) is 0 volts, then the voltage level of the floating gate layer can be calculated as 16 volts*5%+0 volts*95%=0.8 volts.

[0054] In this case, because the voltage difference (e.g., 15.2 volts) between the erase voltage VEL (e.g., voltage V1, 16 volts) and the voltage level of the floating gate layer (e.g., 0.8 volts calculated above) is high enough, the electrons stored in the floating gate layer can be pulled out. Therefore, the erase operation can be performed without using a memory structure with two wells.

[0055] Regarding the erase operation, a high voltage (e.g., voltage V1 in Table 1) can be applied to the junction of the well 105 as the erase line voltage VEL, which can maintain a higher bias voltage and reduce leakage. By using a lower or even negative bias voltage (e.g., voltage V3 shown in Table 1) as the alignment layer voltage VAL, the efficiency of the erase operation can be improved.

[0056] (2) Programming operation:

[0057] Figure 5 for Figure 1 Schematic diagram of a memory device 100 performing a programming operation. According to an embodiment, the programming operation may be performed by channel hot electron injection (CHEI). Figures 1 to 3 , Figure 5 As shown in Table 1, when the memory device 100 performs a programming operation, the alignment layer voltage may be voltage V5.

[0058] The voltages V8 and V6 may be selectively substantially equal to each other, and the voltages V7 , V9 , and V5 may be selectively substantially lower than the voltages V8 and V6 .

[0059] During the programming operation, the voltage V5 may rise from a first level (eg, -2 volts) to a second level (eg, 4 volts) higher than the first level. The voltage V5 may rise gradually or in a stepped waveform.

[0060] When the alignment layer voltage VAL is at a first level (e.g., a negative voltage), the channel between the doped region 152a (related to the source line) and the doped region 152b (related to the bit line) can be more conductive and increase the hole flow, thereby generating more electrons and moving these electrons into the floating gate layer. When the alignment layer voltage VAL is increased to a second level, the ability of the floating gate layer to capture electrons can be improved. Therefore, by increasing the alignment layer voltage VAL, more electrons can be moved into the floating gate layer and the performance of the programming operation can be improved.

[0061] When performing a programming operation, the source line voltage VSL may be voltage V6, the bit line voltage VBL may be voltage V7, and voltage V6 may be higher than voltage V7. The voltage difference between voltages V6 and V7 should be high enough to accelerate holes to impact the drain side of the equivalent transistor next to the source line SL, which may result in the generation of electron-hole pairs. For example, the equivalent transistor may be a P-type transistor, and the equivalent transistor next to the source line SL may be related to Figure 2 The active region 152 is shown.

[0062] When a program operation is performed, the erase line voltage VEL may be a voltage V8, the word line voltage VWL may be a voltage V9, and the voltage V8 may be higher than the voltage V9.

[0063] (3)Soft programming operation:

[0064] Figure 6 for Figure 1 Schematic diagram of the memory device 100 performing a soft programming operation. The soft programming operation can move a limited number of electrons into the floating gate layer (e.g., the polysilicon layer 110). Through the soft programming operation, the equivalent transistor of the active region 152 will not be excessively turned off, thereby reducing the failure rate of the programming operation. Therefore, the soft programming operation can be similar to the programming operation; however, during the soft programming operation, the word line voltage VWL can be adjusted to not turn on the equivalent transistor associated with the select gate.

[0065] like Figures 1 to 3 , Figure 6 As shown in Table 1, when performing a soft programming operation, the erase line voltage VEL, the source line voltage VSL, the bit line voltage VBL, the word line voltage VWL and the alignment layer voltage VAL may be voltage V10, voltage V11, voltage V12, voltage V13 and voltage V14 respectively.

[0066] As described in Table 1, voltage V12 may be lower than voltages V10, V11, V13, and V14. Voltages V10, V11, and V13 may be substantially equal. Voltages V12 and V14 may be substantially lower than or equal to voltages V10, V11, and V13.

[0067] (4) Read operation:

[0068] Figure 7 for Figure 1 Schematic diagram of a memory device 100 performing a read operation. The voltage applied during the read operation may be similar but lower than the voltage applied. Figures 1 to 3 , Figure 7 As shown in Table 1, when a read operation is performed, the erase line voltage VEL, the source line voltage VSL, the bit line voltage VBL, the word line voltage VWL, and the alignment layer voltage VAL may be voltage V15, voltage V16, voltage V17, voltage V18, and voltage V19, respectively. Voltages V15 and V16 may be higher than voltage V17. Voltages V18 and V19 may be lower than or equal to voltage V17. Voltages V15 and V16 may be substantially equal. Voltages V18 and V19 may be substantially equal.

[0069] Regarding the read operation, the bias voltage applied to the alignment layer 180 can adjust the read current, whether the voltage is a positive voltage, zero voltage, or a negative voltage.

[0070] In another embodiment, V8 can be adjusted to be equal to V5; or V10 can be adjusted to be equal to V14; or V15 can be adjusted to be equal to V18 or V19. That is, during programming operation, soft programming operation and reading operation, the erase voltage VEL and the alignment layer voltage VAL are selected to be the same voltage, so that a good operation effect can be obtained.

[0071] In summary, by using the alignment layer 180 formed on the dielectric layer 175, the alignment layer voltage VAL can be applied, and operations such as erase, program, soft program and read can be performed on the memory device 100, wherein the memory device 100 can be formed in a single well 105 instead of two wells. Since only one well is required, the size and area occupied by the memory device 100 can be effectively reduced. In the process, the alignment layer 180 and the dielectric layer 175 can be formed by the same mask, so no additional mask is required, and the process cost can be effectively controlled. Because the embodiments can provide a memory device 100 with a smaller area and a method for operating the memory device 100, it is helpful to solve the long-standing problems faced by the art.

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A memory device, characterized in that: The memory device comprises: trap; A first polysilicon layer and sidewalls are formed above the well; a dielectric layer formed to completely cover the first polysilicon layer and the sidewalls; An alignment layer, formed on the dielectric layer, for receiving an alignment layer voltage and substantially aligned with the dielectric layer in a projection direction; and A first active region formed on the well; The dielectric layer is thicker than the alignment layer, and an area of ​​a first overlapping region between the first polysilicon layer and the first active region is smaller than an area of ​​a second overlapping region between the first polysilicon layer and the dielectric layer excluding the first overlapping region.

2. The memory device according to claim 1, wherein: The memory device further includes: a second active region formed on the well; The first polysilicon layer is formed above the second active region, and an area of ​​the first overlapping region between the first polysilicon layer and the first active region is smaller than an area of ​​a third overlapping region between the first polysilicon layer and the second active region.

3. The memory device according to claim 2, wherein: The memory device further includes a second polysilicon layer formed above the well and the second active region.

4. The memory device according to claim 3, wherein: The dielectric layer and the alignment layer overlap a portion of the second polysilicon layer.

5. The memory device according to claim 3, wherein: The second polysilicon layer is used for receiving a word line voltage.

6. The memory device according to claim 3, wherein: The first polysilicon layer and the second polysilicon layer are both thicker than the dielectric layer.

7. The memory device according to claim 3, wherein: The first active region includes a doped region of a first conductivity type; and The second active region includes a first doped region and a second doped region of a second conductivity type; The second conductivity type is different from the first conductivity type.

8. The memory device according to claim 7, wherein: The doped region of the first active region is used to receive an erase line voltage, the first doped region of the second active region is used to receive a source line voltage, and the second doped region of the second active region is used to receive a bit line voltage.

9. A method of operating a memory device, characterized in that: The memory device includes a well, a first polysilicon layer and sidewalls formed above the well, a second polysilicon layer formed above the well, a dielectric layer formed and completely covering the first polysilicon layer and the sidewalls, an alignment layer formed on the dielectric layer and substantially aligned with the dielectric layer in a projection direction, a first active region formed on the well, and a second active region formed on the well and below the first polysilicon layer and the second polysilicon layer, the method comprising: When the memory device performs an erase operation, a first voltage is applied to the doped region of the first active region, and a second voltage is applied to the first doped region and the second doped region of the second active region; wherein the first voltage is higher than the second voltage, and a voltage difference between the first voltage and the second voltage is less than a preset voltage.

10. The method according to claim 9, characterized in that The preset voltage is a junction breakdown voltage.

11. The method according to claim 9, characterized in that The method further comprises: When the memory device performs the erase operation, applying a third voltage to the alignment layer; The third voltage is lower than or equal to zero voltage.

12. The method according to claim 9, characterized in that The method further comprises: When the memory device performs the erase operation, applying a fourth voltage to the second polysilicon layer; The fourth voltage is lower than the first voltage.

13. The method according to claim 12, characterized in that The second voltage is substantially equal to the fourth voltage.

14. The method according to claim 9, characterized in that The method further comprises: When the memory device performs a programming operation, applying a fifth voltage to the alignment layer; The fifth voltage is increased from a first level to a second level during the programming operation, and the second level is higher than the first level.

15. The method according to claim 14, characterized in that The method further comprises: When the memory device performs the programming operation, a sixth voltage is applied to the first doped region of the second active region, and a seventh voltage is applied to the second doped region of the second active region; The sixth voltage is higher than the seventh voltage.

16. The method according to claim 14, characterized in that The method further comprises: When the memory device performs the programming operation, an eighth voltage is applied to the doped region of the first active region, and a ninth voltage is applied to the second polysilicon layer; The eighth voltage is higher than the ninth voltage.

17. The method according to claim 9, characterized in that The method further comprises: When performing a soft programming operation on the memory device, applying a tenth voltage to the doped region of the first active region, applying an eleventh voltage to the first doped region of the second active region, applying a twelfth voltage to the second doped region of the second active region, applying a thirteenth voltage to the second polysilicon layer, and applying a fourteenth voltage to the alignment layer; The twelfth voltage is lower than the tenth voltage, the eleventh voltage, the thirteenth voltage, and the fourteenth voltage.

18. The method according to claim 9, characterized in that The method further comprises: When performing a read operation on the memory device, applying a fifteenth voltage to the doped region of the first active region, applying a sixteenth voltage to the first doped region of the second active region, applying a seventeenth voltage to the second doped region of the second active region, applying an eighteenth voltage to the second polysilicon layer, and applying a nineteenth voltage to the alignment layer; The fifteenth voltage and the sixteenth voltage are higher than the seventeenth voltage, and the eighteenth voltage and the nineteenth voltage are lower than or equal to the seventeenth voltage.

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