Non-volatile memory and data erasing method thereof

Abstract

The present application discloses a non-volatile memory and a data erasing method. The memory includes a plurality of memory blocks, the memory blocks include a plurality of levels stacked from bottom to top, the levels include a plurality of memory cells, and pseudo memory cells are arranged between adjacent levels. The method includes: applying a step-erasing voltage having a step-like rising voltage waveform to a first level of the plurality of levels to be erased; during the period when the step-erasing voltage is increased from its intermediate level to its peak level, the voltage of at least one predetermined area is increased from its starting level to its peak level, thereby generating a gate-induced drain leakage current in the first level, wherein the predetermined area is adjacent to the first level and includes at least one pseudo memory cell. By setting the predetermined area adjacent to the level to be erased and applying an auxiliary voltage to the pseudo memory cells included in the predetermined area, the gate-induced drain leakage current can be improved on the basis of maintaining the memory performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a non-volatile memory and a method for erasing data of the non-volatile memory. Background Art

[0002] Recently, non-volatile memories with memory cells stacked "vertically" (i.e., in three dimensions (3D)) are widely used in electronic devices, which generally include multiple vertically stacked levels (e.g., a top level, a middle level, and a bottom level in a non-volatile memory formed by a multi-stack process), the levels can be connected by a middle plug, and multiple vertically stacked memory cells can exist in each level. In order to effectively read, write, and erase in a non-volatile memory having multiple levels, each level can be erased separately.

[0003] In addition, as the number of stacked layers of non-volatile memory continues to increase, the hierarchical erase mechanism can be used in conjunction with the gate-induced drain leakage (GIDL) erase mechanism to improve data erase efficiency.

[0004] However, in conventional data erasing methods, the erase carriers of non-volatile memory are usually generated between the top plug of the channel structure and the top select gate transistor, while the middle plug often contains highly doped conductive impurities. Therefore, it is difficult for the erase carriers to cross the potential barrier formed by the middle plug and reach the storage cell to be operated, making it difficult to achieve effective GIDL erasing.

[0005] Therefore, how to implement efficient non-volatile memory level erase operation is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0006] In order to solve or partially solve the above-mentioned problems or other problems existing in the related art, various embodiments of the present application which will be further described below are proposed.

[0007] One aspect of the present application provides a data erasing method for a non-volatile memory, wherein the memory includes a plurality of memory blocks, the memory blocks include a plurality of levels stacked from bottom to top, each level includes a plurality of memory cells, and pseudo memory cells are arranged between adjacent levels, the method comprising: applying a step erasing voltage to a first level to be erased among the plurality of levels, the step erasing voltage having a voltage waveform that rises in a step-like manner; while the step erasing voltage increases from its intermediate level to its peak level, increasing the voltage of at least one predetermined area from its starting level to its peak level, thereby generating a gate-induced drain leakage current in the first level, wherein the predetermined area is adjacent to the first level and includes at least one of the pseudo memory cells.

[0008] According to one embodiment of the present application, a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string includes a plurality of sub-memory cell strings belonging to different levels, a bottom selection gate transistor and a top selection gate transistor, the top selection gate transistor belongs to the top selection level, the top selection level also includes a top pseudo memory cell, the method also includes: during the execution of an erase operation on the first level, applying a first voltage to the top selection level corresponding to the first level, the first voltage having a step-like rising voltage waveform; and after the step erase voltage reaches its intermediate level, raising the voltage of the bottom selection gate transistor from its starting level to its peak level, wherein the peak level of the first voltage is higher than the peak level of the step erase voltage.

[0009] According to one embodiment of the present application, a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string includes a plurality of sub-memory cell strings belonging to different levels, a bottom selection gate transistor and a top selection gate transistor, the top selection gate transistor belongs to the top selection level, the top selection level also includes a top pseudo memory cell, the method also includes: during the execution of an erase operation on the first level, applying a second voltage to the top selection level corresponding to the first level; and after the step erase voltage reaches its intermediate level, setting the top selection level to a floating state, and raising the voltage of the bottom selection gate transistor from its starting level to its peak level.

[0010] According to one embodiment of the present application, a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string also includes a bottom selection gate transistor and a top selection gate transistor, and the plurality of the memory cell strings are formed into the memory block, the memory block includes a vertically stacked bottom level, a top level and a top selection level, wherein the predetermined area includes a first predetermined area and a second predetermined area, the first predetermined area is located between the top level and the top selection level and includes at least one of the pseudo memory cells, and the second predetermined area is adjacent to the bottom selection gate transistor and includes at least one of the pseudo memory cells.

[0011] According to one embodiment of the present application, the memory cell string is formed on a well-doped region of a substrate, and the plurality of memory cells included therein are connected in series from bottom to top to the same bit line, wherein applying a step erase voltage to a first level among the plurality of levels to be erased comprises: applying the step erase voltage to the bit line and the well-doped region corresponding to the first level, respectively; and setting the memory cells of other levels except the first level to a floating state, and applying a low level to the memory cells of the first level or grounding them.

[0012] According to one embodiment of the present application, a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string also includes a bottom selection gate transistor and a top selection gate transistor, and the plurality of the memory cell strings form the memory block, the memory block includes a vertically stacked bottom level, a middle level and a top level, wherein the predetermined area includes at least a first predetermined area and a second predetermined area, when an erase operation is performed on the bottom level or the middle level, the first predetermined area is located between the top level and the middle level and includes at least one of the pseudo memory cells, and the second predetermined area is adjacent to the bottom selection gate transistor and includes at least one of the pseudo memory cells.

[0013] According to one embodiment of the present application, a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, and the plurality of the memory cell strings form the memory block, and the memory block includes a bottom level, a middle level, a top level and a top selection level vertically stacked on the substrate, wherein the predetermined area includes at least a first predetermined area and a second predetermined area, and when an erase operation is performed on the top level, the first predetermined area is located between the top level and the top selection level and includes at least one of the pseudo memory cells, and the second predetermined area is located between the top level and the middle level and includes at least one of the pseudo memory cells.

[0014] According to one embodiment of the present application, a plurality of the memory cell strings located on the well-doped region of the substrate form the memory block, and the memory block includes a vertically stacked bottom level, a middle level, a top level and the top selection level, wherein applying a first voltage to the top selection level corresponding to the first level also includes: during an erase operation on the bottom level, applying the first voltage to the memory cells of the top level, the first pseudo memory cells between the top selection level and the top level, the second pseudo memory cells between the top level and the middle level except for the predetermined area, the fourth pseudo memory cells between the middle level and the bottom level, and the third pseudo memory cells between the bottom selection gate transistor and the well-doped region of the substrate except for the predetermined area, respectively, wherein the peak level of the first voltage is higher than the peak level of the step erase voltage; and setting the memory cells of the middle level to a floating state, and applying a low level to the memory cells of the bottom level or grounding them.

[0015] According to one embodiment of the present application, a plurality of the memory cell strings located on the well doped region of the substrate are formed into the memory block, and the memory block includes a bottom level, a middle level, a top level and the top selection level which are vertically stacked, wherein a second voltage is applied to the top selection level corresponding to the first level, and after the step erase voltage reaches its intermediate level, the top selection level is set to a floating state, and further comprises: during the execution of the erase operation on the bottom level, the memory cells of the top level, the first dummy memory cells between the top selection level and the top level, and the second dummy memory cells between the top level and the middle level are respectively removed from the memory cells of the top level, A second voltage is applied to the portion outside the predetermined area, the fourth pseudo memory cell between the middle level and the bottom level, and the portion outside the predetermined area of ​​the third pseudo memory cell between the bottom selection gate transistor and the well-doped region of the substrate, and after the step erase voltage reaches its intermediate level, the memory cell of the top level, the first pseudo memory cell, the portion outside the predetermined area of ​​the second pseudo memory cell, the fourth pseudo memory cell, and the portion outside the predetermined area of ​​the third pseudo memory cell are set to a floating state; and the memory cell of the middle level is set to a floating state, and a low level is applied to the memory cell of the bottom level or it is grounded.

[0016] According to one embodiment of the present application, a plurality of the memory cell strings located on the well-doped region of the substrate form the memory block, and the memory block includes a vertically stacked bottom level, a middle level, a top level and the top selection level, wherein applying a first voltage to the top selection level corresponding to the first level also includes: during an erase operation on the middle level, applying the first voltage to the memory cells of the top level, the first pseudo memory cells between the top selection level and the top level, the second pseudo memory cells between the top level and the middle level except the predetermined area, the fourth pseudo memory cells between the middle level and the bottom level, and the third pseudo memory cells between the bottom selection gate transistor and the well-doped region of the substrate except the predetermined area, respectively, wherein the peak level of the first voltage is higher than the peak level of the step erase voltage; and setting the memory cells of the bottom level to a floating state, and applying a low level to the memory cells of the middle level or grounding them.

[0017] According to one embodiment of the present application, a plurality of the memory cell strings located on the well doped region of the substrate are formed into the memory block, and the memory block includes a bottom level, a middle level, a top level and the top selection level which are vertically stacked, wherein a second voltage is applied to the top selection level corresponding to the first level, and after the step erase voltage reaches its intermediate level, the top selection level is set to a floating state, further comprising: during the execution of the erase operation on the middle level, the memory cells of the top level, the first dummy memory cells between the top selection level and the top level, and the second dummy memory cells between the top level and the middle level are respectively removed from the memory cells of the top level, the first dummy memory cells between the top selection level and the top level, and the second dummy memory cells between the top level and the middle level. The second voltage is applied to the portion outside the predetermined area, the fourth pseudo memory cell between the middle level and the bottom level, and the portion outside the predetermined area of ​​the third pseudo memory cell between the bottom selection gate transistor and the well-doped region of the substrate, and after the step erase voltage reaches its intermediate level, the memory cells of the top level, the first pseudo memory cells, the portion outside the predetermined area of ​​the second pseudo memory cells, the fourth pseudo memory cells, and the portion outside the predetermined area of ​​the third pseudo memory cells are set to a floating state; and the memory cells of the bottom level are set to a floating state, and a low level is applied to the memory cells of the middle level or they are grounded.

[0018] According to one embodiment of the present application, a plurality of the memory cell strings are formed into the memory block, and the memory block includes a vertically stacked bottom level, a middle level, a top level and the top selection level, wherein applying the first voltage to the top selection level corresponding to the first level also includes: during the execution of the erase operation on the top level, respectively applying the first voltage to the portion of the first pseudo memory cell between the top selection level and the top level except the predetermined area, the portion of the second pseudo memory cell between the top level and the middle level except the predetermined area, the memory cell of the middle level, the fourth pseudo memory cell between the middle level and the bottom level, the memory cell of the bottom level, the bottom selection gate transistor, and the third pseudo memory cell between the bottom selection gate transistor and the well doping region, wherein the peak level of the first voltage is higher than the peak level of the step erase voltage; and applying a low level to the memory cell of the top level or grounding it.

[0019] According to one embodiment of the present application, a plurality of the memory cell strings are formed into the memory block, and the memory block includes a bottom level, a middle level, a top level and the top selection level which are vertically stacked, wherein a second voltage is applied to the top selection level corresponding to the first level, and after the step erase voltage reaches its intermediate level, the top selection level is set to a floating state, and further comprises: during the execution of the erase operation on the top level, a portion of the first pseudo memory cell between the top selection level and the top level, a portion of the second pseudo memory cell between the top level and the middle level, and a portion of the middle selection level respectively except for the predetermined area The second voltage is applied to the memory cells of the layer, the fourth pseudo memory cells between the middle layer and the bottom layer, the memory cells of the bottom layer, the bottom selection gate transistor, and the third pseudo memory cells between the bottom selection gate transistor and the well doping region, and after the step erase voltage reaches its intermediate level, the portion of the first pseudo memory cell except the predetermined area, the portion of the second pseudo memory cell except the predetermined area, the memory cells of the middle layer, the third pseudo memory cell, the memory cells of the bottom layer, and the fourth pseudo memory cells are set to a floating state; and a low level is applied to the memory cells of the top layer or they are grounded.

[0020] Another aspect of the present application provides a non-volatile memory, which includes: a memory array formed on a well-doped region of a substrate and including a plurality of memory cells, wherein a memory cell string in each column is connected to the same bit line to form a memory cell string, and a plurality of the memory cell strings are formed into a memory block, wherein the memory block includes a plurality of vertically stacked levels in a direction perpendicular to the substrate, and the memory cell string includes a plurality of sub-memory cell strings belonging to different levels; and a control circuit coupled to the memory array and configured to control level selection of the plurality of levels, and perform a level erasing operation and a gate induced drain leakage (GIDL) erasing operation on the selected level as described in any one of the data erasing methods for the non-volatile memory provided in one aspect of the present application.

[0021] According to one embodiment of the present application, the storage array is a three-dimensional NAND storage array, and the non-volatile memory is a three-dimensional NAND memory.

[0022] According to the non-volatile memory and the erasing method thereof provided in at least one embodiment of the present application, by setting a predetermined area at a level adjacent to the layer to be erased and applying a predetermined peak voltage (auxiliary voltage) to the pseudo memory cells included in the predetermined area, it is possible to improve the gate-induced drain leakage current while maintaining the overall performance of the non-volatile memory, thereby achieving efficient data erasure of the non-volatile memory.

[0023] Furthermore, in at least one embodiment of the present application, the data erasing efficiency of the non-volatile memory can be improved by applying a first voltage having a step-like rising waveform to a top selection level corresponding to the level to be erased during the execution of a hierarchical erase operation; or by applying a second voltage to the top selection level and floating it at a later stage of the erase operation (the later floating can enable the top selection level to obtain a predetermined peak voltage through voltage coupling). BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0025] Figure 1 is a block diagram of a non-volatile memory according to one embodiment of the present application;

[0026] Figure 2 is a partial structural cross-sectional view of a non-volatile memory according to an embodiment of the present application;

[0027] Figure 3 is a schematic diagram of a local equivalent circuit of a memory array according to an embodiment of the present application;

[0028] Figure 4 is a schematic diagram of a local equivalent circuit of a memory array according to an embodiment of the present application;

[0029] Figure 5 is a flow chart of a method for erasing data of a non-volatile memory according to an embodiment of the present application;

[0030] Figure 6 is a partial circuit structure diagram of a non-volatile memory according to an embodiment of the present application;

[0031] Figure 7 is a partial circuit structure diagram of a non-volatile memory according to another embodiment of the present application;

[0032] Figure 8 is a voltage waveform timing diagram for a non-volatile memory according to one embodiment of the present application;

[0033] Fig. 9 is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of the present application;

[0034] Fig.10 is a voltage waveform timing diagram for a non-volatile memory according to one embodiment of the present application;

[0035] Fig.11is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of the present application;

[0036] Fig.12 is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of the present application;

[0037] Fig.13 is a diagram showing a trend of channel potential changes of a three-dimensional memory according to an embodiment of the present application;

[0038] Fig.14 is a voltage waveform timing diagram for a non-volatile memory according to one embodiment of the present application; and

[0039] Fig.15 is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of the present application. DETAILED DESCRIPTION

[0040] Exemplary embodiments of the present invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. However, the present invention may be implemented in different forms and should not be construed as being limited to the exemplary embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0041] It should also be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on or directly connected to another element or layer, or there can be elements or layers between them. When an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" can refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0042] Throughout the specification, the same reference numerals denote the same components. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

[0043] Although the terms "first", "second", etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms can be used to distinguish one element from another element. Therefore, without departing from the teaching of one or more embodiments, the first level discussed below can be referred to as the second level. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish between different classes or groups of elements in this article. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first class (or first group)", "second class (or second group)", etc.

[0044] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. It should also be understood that when used in this specification, the term "comprising" specifies the presence of the features, regions, steps, operations, elements and / or components set forth, but does not exclude the presence or addition of one or more other features, regions, steps, operations, elements, components and / or groups thereof.

[0045] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figure. It should be understood that, in addition to the orientation depicted in the figure, relative terms are intended to include different orientations of the device. In an exemplary embodiment, when the device in one of the figures is turned over, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Therefore, depending on the specific orientation of the figure, the exemplary term "lower" can include both "lower" and "upper" orientations. Similarly, when the device in one of the figures is turned over, the element described as being "below" or "below" the other elements will then be oriented "above" the other elements. Therefore, the exemplary term "below" or "below" can include both upper and lower orientations.

[0046] Figure 1 FIG. 1 shows a block diagram of a non-volatile memory 100 according to an embodiment of the present application. Figure 1As shown, the non-volatile memory 100 includes a memory array 102 and a control circuit 101 coupled together. In some embodiments, the memory array 102 and the control circuit 101 may be arranged on the same chip. In other embodiments, the memory array 102 may be arranged on an array chip, and the control circuit 101 may be arranged on a different chip (for example, implemented using complementary metal oxide semiconductor (CMOS) technology, and referred to as a CMOS chip). The array chip and the CMOS chip may be electrically coupled together by processes such as bonding. In some embodiments, the non-volatile memory 100 is an integrated circuit (IC) package that encapsulates one or more array chips and CMOS chips.

[0047] The nonvolatile memory 100 may be configured to store data in the memory array 102 and perform operations in response to received commands (CMD). In some embodiments, the nonvolatile memory 100 may receive write commands, read commands, erase commands, etc. and may perform operations accordingly.

[0048] In one embodiment, the nonvolatile memory 100 receives an erase command with an address, and then the nonvolatile memory 100 resets one or more memory cells at the address to an unprogrammed state (or erased state), such as “1” for a NAND memory cell.

[0049] Typically, the storage array 102 may include one or more storage planes 160, and each storage plane in the storage plane 160 may include a plurality of storage blocks (e.g., Figure 1 Each storage block may also include multiple levels (e.g., Figure 1 As shown, block-1 includes level 1 to level M). In some examples, concurrent operations may occur at different storage planes 160. In some embodiments, each of level 1 to level M is a minimum unit for performing an erase operation.

[0050] In some embodiments, the memory array 102 is a flash memory array and is implemented using 3D NAND flash memory technology. In some embodiments, the peripheral circuit 101 includes a row decoder circuit 110, a page buffer circuit 120, a data input / output (I / O) circuit 130, a voltage generator 140, and a control circuit 150 coupled together. The row decoder circuit 110 can receive an address called a row address (R-ADDR), generate a word line (WL) signal and a selection signal (such as a top select gate (TSG) signal, a bottom select gate (BSG) signal, etc.) based on the row address, and provide the WL signal and the selection signal to the memory array 102. Further, during an erase operation, the row decoder circuit 110 provided in the present application can provide appropriate WL signals and selection signals.

[0051] The page buffer circuit 120 is coupled to the bit lines (BL) of the memory array 102 and is configured to buffer data during read and write operations. The data I / O circuit 130 is coupled to the page buffer circuit 120 via the data lines DL. In one example (e.g., during a write operation), the data I / O circuit 130 is configured to receive data from an external circuit of the nonvolatile memory 100 and provide the received data to the memory array 102 via the page buffer circuit 120.

[0052] The voltage generator 140 is configured to generate voltages of appropriate levels for appropriate operation of the nonvolatile memory 100. For example, during a data erase operation, the voltage generator 140 may generate voltages of appropriate levels for bit line voltages, well doping region voltages, various word line voltages, selection voltages, predetermined region voltages, etc. suitable for the erase operation. For example, during a data erase operation, a step erase voltage is provided to a well doping region of the memory array 102. A first voltage is provided to the row decoder 110, so that the row decoder 110 can output a top selection gate signal at an appropriate voltage level during the data erase operation. A peak voltage of a predetermined region is provided to the row decoder 110, so that the row decoder 110 can output a predetermined region signal at an appropriate voltage level during the data erase operation. A step erase voltage is provided to the page buffer circuit 120, so that the page buffer circuit 120 can drive the bit line (BL) at an appropriate voltage level during the erase operation. In addition, the step erase voltage may also be applied to the bit line without passing through the page buffer circuit 120.

[0053] The control circuit 150 is configured to receive a command (CMD) and an address (ADDR), and based on the command and address, provide control signals to circuits such as the row decoder circuit 110, the page buffer circuit 120, the data I / O circuit 130, the voltage generator 140, etc. For example, the control circuit 150 may generate a row address R-ADDR and a column address C-ADDR based on the address ADDR, and provide the row address R-ADDR to the row decoder 110, and provide the column address to the data I / O circuit 130. In another embodiment, the control circuit 150 may control the voltage generator 140 to generate a voltage of an appropriate level based on the received CMD. The control circuit 150 may coordinate other circuits to provide signals to the memory array 102 at appropriate times and at appropriate voltage levels.

[0054] The control circuit 150 may include a first part control circuit 155, which is configured to generate appropriate control signals to control other circuits to provide appropriate signals to the memory array 102 to perform an erase operation, which uses the hierarchical erase mechanism and the GIDL erase mechanism. In other words, the first part control circuit 155 is a control circuit for hybrid erase. Signals with appropriate timing and voltage levels for the memory array 102 can apply the hierarchical erase mechanism and the GIDL erase mechanism to the data erase operation of the non-volatile memory. This application will refer to Figures 5 to 15 The waveform of the signal is described in detail below.

[0055] Figure 2 FIG. 2 shows a partial structural cross-sectional view of a non-volatile memory 200 according to an embodiment of the present application. Figure 2 As shown, in one embodiment of the present application, the nonvolatile memory 200 may include a three-dimensional memory array chip 202 and a peripheral circuit chip 201 electrically coupled together by a process such as bonding.

[0056] In some embodiments, the nonvolatile memory 200 may include a plurality of array chips 202 and a peripheral circuit chip 201. The array chip 202 includes a substrate 203 and a stacked structure 290 formed on the substrate 203. The peripheral circuit chip 201 includes a substrate and a peripheral circuit formed on the substrate. For simplicity, the main surface of the substrate 203 is referred to as an XY plane, and the direction perpendicular to the main surface is referred to as a Z direction.

[0057] The substrate 203 and the substrate of the peripheral circuit chip 201 may be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate and / or a silicon on insulator (SOI) substrate. In other words, the substrate 203 and the substrate of the peripheral circuit chip 201 may include semiconductor materials, such as IV group semiconductors, III-V group compound semiconductors or II-VI group oxide semiconductors. IV group semiconductors may include Si, Ge or SiGe. As an option, the substrate 203 and the substrate of the peripheral circuit chip 201 may also be a bulk wafer or an epitaxial layer, respectively.

[0058] The stacked structure 290 includes alternately stacked gate layers 295 and insulating layers 294. The gate layer 295 is made of a gate stack material such as a high dielectric constant (high-k) gate insulator layer and a metal gate (MG) electrode. The insulating layer 294 is made of an insulating material such as silicon nitride, silicon dioxide, etc. The gate layer 295 and the insulating layer 294 are configured to form a vertically stacked transistor in the Z direction, and the gate layer 295 corresponds to the gate of the transistor.

[0059] The nonvolatile memory 200 may include a memory cell array and peripheral circuits (e.g., a row decoder circuit 110, a page buffer circuit 120, a data I / O circuit 130, a voltage generator 140, a control circuit 150, etc.). The peripheral circuit is formed in a peripheral circuit chip 201, and the memory cell array is formed in an array chip 202. The array chip 202 may include a core region 01 and a staircase region 02, the memory cell array is formed in a portion of a stacked structure 290 located in the core region 01, and includes a plurality of vertical memory cell strings 280. The staircase region 02 may facilitate, for example, connection with the gates of memory cells in the memory cell string 280, the gates of a select gate transistor, and the like. The gates of the memory cells in the memory cell string 280 correspond to word lines in a memory architecture.

[0060] The memory cell string 280 is formed by a channel structure 281 penetrating the stacked structure 290 and extending vertically (along the Z direction) into the substrate 203. In other words, the channel structure 281 and the stacked structure 290 together form the memory cell string 280.

[0061] The channel structure 281 may include a functional layer and a semiconductor layer having a circular shape on the XY plane and extending to the substrate 203 in the Z direction, and the functional layer may include a blocking insulating layer (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride), and a tunneling insulating layer (e.g., silicon oxide). The semiconductor layer may be prepared from any appropriate semiconductor material (such as polycrystalline silicon or single crystal silicon), and the semiconductor material may be selected to be undoped, or may also be selected to include P-type or N-type doped impurities. In one embodiment, a blocking insulating layer may be formed on the sidewall of a hole for the channel structure 281 (the hole may penetrate the stacked structure 290 and extend into the substrate 203), and then a charge storage layer, a tunneling insulating layer, a semiconductor layer, and an insulating filling layer are sequentially stacked from the sidewall. The insulating filling layer may be formed of an insulating material such as silicon oxide and / or silicon nitride, and / or may be formed as an air gap.

[0062] The substrate 203 may include a well-doped region, such as a highly doped semiconductor layer 205 (or referred to as a well-doped region 205), for forming an electrical connection with the semiconductor layer in the channel structure 281. As an option, the semiconductor layer 205 may be electrically connected to the bottom of the semiconductor layer in the channel structure 281. As another option, the semiconductor layer 205 may be electrically connected to the sidewall of the semiconductor layer in the channel structure 281, or may be electrically connected to the bottom and sidewall of the semiconductor layer in the channel structure 281.

[0063] The semiconductor layer 205 may be formed as a source conductive connection of the memory cell string 280. The semiconductor layer 205 may include one or more layers. The semiconductor layer 205 may be made of, for example, silicon material, such as intrinsic polysilicon, doped polysilicon (such as N-type doped silicon or P-type doped silicon, etc.). As an option, the semiconductor layer 205 may also include a metal silicide to improve conductivity. The semiconductor layer 205 is similarly conductively connected to the source of other memory cell strings 280, and thus forms an array common source (ACS). In some embodiments, when the memory cell string 280 is configured to be erased by level, the semiconductor layer 205 may extend and cover the core area and the step area of ​​the memory block to which the level belongs.

[0064] In some embodiments, the vertically stacked transistor formed by the gate layer 295 and the insulating layer 294 may include a memory cell (or may be referred to as a memory cell transistor) and a select gate transistor (e.g., one or more bottom select gate transistors, or one or more top select gate transistors, etc.). The semiconductor layer of the channel structure 281 corresponds to the channel portion of the transistor in the memory cell string 280, and the gate layer 295 corresponds to the gate of the transistor in the memory cell string 280.

[0065] The memory cell may have different threshold voltages based on carrier capture in a portion of the charge storage layer of the channel structure 281, which corresponds to the floating gate of the memory cell. For example, when a large number of holes are captured (stored) in the floating gate of the memory cell transistor, the threshold voltage of the memory cell transistor is lower than a predefined value, and the memory cell transistor is in an unprogrammed state (also referred to as an erased state) corresponding to logic "1". When holes are discharged from the floating gate, the threshold voltage of the memory cell is higher than a predefined value, so the memory cell transistor is in a programmed state corresponding to logic "0".

[0066] Typically, a transistor includes a gate for controlling a channel and has a drain and a source on each side of the channel. As an option, the upper side of the channel of the transistor can be called the drain, and the lower side of the channel of the transistor can be called the source. As another option, the drain and source can be swapped under certain drive configurations. In addition, the top select gate transistor can be connected to the drain above it, and the bottom select gate transistor can be connected to the source below it.

[0067] One or more top select gate transistors are configured to couple / decouple memory cells in the memory cell string 280 to a bit line. One or more bottom select gate transistors are configured to couple / decouple memory cells in the memory cell string 280 to an ACS (common source line).

[0068] The bottom select gate transistor is controlled by the bottom select gate. For example, when the bottom select gate voltage (the voltage applied to the bottom select gate) is greater than the threshold voltage of the bottom select gate transistor, the bottom select gate transistor is turned on, and the memory cell is coupled to the ACS. When the bottom select gate voltage is less than the threshold voltage of the bottom select gate transistor, the bottom select gate transistor is turned off, and the memory cell is decoupled from the ACS. Similarly, the top select gate transistor is controlled by the top select gate.

[0069] In some embodiments, the channel structure 281 has a circular shape in the XY plane and a columnar shape in the XZ plane and the YZ plane. In the XY plane, a plurality of channel structures 281 may be arranged separately from each other and form a memory cell array. The array of the channel structure 281 may have any appropriate array shape, such as a matrix array shape along the X direction and the Y direction, a sawtooth array shape along the X or Y direction, a honeycomb (e.g., hexagonal) array shape, etc. The memory cell array may be divided into a plurality of memory blocks by a gate line gap structure 270 having a spacing with the channel structure 281 in the X direction. Each memory block includes a plurality of levels stacked from bottom to top (Z direction). In other words, a plurality of memory cell strings 280 are formed as memory blocks, and the memory blocks include a plurality of vertically stacked levels in a direction perpendicular to the substrate 203 (Z direction), so that the memory cell string 280 may include a plurality of sub-memory cell strings belonging to different levels.

[0070] In some embodiments, a redundant layer is provided between the multiple levels, and the redundant layer includes at least one dummy memory cell. The dummy memory cell and the memory cell are prepared simultaneously, and can be used for process and electrical buffering.

[0071] Figure 3 A partial equivalent circuit diagram of a memory array 300 according to an embodiment of the present application is shown. Figure 4 A partial equivalent circuit diagram of a memory array 400 according to an embodiment of the present application is shown.

[0072] like Figure 3As shown, as an example, the three-dimensional memory device 300 may be divided into a plurality of memory blocks, each memory block including two levels, such as a top level 452 and a bottom level 450. The three-dimensional memory device 300 may also include a memory string 212 having a plurality of stacked memory cells 340, and the memory cell string 212 may include a plurality of sub-memory cell strings belonging to different levels, wherein a sub-memory cell string formed by a plurality of memory cells 340-1 is in the bottom level 450, and a sub-memory cell string formed by a plurality of memory cells 340-2 is in the top level 452. The three-dimensional memory device 300 also includes a conductive plug 460 between the top level 452 and the bottom level 450. Therefore, in the three-dimensional memory device 300 having a plurality of levels, the memory cell 340-2 in the top level 452 may be electrically connected to the memory cell 340-1 in the bottom level 450 to form the memory string 212. The memory string 212 may also include at least one field effect transistor (e.g., MOSFET) at each end, which is controlled by a bottom select gate 332 and a top select gate 334, respectively. The two corresponding transistors are referred to as a bottom select gate transistor 332-T and a top select gate transistor 334-T. The stacked memory cell 340 may be controlled by a control gate 333, which includes a control gate 333-1 corresponding to the memory cell 340-1 and a control gate 333-2 corresponding to the memory cell 340-2, wherein the control gate 333 is connected to a word line (not shown) of the three-dimensional memory device 300. The drain terminal of the top select gate transistor 334-T may be connected to the bit line 341, and the source terminal of the bottom select gate transistor 332-T may be connected to a well doped region, and the ACS464 may be formed from the well doped region and may be shared by the memory string 212 in the entire memory block.

[0073] Furthermore, the present application also provides a three-dimensional memory including storage blocks at a top level, a middle level, and a bottom level.

[0074] like Figure 4As shown, as an example, the three-dimensional memory device 400 may be divided into a plurality of memory blocks, each memory block including three levels, such as a top level 452, a middle level 454, and a bottom level 450. The three-dimensional memory device 500 may also include a memory string 212 having a plurality of stacked memory cells 340, and the memory cell string 212 may include a plurality of sub-memory cell strings belonging to different levels, wherein a sub-memory cell string formed by a plurality of memory cells 340-1 is in the bottom level 450, a sub-memory cell string formed by a plurality of memory cells 340-3 is in the middle level 454, and a sub-memory cell string formed by a plurality of memory cells 340-2 is in the top level 452. The three-dimensional memory 500 also includes a conductive plug, such as a conductive plug 460 between the top level 452 and the middle level 454. Therefore, in the three-dimensional memory device 500 having multiple levels, the memory cell 340-2 in the top level 452 can be electrically connected to the memory cell 340-3 in the middle level 454, and the memory cell 340-1 in the bottom level 450 to form a memory string 212. The memory string 212 may also include at least one field effect transistor (e.g., MOSFET) at each end, which is controlled by the lower selection gate 332 and the top selection gate 334, respectively. And the two corresponding transistors are referred to as the lower selection gate transistor 332-T and the top selection gate transistor 334-T. The stacked memory cells 340 may be controlled by the control gates 333, which include a control gate 333-1 corresponding to the memory cell 340-1, a control gate 333-3 corresponding to the memory cell 340-3, and a control gate 333-2 corresponding to the memory cell 340-2, wherein the control gates 333 are connected to word lines (not shown) of the three-dimensional memory device 500. The drain terminal of the top select gate transistor 334-T may be connected to the bit line 341, and the source terminal of the lower select gate transistor 332-T may be connected to the doped source line region 344 from which the ACS 464 may be formed and which may be shared by the memory strings 212 in the entire memory block.

[0075] In a non-volatile memory, the memory cells of each row in each level are connected to the same word line WL, and the memory cell strings in each column are connected to the same bit line BL. Each word line may correspond to a page, and a plurality of pages may form a memory block, and a plurality of memory blocks may form a plane. Furthermore, in a non-volatile memory having multiple levels, each level may be processed separately for efficient reading, writing, and erasing. For example, each level in a three-dimensional non-volatile memory may perform an erase operation independently of other levels. In addition, read and write operations may also be performed in a memory page including memory cells sharing the same word line.

[0076] The above describes a three-dimensional non-volatile memory structure including two levels or three levels. The following describes in detail a data erasing method for the above three-dimensional non-volatile memory provided by an embodiment of the present application in conjunction with the accompanying drawings.

[0077] Figure 5 FIG. 1 is a flow chart of a method 1000 for erasing data from a nonvolatile memory according to an embodiment of the present application. Figure 5 As shown, the data erasure verification method 1000 of the non-volatile memory includes:

[0078] In step S1 , a step-erase voltage is applied to a first level among multiple levels to be erased, wherein the step-erase voltage has a voltage waveform that rises in a step shape.

[0079] Step S2, during the period when the step erase voltage is increased from its intermediate level to its peak level, the voltage of at least one predetermined region is increased from its starting level to its predetermined peak level, thereby generating a gate induced drain leakage current in the first level, the predetermined region being adjacent to the first level and including at least one dummy memory cell.

[0080] Each of the above steps will be described in detail below so that those skilled in the art can more clearly understand the specific implementation of the above method 1000.

[0081] Step S1

[0082] Figure 6 It is a partial circuit structure diagram of a non-volatile memory according to one embodiment of the present application. Figure 7 is a partial circuit structure diagram of a non-volatile memory according to another embodiment of the present application.

[0083] In step S1, the non-volatile memory may include a plurality of storage blocks, such as Figure 6 As shown, the memory block may include a memory cell string 212 consisting of a top level 452 and a bottom level 450. As an alternative, Figure 7 As shown, the memory block may also include a memory cell string 212 composed of memory cells in a top level 452, a middle level 454, and a bottom level 450. Any level in the above-mentioned memory strings 212 to be erased may be selected as the first level for performing a level erase operation. The level erase operation refers to performing an erase operation on only at least one level of the memory block, rather than performing an erase operation on all memory strings.

[0084] Combination Figure 6 and Figure 7In one embodiment of the present application, the memory cell string 212 includes a memory cell, a top selection gate transistor 334-T and a bottom selection gate transistor 332-T, wherein TSG represents an electrical signal applied to a top selection gate for controlling the top selection gate transistor 334-T, and BSG represents an electrical signal applied to a bottom selection gate for controlling the bottom selection gate transistor 332-T.

[0085] Furthermore, a redundant layer is provided between the multiple levels, and the redundant layer includes at least one dummy memory cell DMY. The dummy memory cell and the memory cell are prepared at the same time, and can be used for process and electrical buffering. For example, in one embodiment of the present application, the memory cell string 212 includes three top-level selection gate transistors 334-T, and the three top-level selection gate transistors 334-T can form a top-level selection level. As an option, the top-level selection level may include at least one top-level selection gate transistor 334-T, and the number of corresponding top-level selection gate transistors 334-T is not limited in the present application. In addition, the top-level selection level also includes at least one top-level dummy memory cell 334', and the top-level dummy memory cell 334' and the top-level selection gate transistor 334-T are prepared at the same time and used for process and electrical buffering, wherein TSG_DMY represents the electrical signal applied to the gate of the top-level dummy memory cell 334'.

[0086] In addition, a redundant layer including at least one first pseudo memory cell 452' is provided between the top level 452 and the top selection level. The pseudo memory cells and memory cells in the redundant layer are prepared simultaneously, and can be used for process and electrical buffering. GIDL_T represents an electrical signal applied to a predetermined area of ​​the redundant layer to which the first pseudo memory cell 452' belongs. In other words, when an erase operation is performed on a level (e.g., the top level) adjacent to the predetermined area, an electrical signal of GIDL_T may be applied to the predetermined area in the redundant layer, and a first voltage or a second voltage (which will be described in detail later) may be applied to the first pseudo memory cell 452' in the redundant layer except for the predetermined area.

[0087] like Figure 7As shown, a redundant layer including at least one second dummy memory cell 452" and a redundant layer including at least one second dummy memory cell 454' are also provided between the top level 452 and the middle level 454. The dummy memory cells and the memory cells in the above redundant layer are prepared at the same time and can be used for process and electrical buffering. GIDL_M1 represents an electrical signal applied to a predetermined area of ​​the redundant layer to which the second dummy memory cell 452" belongs. In other words, when an erase operation is performed on a layer (e.g., a top layer) adjacent to the predetermined area, an electrical signal of GIDL_M1 may be applied to the predetermined area in the redundant layer, and a first voltage or a second voltage (which will be described in detail later) may be applied to the second pseudo memory cell 452″ in the redundant layer except the predetermined area. GIDL_M0 represents an electrical signal applied to a predetermined area of ​​the redundant layer to which the second pseudo memory cell 454′ belongs. In other words, when an erase operation is performed on a layer (e.g., a bottom layer or a middle layer) adjacent to the predetermined area, an electrical signal of GIDL_M0 may be applied to the predetermined area in the redundant layer, and a first voltage or a second voltage (which will be described in detail later) may be applied to the second pseudo memory cell 454′ in the redundant layer except the predetermined area.

[0088] A redundant layer including at least one third pseudo memory cell 205' is also provided between the bottom selection gate transistor 332-T and the well doping region 205 of the substrate. The pseudo memory cells and memory cells in the redundant layer are prepared simultaneously and can be used for process and electrical buffering. GIDL_B represents an electrical signal applied to a predetermined area of ​​the redundant layer to which the third pseudo memory cell 205' belongs. In other words, when an erase operation is performed on a layer (e.g., a bottom layer or a middle layer) adjacent to the predetermined area, an electrical signal of GIDL_B may be applied to the predetermined area in the redundant layer, and a first voltage or a second voltage (which will be described in detail later) may be applied to the third pseudo memory cell 205' in the redundant layer except for the predetermined area.

[0089] In addition, a redundancy layer including at least one fourth dummy memory cell 450' is disposed between the middle level 454 and the bottom level 450. The dummy memory cells and memory cells in the redundancy layer are fabricated simultaneously and used for process and electrical buffering.

[0090] Figure 8 1 is a voltage waveform timing diagram for a non-volatile memory according to one embodiment of the present application. Fig. 9 is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of the present application. Fig.10 1 is a voltage waveform timing diagram for a non-volatile memory according to one embodiment of the present application. Fig.11 is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of the present application. Fig.12is a voltage waveform timing diagram for a non-volatile memory according to yet another embodiment of the present application.

[0091] The erasing method of the non-volatile memory provided in the present application can improve the gate-induced drain leakage current while maintaining the overall performance of the non-volatile memory, thereby achieving efficient data erasure of the non-volatile memory by setting a predetermined area adjacent to the level where the erasing operation is to be performed and applying a predetermined peak voltage (auxiliary voltage) to the pseudo storage cells included in the predetermined area.

[0092] Specifically, Figures 6 to 12 As shown, a step erase voltage with a step-shaped rising voltage waveform may be applied to the first level of the plurality of to-be-erased operations. For example, the step erase voltage electrical signal may be applied to the bit line 341 and the well doped region 205 corresponding to the first level, respectively.

[0093] by Figure 8 As shown in the example, BL represents the electrical signal applied to the bit line 341. HVNW represents the electrical signal applied to the well doping region 205. The step erase voltage has a step-shaped voltage waveform, the first step spans the time period from T0 to T2, and the voltage rises from the starting level to the intermediate level Vepre. The second step spans the time period from T2 to T3, and the voltage rises from the intermediate level Vepre to the peak level Vers. The value of the intermediate level Vepre can be selected, for example, between 1 volt and 4 volts. The value of the peak level Vers can be selected, for example, between 16 volts and 22 volts, and the time period from T2 to T3 is approximately between 0.4 milliseconds and 0.9 milliseconds.

[0094] In addition, WLs represents an electrical signal applied to the gate of the storage unit included in each level. When performing a data erase operation, the gate of the storage unit included in the first level to be erased should also be grounded or connected to a low level. At the same time, the gates of the storage units included in other levels that are not erased are set to a floating state. When the circuit structure of other levels that are not erased is in a floating state, it does not assume the circuit interconnection function. It will be understood by those skilled in the art that in this specification, when an element (or component, assembly, member, etc.) is referred to as being in a floating state, it is intended to explain that the element (or component, assembly, member, etc.) does not form an electrical path with other elements (or components, assemblies, members, etc.).

[0095] Step S2

[0096] Combination Figure 6 , Figure 8 ,and Fig. 9Step S2, during the period when the step erase voltage is increased from its intermediate level to its peak level, increases the voltage of at least one predetermined region from its starting level to its peak level, thereby generating a gate induced drain leakage current in the first level, the predetermined region being adjacent to the first level and including at least one dummy memory cell, may for example include the following:

[0097] In one embodiment of the present application, Figure 6 and Figure 8 , the storage block formed by the plurality of storage cell strings 212 includes only the bottom level 450 and the top level 452. When the bottom level 450 is subjected to a data erasing operation, the predetermined area may include a first predetermined area and a second predetermined area. The first predetermined area may be selected in a redundant layer between the top level 452 and the top selection level, and include at least one first dummy storage cell 452'; and the second predetermined area may be selected in a redundant layer adjacent to the bottom selection gate transistor 332-T, and include at least one third dummy storage cell 205'.

[0098] During the period T2 to T3 when the electrical signals BL and HVNW increase from their intermediate levels Vepre to their peak levels Vers, electrical signals GIDL_T and GIDL_B may be applied to the first predetermined region and the second predetermined region, respectively, to increase them from their starting levels to their peak levels Vgid1. As an option, the starting levels of the first predetermined region and the second predetermined region may be 0 volts, and the peak level Vgid1 may be selected, for example, between 8 and 15 volts.

[0099] In one embodiment of the present application, Figure 6 and Fig. 9 , the storage block formed by the plurality of storage cell strings 212 includes only the bottom level 450 and the top level 452. When the data erasing operation is performed on the top level 452, the predetermined area may include a first predetermined area and a second predetermined area. The first predetermined area may be selected in a redundant layer between the top level 452 and the top selection level, and include at least one first dummy storage cell 452'; and the second predetermined area may be selected in a redundant layer adjacent to the bottom selection gate transistor 332-T, and include at least one third dummy storage cell 205'.

[0100] During the period T2 to T3 when the electrical signals BL and HVNW increase from their intermediate levels Vepre to their peak levels Vers, electrical signals GIDL_T and GIDL_B may be applied to the first predetermined region and the second predetermined region, respectively, to increase them from their starting levels to their peak levels Vgid1. As an option, the starting levels of the first predetermined region and the second predetermined region may be 0 volts, and the peak level Vgid1 may be selected, for example, between 8 and 15 volts.

[0101] Combination Figure 7 , Fig.10 , Fig.11 and Fig.12 , when the memory block formed by the plurality of memory cell strings 212 includes only the bottom level 450, the middle level 454, and the top level 452, step S2 increases the voltage of at least one predetermined region from its starting level to its peak level during the period when the step erase voltage increases from its intermediate level to its peak level, thereby generating a gate induced drain leakage current in the first level, the predetermined region being adjacent to the first level and including at least one dummy memory cell may, for example, include the following:

[0102] In one embodiment of the present application, Figure 7 and Fig.10 When the data is erased on the lower level 450, the predetermined area may include at least a first predetermined area and a second predetermined area. The first predetermined area may be selected between the top level 452 and the middle level 454 and include at least one second dummy memory cell 454'; and the second predetermined area may be selected in a redundant layer adjacent to the bottom selection gate transistor 332-T and include at least one third dummy memory cell 205'.

[0103] During the period T2 to T3 when the electrical signals BL and HVNW increase from their intermediate levels Vepre to their peak levels Vers, electrical signals GIDL_M0 and GIDL_B may be applied to the first predetermined region and the second predetermined region, respectively, to increase them from their starting levels to their peak levels Vgid1. As an option, the starting levels of the first predetermined region and the second predetermined region may be 0 volts, and the peak level Vgid1 may be selected, for example, between 8 and 15 volts.

[0104] In one embodiment of the present application, Figure 7 and Fig.11 When the data is erased on the top level 452, the predetermined area may include at least a first predetermined area and a second predetermined area. The first predetermined area may be selected between the top level 452 and the middle level 454 and include at least one second dummy memory cell 454'; and the second predetermined area may be selected in a redundant layer adjacent to the bottom selection gate transistor 332-T and include at least one third dummy memory cell 205'.

[0105] During the period T2 to T3 when the electrical signals BL and HVNW increase from their intermediate levels Vepre to their peak levels Vers, electrical signals GIDL_M0 and GIDL_B may be applied to the first predetermined region and the second predetermined region, respectively, to increase them from their starting levels to their peak levels Vgid1. As an option, the starting levels of the first predetermined region and the second predetermined region may be 0 volts, and the peak level Vgid1 may be selected, for example, between 8 and 15 volts.

[0106] In one embodiment of the present application, Figure 7 and Fig.12 When the data erasing operation is performed on the top level 452, the predetermined area may include at least a first predetermined area and a second predetermined area. The first predetermined area may be selected in a redundant layer between the top level 452 and the top selection level, and include at least one first dummy storage unit 452'; and the second predetermined area may be selected between the top level 452 and the middle level 454, and include at least one second dummy storage unit 452".

[0107] During the period T2 to T3 when the electrical signals BL and HVNW increase from their intermediate levels Vepre to their peak levels Vers, electrical signals GIDL_T and GIDL_M1 may be applied to the first predetermined region and the second predetermined region, respectively, to increase them from their starting levels to their peak levels Vgid1. As an option, the starting levels of the first predetermined region and the second predetermined region may be 0 volts, and the peak level Vgid1 may be selected, for example, between 8 and 15 volts.

[0108] Fig.13 1 is a graph showing a trend of channel potential variation of a three-dimensional memory according to an embodiment of the present application. Fig.13 As shown, after the above operation, by applying the step erasing voltage shown in curve 10 to the bit line and the well doping region respectively, and applying the auxiliary erasing voltage with a peak level of Vgid1 to at least one dummy memory cell in the predetermined region, a channel potential shown in curve 11 can be formed, and the holes (such as Figure 6 and Figure 7The holes are injected into and captured in the charge storage layer of the channel structure (or electrons are extracted from the charge storage layer). When holes are captured in the charge storage layer of the memory cell, the threshold voltage of the memory cell is reduced, and the memory cell can enter an unprogrammed state (or an erased state). By selecting a predetermined area near the level where the erase operation is to be performed, and applying an auxiliary erase voltage with a peak level of Vgidl to at least one dummy memory cell in the predetermined area, it is possible to avoid the generation of erase carriers of the non-volatile memory between the top plug of the channel structure and the top selection gate transistor as in the conventional data erase method, and then the erase carriers (holes) can avoid the potential barrier formed by the middle plug and reach the memory cell to be operated, thereby achieving effective gate-induced drain leakage GIDL erasure.

[0109] However, in order to further improve the data erasing efficiency of the non-volatile memory, during the execution of the hierarchical erasing operation, a first voltage having a step-like rising waveform may be applied to the top selection level corresponding to the level to be erased; or by applying a second voltage to the above-mentioned top selection level and floating it at the later stage of the erasing operation (the later floating may enable the top selection level to obtain a predetermined peak voltage through voltage coupling), the data erasing efficiency of the non-volatile memory may be improved.

[0110] Fig.14 1 is a voltage waveform timing diagram for a non-volatile memory according to one embodiment of the present application. Fig.15 is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of the present application.

[0111] Specifically, refer to Figure 6 and Fig.14 In one embodiment of the present application, during the execution of the erase operation of the first level, a first voltage having a step-shaped rising voltage waveform may be applied to the top selection level corresponding to the first level (including the top selection gate transistor 334-T and the top pseudo memory cell 334'). The first auxiliary step spans the time period from T0 to T2, and the voltage rises from the starting level to the intermediate level. The second step spans the time period from T2 to T3, and the voltage rises from the intermediate level to the peak level Vtsg. The value of the intermediate level may be selected, for example, between 3 volts and 10 volts. The peak level Vtsg may be higher than the peak level Vers of the step erase voltage, and further, the peak level Vtsg may be approximately 5 volts to 10 volts higher than the peak level Vers.

[0112] In addition, after the step erase voltage reaches its intermediate level Vepre, the voltage of the bottom selection gate transistor 332 -T may be increased from its starting level to its peak level Vbsg to achieve the conduction of the memory cell string 212 .

[0113] Fig.15 is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of the present application.

[0114] Specifically, refer to Figure 6 and Fig.15 In one embodiment of the present application, during the erase operation of the first level, a second voltage may be applied to the top selection level corresponding to the first level (including the top selection gate transistor 334-T and the top pseudo memory cell 334'). During the time period from T0 to T2, the voltage is increased from the starting level to the intermediate level. As an option, the value of the intermediate level may be selected, for example, between 3 volts and 10 volts. After the second voltage reaches its intermediate level Vepre (at Fig.15 At the time point T1 shown in the figure, the voltage of the top selection layer can be set to a floating state while the voltage of the top selection layer is maintained at the intermediate level. The voltage of the top selection layer will continue to rise due to the coupling effect of the step erase voltage, forming a Fig.15 The voltage waveform shown by the middle dotted line is a step-shaped waveform, and its peak level Vtsg may be substantially higher than the peak level Vers of the step erase voltage by 5 volts to 10 volts.

[0115] In addition, after the step erase voltage reaches its intermediate level Vepre, the voltage of the bottom selection gate transistor 332 -T may be increased from its starting level to its peak level Vbsg to achieve the conduction of the memory cell string 212 .

[0116] like Fig.13 As shown, after the above operation, a first voltage having a step-shaped rising waveform is applied to the top selection level corresponding to the level to be erased, or a second voltage is applied to the top selection level and then it is floated at the end of the erase operation, so that a channel potential as shown in curve 12 can be formed. Compared with the channel potential curve 11 representing that the above operation is not performed, by increasing the electric field applied to the PN junction, the gate induced drain leakage (GIDL) current caused by the band-to-band tunneling can be increased, and effective gate induced drain leakage GIDL erasure can be achieved, thereby improving the data erasure efficiency of the non-volatile memory.

[0117] Since the contents and structures involved in the erasing method of the two-level structure described above can be fully or partially applied to the non-volatile memory structure including multiple levels described below, the related or similar contents will not be repeated.

[0118] Reference again Figure 7 , Fig.10 , Fig.11 and Fig.12, when the memory block formed by the plurality of memory cell strings 212 includes a bottom level 450, a middle level 454, and a top level 452, the operation of applying the first voltage to the top selection level corresponding to the first level further includes:

[0119] In one embodiment of the present application, again referring to Figure 7 and Fig.10 During the erase operation on the bottom level 450, a first voltage (not shown) is applied to the memory cells of the top level 452, the first pseudo memory cells 452' between the top selection level and the top level 452, the second pseudo memory cells 452" and 454' between the top level and the middle level except the first predetermined area, the fourth pseudo memory cells 450' between the middle level 454 and the bottom level 450, and the third pseudo memory cells 205' between the bottom selection gate transistor 332-T and the well doping region 205 of the substrate except the second predetermined area, respectively, wherein the peak level of the first voltage may be higher than the peak level Vers of the step erase voltage, and further, the peak level may be approximately 5 volts to 10 volts higher than the peak level Vers. In addition, the operation also includes setting the memory cells of the middle level 454 to a floating state, and applying a low level to the memory cells of the bottom level 450 or grounding them.

[0120] In one embodiment of the present application, again referring to Figure 7 and Fig.11 During the erase operation on the middle level 454, a first voltage (not shown) is applied to the memory cells of the top level 452, the first dummy memory cells between the top selection level and the top level 452, the portions 452" and 454' of the second dummy memory cells between the top level 452 and the middle level 454 except the first predetermined area, the fourth dummy memory cells 450' between the middle level 454 and the bottom level 450, and the portions of the third dummy memory cells 205' between the bottom selection gate transistor 332-T and the well doping region 205 of the substrate except the second predetermined area, respectively, wherein the peak level of the first voltage may be higher than the peak level Vers of the step erase voltage, and further, the peak level may be approximately 5 volts to 10 volts higher than the peak level Vers. In addition, the operation also includes setting the memory cells of the bottom level 450 to a floating state, and applying a low level to the memory cells of the middle level 454 or grounding them.

[0121] In one embodiment of the present application, again referring to Figure 7 and Fig.12During the erase operation on the top level 452, a first voltage (not shown) is applied to a portion of a first pseudo memory cell 452' between the top selection level and the top level 452 except a first predetermined area, a portion 454' of a second pseudo memory cell between the top level 452 and the middle level 454 except a second predetermined area, a memory cell of the middle level 454, a fourth pseudo memory cell 450' between the middle level 454 and the bottom level 450, a memory cell of the bottom level 450, a bottom selection gate transistor 332-T, and a third pseudo memory cell 205' between the bottom selection gate transistor 332-T and the well doping region 205, respectively, wherein a peak level of the first voltage may be higher than a peak level Vers of the step erase voltage, and further, the peak level may be approximately 5 volts to 10 volts higher than the peak level Vers. In addition, the operation also includes applying a low level to the memory cell of the top level 452 or grounding it.

[0122] In addition, as an option, when the memory block formed by the plurality of memory cell strings 212 includes a bottom level 450, a middle level 454, and a top level 452, the operations of applying the second voltage to the top selection level corresponding to the first level, and setting the top selection level to a floating state after the step erase voltage reaches an intermediate level thereof, further include:

[0123] In one embodiment of the present application, again referring to Figure 7 and Fig.10 , during the erase operation on the bottom level 450, a second voltage ( 452″ and 454′) is applied to the memory cells of the top level 452, the first dummy memory cells between the top selection level and the top level 452, the second dummy memory cells between the top level 452 and the middle level 454 except the first predetermined area, the fourth dummy memory cells 450′ between the middle level 454 and the bottom level 450, and the third dummy memory cells 205′ between the bottom selection gate transistor 332-T and the well doping region 205 of the substrate except the second predetermined area. Fig.10 In the time period from T0 to T2, the second voltage is increased from the initial level to the intermediate level. As an option, the value of the intermediate level can be selected, for example, between 3 volts and 10 volts. After the step erase voltage reaches its intermediate level Vepre (at Fig.14 At the time point T2 shown in the figure, the memory cell of the top level 452, the first dummy memory cell 452', the part 452" and 454' of the second dummy memory cell excluding the first predetermined area, the fourth dummy memory cell 450', and the part of the third dummy memory cell 205' excluding the second predetermined area are set to a floating state. The voltage of the above structure will continue to rise due to the coupling effect of the step erase voltage, forming a structure as shown in FIG. Fig.10 The step-shaped voltage waveform shown in ( Fig.10 The operation also includes setting the memory cell of the middle level 454 to a floating state ( Fig.10 and applies a low level to the memory cell of the bottom level 450 or grounds it.

[0124] In one embodiment of the present application, again referring to Figure 7 and Fig.11 , during the erase operation on the middle level 454, a second voltage ( ) is applied to the memory cells of the top level 452, the first dummy memory cells between the top selection level and the top level 452, the second dummy memory cells between the top level 452 and the middle level 454 except the first predetermined area, the fourth dummy memory cells 450' between the middle level 454 and the bottom level 450, and the third dummy memory cells 205' between the bottom selection gate transistor 332-T and the well doping region 205 of the substrate except the second predetermined area. Fig.11 In the time period from T0 to T2, the second voltage is increased from the initial level to the intermediate level. As an option, the value of the intermediate level can be selected, for example, between 3 volts and 10 volts. After the step erase voltage reaches its intermediate level Vepre (at Fig.14 At the time point T2 shown in the figure, the memory cell of the top level 452, the first dummy memory cell 452', the part 452" and 454' of the second dummy memory cell excluding the first predetermined area, the fourth dummy memory cell 450', and the part of the third dummy memory cell 205' excluding the second predetermined area are set to a floating state. The voltage of the above structure will continue to rise due to the coupling effect of the step erase voltage, forming a structure as shown in FIG. Fig.11 The step-shaped voltage waveform shown ( Fig.11 The operation also includes setting the memory cell of the bottom level 450 to a floating state ( Fig.11 and applies a low level to the storage cell in the middle level 454 or grounds it.

[0125] In one embodiment of the present application, again referring to Figure 7 and Fig.12, during the erase operation on the top level 452, a second voltage ( ) is applied to a portion of a first pseudo memory cell 452' between the top selection level and the top level 452 except for a first predetermined area, a portion 454' of a second pseudo memory cell between the top level 452 and the middle level 454 except for a second predetermined area, a memory cell of the middle level 454, a fourth pseudo memory cell 450' between the middle level 454 and the bottom level 450, a memory cell of the bottom level 450, a bottom selection gate transistor 332-T, and a third pseudo memory cell 205' between the bottom selection gate transistor 332-T and the well doping region 205. Fig.12 The solid line portion of the Floating line of FIG. 1 ). In the time period from T0 to T2, the voltage rises from the initial level to the intermediate level. As an option, the value of the intermediate level can be selected, for example, between 3 volts and 10 volts. After the step erase voltage reaches its intermediate level Vepre (at Fig.14 At the time point T2 shown in the figure, the portion of the first dummy memory cell 452' except the first predetermined area, the portion of the second dummy memory cell 454' except the second predetermined area, the memory cell of the middle level 454, the fourth dummy memory cell 450', the memory cell of the bottom level 450, and the third dummy memory cell 205' are set to a floating state. The voltage of the above structure will continue to rise due to the coupling effect of the step erase voltage, forming a voltage as shown in FIG. Fig.12 The step-shaped voltage waveform shown ( Fig.12 The Floating line of the top level 452 is also provided, and its peak level can also meet the peak level Vers of the step erasing voltage which is approximately 5 volts to 10 volts higher than that of the step erasing voltage. In addition, the operation also includes applying a low level to the memory cell of the top level 452 or grounding it.

[0126] By applying a first voltage with a step-like rising waveform to the above-mentioned structure corresponding to the level to be erased during the execution of the hierarchical erase operation, or by applying a second voltage to the above-mentioned top selection level and floating it at the later stage of the erase operation (the later floating can make the top selection level obtain a predetermined peak voltage through voltage coupling), the electric field applied to the PN junction can be increased, thereby increasing the gate-induced drain leakage (GIDL) current caused by band-to-band tunneling, and effectively improving the gate-induced drain leakage GIDL erase.

[0127] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A method for erasing data from a non-volatile memory, characterized in that: The memory includes a plurality of storage blocks, the storage blocks include a plurality of levels stacked from bottom to top, each level includes a plurality of storage cells, and dummy storage cells are arranged between adjacent levels, and the method includes: Applying a step erase voltage to a first level to be erased among the multiple levels, the step erase voltage having a voltage waveform rising in a step shape; and During the step-erase voltage is increased from its intermediate level to its peak level, the voltage of at least one predetermined region is increased from its starting level to its peak level, thereby generating a gate-induced drain leakage current in the first level, wherein the predetermined area is adjacent to the first level and includes at least one of the dummy storage cells; and A peak level of a voltage of the predetermined region is greater than a middle level of the step-erase voltage, and a peak level of a voltage of the predetermined region is less than a peak level of the step-erase voltage.

2. The method according to claim 1, characterized in that A plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string includes a plurality of sub-memory cell strings belonging to different levels, a bottom selection gate transistor and a top selection gate transistor, the top selection gate transistor belongs to a top selection level, the top selection level also includes a top dummy memory cell, and the method further includes: During the erase operation on the first level, applying a first voltage to a top selection level corresponding to the first level, the first voltage having a voltage waveform rising in a step shape; and After the step erase voltage reaches its intermediate level, the voltage of the bottom selection gate transistor is increased from its starting level to its peak level, The peak level of the first voltage is higher than the peak level of the step erase voltage.

3. The method according to claim 1, characterized in that A plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string includes a plurality of sub-memory cell strings belonging to different levels, a bottom selection gate transistor and a top selection gate transistor, the top selection gate transistor belongs to a top selection level, the top selection level also includes a top dummy memory cell, and the method further includes: During the execution of the erase operation on the first level, applying a second voltage to a top selection level corresponding to the first level; and After the step-erase voltage reaches its intermediate level, the top selection level is set to a floating state, and the voltage of the bottom selection gate transistor is increased from its starting level to its peak level.

4. The method according to any one of claims 1 to 3, wherein a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string further comprising a bottom selection gate transistor and a top selection gate transistor, and the plurality of the memory cell strings are formed into the memory block, the memory block comprising a bottom level, a top level and a top selection level stacked vertically, characterized in that: The predetermined area includes a first predetermined area and a second predetermined area, The first predetermined area is located between the top level and the top selection level and includes at least one of the dummy memory cells, and the second predetermined area is adjacent to the bottom selection gate transistor and includes at least one of the dummy memory cells.

5. The method according to claim 4, wherein the memory cell string is formed on a well-doped region of a substrate, and the plurality of memory cells included therein are connected in series from bottom to top to the same bit line, characterized in that: Applying a step erasing voltage to a first level among the multiple levels to be erased comprises: applying the step erase voltage to the bit line and the well doping region corresponding to the first level respectively; and The memory cells of the other layers except the first layer are set to a floating state, and a low level is applied to the memory cells of the first layer or they are grounded.

6. The method according to any one of claims 1 to 3, wherein a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, wherein the memory cell string further comprises a bottom selection gate transistor and a top selection gate transistor, wherein the plurality of the memory cell strings form the memory block, wherein the memory block comprises a bottom level, a middle level and a top level stacked vertically, wherein: The predetermined area at least includes a first predetermined area and a second predetermined area. When the erase operation is performed on the bottom level or the middle level, The first predetermined region is located between the top level and the middle level and includes at least one of the dummy memory cells, and the second predetermined region is adjacent to the bottom selection gate transistor and includes at least one of the dummy memory cells.

7. The method according to any one of claims 1 to 3, wherein a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, and a plurality of the memory cell strings form the memory block, and the memory block comprises a bottom level, a middle level, a top level and a top selection level vertically stacked on a substrate, characterized in that: The predetermined area at least includes a first predetermined area and a second predetermined area. Wherein, when performing an erase operation on the top level, the first predetermined area is located between the top level and the top selection level and includes at least one of the pseudo storage cells, and the second predetermined area is located between the top level and the middle level and includes at least one of the pseudo storage cells.

8. The method according to claim 2, wherein a plurality of the memory cell strings located on the well doping region of the substrate are formed into the memory block, the memory block comprising a bottom level, a middle level, a top level and the top selection level stacked vertically, characterized in that: Applying a first voltage to a top selection level corresponding to the first level further comprises: During the erase operation on the bottom level, the first voltage is applied to the memory cells of the top level, the first dummy memory cells between the top selection level and the top level, the second dummy memory cells between the top level and the middle level except the predetermined area, the fourth dummy memory cells between the middle level and the bottom level, and the third dummy memory cells between the bottom selection gate transistor and the well doping region of the substrate except the predetermined area, respectively, wherein the peak level of the first voltage is higher than the peak level of the step erase voltage; and The memory cells of the middle level are set to a floating state, and a low level is applied to the memory cells of the bottom level or they are grounded.

9. The method according to claim 3, wherein a plurality of the memory cell strings located on the well doping region of the substrate are formed into the memory block, the memory block comprising a bottom level, a middle level, a top level and the top selection level stacked vertically, characterized in that: Applying a second voltage to a top selection level corresponding to the first level, and after the step erase voltage reaches an intermediate level thereof, setting the top selection level to a floating state further comprises: During the erase operation on the bottom level, a second voltage is applied to the memory cells of the top level, the first dummy memory cells between the top selection level and the top level, the second dummy memory cells between the top level and the middle level except the predetermined area, the fourth dummy memory cells between the middle level and the bottom level, and the third dummy memory cells between the bottom selection gate transistor and the well doping region of the substrate except the predetermined area, and after the step erase voltage reaches an intermediate level thereof, the memory cells of the top level, the first dummy memory cells, the second dummy memory cells except the predetermined area, the fourth dummy memory cells, and the third dummy memory cells except the predetermined area are set to a floating state; and The memory cells of the middle level are set to a floating state, and a low level is applied to the memory cells of the bottom level or they are grounded.

10. The method according to claim 2, wherein a plurality of the memory cell strings located on the well doping region of the substrate are formed into the memory block, the memory block comprising a bottom level, a middle level, a top level and the top selection level stacked vertically, characterized in that: Applying a first voltage to a top selection level corresponding to the first level further comprises: During the erase operation on the middle level, the first voltage is applied to the memory cells of the top level, the first dummy memory cells between the top selection level and the top level, the second dummy memory cells between the top level and the middle level except the predetermined area, the fourth dummy memory cells between the middle level and the bottom level, and the third dummy memory cells between the bottom selection gate transistor and the well doping region of the substrate except the predetermined area, respectively, wherein the peak level of the first voltage is higher than the peak level of the step erase voltage; and The memory cells of the bottom level are set to a floating state, and a low level is applied to the memory cells of the middle level or they are grounded.

11. The method according to claim 3, wherein a plurality of the memory cell strings located on the well doping region of the substrate are formed into the memory block, the memory block comprising a bottom level, a middle level, a top level and the top selection level stacked vertically, characterized in that: Applying a second voltage to a top selection level corresponding to the first level, and after the step erase voltage reaches an intermediate level thereof, setting the top selection level to a floating state further comprises: During the erase operation on the middle level, the second voltage is applied to the memory cells of the top level, the first dummy memory cells between the top selection level and the top level, the second dummy memory cells between the top level and the middle level except the predetermined area, the fourth dummy memory cells between the middle level and the bottom level, and the third dummy memory cells between the bottom selection gate transistor and the well doping region of the substrate except the predetermined area, and after the step erase voltage reaches the intermediate level thereof, the memory cells of the top level, the first dummy memory cells, the second dummy memory cells except the predetermined area, the fourth dummy memory cells, and the third dummy memory cells except the predetermined area are set to a floating state; and The memory cells of the bottom level are set to a floating state, and a low level is applied to the memory cells of the middle level or they are grounded.

12. The method according to claim 2, wherein a plurality of the memory cell strings located on the well doping region of the substrate are formed into the memory block, the memory block comprising a bottom level, a middle level, a top level and the top selection level stacked vertically, characterized in that: Applying a first voltage to a top selection level corresponding to the first level further comprises: During the erase operation on the top level, the first voltage is applied to a portion of a first dummy memory cell between the top selection level and the top level except the predetermined area, a portion of a second dummy memory cell between the top level and the middle level except the predetermined area, a memory cell of the middle level, a fourth dummy memory cell between the middle level and the bottom level, a memory cell of the bottom level, the bottom selection gate transistor, and a third dummy memory cell between the bottom selection gate transistor and a well doping region of the substrate, respectively, wherein a peak level of the first voltage is higher than a peak level of the step erase voltage; and A low level is applied or grounded to the memory cells of the top level.

13. The method according to claim 3, wherein a plurality of the memory cell strings located on the well doping region of the substrate are formed into the memory block, the memory block comprising a bottom level, a middle level, a top level and the top selection level stacked vertically, characterized in that: Applying a second voltage to a top selection level corresponding to the first level, and after the step erase voltage reaches an intermediate level thereof, setting the top selection level to a floating state further comprises: During the erase operation on the top level, the second voltage is applied to the portion of the first dummy memory cell between the top selection level and the top level except the predetermined area, the portion of the second dummy memory cell between the top level and the middle level except the predetermined area, the memory cell of the middle level, the fourth dummy memory cell between the middle level and the bottom level, the memory cell of the bottom level, the bottom selection gate transistor, and the third dummy memory cell between the bottom selection gate transistor and the well doping region of the substrate, respectively, and after the step erase voltage reaches its intermediate level, the portion of the first dummy memory cell except the predetermined area, the portion of the second dummy memory cell except the predetermined area, the memory cell of the middle level, the third dummy memory cell, the memory cell of the bottom level, and the fourth dummy memory cell are set to a floating state; and A low level is applied or grounded to the memory cells of the top level.

14. A non-volatile memory, characterized in that: The non-volatile memory comprises: A memory array formed on a well-doped region of a substrate and comprising a plurality of memory cells, wherein a memory cell string in each column is connected to the same bit line to form a memory cell string, a plurality of the memory cell strings are formed into a memory block, the memory block comprises a plurality of levels stacked vertically in a direction perpendicular to the substrate, and the memory cell string comprises a plurality of sub-memory cell strings belonging to different levels; and A control circuit is coupled to the storage array and configured to control level selection of the multiple levels and perform a data erasing operation according to any one of claims 1 to 13 on the selected level.

15. The nonvolatile memory according to claim 14, wherein: The storage array is a three-dimensional NAND storage array, and the non-volatile memory is a three-dimensional NAND memory.

Images