System and method for processing wafer height data

Abstract

The disclosure provides a system and method for processing silicon wafer height data. The system comprises a data acquisition module including multiple signal acquisition channels for parallel acquisition of data corresponding to at least one detection point on the surface of the silicon wafer; a control module for receiving a synchronization trigger signal to trigger the data acquisition module to acquire data when a displacement table moves to a target position on the silicon wafer, wherein the control module is realized based on an embedded FPGA chip; a parallel-to-serial conversion module for converting the parallel acquired data into serial data; a VPX data transmission interface module for receiving the serial data and converting the serial data into parallel data, wherein the VPX data transmission interface module and the parallel-to-serial conversion module transmit data through a VPX serial bus transmission protocol; and an upper computer for processing the parallel data.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a processing system and method for wafer height data. BACKGROUND

[0002] In a mainstream photolithography process, exposure imaging of a photolithography device is a key node, and therefore, the precision of exposure focusing needs to be ensured to ensure the photolithography precision of the photolithography device. In this context, it is generally necessary to control the exposure precision to be within nm level. In order to ensure that the wafer is not out of focus during exposure, the wafer height information needs to be collected and processed, and the height of a displacement table is adjusted online during exposure to control the wafer to be on the best focal plane in the exposure area during exposure.

[0003] In a traditional photolithography process, a VME control system is used to control the exposure position of a wafer. However, the VME control system has inherent disadvantages such as data delay and data jitter in the data transmission process, which causes a certain error between the target position and the collected position during the collection of the position information during the movement of the displacement table, and a time delay error phenomenon in the task scheduling of the operating system, thereby affecting the exposure precision.

[0004] DISCLOSURE

[0005] Based on this, the present disclosure provides, in one aspect, a processing system for wafer height data, comprising: a data collection module comprising a plurality of signal collection channels for collecting data corresponding to at least one detection point on the surface of a wafer in parallel; a control module for receiving a synchronization trigger signal to trigger the data collection module to collect data when a displacement table moves to a target position on the wafer, wherein the control module is implemented based on an embedded FPGA chip; a parallel-to-serial conversion module for converting the parallel collected data into serial data; a VPX data transmission interface module for receiving the serial data and converting the serial data into parallel data, wherein the VPX data transmission interface module and the parallel-to-serial conversion module perform data transmission through a VPX serial bus transmission protocol; and an upper computer for processing the parallel data.

[0006] According to an embodiment of the present disclosure, the data collection module comprises: a photodetector array for converting optical signals of at least one detection point on the surface of a wafer into electrical signals; a photoelectric conversion conditioning circuit for processing the electrical signals to improve the signal-to-noise ratio of the electrical signals; and a sampling unit for sampling the electrical signals to convert the electrical signals into digital signals, wherein the sampling unit comprises at least one ADC sampling chip, and each ADC sampling chip comprises a plurality of sampling channels to realize parallel sampling.

[0007] According to an embodiment of the present disclosure, the photoelectric conversion conditioning circuit comprises a transconductance circuit for transconductance amplification of the electrical signal; and a filter circuit for low-pass filtering of the electrical signal.

[0008] According to an embodiment of the present disclosure, the transconductance circuit is implemented based on a 16-bit operational amplifier chip.

[0009] According to an embodiment of the present disclosure, the sampling frequency of the sampling unit is in the order of megahertz.

[0010] According to an embodiment of the present disclosure, the transmission structure of the synchronization trigger signal uses a differential transmission interface.

[0011] According to an embodiment of the present disclosure, the processing system further comprises a level acquisition module configured to acquire a high level of a signal received by the control module; and a judgment module configured to judge whether the high level can be continuously acquired for a plurality of clocks, and send a signal to the control module to prompt that the currently received signal is a synchronization trigger signal if the high level can be continuously acquired for the plurality of clocks.

[0012] According to an embodiment of the present disclosure, the processing system further comprises a temperature control chip configured to acquire a temperature of the FPGA chip and control the temperature of the FPGA chip according to an instruction of the host computer, wherein the temperature control chip and the host computer perform data transmission through a VPX serial bus transmission protocol.

[0013] According to an embodiment of the present disclosure, the parallel-to-serial conversion module is further configured to perform low-pass filtering on the serial data.

[0014] Another aspect of the present disclosure provides a processing method for silicon wafer height data based on the above processing system, comprising: judging whether a current position of a displacement table is at a target position; if yes, sending a synchronization trigger signal to a control module to make the control module synchronously trigger a data acquisition module to acquire data corresponding to at least one detection point on a surface of a silicon wafer in parallel; converting the data acquired in parallel into serial data, sending the serial data to a VPX data transmission interface module based on a VPX serial bus transmission protocol, converting the serial data into parallel data through the VPX data transmission interface module; and processing the parallel data through a host computer to obtain height data of the silicon wafer. BRIEF DESCRIPTION OF DRAWINGS

[0015] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 A structure block diagram of a processing system for silicon wafer height data provided by an embodiment of the present disclosure is schematically shown.

[0017] Figure 2A structural block diagram of a control module based on an embedded FPGA chip is shown schematically.

[0018] Figure 3 A structural block diagram of a processing system of wafer height data is shown schematically.

[0019] Figure 4 A flow chart of data collection based on the processing system of wafer height data is shown schematically. DETAILED DESCRIPTION

[0020] For the purpose of clarity, technical solutions and advantages of the present disclosure, the present disclosure is further described in detail below with reference to specific embodiments and drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0021] The terms used herein are only used to describe specific embodiments, and are not intended to limit the present disclosure. The terms "include", "contain" and the like used herein indicate the existence of the described features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0022] In the present disclosure, unless otherwise explicitly specified and limited, the terms "mount", "connect", "connect", "fix" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected or can communicate with each other; it can be directly connected, or it can be indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0023] In the description of the present disclosure, it should be understood that the terms "longitudinal", "length", "circumferential", "front", "back", "left", "right", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present disclosure and simplify the description, and do not indicate or imply that the subsystems or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0024] Throughout the drawings, the same or like elements are denoted by the same or similar reference numbers. Conventional structures or configurations can be omitted when they can cause an understanding of the present disclosure to be obscured. Also, the shape, size, positional relation of the components in the drawings do not reflect actual size, proportion and actual positional relation. In addition, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.

[0025] Similarly, to simplify the present disclosure and to help understand one or more of the various disclosed aspects, in the above description of the exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together in a single embodiment, figure or description of a related aspect. Descriptions of the same or similar elements in several embodiments or aspects of the disclosure are not intended to exclude those elements from other embodiments or aspects of the disclosure. Reference numerals introduced in one embodiment or aspect of the disclosure can be used in other embodiments or aspects of the disclosure. The descriptions of the various embodiments or aspects of the disclosure are not intended to exclude that the described features can be used in any combination other than the combinations explicitly described. Descriptions of the various embodiments or aspects of the disclosure in the specification of the present disclosure do not exclude that one or more of the described features can be used in one or more embodiments or aspects of the disclosure.

[0026] Furthermore, the terms "first", "second", etc. are used herein only to describe different instances, and do not imply a relative importance or a specific order of calling. The features defined with "first" and "second" can include one or more of the features explicitly or implicitly. In the description of the present disclosure, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified.

[0027] The purpose of the embodiments of the present disclosure is to provide a system for high-silicon-chip data acquisition and processing based on VPX bus, which introduces a displacement table position synchronous triggering mechanism to solve the error phenomenon of target position and actual acquisition position. The system uses multi-channel high-speed parallel sampling, uses an embedded FPGA chip to control the acquisition of displacement table position and real-time acquisition, storage and processing of optical signals, and solves the time delay error in the task scheduling process of the upper computer software. The system uses VPX serial bus transmission protocol, has strong anti-interference ability, stable transmission process, and good effect on the effectiveness of the acquired data.

[0028] Figure 1 An exemplary structure block diagram of a high-silicon-chip data processing system is shown.

[0029] As shown in Figure 1 The high-silicon-chip data processing system may, for example, include a data acquisition module, a control module, a parallel-to-serial conversion module, a VPX data transmission interface module, and an upper computer.

[0030] The data acquisition module comprises a plurality of signal acquisition channels, and is configured to acquire data corresponding to at least one detection point on the surface of the silicon wafer in parallel.

[0031] In an embodiment of the present disclosure, the data acquisition module may, for example, comprise a photodetector array, a photoelectric conversion conditioning circuit and a sampling unit.

[0032] The photodetector array is configured to convert the optical signal of the at least one detection point on the surface of the silicon wafer into an electrical signal. Specifically, a plurality of detection points of the photodetector array measure the upper surface of the silicon wafer at the same time, and the temperature of the surface of the silicon wafer is calculated according to the formula. The photodetector array may be a photodiode array (PDA) comprising a plurality of equal numbers of o light, e light and captured light, which converts the optical signal into an electrical signal. The current intensity value is in a functional relationship with the light intensity, and the current increases with the increase of the light intensity signal. In addition, a reverse voltage generator can be used to provide a reverse voltage for the photodetector array.

[0033] The photoelectric conversion conditioning circuit is configured to process the electrical signal to improve the signal-to-noise ratio of the electrical signal. Specifically, since the current signal acquired by the photodetector array is weak, the photoelectric conversion conditioning circuit is introduced to process the acquired electrical signal so as to obtain more accurate and convenient processing of the high-speed data of the silicon wafer. The photoelectric conversion conditioning circuit may, for example, comprise a transconductance circuit and a filter circuit. The transconductance circuit is configured to transconduct amplification of the electrical signal, i.e. to convert the weak current signal into a voltage signal. The transconductance circuit may be implemented based on a 16-bit operational amplifier chip, which can ensure high precision, stable operation and other requirements. The filter circuit is configured to perform low-pass filtering on the electrical signal to filter out the corresponding noise signal, thereby improving the signal-to-noise ratio of the signal.

[0034] The sampling unit is configured to sample the electrical signal and convert the electrical signal (analog signal) into a digital signal.

[0035] Figure 2 A structural block diagram of the control module based on the embedded FPGA chip provided by an embodiment of the present disclosure is schematically shown.

[0036] As shown in Figure 2 The sampling unit may, for example, comprise at least one ADC sampling chip, and each ADC sampling chip may comprise a plurality of sampling channels to realize multi-channel parallel sampling and sample the o light and e light at the same time. In a specific example of the present disclosure, each ADC sampling chip may comprise 4 analog channel inputs, and 6 ADC sampling chips can realize 24 analog channels, which can cover 21 light channels of the photoelectric array and meet the requirements of multi-channel data acquisition and solve the errors caused by the traditional time-sharing acquisition method. The sampling frequency of the sampling unit is in the order of megahertz.

[0037] The control module is used to receive a synchronization trigger signal to trigger the data acquisition module to acquire data when the displacement table moves to a target position on the silicon wafer, wherein the control module is realized based on an embedded FPGA chip.

[0038] With reference to the above Figure 2 In the process of measuring the height of the silicon wafer, data acquisition needs to be performed at the corresponding displacement table position, so a synchronization mechanism is introduced, and after the displacement table moves to the target position, a synchronization trigger signal is sent to the control module to make the control module control the data acquisition module to enter the data acquisition stage, thereby ensuring simultaneous acquisition of multi-channel data. Specifically, the embedded FPGA chip sends corresponding timing logic control data acquisition according to the communication protocol of the ADC chip, and the control module receives ADC digital signals by generating a serial clock signal (SCKI). The clock frequency of the embedded FPGA chip is in the order of Mhz, so as to ensure that the sampling frequency of the sampling unit is in the order of megahertz. The high sampling rate ensures the accuracy of optical data acquisition, and thus more accurate values are obtained in the process of measuring the height of the silicon wafer.

[0039] Further, the transmission interface of the synchronization trigger signal uses a high-speed differential transmission interface, which is connected to the data acquisition module and the data transmission module, respectively. The differential data is used to transmit the trigger signal, and the strong anti-interference ability of the differential transmission is used to greatly ensure the stability of the synchronization signal, and the transmission stage also plays a guarantee role for the data transmission of the entire system.

[0040] The parallel-to-serial conversion module is used to convert the parallel acquired data into serial data. In addition, the parallel-to-serial conversion module is also used to perform low-pass filtering on the digital signals obtained by sampling, so as to further ensure the quality of the sampling signals.

[0041] The VPX data transmission interface module is used to receive serial data and convert the serial data into parallel data, wherein the VPX data transmission interface module and the parallel-to-serial conversion module perform data transmission through a VPX serial bus transmission protocol. Since the VPX serial bus transmission protocol is a protocol for realizing data serial transmission, and the subsequent host computer processes data in parallel, the parallel acquired data needs to be converted into serial data first, and then the serial data is converted into parallel data and sent to the host computer for processing.

[0042] The host computer is used to receive the parallel data forwarded by the VPX data transmission interface module through a high-speed transmission cable, and process the data to obtain the height data of the silicon wafer.

[0043] In addition, the cable of the high-speed transmission interface in the system adopts a customized cable, and high-quality cables are used for data transmission according to the corresponding interface definition, so that the stability of the transmitted data is ensured, and the integration of the entire system is facilitated. The high-speed data transmission interface includes serial data transmitted from the VPX to the data acquisition board, serial data exported from the data acquisition module to the VPX, a synchronous trigger signal, and a power supply part.

[0044] Figure 3 A structural block diagram of a processing system for processing wafer height data is illustratively shown.

[0045] As Figure 3 shown, the processing system further includes a level acquisition module, a judgment module, and a temperature control chip.

[0046] The level acquisition module is configured to acquire a high level of a signal received by the control module.

[0047] The judgment module is configured to judge whether a high level can be continuously acquired for a plurality of clocks, and in the case that a high level can be continuously acquired for a plurality of clocks, send a signal to the control module to prompt that the currently received signal is a synchronous trigger signal.

[0048] Specifically, in the receiving stage of the synchronous trigger signal, the rising edge of the synchronous trigger signal needs to be acquired, and in order to prevent false acquisition, the following mechanism is added: after the rising edge acquired in the first clock stage, continue to acquire for a plurality of clocks, if the corresponding high level can be continuously acquired, it is proved to be a synchronous trigger signal, and if not, it is not a trigger signal. This mechanism ensures the accuracy of synchronous acquisition and prevents the acquisition of false wafer height information caused by false triggering.

[0049] The temperature control chip is configured to acquire the temperature of the FPGA chip and control the temperature of the FPGA chip according to the instruction of the host computer, wherein the temperature control chip and the host computer perform data transmission through a VPX serial bus transmission protocol. Since the entire displacement table system is a super-clean space, the temperature change is small, and in cooperation with the corresponding temperature control chip, a low sampling frequency (HZ) can be used. In this system, temperature sampling control and data sampling are transmitted in parallel, which increases the real-time monitoring of the temperature on the host computer interface, and further ensures that the FPGA chip is in a stable operating environment during data acquisition.

[0050] In addition, the system is also provided with power distribution and electrical safety protection components to ensure the safe and stable operation of the entire system.

[0051] Figure 4 A flowchart of data acquisition based on the above wafer height data processing system is illustratively shown.

[0052] AsFigure 4 As shown, the acquisition process includes: judging whether the current position of the displacement table is at the target position, that is, the external synchronization pulse is focused. If not, continue to wait, and do not perform data acquisition. If yes, send a synchronization trigger signal to the control module to make the control module trigger the data acquisition module in parallel to acquire the data corresponding to at least one detection point on the surface of the silicon wafer, convert the parallel acquired data into serial data, send the serial data to the VPX data transmission interface module based on the VPX serial bus transmission protocol, convert the serial data into parallel data through the VPX data transmission interface module, process the parallel data through the upper computer, and obtain the height data of the silicon wafer. The temperature of the control module based on the FPGA chip is monitored during the data acquisition process.

[0053] In summary, the processing system for silicon wafer height data provided by the embodiments of the present disclosure uses a displacement table position synchronization trigger mechanism, a multi-channel high-speed parallel sampling, and a VPX transmission overall mutually coordinated architecture to respectively solve the target position and actual position error, the time delay error of the upper computer software in the task scheduling process, and improve the data transmission stability, thereby achieving good solving effect, accurately measuring the height of the silicon wafer surface, and providing strong data support for the exposure imaging stage in the advanced measurement and control system. The system has the advantages of high precision, strong expandability, stable system structure, and the like.

[0054] The above-described specific embodiments further illustrate the purpose, technical solutions, and beneficial effects of the present disclosure. It should be understood that the above-described specific embodiments are merely examples of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, and the like made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A processing system for wafer height data, comprising: a data acquisition module comprising a plurality of signal acquisition channels for acquiring data corresponding to at least one detection point on the wafer surface in parallel; a control module for receiving a synchronization trigger signal to trigger the data acquisition module to acquire data when a displacement table moves to a target position on the wafer, wherein the control module is implemented based on an embedded FPGA chip; a parallel-to-serial conversion module for converting the data acquired in parallel into serial data; a VPX data transmission interface module for receiving the serial data and converting the serial data into parallel data, wherein the VPX data transmission interface module and the parallel-to-serial conversion module transmit data through a VPX serial bus transmission protocol; a host computer for processing the parallel data; a level acquisition module for acquiring a high level of a signal received by the control module; a judgment module for judging whether a high level can be acquired continuously for a plurality of clocks, and sending a signal to the control module to prompt that the current received signal is the synchronization trigger signal if a high level can be acquired continuously for a plurality of clocks.

2. The processing system of claim 1, wherein, The data acquisition module comprises: a photodetector array for converting optical signals of at least one detection point on the wafer surface into electrical signals; a photoelectric conversion conditioning circuit for processing the electrical signals to improve the signal-to-noise ratio of the electrical signals; a sampling unit for sampling the electrical signals to convert the electrical signals into digital signals, wherein the sampling unit comprises at least one ADC sampling chip, and each ADC sampling chip comprises a plurality of sampling channels to achieve parallel sampling.

3. The processing system of claim 2, wherein, The photoelectric conversion conditioning circuit comprises: a transconductance circuit for transconductance amplification of the electrical signals; a filter circuit for low-pass filtering of the electrical signals.

4. The processing system of claim 3, wherein, The transconductance circuit is implemented based on a 16-bit operational amplifier chip.

5. The processing system of claim 2, wherein, The sampling frequency of the sampling unit is in the order of megahertz.

6. The processing system of claim 1, wherein, The transmission structure of the synchronization trigger signal uses a differential transmission interface.

7. The processing system of claim 1, further comprising: a temperature control chip for acquiring the temperature of the FPGA chip and controlling the temperature of the FPGA chip according to instructions from the host computer, wherein the temperature control chip and the host computer transmit data through a VPX serial bus transmission protocol.

8. The processing system of claim 1, wherein, The parallel-to-serial conversion module is also used for low-pass filtering of the serial data. 9.A method for processing wafer height data based on the processing system of any one of claims 1-8, comprising: judging whether a current position of a displacement table is at a target position; if yes, sending a synchronization trigger signal to a control module to trigger the control module to trigger a data acquisition module to acquire data corresponding to at least one detection point on the wafer surface in parallel; converting the data acquired in parallel into serial data, sending the serial data to a VPX data transmission interface module based on a VPX serial bus transmission protocol, and converting the serial data into parallel data through the VPX data transmission interface module; processing the parallel data through a host computer to obtain the height data of the wafer.

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