Phase change memory and method for manufacturing the same

Abstract

The present invention provides a phase change memory and a manufacturing method thereof. The phase change memory includes: a P-type phase change material layer, an N-type thermoelectric material layer, and a select gate layer stacked in sequence along the longitudinal direction; the P-type phase change material layer, the N-type thermoelectric material layer, and the select gate layer are externally connected to a power supply to form a closed loop, and the select gate layer has an open state and a closed state; when the select gate layer is open, the contact interface between the P-type phase change material layer and the N-type thermoelectric material layer is in an electronic refrigeration mode. In this embodiment, by forming a loop with the P-type phase change material layer and the N-type thermoelectric material layer, a corresponding current is generated in the loop. When the current flows through the contact area between the P-type phase change material layer and the N-type thermoelectric material layer, the heat in the contact area is absorbed, resulting in a refrigeration phenomenon, thereby reducing the temperature at the interface of the phase change memory cell during reading, reducing the disturbance of the read pulse to the phase change memory cell, reducing the reading error value of the phase change memory cell, and avoiding the loss of stored information.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a phase change memory and a manufacturing method thereof. Background Art

[0002] A phase change random access memory (PCRAM) is a solid-state semiconductor non-volatile memory, which has the advantages of high-speed reading, high erasable and writable times, non-volatility, small element size, low power consumption, etc. Compared with a dynamic random access memory (DRAM), it has lower cost, the information will not be lost after power-off, higher storage density, and lower power consumption. Therefore, it is considered a new type of non-volatile memory with great development prospects.

[0003] The most core part of the phase change memory is a phase change material layer (PCM) based on chalcogenide compounds. The phase change material layer capable of storing data has at least two significantly distinguishable solid-phase structures. For example, one state, the amorphous state (disordered), can have a high resistance, while the other state, the crystalline state (ordered), can have a low resistance. When the phase change material layer is applied to PCRAM, the significantly different resistance values in the disordered and ordered states are mainly used as the "0" and "1" states for data storage. The transition from the metastable amorphous phase to the stable crystalline phase is obtained by heating it above its crystallization temperature for a sufficient time to make it fully crystallized. The reverse process is to heat the crystalline structure to melting and rapidly cool it, that is, to undergo a rapid annealing process to condense into the amorphous state.

[0004] With the demand for higher-performance products by people, how to further improve the reliability and stability of the phase change memory, reduce read interference, and avoid the loss of stored information has become one of the technical problems that need to be urgently solved by those skilled in the art. Summary of the Invention

[0005] The purpose of the present invention is to provide a phase change memory, which improves the reliability and stability of the phase change memory, reduces the perturbation of read pulses or surge currents to the phase change memory cells, and avoids the loss of stored information.

[0006] The present invention provides a phase change memory, including:

[0007] A phase change memory cell, the phase change memory cell includes a P-type phase change material layer, an N-type thermoelectric material layer, and a select layer stacked in sequence along the longitudinal direction; wherein, the P-type phase change material layer, the N-type thermoelectric material layer, and the select layer are externally connected to a power supply to form a closed loop, and the select layer has an open state and a closed state; when the select layer is open, the contact interface between the P-type phase change material layer and the N-type thermoelectric material layer is an electronic refrigeration mode.

[0008] Further, the N-type thermoelectric material layer comprises one or more combinations of Bi, Te, Sb, Sn and Se elements.

[0009] Further, the N-type thermoelectric material layer comprises one or more combinations of Bi2Te3, Sb2Te3, Bi2Se3 and SnSe.

[0010] Further, metal atoms are doped into the N-type thermoelectric material layer.

[0011] Further, the P-type phase change material layer comprises a chalcogenide semiconductor material.

[0012] Further, it further comprises: a top electrode layer located above the P-type phase change material layer, an intermediate electrode layer located between the N-type thermoelectric material layer and the selection layer, and a bottom electrode layer located below the selection layer, wherein the positive terminal of the external power supply is connected to the bottom electrode layer and the negative terminal is connected to the top electrode layer.

[0013] Further, it further comprises a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction, the first direction and the second direction being orthogonal; the phase change memory cells are arranged in an array, and each of the phase change memory cells is respectively disposed at the intersection of the corresponding word line and bit line.

[0014] The present invention also provides a method for manufacturing a phase change memory, comprising the following steps:

[0015] Stacking a P-type phase change material layer, an N-type thermoelectric material layer and a selection layer in sequence along the longitudinal direction;

[0016] Wherein, the P-type phase change material layer, the N-type thermoelectric material layer and the selection layer are externally connected to a power supply to form a closed loop, and the selection layer has an open state and a closed state; when the selection layer is open, the contact interface between the P-type phase change material layer and the N-type thermoelectric material layer is in an electronic refrigeration mode.

[0017] Further, the N-type thermoelectric material layer comprises one or more combinations of Bi2Te3, Sb2Te3, Bi2Se3 and SnSe.

[0018] Further, the preparation method of the N-type thermoelectric material layer comprises: preparing SnSe precursor powder by mechanical alloying, preparing polycrystalline SnSe bulk material by using a spark plasma sintering technique, and doping one or more combinations of Bi, Ti, Pb in SnSe to form N-type SnSe.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The present invention provides a phase change memory and a manufacturing method thereof. The phase change memory includes phase change memory cells, and each phase change memory cell includes a P-type phase change material layer, an N-type thermoelectric material layer, and a select gate layer stacked in sequence along the longitudinal direction. Among them, the P-type phase change material layer, the N-type thermoelectric material layer, and the select gate layer are externally connected to a power source to form a closed loop, and the select gate layer has an open state and a closed state. When the select gate layer is open, the contact interface between the P-type phase change material layer and the N-type thermoelectric material layer is in an electronic refrigeration mode. In this embodiment, by forming a loop with the P-type phase change material layer and the N-type thermoelectric material layer, a corresponding current is generated in the loop. When the current flows through the contact area between the P-type phase change material layer and the N-type thermoelectric material layer, the heat in the contact area will be absorbed, resulting in a refrigeration phenomenon, thereby reducing the temperature at the interface of the phase change memory cell during reading, reducing the disturbance of the read pulse to the phase change memory cell, reducing the read error value of the phase change memory cell, and avoiding the loss of stored information. Description of the Drawings

[0021] Figure 1 It is a schematic structural diagram of a phase change memory.

[0022] Figure 2 It is a three-dimensional schematic diagram of the phase change memory according to an embodiment of the present invention.

[0023] Figure 3 It is along the Figure 2 profile structural schematic diagram of the XOZ plane in the present invention.

[0024] Figure 4 It is a schematic flowchart of the manufacturing method of the phase change memory according to an embodiment of the present invention.

[0025] Among them, the reference numerals are as follows:

[0026] 01 - Phase change memory cell; PCM - Phase change material layer; Ea - Top electrode; Eb - Intermediate electrode; Ec - Bottom electrode; OTS - Select gate layer; 10 - Phase change memory cell; 101 - P-type phase change material layer; 102 - N-type thermoelectric material layer; C - Cold end region; WL - Word line; TE - Top electrode layer; OTS - Select gate layer; BE - Bottom electrode layer; BL - Bit line. Detailed Embodiments

[0027] As described in the background art, the reliability and stability of the phase change memory need to be improved, and it is necessary to reduce reading interference and avoid the loss of stored information.

[0028] Specifically, as Figure 1As shown, the phase change memory cell 01 of the phase change memory includes a phase change material layer PCM, a top electrode Ea, an intermediate electrode Eb, and a bottom electrode Ec, as well as a select gate layer OTS located between the two electrodes Eb and Ec. The intermediate electrode Eb, the select gate layer OTS, and the bottom electrode Ec together constitute a selector. When performing a write / erase operation on the phase change memory cell, the selector can maintain an open (conductive) state, causing the phase change material layer PCM to undergo a phase change. After the write / erase operation is completed, the selector remains in a closed state.

[0029] A phase change memory is a memory that utilizes Joule heat to induce a material phase change to cause a resistance change. Specifically, a phase change memory is a non-volatile solid-state storage technology that utilizes reversible thermally assisted switching of a phase change material (such as a chalcogenide compound, such as GST (germanium antimony telluride)) between different resistances; after applying a reset write current, the temperature of the phase change material layer (PCM) of the phase change memory rapidly increases. After reaching the melting point of the phase change material layer, the material of the phase change material layer rapidly cools within a short time and is fixed in the amorphous state, which is a high-resistance state. In order to make the material of the phase change material layer return to the crystalline state, a set current needs to be applied, and the phase change material layer needs to be heated to between the crystallization temperature and the melting temperature, thereby enabling the rapid growth of crystal nuclei and microcrystals in the phase change material layer. It can be seen that Joule heat controls the entire phase change storage process of the phase change memory. By generating heat to trigger the amorphous or crystalline state of the phase change material to represent the numerical values 1 or 0, the programming or erasing of the PCM cell is thus achieved.

[0030] Applying a rapid voltage pulse to the phase change memory cell 01, with an amplitude between the threshold voltages corresponding to the low resistance and the high resistance of the phase change material layer PCM, thus enables the reading of the phase change memory cell 01. For the phase change material layer PCM in the high-resistance state, this voltage pulse cannot turn on the select gate, so no current can be detected and "0" is read; however, for the phase change material layer PCM in the low-resistance state, the read pulse is sufficient to turn on the select gate, so a large current can be detected, thereby reading "1".

[0031] Therefore, for the phase change material layer PCM in the low resistance state, each read operation will turn on the select transistor, and thus a large current will flow through the phase change memory cell 01. For the select transistor, since the turn-on speed of the select transistor is much slower than the RC delay time in the phase change memory cell array, there will be a large surge current every time the select transistor is turned on. The amplitude of the surge current is determined by the voltage across the phase change memory cell 01 and the change rate of the resistance between the turn-on and turn-off states of the select transistor. The action time of the surge current is jointly determined by the turn-on time of the select transistor itself and the RC delay time of the circuit. Therefore, the surge current generated each time the select transistor is turned on is equivalent to a reset pulse operation, which makes it easy for the phase change material layer PCM in the low resistance state to be disturbed into the high resistance state during each read operation, resulting in the loss of stored information.

[0032] The inventors recognized the above problems and, based on research, proposed the present invention. Embodiments of the present invention provide a phase change memory. The following further details the present invention with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention.

[0033] Embodiments of the present invention provide a phase change memory, including:

[0034] A phase change memory cell, the phase change memory cell includes a P-type phase change material layer, an N-type thermoelectric material layer, and a select layer stacked in sequence along the longitudinal direction; wherein, the P-type phase change material layer, the N-type thermoelectric material layer, and the select layer are externally connected to a power supply to form a closed loop, and the select layer has an on state and an off state; when the select layer is turned on, the contact interface between the P-type phase change material layer and the N-type thermoelectric material layer is in an electronic refrigeration mode.

[0035] In this embodiment, the P-type phase change material layer and the N-type thermoelectric material layer are formed into a loop, and a corresponding current is generated in the loop. Using the Peltier effect, when the current flows through the contact area between the P-type phase change material layer and the N-type thermoelectric material layer, the heat in the contact area will be absorbed, generating a refrigeration phenomenon, thereby reducing the temperature at the interface of the phase change memory cell during reading, reducing the disturbance of the read pulse to the phase change memory cell, reducing the read error value of the phase change memory cell, and avoiding the loss of stored information.

[0036] The following combines Figure 2 and Figure 3 to introduce in detail the phase change memory of the embodiments of the present invention.

[0037] Exemplarily, the phase change memory of this embodiment has word lines (WL) extending along a first direction (e.g., the X direction) and bit lines (BL) extending along a second direction (e.g., the Y direction), and the first direction and the second direction are orthogonal; the phase change memory cell 10 is disposed at the intersection of the word line WL and the bit line BL, and the phase change memory cell 10 is, for example, a columnar structure. The phase change memory cell includes a P-type phase change material layer 101, an N-type thermoelectric material layer 102, and a select gate layer OTS stacked in sequence.

[0038] Among them, the P-type phase change material layer (P-PCM) 101 includes a chalcogenide semiconductor material, and the chalcogenide semiconductor material may include a combination of one or more of the elements S, N, O, Cu, Si, and Au doped therein; the chalcogenide semiconductor material may also include at least one of Ge-Sb-Te based phase change materials (also known as GST), Ge-Te based phase change materials, Ge-Sb based phase change materials, Si-Sb-Te based phase change materials, Sb-Te based phase change materials, Sb based phase change materials, etc., and may be a combination of two phase change materials, a combination of three phase change materials, or a combination of more phase change materials. Among them, the Ge-Sb-Te based phase change material is composed of three elements Ge, Sb, and Te, and may include but is not limited to Ge3Sb4Te8, Ge2Sb2Te5, Ge2Sb2Te4, GeSb2Te4, etc., and the Ge-Te based phase change material is composed of two elements Ge and Te. Among them, the Ge-Sb based phase change material is composed of two elements Ge and Sb, and the Si-Sb-Te based phase change material is composed of three elements Si, Sb, and Te, and may include but is not limited to: Si 11 Sb 57 Te 32 、Si 18 Sb 52 Te 30 、Si 24 Sb 48 Te 28 etc.

[0039] Based on the situation that the phase change material contained in the phase change material layer PCM can be single or a combination of multiple phase change materials, the present invention does not specifically limit the number of layers of the phase change material layer PCM, which can be a single layer or multiple layers, such as 2 layers, 3 layers, 4 layers, 5 layers, 6 layers or even more layers. The crystallization temperature and threshold voltage of adjacent two layers of phase change materials can be different. When the pulse voltage or pulse current corresponding to the phase change materials with different crystallization temperatures and threshold voltages is also different, in this way, under a pulse voltage or pulse current of a specific magnitude, it may make the phase change materials of all layers of the phase change material layer PCM be in the low resistance state, or it may make the phase change materials of all layers of the phase change material layer PCM be in the high resistance state, or it may make the phase change materials of some layers be in the low resistance state while the phase change materials of other layers be in the high resistance state. Thus, the low resistance state of the phase change memory corresponds to the crystallization of all or part of the phase change materials in the phase change material layer PCM, and the high resistance state of the phase change memory corresponds to the amorphous state of the phase change material layer PCM.

[0040] The N-type thermoelectric material layer includes one or a combination of two or more of the elements Bi, Te, Sb, Sn and Se, such as a combination of one or two or more of Bi2Te3, Sb2Te3, Bi2Se3 and SnSe. Among them, SnSe (tin selenide) has particularly excellent thermoelectric performance; the inventor found through research that by doping one or a combination of two or more of Bi, Ti, and Pb in SnSe to form N-type SnSe, and by using means such as doping to regulate the conduction characteristics of SnSe, while obtaining the N-type SnSe material, its thermoelectric performance can be greatly improved. For example, when Ti and Pb are co-doped in SnSe, and when the doping amount of Ti is greater than 6%, the conductivity of the N-type SnSe material is also effectively improved; when the doping amount of Pb is 20% - 25%, the thermoelectric performance of the N-type SnSe material is optimal. Compared with the case without Pb doping, the highest ZT value (i.e., the dimensionless thermoelectric figure of merit, ZT=(S2σ / k)T) can reach 0.37.

[0041] Specifically, the SnSe precursor powder can be prepared by mechanical alloying, and then the SnSe thin film can be prepared by vacuum thermal evaporation technology. Under this thermal evaporation condition, Ti and Pb are co-doped to form the N-type SnSe thin film.

[0042] In another embodiment, SnSe can also be doped with Br (bromine) to prepare N-type SnSe. The Br-doped SnSe has an overlapping interlayer charge density, effectively improving the conductivity of the SnSe material.

[0043] In another embodiment, a small amount of metal atoms (such as Ag or Cu) can also be doped into the N-type SnSe semiconductor thin film structure. This metal atom-doped thermoelectric material makes full use of the multi-layered structure and stable chemical properties of the SnSe semiconductor. At the same time, it also utilizes the good electron transport characteristics of Ag and Cu atoms doped into the microstructure, which can effectively increase the carrier concentration and transport efficiency of the N-type SnSe thermoelectric thin film, thereby improving the conductivity of N-type SnSe without changing its conduction type.

[0044] In this embodiment, by using SnSe as the N-type thermoelectric material layer, it has the following advantages: (1) SnSe has remarkable characteristics such as low toxicity, environmental friendliness, and ultra-low lattice thermal conductivity, and can undergo a phase change at a phase change temperature higher than 800K, changing from the orthorhombic Pnma structure to the orthorhombic Cmcm structure, so it has stable performance below the phase change temperature; (2) SnSe has a relatively high carrier concentration, and the carrier concentration can be further increased by introducing vacancies, (3.94×10 19 cm -3 ), so this material has good electrical conductivity characteristics; (3) SnSe has a relatively complex energy band structure and a suitable band gap (about 0.9eV), so this material has good electrical conductivity characteristics; (4) SnSe has dense crystal defects, including lattice distortion, dislocations, microcrystal bending, and obvious grain boundary density. These crystal defects can effectively scatter phonons of different frequencies, thereby effectively reducing the thermal conductivity of the material. For example, the thermal conductivity of SnSe is (0.17W×m -1 k -1 ); (5) SnSe has a high thermoelectric figure of merit (ZT value) and can achieve a maximum refrigeration temperature difference of about 40 - 50°C; therefore, the thermoelectric performance of SnSe can be improved from different aspects. N-type SnSe has a relatively high carrier concentration.

[0045] In this embodiment, a loop is formed by a P-type phase change material layer and an N-type thermoelectric material layer. A corresponding current is generated in the loop. When the current flows through the contact area between the P-type phase change material layer and the N-type thermoelectric material layer, the heat in the contact area will be absorbed, thereby generating a weak refrigeration phenomenon. That is, the Peltier effect is utilized (the Peltier effect, its physical phenomenon is as follows: when an electric current flows through a closed loop composed of two different materials, heat is released or absorbed at the material joint depending on the direction of the current. This absorbed or dissipated heat is called Peltier heat. The heat calculation formula can be expressed as: Q = πI. Where π is the Peltier coefficient, related to the thermoelectric power factor, π = (a1 - a2)T, a1 and a2 are the thermoelectric powers of the two materials forming the loop, T is the temperature of the relevant joint; I is the current in the loop) to achieve an electronic refrigeration mode at the interface between the two, thereby reducing the temperature at the interface of the phase change memory cell during reading, reducing the disturbance of the read pulse to the phase change memory cell, and further ensuring the stability of the stored data.

[0046] The select layer OTS is located below the N-type thermoelectric material layer 102, or the select layer OTS is located above the P-type phase change material layer 101. The select layer OTS (Ovonic Threshold Switch) is, for example, a bidirectional threshold switch. The basic principle of the select layer OTS is: using an electrical signal to control the switch of the select layer. When an electrical signal is applied to the select layer to cause the select layer OTS to change from a high-resistance state to a low-resistance state, the select layer is in the on state at this time; when the electrical signal is removed, the select layer OTS changes from a low-resistance state to a high-resistance state again, and the select layer is in the off state.

[0047] In some embodiments, the phase change memory has a plurality of word lines (WL) extending along a first direction (e.g., the X direction) and a plurality of bit lines (BL) extending along a second direction (e.g., the Y direction), and the first direction and the second direction are orthogonal; the phase change memory has a plurality of phase change memory cells 10 arranged in an array, and the phase change memory cells 10 are respectively disposed at the intersections of the corresponding word lines WL and bit lines BL, and the phase change memory cells 10 are columnar structures.

[0048] The word line WL can be formed of a material including at least one of conductive materials such as cobalt (Co), rhodium (Rh), or ruthenium (Ru), and the bit line BL can be formed of a material including at least one of conductive materials such as cobalt (Co), rhodium (Rh), or ruthenium (Ru). Voltages are applied to both ends of the word line and the bit line respectively to perform electrical access to each phase change memory cell 10.

[0049] Such as Figure 3As shown, the phase change memory cell 10 further includes: a top electrode layer TE located above the P-type phase change material layer 101, an intermediate electrode layer ME located between the N-type thermoelectric material layer 102 and the selection layer OTS, and a bottom electrode layer BE located below the selection layer OTS; wherein, the materials of the bottom electrode layer BE, the intermediate electrode layer ME, and the top electrode layer TE can be the same or different, and can be selected from one or more of C, Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, and Ni respectively; the positive end of the voltage applied across the phase change memory cell 10 is connected to the bottom electrode layer, and the negative end of the voltage is connected to the top electrode layer. The top electrode layer and the bottom electrode layer serve as the hot ends, and the temperature increases as heat flows in.

[0050] When the phase change memory operates, a voltage is applied across the two ends of the phase change memory cell 10 to form a loop with the P-type phase change material layer and the N-type thermoelectric material layer. A corresponding current is generated in the loop. When the current flows through the contact area between the P-type phase change material layer and the N-type thermoelectric material layer, the heat in the contact area is absorbed, resulting in a refrigeration phenomenon. That is, an electronic refrigeration mode is realized at the interface between the two by using the Peltier effect, thereby reducing the temperature at the interface of the phase change memory cell during reading, reducing the disturbance of the read pulse to the phase change memory cell, and avoiding the loss of stored information.

[0051] Based on the same inventive concept, this embodiment also provides a manufacturing method for a phase change memory, including the following steps:

[0052] S1. Stack a P-type phase change material layer, an N-type thermoelectric material layer, and a selection layer sequentially along the longitudinal direction;

[0053] Wherein, the P-type phase change material layer, the N-type thermoelectric material layer, and the selection layer are externally connected to a power source to form a closed loop. The selection layer has an open state and a closed state; when the selection layer is open, the contact interface between the P-type phase change material layer and the N-type thermoelectric material layer is in an electronic refrigeration mode.

[0054] Specifically, to form a phase change memory cell on a substrate, first, a substrate is provided, which is any suitable substrate material, such as silicon, germanium, silicon-on-insulator, etc.; then, through suitable process methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, a stacked structure including a selection layer, an N-type thermoelectric material layer, and a P-type phase change material layer is sequentially formed on the substrate. The P-type phase change material layer 101 is adjacent to and in contact with the N-type thermoelectric material layer 102.

[0055] Exemplarily, the N-type thermoelectric material layer includes one or more combinations of elements Bi, Te, Sb, Sn, and Se, such as one or more combinations of Bi2Te3, Sb2Te3, Bi2Se3, and SnSe. Among them, SnSe (tin selenide) has particularly excellent thermoelectric properties; the SnSe precursor powder is prepared by mechanical alloying, and the polycrystalline SnSe bulk material is prepared by using spark plasma sintering technology. One or more combinations of Bi, Ti, and Pb are doped in SnSe to form N-type SnSe. By using means such as doping to regulate the conduction characteristics of SnSe, while obtaining the N-type SnSe material, its thermoelectric properties can be greatly improved.

[0056] A top electrode layer TE located above the P-type phase change material layer 101, an intermediate electrode layer ME located between the N-type thermoelectric material layer 102 and the strobing layer OTS, and a bottom electrode layer BE located below the strobing layer OTS can also be formed. The methods that can be adopted for the bottom electrode layer BE, the intermediate electrode layer ME, and the top electrode layer TE include but are not limited to sputtering method, evaporation method, chemical vapor deposition method (CVD), plasma enhanced chemical vapor deposition method (PECVD), low pressure chemical vapor deposition method (LPCVD), metal organic chemical vapor deposition method (MOCVD), molecular beam epitaxy method (MBE), atomic vapor deposition method (AVD), or atomic layer deposition method (ALD), etc.

[0057] In summary, this embodiment provides a phase change memory and a manufacturing method thereof. The phase change memory includes: a P-type phase change material layer, an N-type thermoelectric material layer, and a strobing layer stacked in sequence along the longitudinal direction; the P-type phase change material layer, the N-type thermoelectric material layer, and the strobing layer are externally connected to a power supply to form a closed loop, and the strobing layer has an open state and a closed state; when the strobing layer is open, the contact interface between the P-type phase change material layer and the N-type thermoelectric material layer is in an electronic refrigeration mode. In this embodiment, by forming a loop with the P-type phase change material layer and the N-type thermoelectric material layer, a corresponding current is generated in the loop. When the current flows through the contact area between the P-type phase change material layer and the N-type thermoelectric material layer, the heat in the contact area will be absorbed, generating a refrigeration phenomenon, thereby reducing the temperature at the interface of the phase change memory cell during reading, reducing the disturbance of the read pulse to the phase change memory cell, reducing the read error value of the phase change memory cell, and avoiding the loss of stored information.

[0058] The various embodiments in this specification are described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the methods disclosed in the embodiments, since they correspond to the devices disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description in the method part.

[0059] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the rights of the present invention in any way. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical content disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and decorations made to the above embodiments according to the technical essence of the present invention without departing from the technical solution of the present invention all fall within the protection scope of the technical solution of the present invention.

Claims

1. A phase change memory, characterized in that, Including: A phase change memory cell, which includes a P-type phase change material layer, an N-type thermoelectric material layer, and a select layer stacked in sequence along the longitudinal direction; wherein, the P-type phase change material layer, the N-type thermoelectric material layer, and the select layer are externally connected to a power supply to form a closed loop, and the select layer has an open state and a closed state; when the select layer is open, the contact interface between the P-type phase change material layer and the N-type thermoelectric material layer is in an electronic refrigeration mode. The N-type thermoelectric material layer includes one or a combination of two or more of Bi2Te3, Sb2Te3, and Bi2Se3, and SnSe; in the SnSe, one or a combination of two or more of Bi, Ti, and Pb is doped to form N-type SnSe.

2. The phase change memory according to claim 1, wherein The N-type thermoelectric material layer includes one or a combination of two or more of the elements Bi, Te, Sb, Sn, and Se.

3. The phase change memory according to claim 1, wherein Metal atoms are also doped in the N-type thermoelectric material layer.

4. The phase change memory according to claim 1, wherein The P-type phase change material layer includes a chalcogenide semiconductor material.

5. The phase change memory according to claim 1, characterized in that, Also including: A top electrode layer located above the P-type phase change material layer, an intermediate electrode layer located between the N-type thermoelectric material layer and the select layer, and a bottom electrode layer located below the select layer. The positive terminal of the externally connected power supply is connected to the bottom electrode layer, and the negative terminal is connected to the top electrode layer.

6. The phase change memory according to any one of claims 1-5, characterized in that, Also including a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction, where the first direction and the second direction are orthogonal; the phase change memory cells are arranged in an array, and each phase change memory cell is respectively disposed at the intersection of the corresponding word line and bit line.

7. A manufacturing method of a phase change memory, characterized in that, Including the following steps: Stacking a P-type phase change material layer, an N-type thermoelectric material layer, and a select layer in sequence along the longitudinal direction; Wherein, the P-type phase change material layer, the N-type thermoelectric material layer, and the select layer are externally connected to a power supply to form a closed loop, and the select layer has an open state and a closed state; when the select layer is open, the contact interface between the P-type phase change material layer and the N-type thermoelectric material layer is in an electronic refrigeration mode. The N-type thermoelectric material layer includes one or a combination of two or more of Bi2Te3, Sb2Te3, and Bi2Se3, and SnSe; in the SnSe, one or a combination of two or more of Bi, Ti, and Pb is doped to form N-type SnSe.

8. The manufacturing method of the phase change memory according to claim 7, characterized in that, The preparation method of the N-type thermoelectric material layer includes: preparing a SnSe precursor powder by mechanical alloying and preparing a polycrystalline SnSe bulk material by using a spark plasma sintering technique.

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