Power management chip high and low side driving signal timing optimization method and system

Abstract

The application provides a power management chip high-low side driving signal timing optimization method and system. Wherein, the method collects temperature data of the power management chip under switching transient working condition by infrared thermal imaging technology, synchronously obtains three-dimensional temperature field distribution of the surface and internal junction temperature of the packaging layer; based on the spatial continuity of the temperature field, the temperature variation characteristics of the power device area are extracted, and the temperature gradient is converted into the Seebeck voltage by using the thermoelectric material embedded in the hot spot area to construct a dynamic thermoelectric feedback network; the coupling relationship between the hot carrier concentration and the driving signal phase shift is established according to the Seebeck voltage data, the disturbance of the hot carrier mobility change on the MOSFET switching delay is quantified; based on the coupling relationship, the rising / falling edge slope of the gate voltage is adjusted, the phase deviation caused by the hot carrier effect is eliminated through dynamic compensation, and the switching performance is optimized. The application improves the dynamic response accuracy of the power management chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip high-low side drive signal timing optimization, and particularly relates to a power management chip high-low side drive signal timing optimization method and system. BACKGROUND

[0002] Under the condition of sudden change of large current load, the high-low side drive signal of the power management chip is prone to dead time timing misalignment due to hot carrier effect, parasitic parameter coupling and other factors, causing the risk of bridge arm shoot-through or increased switching loss. Especially in the scenes of new energy vehicles and high-power converters, rapid jump of load current will exacerbate the phase shift of drive signal, and traditional open-loop control is difficult to dynamically compensate the timing deviation, so there is an urgent need for a closed-loop optimization method capable of monitoring the dead time timing and adaptively adjusting the edge slope of the drive signal.

[0003] A typical solution to this problem is a dynamic dead time adjustment technology based on gate voltage sampling feedback: by high-speed acquisition of the gate voltage waveform of high-low side MOSFET, the timing deviation of the rising / falling edge is detected in combination with the digital controller, and the dead time is dynamically adjusted to avoid shoot-through. This scheme uses hardware-in-the-loop simulation to optimize control parameters, and can respond to load mutation at the microsecond level.

[0004] Although the above-mentioned scheme can alleviate the timing misalignment problem, it relies on voltage sampling feedback and cannot directly perceive the influence of chip internal junction temperature change and hot carrier mobility nonlinearity disturbance. Especially under high temperature and large current transient conditions, the edge distortion of the gate voltage is strongly related to the hot carrier concentration, and it is difficult to accurately quantify the phase shift caused by the thermal-electric coupling effect through electrical signal feedback only, resulting in compensation lag or over-regulation, which ultimately limits the improvement of system dynamic performance. SUMMARY

[0005] The present application provides a power management chip high-low side drive signal timing optimization method and system to solve the problem of chip high-low side drive signal timing difference in the prior art.

[0006] In a first aspect, the present application provides a power management chip high-low side drive signal timing optimization method, comprising:

[0007] Collecting infrared thermal image data of the power management chip under switching transient condition, and synchronously acquiring three-dimensional temperature field distribution of the surface and internal junction temperature of the chip package layer;

[0008] Based on the spatial continuity of the three-dimensional temperature field distribution, extracting the temperature variation characteristics of the chip power device region;

[0009] Converting the temperature gradient in the temperature variation feature into a spatially discrete Seebeck voltage distribution by embedding a thermoelectric material in a specific hotspot region of the chip package layer to construct a dynamic thermoelectric feedback network;

[0010] Based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, a coupling response relationship between the dynamic response of the hot carrier concentration and the phase shift of the driving signal is established to quantify the time-varying disturbance of the nonlinear fluctuation of the hot carrier mobility on the switching delay of the high-low side MOSFET device;

[0011] According to the time-varying disturbance parameters output by the coupling response relationship, the rising edge slope and the falling edge slope of the gate voltage of the high-low side MOSFET device are reconstructed;

[0012] By matching the dynamic compensation parameters of the rising edge slope and the falling edge slope, the phase deviation of the driving signal caused by the hot carrier concentration is compensated within the switching period.

[0013] Optionally, by matching the dynamic compensation parameters of the rising edge slope and the falling edge slope, the phase deviation of the driving signal caused by the hot carrier concentration is compensated within the switching period, comprising:

[0014] At the beginning of the switching period, the peak timing of the bus voltage waveform generated by the dynamic thermoelectric feedback network in the current period is monitored, and the dynamic compensation parameters including the rising edge slope compensation coefficient and the falling edge slope compensation coefficient are retrieved from the corresponding relationship table established by the coupling response relationship according to the peak timing of the bus voltage waveform;

[0015] The rising edge slope compensation coefficient is multiplied by the positive voltage change rate of the reconstructed accelerated rising section to obtain the compensated rising edge execution parameter, and similarly the falling edge slope compensation coefficient is multiplied by the negative voltage change rate of the reconstructed accelerated falling section to obtain the compensated falling edge execution parameter;

[0016] In the rising edge time window of the current switching period, the driving circuit is controlled to output the positive voltage change rate according to the compensated rising edge execution parameter, and similarly in the falling edge time window, the driving circuit is controlled to output the negative voltage change rate according to the compensated falling edge execution parameter.

[0017] Optionally, according to the time-varying disturbance parameters output by the coupling response relationship, the rising edge slope and the falling edge slope of the gate voltage of the high-low side MOSFET device are reconstructed, comprising:

[0018] acquire an initial rising edge time point and an initial falling edge time point of the original gate drive signal in a switching cycle, and calculate a required forward shift time amount of the initial rising edge time point and a required backward shift time amount of the initial falling edge time point according to a phase shift in the time-varying disturbance parameter;

[0019] set a new rising edge starting point at a position of the forward shift time amount before the initial rising edge time point, and increase a positive voltage change rate based on an original rising edge slope to form an accelerated rising section, and set a new falling edge starting point at a position of the backward shift time amount after the initial falling edge time point, and increase a negative voltage change rate based on an original falling edge slope to form an accelerated falling section;

[0020] connect an end point of the accelerated rising section to an original rising edge vertex, and connect a start point of the accelerated falling section to an original falling edge vertex, to complete a reconstructed rising edge slope and falling edge slope waveform.

[0021] Optionally, based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, a coupling response relationship between a dynamic response of a hot carrier concentration and a phase shift of a drive signal is established to quantify time-varying disturbance of a hot carrier mobility nonlinear fluctuation on a high-low side MOSFET device switching delay, including:

[0022] synchronously acquire a bus voltage waveform and a gate drive signal waveform of the thermoelectric feedback network in a switching transient process, and measure a time sequence deviation between a peak time sequence of the bus voltage waveform and a rising edge / falling edge turning point of the gate drive signal;

[0023] establish a corresponding relationship table between a bus voltage change rate and a time sequence deviation amount of the gate drive signal, and convert discrete voltage distribution data into a drive signal phase shift amount through the corresponding relationship table;

[0024] calculate a hot carrier mobility disturbance parameter according to a cumulative effect of the phase shift amount with a switching cycle number.

[0025] Optionally, based on spatial continuity of the three-dimensional temperature field distribution, a temperature variation feature of a chip power device region is extracted, including:

[0026] identify a spatial coordinate range corresponding to the power device region in the three-dimensional temperature field distribution, and extract a time-temperature variation curve of all grid points in the power device region in a switching cycle;

[0027] calculate a similarity of temperature variation curves between adjacent grid points, merge continuous spatial regions with a similarity exceeding a threshold value, and select a grid point with a maximum temperature variation amplitude in the merged continuous region as a feature monitoring point;

[0028] record the highest temperature value, the lowest temperature value and the temperature change rate of the feature monitoring point in each switching cycle as the temperature change feature.

[0029] Optionally, the temperature gradient in the temperature change feature is converted into a spatially discrete Seebeck voltage distribution by embedding a thermoelectric material in a specific hotspot area of the chip package layer, to construct a dynamic thermoelectric feedback network, including:

[0030] Embedding an array of bismuth telluride-based thermoelectric material units in the area of the chip package layer corresponding to the spatial position of the feature monitoring point;

[0031] Connecting the two ends of each thermoelectric material unit to the upper surface of the package layer and the silicon substrate junction, respectively, when an axial temperature gradient is generated in the power device area, each thermoelectric material unit generates a discrete voltage signal according to the temperature difference between the two ends;

[0032] Parallelly connecting the discrete voltage signal output ends of all thermoelectric material units to form a feedback bus, to constitute a thermoelectric feedback network with a spatially discrete voltage distribution.

[0033] Optionally, the infrared thermal image data of the power management chip under switching transient operating conditions is collected, and the three-dimensional temperature field distribution of the surface and internal junction temperature of the chip package layer is synchronously obtained, including:

[0034] Aligning the high-speed infrared thermal imager to the upper surface of the chip package layer, and collecting infrared thermal image data under switching transient operating conditions;

[0035] Based on the thickness and thermal conductivity parameters of each layer of material of the chip package layer, an axial heat conduction equation from the surface of the package layer to the internal junction temperature area is established, and the infrared thermal image data is input as a boundary condition into the axial heat conduction equation, and the axial temperature distribution of the internal package material and the junction temperature area is calculated layer by layer;

[0036] Spatially superimposing the axial temperature distribution at each sampling time on the surface two-dimensional infrared thermal image data at the corresponding time to form a three-dimensional temperature field distribution.

[0037] In a second aspect, the present application provides a power management chip high-low side drive signal timing optimization system, including:

[0038] The acquisition module collects infrared thermal image data of the power management chip under switching transient operating conditions, and synchronously obtains the three-dimensional temperature field distribution of the surface and internal junction temperature of the chip package layer;

[0039] The extraction module extracts the temperature change feature of the chip power device area based on the spatial continuity of the three-dimensional temperature field distribution;

[0040] a constructing module, which converts a temperature gradient in the temperature variation feature into a spatially discrete Seebeck voltage distribution by embedding a thermoelectric material in a specific hotspot region of the chip package layer, to construct a dynamic thermoelectric feedback network;

[0041] a establishing module, which establishes a coupling response relationship between a dynamic response of the hot carrier concentration and a phase shift of the driving signal based on Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, to quantify time-varying disturbance of the nonlinear fluctuation of the hot carrier mobility on the switching delay of the high-low side MOSFET device;

[0042] a reconstructing module, which reconstructs a rising edge slope and a falling edge slope of the gate voltage of the high-low side MOSFET device according to time-varying disturbance parameters output by the coupling response relationship;

[0043] a switching module, which compensates for the phase deviation of the driving signal caused by the hot carrier concentration in the switching cycle by matching dynamic compensation parameters of the rising edge slope and the falling edge slope.

[0044] In a third aspect, an embodiment of the present application provides a computing device, including a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component, to implement the power management chip high-low side driving signal timing optimization method in the first aspect.

[0045] In a fourth aspect, an embodiment of the present application provides a computer storage medium, which stores a computer program; when the computer program is executed by a computer, the power management chip high-low side driving signal timing optimization method in the first aspect is implemented.

[0046] In the embodiment of the present application, infrared thermal image data of the power management chip under switching transient operating conditions is collected, and a three-dimensional temperature field distribution of the surface and internal junction temperature of the chip package layer is synchronously acquired; based on the spatial continuity of the three-dimensional temperature field distribution, temperature variation features of the chip power device region are extracted; a dynamic thermoelectric feedback network is constructed by converting a temperature gradient in the temperature variation features into a spatially discrete Seebeck voltage distribution through embedding a thermoelectric material in a specific hotspot region of the chip package layer; a coupling response relationship between a dynamic response of the hot carrier concentration and a phase shift of the driving signal is established based on Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, to quantify time-varying disturbance of the nonlinear fluctuation of the hot carrier mobility on the switching delay of the high-low side MOSFET device; a rising edge slope and a falling edge slope of the gate voltage of the high-low side MOSFET device are reconstructed according to time-varying disturbance parameters output by the coupling response relationship; and the phase deviation of the driving signal caused by the hot carrier concentration is compensated for in the switching cycle by matching dynamic compensation parameters of the rising edge slope and the falling edge slope.

[0047] The application has the following beneficial effects:

[0048] The non-contact high-precision synchronous monitoring of the chip surface and internal junction temperature is realized, and spatial continuous temperature field data is provided for thermal analysis. The key heating area is focused, and the temperature gradient change law under transient operating conditions is identified to provide input features for thermal-electric feedback. The thermal-electric effect is directly perceived to thermal disturbance, a dynamic feedback network is constructed, and the delay of traditional electric signal sampling is avoided. The time-varying influence of thermal carrier mobility fluctuation on switch delay is quantified, and the physical mechanism of thermal-electric coupling is revealed. The driving signal waveform is dynamically adjusted to offset the phase deviation caused by thermal carriers, and the timing error is suppressed from the source. The edges of the driving signal are closed-loop corrected within the switching period to ensure the dead-time timing accuracy and avoid bridge arm shoot-through or loss increase.

[0049] Further, at the beginning of the switching period, the rising edge / falling edge slope compensation coefficient is retrieved from the pre-established coupling relationship table according to the bus voltage peak timing of the dynamic thermal-electric feedback network; the coefficient is multiplied by the reconstructed positive / negative voltage change rate respectively to generate the compensated execution parameters; finally, the driving circuit output is controlled according to the corrected slope within the corresponding time window to realize closed-loop compensation of the phase deviation.

[0050] The application realizes the adaptive adjustment of the driving signal slope within the switching period through the dynamic matching of the bus voltage timing and the compensation parameters, accurately offsets the phase deviation caused by the fluctuation of thermal carrier concentration, and significantly improves the performance and reliability of the dead-time timing control.

[0051] These and other aspects of the application will become more apparent from the following description of embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0053] Figure 1 A flowchart of a high-low side driving signal timing optimization method of a power management chip provided by the application is shown;

[0054] Figure 2 A structural schematic diagram of a power management chip high-low side driving signal timing optimization system provided by the application is shown;

[0055] Figure 3 A structural schematic diagram of a computing device provided by the application is shown. DETAILED DESCRIPTION

[0056] In order for those skilled in the art to better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0057] In some processes described in the specification and claims of the present application and the above description, a plurality of operations appearing in a specific order are included, but it should be clearly understood that these operations can be executed in the order appearing in the text or in parallel, and the serial numbers of the operations, such as 101, 102, etc., are only used to distinguish different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes can include more or fewer operations, and the operations can be executed in sequence or in parallel. It should be noted that the "first", "second", etc. in the text are used to distinguish different messages, devices, modules, etc., and do not represent the order, nor do "first" and "second" represent different types.

[0058] In the field of timing control of high and low side drive signals of power management chips, the existing scheme mainly relies on dynamic dead zone adjustment technology of gate voltage sampling feedback, which detects the edge timing of the drive signal at high speed and corrects the dead zone time in a closed loop. However, this scheme has an essential defect: it only indirectly adjusts the timing through electrical signal feedback and cannot directly perceive the dynamic changes of the internal hot carrier concentration and junction temperature distribution of the chip. Especially under the condition of sudden load change, the nonlinear fluctuation of hot carrier mobility will cause thermal distortion of the gate voltage waveform, and the traditional electrical signal sampling not only cannot quantify this thermal-electric coupling effect, but also causes delay in compensation response due to temperature sensor lag, ultimately resulting in overcompensation or undercompensation of the dead zone timing, which seriously restricts the switching reliability in large current scenarios.

[0059] To solve the above problems, the present application proposes a drive signal timing optimization method based on infrared thermal image and thermoelectric feedback fusion, which is innovative in that it synchronously acquires the three-dimensional temperature field distribution of the chip through infrared thermal imaging, combines the embedded thermoelectric material to directly convert the temperature gradient into a Seebeck voltage, and constructs a thermal-electric coupled feedback network. Specifically, by establishing a dynamic response model of hot carrier concentration and phase shift, the influence of temperature disturbance on switching delay is accurately quantified, and the rising / falling edge slope of the gate voltage is dynamically reconstructed for compensation. This method breaks through the limitations of traditional electrical signal feedback, realizes full-link closed-loop control from "temperature field → carrier mobility → drive timing", fundamentally solves the monitoring and compensation problem of thermal phase shift, avoids the inherent defect of temperature sensor lag, and improves the response accuracy of hot spot areas through the spatial discrete distribution of thermoelectric materials, ultimately ensuring the stability and reliability of the dead zone timing under large current sudden change conditions.

[0060] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0061] Figure 1 A flow chart of a method for optimizing high and low side driving signal timing of a power management chip is provided in the embodiments of the present application, as shown in Figure 1 The method comprises the following steps.

[0062] 101, collecting infrared thermal image data of the power management chip under switching transient operating conditions, and synchronously acquiring three-dimensional temperature field distribution of the surface and internal junction temperature of the chip packaging layer;

[0063] Optionally, the collecting infrared thermal image data of the power management chip under switching transient operating conditions, and synchronously acquiring three-dimensional temperature field distribution of the surface and internal junction temperature of the chip packaging layer in step 101 can specifically include:

[0064] 1011, aiming the high-speed infrared thermal imager at the upper surface of the chip packaging layer, and collecting infrared thermal image data under switching transient operating conditions;

[0065] 1012, based on the thickness and thermal conductivity parameters of each layer of material of the chip packaging layer, establishing an axial heat conduction equation from the surface of the packaging layer to the internal junction temperature region, and inputting the infrared thermal image data as a boundary condition into the axial heat conduction equation, and calculating the axial temperature distribution of the internal packaging material and the junction temperature region layer by layer;

[0066] 1013, spatially superimposing the axial temperature distribution at each sampling time and the surface two-dimensional infrared thermal image data at the corresponding time to form a three-dimensional temperature field distribution.

[0067] In the above scheme, the high-speed infrared thermal imager refers to a device that can quickly capture the infrared radiation of the surface of an object. By detecting the thermal radiation intensity of different positions on the surface of the object, an image reflecting the temperature distribution of the surface is generated, which is suitable for capturing scenes with temperature changes in a short time. The switching transient state refers to the transition state of the switching element (such as MOSFET) in the power management chip, which is rapidly turned on and off. At this time, the current and voltage inside the chip change rapidly, which may cause the local temperature to rise rapidly or fluctuate. The packaging layer refers to the protective structure outside the chip, which is usually composed of multiple layers of materials (such as ceramics, metals, plastics, etc.), and plays a role in fixing the chip, connecting the circuit, and dissipating heat. The thickness and thermal conductivity of each layer of material will affect the speed of heat transfer. The thermal conductivity parameter refers to the ability of a material to conduct heat, and the larger the value, the easier the material conducts heat (for example, metal has high thermal conductivity, and plastic has low thermal conductivity). The heat conduction equation refers to a mathematical model that describes the heat transfer in the thickness direction (axial direction) of the packaging layer, considering factors such as temperature changes over time and space, material thermal conductivity, etc., which is used to calculate the temperature distribution at different positions inside the packaging layer. The two-dimensional infrared thermal image data of the surface refers to the temperature distribution image of the upper surface of the chip packaging layer collected by the high-speed infrared thermal imager, which presents the temperature values of each point in a two-dimensional plane, reflecting the instantaneous temperature of the surface under transient conditions. The three-dimensional temperature field distribution refers to the combination of the two-dimensional temperature data of the surface of the packaging layer and the axial temperature distribution data inside, forming a three-dimensional space temperature distribution model containing temperature information of each position on the surface and inside, which fully displays the temperature distribution of the chip under transient conditions.

[0068] In the embodiments of the present application, first, the upper surface of the chip packaging layer is imaged using a high-speed infrared thermal imager through step 1011, and the collection is started under the switching transient state to quickly obtain infrared thermal image data at multiple time points. For example, at the moment when the switching element of the chip is switched from off to on, for example, for 10 microseconds, the thermal imager continuously shoots at a high frame rate, for example, 5000 frames per second, and records the temperature distribution image of the surface of the packaging layer at each moment. These images contain temperature information of each point on the surface, providing basic data for subsequent calculations.

[0069] Secondly, based on the thickness of each layer of material of the packaging layer, such as the thickness of the bottom ceramic layer being 0.1mm, the thickness of the middle metal layer being 0.2mm, the thickness of the top plastic layer being 0.3mm, and the thermal conductivity parameters, such as the thermal conductivity of the ceramic being 10W / (m·K), the thermal conductivity of the metal layer being 50W / (m·K), and the thermal conductivity of the plastic layer being 0.5W / (m·K), an equation describing the heat transfer in the axial direction is established, which is where is the thermal diffusivity, which is derived from , is the density, is the specific heat capacity, is the temperature, is the time, The axial distance is the distance along the normal line of the surface of the packaging layer to the inside of the chip. The infrared thermal image data collected in 1011 is taken as the boundary condition, i.e., the initial temperature value of each point on the surface, which is substituted into the equation, and the temperature distribution of each layer inside the packaging material at different times is calculated layer by layer through numerical calculation methods such as finite difference method. For example, starting from the top plastic layer, the temperature change of the next metal layer is calculated according to its thermal conductivity and surface temperature, and then the temperature of the bottom ceramic layer is calculated in turn, until the junction temperature region inside the chip, i.e., the core heating part of the chip, is reached.

[0070] Finally, the axial temperature distribution inside the packaging layer (including the temperature values of each layer of material at different depths) calculated by step 1012 at each sampling time (such as t1, t2, t3) is spatially superimposed with the surface two-dimensional infrared thermal image data (temperature values of each point on the surface) collected at the corresponding time by step 1011. For example, the surface thermal image data at t1 shows that the temperature of a certain point on the surface is 80°C, while the axial calculation result shows that the temperature of the metal layer 0.1 mm below that point is 90°C, the temperature of the ceramic layer 0.3 mm below is 70°C, and the temperature of the junction temperature region 0.5 mm below is 100°C. These temperature values at different depths are integrated with the temperature value of the surface in the same three-dimensional coordinate system to form a three-dimensional temperature field distribution model containing temperature information of the surface and the inside, which intuitively shows the temperature change of the chip from the surface to the internal junction temperature region under transient operating conditions.

[0071] For example, in actual testing, a power management chip (referred to as chip X) with a multi-layer packaging structure was selected, and its packaging layer was composed of a ceramic substrate (0.15 mm thick, thermal conductivity 12 W / (m·K)), a copper metal layer (0.2 mm thick, thermal conductivity 380 W / (m·K)), and an epoxy resin layer (0.3 mm thick, thermal conductivity 0.3 W / (m·K)). A high-speed infrared thermal imager (model H) with a frame rate of 5000 frames / second was used,

[0072] Specifically, during the transient process of the switching element of chip X from off to on (duration about 100 ms), continuous shooting was performed on the upper surface of its packaging layer, and the surface two-dimensional infrared thermal image data at different time points were collected. ​The two-dimensional infrared thermal image data at t=0 μs is then obtained. Then, according to the thickness and thermal conductivity parameters of each layer of material, the axial heat conduction equation is established, the surface thermal image data at t=0 μs (the initial temperature of each point) is taken as the boundary condition, and after being substituted into the equation, the temperature distribution inside the ceramic substrate at t=2 μs (such as the temperature at 0.05 mm from the surface is 75°C, and the temperature at 0.15 mm is 60°C), the temperature distribution of the copper metal layer at t=5 μs (such as the temperature at 0.2 mm from the surface is 85°C), the temperature distribution of the epoxy resin layer at t=8 μs (such as the temperature at 0.25 mm from the surface is 90°C), and the temperature of the junction temperature region (such as the temperature at 0.5 mm from the surface is 110°C) are calculated by the finite difference method. Finally, the axial temperature distributions at different times are superimposed with the corresponding surface thermal image data to form a three-dimensional temperature field distribution from the surface to the junction temperature region. For example, at t=5 μs, the temperature of a certain point on the surface is 95°C, the temperature of the copper layer 0.1 mm below is 100°C, the temperature of the epoxy resin layer 0.3 mm below is 80°C, and the temperature of the junction temperature region 0.5 mm below is 110°C, thereby comprehensively displaying the temperature distribution of the chip under this transient operating condition.

[0073] This step can accurately obtain the three-dimensional temperature distribution of the chip from the surface to the junction temperature region during the switching transient operating condition by collecting and calculating the surface and internal temperature data of the chip packaging layer, thereby providing specific temperature data support for subsequent analysis of the influence of high and low side drive signal timing on temperature, helping to identify temperature abnormal regions and key time nodes, and thereby providing a basis for optimizing the drive signal timing to reduce the risk of local overheating.

[0074] 102. Based on the spatial continuity of the three-dimensional temperature field distribution, the temperature variation characteristics of the power device region of the chip are extracted;

[0075] Optionally, the step of extracting the temperature variation characteristics of the power device region of the chip based on the spatial continuity of the three-dimensional temperature field distribution in step 102 can specifically include:

[0076] 1021. Identifying the spatial coordinate range corresponding to the power device region in the three-dimensional temperature field distribution, and extracting the time-temperature variation curve of all grid points in the power device region within the switching period;

[0077] 1022. Calculating the similarity of the temperature variation curves between adjacent grid points, merging the continuous spatial regions with a similarity exceeding a threshold value, and selecting the grid point with the largest temperature variation amplitude in the merged continuous region as a feature monitoring point;

[0078] 1023. Recording the highest temperature value, the lowest temperature value, and the temperature variation rate of the feature monitoring point in each switching period as the temperature variation characteristics.

[0079] In the above scheme, the temperature variation feature refers to a key indicator used to describe the temperature change of the feature monitoring point, mainly including heat flux density and temperature gradient. The three-dimensional temperature field distribution refers to the specific temperature value of each micro location point in the entire three-dimensional space from the packaging surface to the core junction of the chip at each sampling time. This is like establishing a three-dimensional temperature map that changes over time inside the chip. Spatial continuity refers to the temperature change behavior (such as the trend and speed of temperature rise / fall) of adjacent location points in physical space, which is usually similar. Just like the temperature change of adjacent rooms is usually closer than rooms far apart. The power device region refers to the area where the core electronic elements that actually perform switching operations (turn on or off current) are located inside the chip. These areas will generate a large amount of heat when switching, and are the focus of heat analysis. The grid point refers to the three-dimensional grid (like a small cubic lattice) divided into countless small three-dimensional grids in the three-dimensional temperature field for calculation and storage convenience. The vertex (or center point) of each grid is a temperature data point. The time-temperature change curve refers to the curve formed by the temperature value of a certain grid point changing with time over a period of time (such as a complete switching action period). Similarity refers to a numerical indicator of the similarity of the shape of two time-temperature change curves. The closer the shape (for example, both rising and falling), the higher the similarity value. The feature monitoring point refers to a few key location points in the power device region that best represent the overall temperature change characteristics (maximum fluctuation amplitude or fastest change) of the region.

[0080] In the embodiments of the present application, first, according to the three-dimensional temperature field data generated by step 101, the "block" occupied by the power device in the three-dimensional space is located, and the three-dimensional coordinate set of all grid points in the block is obtained. Then, for each grid point in the power device block, the temperature value recorded at each sampling time during the complete power switching process (such as a MOS tube from off to on and then off) is extracted. Connecting these temperature values in chronological order, the "time-temperature change curve" of each grid point is obtained. This is equivalent to drawing a chart for each micro location in the power device region that records how its own temperature fluctuates over time. For example, in a power device region containing 1000 grid points, this step generates 1000 independent temperature change curves.

[0081] Secondly, by step 1022, the grid points in the power device region are traversed For each grid point, its time-temperature curve is compared with the time-temperature curves of its immediate neighbors (such as 6 face neighbors) The similarity is calculated one by one. One commonly used calculation method is the Pearson correlation coefficient , the formula is as follows:

[0082]

[0083] wherein, is the temperature of the adjacent grid point and at time , is the average temperature of the adjacent grid point and in the entire switching cycle, is the total number of sampling times contained in the switching cycle. The value is between -1 and 1: greater than 0.9 is usually considered to be highly positively correlated (highly synchronized in trend), and greater than 0.7 can be considered to be significantly correlated. Set a high threshold, for example, threshold = 0.85, if the calculated of the adjacent two points exceeds this threshold, it is considered that the temperature change of the two points is almost "synchronized" and should belong to the same thermal response region. Merge the continuous spatial regions with high similarity: use the region growing algorithm in image processing. Starting from a seed point, continuously include points adjacent to the current point and with a similarity exceeding the threshold into the same region block. Finally, the entire power device region is divided into several (possibly one or more) continuous sub-regions with highly consistent internal temperature changes. Then in each merged continuous sub-region, traverse all the grid points in the region, calculate the temperature change amplitude recorded by each point in its temperature change curve, i.e. the difference between the maximum temperature and the minimum temperature, and select the grid point with the largest amplitude value as the monitoring point representing the temperature change characteristics of the entire continuous sub-region.

[0084] Finally, through step 1023, each feature monitoring point selected in step 1022 (one for each sub-region) is analyzed one by one to find the highest temperature value of the curve in this period and record it, find the lowest temperature value of the curve in this period and record it, find the fastest part of the curve in temperature rising or falling, which is usually just turned on or just turned off. According to the ratio of the temperature difference of the selected two points in this period to the corresponding time difference , the temperature change rate is calculated, i.e. , and then the highest temperature value, the lowest temperature value and the temperature change rate of each feature detection point are recorded as the temperature change characteristics.

[0085] For example, analyze the thermal behavior of a power chip used for motor control in switching transient:

[0086] Specifically, first, the transient three-dimensional temperature field of the chip (set as chip B) during the power switch action is constructed. By using the layout information of chip B, the area containing two power MOS tubes (MOS tube 1 and MOS tube 2) inside is located as a target power device area, and then the temperature data of 1500 grid points contained in the area within 10 consecutive switching cycles is extracted to generate 1500 temperature change curves. By calculating the Pearson correlation coefficient between adjacent grid point curves, it is found that the correlation coefficient between points in the area where MOS tube 1 is located is generally higher than 0.9 (very similar), the similarity in the area where MOS tube 2 is located is also high (also higher than the threshold of 0.85), but the point similarity between MOS tube 1 and MOS tube 2 is lower than 0.7 (different in change). Therefore, the entire power device area is divided into two continuous sub-areas (sub-area A represents MOS tube 1, and sub-area B represents MOS tube 2). In sub-area A, grid point M (temperature changes from 45°C to 125°C during switching, temperature difference 80°C) is found, and in sub-area B, grid point N (temperature changes from 42°C to 118°C, temperature difference 76°C) is found, which are respectively taken as feature monitoring points. Then, for the 3rd switching cycle, the temperature characteristics of point M are recorded: , the maximum temperature rise rate appears within 1 microsecond after the switch is turned on, and the section (the temperature rises from 50°C to 106°C within 0.8 μs) is calculated, and the maximum temperature drop rate is recorded . The same recording is also done for point N. These indicators represent the temperature change of the core area of the two power MOS tubes. The core effect of this step is to make full use of the natural law of temperature change inside the chip (similar changes of adjacent points), intelligently locate the core high-temperature area of the most critical heat generating device from the massive three-dimensional transient temperature data, and select a small number of representative monitoring points in the area that can most directly reflect the temperature change, and then extract the key indicators (maximum temperature, minimum temperature and temperature change speed) that quantitatively describe the temperature change. This greatly simplifies the complexity of subsequent analysis, enabling analysts to quickly and focusedly grasp the most severe hot spot and thermal shock state of the chip power device during the switching transient process.

[0087] 103. By embedding thermoelectric materials in the specific hot spot area of the chip packaging layer, the temperature gradient in the temperature change characteristics is converted into a spatially discrete Seebeck voltage distribution to construct a dynamic thermoelectric feedback network.

[0088] Optionally, the step 103 of converting the temperature gradient in the temperature change characteristics into a spatially discrete Seebeck voltage distribution by embedding thermoelectric materials in the specific hot spot area of the chip packaging layer to construct a dynamic thermoelectric feedback network can specifically include:

[0089] 1031. Embedding an array of Bi2Te3-based thermoelectric material units in the region of the chip package layer corresponding to the spatial location of the feature monitoring point;

[0090] 1032. Connecting the two ends of each thermoelectric material unit to the upper surface of the package layer and the silicon substrate junction, respectively, so that when an axial temperature gradient is generated in the power device region, each thermoelectric material unit generates a discrete voltage signal according to the temperature difference between its two ends;

[0091] 1033. Connecting the discrete voltage signal output terminals of all the thermoelectric material units in parallel to form a feedback bus, constituting a thermoelectric feedback network with a spatially discrete voltage distribution.

[0092] In the above scheme, thermoelectric material refers to a special material that can directly convert heat into electricity. When there is a temperature difference between the two ends of this material, a voltage will be generated between its two ends, similar to a micro thermoelectric generator. The specific hot spot region refers to the key region identified in step 102, i.e., the location of the power device inside the chip and the vicinity of the selected feature monitoring point. These regions have the most dramatic temperature changes during switching. The temperature gradient (axial) refers to the degree of temperature difference in the vertical direction from the surface of the chip package layer down to the core region of the chip, which is measured in step 101. The lower end near the core of the chip has a higher temperature, and the upper end near the surface of the package has a relatively lower temperature, forming a temperature change. The Seebeck effect refers to the basic working principle of thermoelectric materials: when there is a temperature difference between the two ends of the material, an internal voltage (called Seebeck voltage) will be generated. The greater the temperature difference, the greater the voltage generated. The spatially discrete Seebeck voltage distribution refers to the independent arrangement of thermoelectric material units at multiple different locations in the key hot spot region of the chip package layer. Each unit will independently generate a voltage signal according to the temperature difference between its two ends. These voltage signals come from different spatial locations (discrete points), and their collection constitutes a "spatial distribution" of voltage. The dynamic thermoelectric feedback network refers to the parallel connection of the voltage signals generated by the above-mentioned multiple thermoelectric material units to form a total data signal line (feedback bus). The total voltage signal on this bus will change (dynamically) with the temperature fluctuations of the hot spot region caused by the switching of the chip, and this signal can be used as a feedback input for the chip control system.

[0093] In the embodiments of the present application, according to the region corresponding to the location of the feature monitoring point determined in step 102, i.e., the core region above which the temperature changes most dramatically inside the chip, a plurality of small independent thermoelectric material units are precisely embedded. These units are arranged in a regular array, such as a small dot array or grid. The shape of each unit can be designed as a micro column or a sheet, with its height direction coinciding with the axial direction (thickness direction) of the chip package layer. For example, if step 102 determines that the feature monitoring point M is located at coordinates (x, y) on the chip package layer, a plurality of thermoelectric material units can be embedded in the region of the chip package layer corresponding to the coordinates (x, y) in a regular array, such as a small dot array or grid. Then, during packaging, a thermoelectric unit is vertically embedded above the position of the planar coordinate point in the packaging layer If there are three feature monitoring points, three thermoelectric units are embedded above the positions of the three points .

[0094] Secondly, by step 1032, it is ensured that each embedded thermoelectric material unit is exposed at both ends in the thickness direction (axial direction) at specific positions, the upper end is connected to (or close to) the uppermost surface of the packaging layer, i.e. the chip shell or heat sink position, and the lower end is connected to (or close to) the silicon substrate below the feature monitoring point, i.e. the core area where the chip actually works.

[0095] For example, Company C develops a high-performance power converter chip (Chip D). After such an arrangement, when the power device in the chip works, the high temperature generated at the junction area below it will form a temperature difference in the vertical direction with the upper surface of the package (usually lower temperature). According to the Seebeck effect, each thermoelectric material unit will generate a tiny voltage signal based on the actual temperature difference it feels at both ends independently , which is proportional to the temperature difference, and the direction depends on the direction of the temperature difference (high temperature end negative, low temperature end positive). Its mathematical expression is: . Where is the Seebeck voltage generated by the thermoelectric material unit, is the Seebeck coefficient of the thermoelectric material unit, which is a material property parameter, is the temperature difference between the lower end and the upper end of the thermoelectric material unit.

[0096] Finally, by step 1033, the output electrodes (the pair of electrodes that generate voltage) of all thermoelectric material units (such as U1, U2, U3) embedded at multiple hot spot positions (such as positions corresponding to feature monitoring points) are connected to the same common wire (i.e. in parallel). In this way, the total voltage on this common wire (feedback bus) represents the sum of the output voltages of all parallel thermoelectric units, or, if it is a linear system, it can be considered as the average effect of each unit voltage. The total voltage changes with the temperature gradient at different hot spot positions in the chip and the thermal state of the entire chip. This dynamically changing voltage signal can be used as the thermoelectric feedback signal output of the control system. For example, 15mV generated by U1, 10mV generated by U2, and 12mV generated by U3 are connected in parallel to the same feedback bus, assuming no load, then the bus voltage is approximately the combined value of their common influence (parallel is usually a signal convergence point).

[0097] ​Specifically, first, two key feature monitoring points P1 and P2 are determined in the core power area of the chip D. In the packaging process of the chip D, a bismuth telluride thermoelectric unit H1 is precisely embedded in the packaging layer directly above the position P1, and a thermoelectric unit H2 is embedded directly above the position P2. Both H1 and H2 are small columnar structures, the top of which is connected to the bottom surface of the aluminum cover of the packaging shell (as a cold end reference point), and the bottom of which is connected to the junction area of the silicon chip (a hot end heat source). When the power transistors inside the chip D switch at high speed, an axial temperature difference of about 100 degrees is generated at P1, and an axial temperature difference of 80 degrees is generated at P2. The Seebeck coefficient of the Bi2Te3 thermoelectric material used is about Therefore, the voltage generated by the H1 unit is The voltage generated by the H2 unit is The two voltage output lines are connected in parallel to the same feedback bus F. The voltage signal on the bus F is which comprehensively reflects the dynamic temperature changes of the two core hot spots of the chip D and is introduced into the control circuit part of the chip as a thermal state feedback signal.

[0098] The core effect of this step is to realize in-situ, passive (without external power supply) and direct electrical sensing of the temperature gradient of the key points inside the chip. By embedding the thermoelectric material unit directly below the specific hot spot area inside the packaging layer, and skillfully using the vertical temperature difference (temperature gradient) generated by the chip itself, the temperature difference is automatically converted into a discrete electrical signal by means of the Seebeck effect. Parallel combination of these electrical signals from the core hot spot area forms a global feedback voltage signal that can dynamically reflect the overall temperature rise state of the hot spots inside the chip. This provides a direct and reliable physical basis for feedback path for subsequent precise thermal state monitoring and closed-loop management (such as adaptive adjustment of switching frequency) inside the chip without complex external sensors.

[0099] 104. Based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, a coupling response relationship between the dynamic response of the hot carrier concentration and the phase shift of the driving signal is established to quantify the time-varying disturbance of the nonlinear fluctuation of the hot carrier mobility on the switching delay of the high-low side MOSFET device;

[0100] Optionally, in step 104, based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, a coupling response relationship between the dynamic response of the hot carrier concentration and the phase shift of the driving signal is established to quantify the time-varying disturbance of the nonlinear fluctuation of the hot carrier mobility on the switching delay of the high-low side MOSFET device can specifically include:

[0101] 1041、In the switching transient process, the bus voltage waveform and the gate drive signal waveform of the thermoelectric feedback network are synchronously collected, the peak timing of the bus voltage waveform is measured in time deviation with the rising edge / falling edge turning point of the gate drive signal;

[0102] 1042、A corresponding relationship table of bus voltage change rate and gate drive signal time deviation amount is established, and the discrete voltage distribution data is converted into a drive signal phase shift amount through the corresponding relationship table;

[0103] 1043、The thermal carrier mobility perturbation parameter is calculated according to the cumulative effect of the phase shift amount with the number of switching cycles.

[0104] In the above scheme, the dynamic thermoelectric feedback network refers to the thermoelectric unit array embedded in the hotspot area of the chip packaging layer converting the axial temperature gradient it senses into a discrete voltage signal, and the discrete voltage signals are connected in parallel to form a total feedback voltage. The Seebeck voltage distribution data refers to the changing total voltage signal, which comprehensively reflects the dynamic temperature rise state of the chip core area. The thermal carrier refers to the high-energy electron (carrier) generated by the chip under the action of heat. The higher the temperature, the greater the concentration of high-energy electrons, and the more active their movement behavior. The dynamic response of the thermal carrier concentration refers to the speed of the number of high-energy electrons changing with the instantaneous fluctuation of the chip temperature. The drive signal phase shift refers to the time delay of the rising edge or falling edge of the actual control MOSFET switching action signal (such as the gate voltage). Ideally, the signal should jump on time, but the heat effect will interfere with the time point. The thermal carrier mobility is a parameter describing the ease of electron movement in semiconductor materials. When the temperature rises, the lattice vibration intensifies, which hinders the movement of electrons, resulting in a decrease in mobility. The nonlinear fluctuation refers to the fact that the mobility does not change linearly with temperature, but fluctuates irregularly. The time-varying disturbance of switching delay refers to the unstable change of the mobility due to the fluctuation of the temperature, which causes the time (switching delay) required for the MOSFET (such as high-side and low-side MOSFET) to actually turn on or off after receiving the drive instruction to also change unpredictably.

[0105] In the embodiments of the present application, first, the high-speed data acquisition device is used to record two key waveforms in step 1041: one is the voltage on the thermoelectric feedback bus, and the other is the gate drive signal for controlling the power MOSFET switch, such as the signal for controlling the high-side or low-side MOSFET. When the MOSFET switching action occurs, for example, the rising edge of the gate voltage represents the turn-on instruction, and due to the heat effect, the actual turn-on or turn-off action will lag. The analyst focuses on the peak point of voltage , that is, the position of the most intense moment of thermal fluctuation on the time axis , and the position of the turning point of the gate drive signal edge For example, the midpoint of the rising edge. Calculate the time difference between the two: This time difference is the phase shift of the heat-induced drive signal, i.e. the timing deviation.

[0106] Secondly, by step 1042, observe the severity of the thermoelectric voltage change, i.e. the instantaneous change rate of the voltage when the thermal shock occurs, collect multiple sets of data under different working conditions (produce different degrees of temperature fluctuation), record the instantaneous change rate of the thermoelectric voltage near the peak of the thermal fluctuation and the time difference corresponding to the switch, and sort out the corresponding injection table.

[0107] Finally, by step 1043, define a thermal carrier mobility disturbance parameter A commonly used calculation method is to calculate a cumulative effect factor based on the phase shift of the last continuous switching action: Or use the weighted average form (the closer the influence is greater): Where is the weight coefficient of the th switch, i.e. The parameter is a quantitative index used to represent the overall disturbance of the thermal carrier mobility due to the accumulation of multiple thermal shocks.

[0108] For example, Company D develops a high-efficiency server power module:

[0109] Specifically, a dynamic thermoelectric feedback network is established to monitor the temperature fluctuations at key points inside the chip. When testing the switching process of a bridge power circuit (including high-side and low-side MOSFETs), the falling edge of the low-side MOSFET gate drive, i.e. the turn-off instruction time , and the peak value of the thermoelectric feedback voltage immediately following it are captured . At the same time, the change rate of the thermoelectric voltage near is recorded (negative sign indicates voltage drop). Through a pre-established corresponding relationship table, the change rate of corresponds to (approximately 0.13 μs as measured). Ten switching operations are continuously tested to obtain ten values. When calculating the mobility disturbance parameter, take the unweighted average of the last switch: Then the parameter is obtained. This characterizes the average time deviation of the increase in switching delay caused by carrier mobility disturbance of the low-side MOSFET under the accumulation of recent switching heat.

[0110] The core effect of this step is to establish a direct quantifiable correlation from the chip internal thermal state fluctuation (indirectly reflected by the thermoelectric voltage) to the actual switching action time deviation (phase shift) of the power MOSFET. By capturing the relationship between the change rate of the thermoelectric signal and the time shift of the driving signal, the transient temperature gradient feedback is efficiently converted into an estimated value of the switching delay disturbance; further considering the thermal accumulation effect of multiple switching, the comprehensive parameter representing the degree of continuous disturbance of the thermal carrier mobility is calculated, which provides a key quantitative index for understanding the instantaneous and cumulative influence of thermal effect on the switching dynamic characteristics, and lays a data foundation for subsequent driving signal compensation or thermal management strategy optimization.

[0111] 105、According to the time-varying disturbance parameter output according to the coupling response relationship, the rising edge slope and the falling edge slope of the gate voltage of the high-low side MOSFET device are reconstructed.

[0112] Optionally, the time-varying disturbance parameter output according to the coupling response relationship in step 105 can specifically include:

[0113] 1051、Obtain the initial rising edge time point and the initial falling edge time point of the original gate driving signal within the switching period, and calculate the forward time amount required for the initial rising edge time point and the backward time amount required for the initial falling edge time point according to the phase shift in the time-varying disturbance parameter;

[0114] 1052、Set a new rising edge starting point at the forward time amount position before the initial rising edge time point, and increase the positive voltage change rate based on the original rising edge slope to form an accelerated rising section, and similarly set a new falling edge starting point at the backward time amount position after the initial falling edge time point, and increase the negative voltage change rate based on the original falling edge slope to form an accelerated falling section;

[0115] 1053、Connect the end point of the accelerated rising section to the original rising edge vertex, and connect the starting point of the accelerated falling section to the original falling edge starting point, to complete the reconstructed rising edge slope and falling edge slope waveforms.

[0116] In the above scheme, the time-varying disturbance parameter refers to a hot carrier mobility disturbance parameter, which is a time quantity representing the average time delay caused by recent thermal accumulation on switch action. Reconstruction refers to active modification and adjustment of the original control signal waveform to compensate for the negative effects of thermal effects. The gate voltage refers to the core signal that controls the MOSFET switch. High level turns on, low level turns off. The rising slope refers to the voltage change rate (such as V / μs) when the gate voltage jumps from low to high. The greater the slope, the faster the switch is turned on. The falling slope refers to the voltage change rate (such as V / μs) when the gate voltage jumps from high to low. The greater the slope, the faster the switch is turned off. Accelerated rising segment / accelerated falling segment refers to a short slope signal segment with a steeper slope added to the original signal waveform, used to accelerate the completion of switch action.

[0117] In the embodiments of the present application, first, the original, uncompensated gate drive signal waveform is obtained through step 1051, wherein the key time points include: the initial rising edge starting point, i.e. the time when the voltage starts to rise, the initial rising edge vertex, i.e. the time when the voltage reaches the high level, the initial falling edge starting point, i.e. the time when the voltage starts to fall, and the initial falling edge ending point, i.e. the time when the voltage reaches the low level. The time-varying disturbance parameter R obtained in step 104 represents the average delay amount caused by thermal effects on switch action. Compensation needs to be made for turn-on (rising edge) and turn-off (falling edge) respectively, i.e. the amount of time required to move forward the initial rising edge time point and the amount of time required to move backward the initial falling edge time point are determined according to the difference between the original time and the time-varying disturbance parameter.

[0118] Secondly, in the power device switching timing compensation process through step 1052, firstly for the rising edge action: based on the advance time calculated by the thermal disturbance parameter (such as 0.2 μs), the original rising edge starting time (such as t = 5.0 μs) is adjusted forward to the new coordinate (such as t = 4.8 μs). At this new starting point, instead of using the original voltage change rate, a steeper positive slope is designed - based on the original rising slope (such as 8V / μs), the voltage change intensity is increased by a preset proportion (such as 1.5 times, i.e. 12V / μs), thereby forming an accelerated rising section with shorter duration but more intense change. This steep slope makes the gate voltage complete the initial jump in a very short time (such as 0.15 μs) and quickly cross the key threshold of the conduction process. The reverse operation is implemented for the falling edge simultaneously: according to the delay time (such as 0.2 μs), the original falling edge starting point (such as t = 15.0 μs) is moved backward to the new trigger point (such as t = 15.2 μs). At this shifted time coordinate, an intensified negative voltage change rate is adopted - based on the original falling slope (such as -10V / μs), the change amplitude is multiplied (such as increased to -15V / μs), and an accelerated section with cliff-like falling is constructed. This design makes the gate voltage separate from the conduction interval at a nearly free-fall speed after the start of the turn-off action, greatly shortening the turn-off delay window.

[0119] Finally, the core of signal reconstruction through step 1053 is to realize seamless connection between the accelerated section and the original waveform. For the rising edge part, when the accelerated rising section reaches the preset voltage value (such as 2.8V) with its enhanced slope (such as 12V / μs), the voltage point at this time (spatial-time coordinate such as t = 4.95 μs, V = 2.8V) is immediately connected to the target vertex of the original rising edge (such as the designed value 21V), and at this time the original slope (8V / μs) is maintained to continue completing the remaining voltage rise - essentially, it is to continue the voltage increment task of the accelerated section at the original rate, which not only inherits the time gain of the accelerated section, but also continues the smooth voltage transition required by the design. For the falling edge, the mirror logic is adopted: the original falling edge first runs at its standard slope (-10V / μs) to the delayed start time (such as t = 15.2 μs), and at the moment when the voltage drops to the transition point value (such as 19V), the preset accelerated falling section (-15V / μs) is connected to perform the final turn-off sprint. This "first original and then accelerated" relay strategy ensures that the first half of the turn-off action unloads the charge at the conventional rate, and switches to the enhanced slope at the critical moment to achieve the violent clamping of the finishing stage. Through the double anchoring mechanism - the rising edge takes the target voltage as the end anchor and the falling edge takes the starting voltage as the start anchor - the reconstructed waveform not only accurately compensates for the thermal delay gap in the time domain, but also realizes the continuous derivability of the conduction and turn-off trajectories in the voltage domain. Finally, it presents a staircase-like edge with a compensation step on the oscilloscope, and its macroscopic slope presents a segmented linear transition feature.

[0120] For example, in the actual measurement of chip E (applied to a certain electric tool motor drive system):

[0121] Specifically, based on the thermal mobility disturbance parameter R = 0.2 μs, the technician reconstructs the original drive signal of the high-side MOSFET: first, the rising edge starting point is moved forward by 0.2 μs from the original t = 5.0 μs to t = 4.8 μs, and an acceleration segment of 0.15 μs is generated at a slope of +12V / μs (1.5 times the original slope of 8V / μs), making the voltage rise from 1V to 2.8V; then it is seamlessly switched back to the original slope of 8V / μs at t = 4.95 μs, taking 2.275 μs to complete the remaining 18.2V rise to the target 21V, and the overall turn-on completion time is optimized to t≈7.225 μs (earlier than the original 7.5 μs). For the falling edge, the original starting point t = 15.0 μs is maintained to drop to t = 15.2 μs at a slope of -10V / μs (at this time the voltage is 19V), and then an acceleration segment with a slope of -15V / μs is started, which only takes 1.2 μs to reduce the voltage from 19V to 1V, making the turn-off action complete at t = 16.4 μs (0.6 μs shorter than the original 17.0 μs). Through the precise splicing of the steep acceleration segment and the original segment, this reconstruction strategy effectively offsets the delay impact of thermal effects on switching timing.

[0122] The core effect of this step is to actively counteract the negative impact of switching delay caused by thermal effects. Using the thermal disturbance time parameter quantified in step 104, a short but steep voltage ramp segment is intelligently inserted before and after the key time nodes of the original drive signal. This signal reconstruction strategy significantly improves the initial response speed of turn-on and turn-off actions, effectively "recovers" the sluggishness of switching actions caused by the reduction of hot carrier mobility in the time dimension, and ultimately ensures that high and low side MOSFET devices can complete switching actions at more accurate times, improving power conversion efficiency and reducing switching loss risk.

[0123] 106、Through matching the dynamic compensation parameters of the rising edge slope and the falling edge slope, the phase deviation of the drive signal caused by the thermal carrier concentration is compensated within the switching cycle.

[0124] Optionally, the step 106 of compensating the phase deviation of the drive signal caused by the thermal carrier concentration within the switching cycle by matching the dynamic compensation parameters of the rising edge slope and the falling edge slope can specifically include:

[0125] 1061、At the beginning of the switching cycle, monitor the peak timing of the bus voltage waveform generated by the dynamic thermal feedback network in the current cycle, and retrieve the dynamic compensation parameters from the corresponding relationship table established based on the coupling response relationship according to the peak timing of the bus voltage waveform, the dynamic compensation parameters including rising edge slope compensation coefficients and falling edge slope compensation coefficients;

[0126] 1062. Multiply the rising edge slope compensation coefficient by the positive voltage change rate of the reconstructed accelerated rising segment to obtain the compensated rising edge execution parameters. Similarly, multiply the falling edge slope compensation coefficient by the negative voltage change rate of the reconstructed accelerated falling segment to obtain the compensated falling edge execution parameters.

[0127] 1063. Within the rising edge time window of the current switching cycle, the driving circuit is controlled to output a positive voltage change rate according to the compensated rising edge execution parameters. Similarly, within the falling edge time window, the driving circuit is controlled to output a negative voltage change rate according to the compensated falling edge execution parameters.

[0128] In the above scheme, the dynamic compensation parameter refers to a coefficient dynamically adjusted based on the thermoelectric feedback signal, used to fine-tune the voltage change rate of the reconstructed waveform. The bus voltage waveform refers to the combined voltage signal output by the parallel thermoelectric units; its peak occurrence time reflects the moment of most severe temperature rise inside the chip. The rising edge slope compensation coefficient is a proportional factor used to adjust the slope of the accelerating rising segment based on the thermal state. The falling edge slope compensation coefficient is similarly used to adjust the slope of the accelerating falling segment. The compensated execution parameter refers to the actual voltage change rate command value finally output to the drive circuit. The switching cycle refers to the complete time window for the power device to complete one turn-on and turn-off operation.

[0129] In this embodiment, firstly, at the instant the power switching cycle starts in step 1061, the control system immediately begins tracking the thermoelectric feedback bus voltage. This bus signal is generated by the thermoelectric unit array in the hot spot area of ​​the packaging layer, and the moment its voltage peak appears precisely reflects the time node of the most severe temperature rise inside the chip. Bus waveform data is continuously captured by a high-speed sampling circuit, and a sliding window extreme value detection algorithm (e.g., local derivative zero-crossing determination) is used to lock the absolute peak coordinates within the current cycle (e.g., detecting a voltage spike at t=5.25μs). This moment is then compared with the theoretical edge standard timing of the drive signal (e.g., the design value t=5.0μs) at the nanosecond level to calculate the thermal delay deviation (+0.25μs in this example). The three-dimensional relational mapping table pre-stored in memory is then activated (this table was established in step 104 and contains the correspondence between delay deviation and compensation coefficient). Based on the 0.25μs offset value, the associated data unit is automatically indexed to extract the dynamic compensation parameter set required for this operating condition: including the rising edge slope compensation coefficient (such as a 1.5x enhancement factor) for improving the turn-on speed and the falling edge slope compensation coefficient (such as a 1.4x enhancement factor) for optimizing the turn-off response. The entire process completes the closed-loop decision-making from thermal characteristic monitoring to compensation parameter retrieval within microseconds, ensuring that each switching cycle can match the accurate compensation strategy for the current hot carrier disturbance.

[0130] Secondly, the base slope of the accelerated rising segment in step 105 and the base slope of the accelerated falling segment in step 105 and the dynamic compensation coefficients of the current switching cycle, including the rising slope compensation coefficient (a dimensionless scaling factor, >1 means enhancement) and the falling slope compensation coefficient , the key operation is performed by multiplication: the compensated rising slope execution slope , the compensated falling slope execution slope .

[0131] Finally, through step 1063, the driving control system converts the dynamically calculated slope execution parameters into physical output within the precisely defined switching action time window: when the switching cycle enters the preset rising edge period (for example, the accelerated rising window starting from the new starting point t=4.8µs), the driving chip immediately loads the compensated rising edge execution parameter (such as +19.5V / µs), forces the rising rate of the gate voltage to be higher than the conventional speed through the internal current source module, and charges the MOSFET gate capacitance at a speed that exceeds the conventional speed, thereby offsetting the negative effects of hot carrier migration lag; synchronously in the falling edge period (such as the delayed turn-off window t=15.2µs to 16.4µs), the control system switches to the compensated negative execution parameter (such as -21.6V / µs), and the driving chip output stage is converted to a large current sink mode to quickly extract the gate charge at a nearly vertical voltage drop slope, violently compressing the turn-off delay time. This dynamically locked timing slope loading mechanism ensures that the heat disturbance compensation amount of each switching cycle can be mapped to the actual output strength of the driving circuit, and finally presents a switching trajectory at the power device end that precisely counteracts the heat carrier concentration fluctuation.

[0132] For example, a certain power tool power module (chip F) detects that the peak value of the hot bus voltage appears at (the ideal value is 5.0µs, with a delay of 0.25µs).

[0133] Specifically, the preset mapping table is queried, and the delay of 0.25µs corresponds to . The original slope of the accelerated rising segment of the cycle reconstruction waveform is +12V / µs, and the accelerated falling segment is -15V / µs. The execution parameters are calculated as: , . The driving chip outputs at a rate of +18V / µs for 0.2µs at (the new rising edge starting point), making the voltage rise from 1V to 4.6V; at (the new falling edge starting point), the voltage is reduced from 19V to 1V at a rate of -21V / µs within 0.8µs, compressing the switching action within the heat shock time window.

[0134] This step dynamically enhances the voltage variation strength of the drive waveform by matching the thermal feedback signal with the preset mapping rule: when thermal delay is detected, the compensation coefficient is automatically increased to force the carrier migration process with a steeper voltage slope. This closed-loop strategy integrates thermal disturbance identification (step 104), waveform reconstruction (step 105), and real-time compensation (step 106) into an adaptive system, ensuring that the switch action always follows the target timing and significantly reduces the parasitic interference of thermal effects on the dynamic performance of power devices.

[0135] The following is a complete example of steps 101-106:

[0136] An industrial servo drive (System B) uses a double-parallel half-bridge topology, and its core power management chip (PMIC-POWER) operates at 10 kHz high-frequency switching. The system monitors a 160ns delay in the second-phase high-side MOSFET during the turn-on phase, and infrared scanning shows that the surface temperature of this area reaches 142°C (the average temperature of other areas is 102°C), resulting in a 3.1% reduction in system energy efficiency. To optimize this timing disturbance, the following full-flow compensation is performed:

[0137] First, use the HTX-9000 high-speed infrared thermal imager (80,000 frames / s) to aim at the second-phase area of the PMIC-POWER chip, and continuously collect the surface temperature distribution during the MOSFET turn-on transient (15μs). Based on the three-layer packaging structure, the thermal conduction model is established for the silicone layer (0.18mm thick, thermal conductivity 0.4W / mK), copper layer (0.12mm, 398W / mK), and ceramic substrate (0.1mm, 25W / mK): When t=2μs, the surface hot spot reaches 132°C (coordinates x5.1mm, y4.3mm), and the solution is obtained as follows: when t=5μs, the temperature at the bottom of the ceramic substrate 0.2mm away from the surface rises to 155°C. Finally, the three-dimensional temperature field is constructed by merging the axial temperature and surface thermal image data at this moment, clearly showing a 23°C / mm temperature gradient from the surface 132°C to the junction area 155°C.

[0138] Second, frame the core area of the power device in the temperature field ( ), and extract the time-temperature curves of 720 grid points. Through Pearson correlation coefficient analysis (threshold 0.88), three thermal response sub-areas are divided, and the point P1 with the most severe temperature jump in sub-area A is selected: the temperature jumps from 48°C to 152°C (change 104°C) in The maximum temperature rise rate is 92°C / μs and the transient characteristic value is recorded.

[0139] Then, Bi2Te3 thermoelectric unit TH1 (Seebeck coefficient -240 μV / K) is embedded at the position corresponding to feature point P1 (x5.2 mm, y4.2 mm directly above), the cold end is connected to a heat dissipation cover plate (constant temperature 65℃), and the hot end is directly connected to the silicon junction region. When the chip is working, the junction region reaches 155℃ (T1=155℃) , the output voltage of TH1 is: The output of other phase thermoelectric units is connected in parallel to form the bus voltage It is found through monitoring that the main peak value appears at t=4.8 μs (lagging behind the midpoint of the rising edge of the ideal gate drive by 0.95 μs).

[0140] Subsequently, the mapping of the bus voltage change rate and the timing offset is built: The corresponding is (calibrated through 15 groups of experiments). The values of the last 6 switching times are taken , and the weighted average is calculated according to the weight : The hot carrier mobility disturbance parameter is obtained.

[0141] Then, the original rising edge starting point is moved forward by R value to ; a steep slope of +28V / μs (1.56 times of the original slope 18V / μs) is set in the interval , the gate voltage is pushed up from 1.8V to 5.8V in the interval , and then the original slope is switched back to use to rise to the target 24V, and the total opening time is compressed by 22%.

[0142] Finally, when the peak value of V_fb lags behind by 1.02 μs in the new switching cycle, the dynamic compensation coefficient 1.62 is obtained through table lookup, and it is multiplied by the preset acceleration slope 28V / μs to obtain the execution parameter 45.36V / μs. The driving IC outputs at this rate at instant, and the 1.8V→7.3V transition is completed in only 0.12 μs (37% faster than the original design), finally making the switching delay stable in the interval of 35±5 ns.

[0143] Figure 2 A structure schematic diagram of a power management chip high-low side driving signal timing optimization system is provided for the embodiments of the present application, as shown in Figure 2 , the system comprises:

[0144] An acquisition module 21 acquires infrared thermal image data of the power management chip under switching transient working conditions, and synchronously acquires the three-dimensional temperature field distribution of the surface and internal junction temperature of the chip packaging layer;

[0145] The extraction module 22 extracts the temperature variation characteristics of the chip power device region based on the spatial continuity of the three-dimensional temperature field distribution;

[0146] The construction module 23 converts the temperature gradient in the temperature variation characteristics into a spatially discrete Seebeck voltage distribution by embedding a thermoelectric material in a specific hot spot region of the chip packaging layer, to construct a dynamic thermoelectric feedback network;

[0147] The establishment module 24 establishes a coupling response relationship between the dynamic response of the hot carrier concentration and the phase shift of the driving signal based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, to quantify the time-varying disturbance of the nonlinear fluctuation of the hot carrier mobility on the switching delay of the high-low side MOSFET device;

[0148] The reconstruction module 25 reconstructs the rising edge slope and the falling edge slope of the gate voltage of the high-low side MOSFET device according to the time-varying disturbance parameters output by the coupling response relationship;

[0149] The switching module 26 compensates for the phase deviation of the driving signal caused by the hot carrier concentration by matching the dynamic compensation parameters of the rising edge slope and the falling edge slope in the switching period.

[0150] Figure 2 The power management chip high-low side driving signal timing optimization system can perform Figure 1 The power management chip high-low side driving signal timing optimization method of the embodiment has been described above. The specific operation of each module and unit of the power management chip high-low side driving signal timing optimization system in the above embodiment has been described in detail in the embodiment related to the method, and will not be described in detail here.

[0151] In one possible design, Figure 2 The power management chip high-low side driving signal timing optimization system of the embodiment can be implemented as a computing device, such as Figure 3 As shown, the computing device can include a storage component 31 and a processing component 32.

[0152] The storage component 31 stores one or more computer instructions, wherein the one or more computer instructions are called and executed by the processing component 32.

[0153] The processing component 32 is configured to perform the above Figure 1 The power management chip high-low side driving signal timing optimization method of the embodiment.

[0154] The processing component 32 can include one or more processors to execute computer instructions to complete all or part of the steps in the above method. Of course, the processing component can also be one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components, configured to perform the methods described above.

[0155] The storage component 31 is configured to store various types of data to support the operation of the terminal. The storage component can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0156] Of course, the computing device can also include other components, such as an input / output interface, a display component, a communication component, etc.

[0157] The input / output interface provides an interface between the processing component and the peripheral interface module, which can be an output device, an input device, etc.

[0158] The communication component is configured to facilitate wired or wireless communication between the computing device and other devices, etc.

[0159] The computing device can be a physical device or an elastic computing host provided by a cloud computing platform, and the computing device can be a cloud server, and the processing component, the storage component, etc. can be a basic server resource rented or purchased from the cloud computing platform.

[0160] The embodiment of the present application also provides a computer storage medium, which stores a computer program, and the computer program can implement the above-mentioned Figure 1 The power management chip high-low side drive signal timing optimization method of the embodiment shown.

[0161] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0162] The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected to achieve the purposes of the embodiments according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0163] Through the description of the above embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software and the necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of software products, and the computer software products can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and include a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0164] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for optimizing the timing of high and low side drive signals of a power management chip, characterized in that, The application relates to a method for quantifying the nonlinear fluctuation of hot carrier mobility in high-side and low-side MOSFET devices, and reconstructing the rising and falling edge slopes of the gate voltage of the MOSFET devices. The application comprises the following steps: Infrared thermal image data of a power management chip under switching transient conditions is collected, and the three-dimensional temperature field distribution of the surface and internal junction temperature of the chip packaging layer is synchronously obtained; Based on the spatial continuity of the three-dimensional temperature field distribution, the temperature variation characteristics of the chip power device region are extracted; By embedding a thermoelectric material in a specific hot spot region of the chip packaging layer, the temperature gradient in the temperature variation characteristics is converted into a spatially discrete Seebeck voltage distribution to construct a dynamic thermoelectric feedback network; Based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, the coupling response relationship between the dynamic response of hot carrier concentration and the phase shift of the driving signal is established to quantify the time-varying disturbance of the nonlinear fluctuation of hot carrier mobility on the switching delay of high-side and low-side MOSFET devices; According to the time-varying disturbance parameters output by the coupling response relationship, the rising and falling edge slopes of the gate voltage of high-side and low-side MOSFET devices are reconstructed; By matching the dynamic compensation parameters of the rising and falling edge slopes, the phase deviation of the driving signal caused by the hot carrier concentration is compensated in the switching cycle. The application comprises the following steps: At the beginning of the switching cycle, the peak timing of the bus voltage waveform generated by the dynamic thermoelectric feedback network in the current cycle is monitored, and the dynamic compensation parameters, including the rising edge slope compensation coefficient and the falling edge slope compensation coefficient, are retrieved from the corresponding relationship table established by the coupling response relationship according to the peak timing of the bus voltage waveform. The rising edge slope compensation coefficient is multiplied by the positive voltage change rate of the reconstructed accelerated rising section to obtain the compensated rising edge execution parameter, and the falling edge slope compensation coefficient is multiplied by the negative voltage change rate of the reconstructed accelerated falling section to obtain the compensated falling edge execution parameter. In the rising edge time window of the current switching cycle, the positive voltage change rate of the driving circuit is controlled according to the compensated rising edge execution parameter, and in the falling edge time window, the negative voltage change rate of the driving circuit is controlled according to the compensated falling edge execution parameter. Based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, the coupling response relationship between the dynamic response of hot carrier concentration and the phase shift of the driving signal is established to quantify the time-varying disturbance of the nonlinear fluctuation of hot carrier mobility on the switching delay of high-side and low-side MOSFET devices. During the switching transient process, the bus voltage waveform and the gate driving signal waveform of the thermoelectric feedback network are synchronously collected, the peak timing of the bus voltage waveform is measured in time sequence deviation with the rising edge / falling edge turning point of the gate driving signal, a corresponding relationship table of the bus voltage change rate and the gate driving signal time sequence deviation amount is established, the discrete voltage distribution data is converted into the driving signal phase shift amount through the corresponding relationship table, and the hot carrier mobility disturbance parameter is calculated according to the cumulative effect of the phase shift amount with the switching cycle number.

2. The method of claim 1, wherein, According to the coupling response relationship output, the time-varying disturbance parameter is used to reconstruct the rising edge slope and the falling edge slope of the high-low side MOSFET device gate voltage, including: Obtaining the initial rising edge time point and the initial falling edge time point of the original gate drive signal in the switching cycle, and calculating the required forward time amount of the initial rising edge time point and the required backward time amount of the initial falling edge time point according to the phase offset in the time-varying disturbance parameter; Setting a new rising edge starting point at the forward time amount position before the initial rising edge time point, and increasing the positive voltage change rate based on the original rising edge slope to form an accelerated rising section, and similarly setting a new falling edge starting point at the backward time amount position after the initial falling edge time point, and increasing the negative voltage change rate based on the original falling edge slope to form an accelerated falling section; Connecting the terminal point of the accelerated rising section to the original rising edge vertex, and connecting the starting point of the accelerated falling section to the original falling edge starting point to complete the reconstructed rising edge slope and falling edge slope waveform.

3. The method of claim 1, wherein, Based on the spatial continuity of the three-dimensional temperature field distribution, the temperature variation characteristics of the chip power device region are extracted, including: Identifying the spatial coordinate range corresponding to the power device region in the three-dimensional temperature field distribution, and extracting the time-temperature variation curve of all grid points in the power device region in the switching cycle; Calculating the similarity of the temperature variation curves between adjacent grid points, merging the continuous spatial regions with similarity exceeding the threshold value, and selecting the grid point with the largest temperature variation amplitude in the merged continuous region as the feature monitoring point; Recording the highest temperature value, the lowest temperature value and the temperature variation rate of the feature monitoring point in each switching cycle as the temperature variation characteristics.

4. The method of claim 3, wherein, By embedding the thermoelectric material in the specific hot spot region of the chip packaging layer, the temperature gradient in the temperature variation characteristics is converted into a spatially discrete Seebeck voltage distribution to construct a dynamic thermoelectric feedback network, including: Embedding a bismuth telluride-based thermoelectric material unit array in the region corresponding to the spatial position of the feature monitoring point in the chip packaging layer; Connecting the two ends of each thermoelectric material unit to the upper surface of the packaging layer and the silicon substrate junction, respectively, when the power device region generates an axial temperature gradient, each thermoelectric material unit generates a discrete voltage signal according to the temperature difference between the two ends; The output ends of the discrete voltage signals of all thermoelectric material units are connected in parallel to form a feedback bus, constituting a thermoelectric feedback network with a spatially discrete voltage distribution.

5. The method of claim 1, wherein, Collecting infrared thermal image data of the power management chip under switching transient conditions, and synchronously acquiring three-dimensional temperature field distribution of the chip packaging layer surface and internal junction temperature, including: Aligning the high-speed infrared thermal imager to the upper surface of the chip packaging layer, and collecting infrared thermal image data under switching transient conditions; Based on the thickness and thermal conductivity parameters of each layer of material of the chip packaging layer, an axial heat conduction equation from the surface of the packaging layer to the internal junction temperature region is established, and the infrared thermal image data is input as a boundary condition into the axial heat conduction equation, and the axial temperature distribution of the internal packaging material and the junction temperature region is calculated layer by layer; The axial temperature distribution of each sampling time is spatially superimposed with the surface two-dimensional infrared thermal image data of the corresponding time to form a three-dimensional temperature field distribution.

6. A system for power management chip high and low side drive signal timing optimization, for performing the method of any one of claims 1-5, wherein, The method comprises the following steps: An acquisition module acquires infrared thermal image data of a power management chip under switching transient operating conditions, and synchronously acquires three-dimensional temperature field distributions of the surface and internal junction temperature of the chip package layer; An extraction module extracts temperature variation characteristics of the chip power device region based on the spatial continuity of the three-dimensional temperature field distribution; A construction module converts temperature gradients in the temperature variation characteristics into spatially discrete Seebeck voltage distributions through thermoelectric materials embedded in specific hot spot regions of the chip package layer, so as to construct a dynamic thermoelectric feedback network; An establishment module establishes a coupling response relationship between the dynamic response of hot carrier concentration and the phase shift of a driving signal based on Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, so as to quantify time-varying disturbances of the nonlinear fluctuation of hot carrier mobility on the switching delay of high-low side MOSFET devices; A reconstruction module reconstructs the rising edge slope and falling edge slope of the gate voltage of a high-low side MOSFET device according to time-varying disturbance parameters output by the coupling response relationship; A switching module compensates for the phase deviation of a driving signal caused by the hot carrier concentration by matching dynamic compensation parameters of the rising edge slope and falling edge slope within the switching period.

7. A computing device, comprising: The method comprises a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component to realize the power management chip high-low side driving signal timing optimization method of any one of claims 1-5.

8. A computer storage medium, characterized in that The computer program is stored in the computer and is executed by the computer to realize the power management chip high-low side driving signal timing optimization method of any one of claims 1-5.

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