Embedded Flash Memory Architecture for Implementing Interconnect Redundancy

Abstract

The present disclosure relates to a memory architecture, including a plurality of memory cell sub-arrays, a plurality of sense amplifiers connected to the sub-arrays; a plurality of original pads; at least one redundant pad; a plurality of data lines; and a redundant register connected to the plurality of original pads, the plurality of redundant pads, and the data lines, which implements interconnection redundancy and connects one of the redundant pads to the data line when a defective addressed original pad is detected. The present disclosure also relates to a system-on-chip (SoC) component including the memory architecture and an interconnection redundancy management block included in the memory architecture. A method for managing the interconnection redundancy of the memory architecture and / or the SoC is also described.

Description

Technical Field

[0001] The present disclosure relates to a flash memory architecture, and more particularly to a flash memory architecture that implements interconnect redundancy. Background Art

[0002] Non-volatile memory can provide persistent data by retaining stored data without power, and can include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and variable resistance memories such as phase change random access memory (PCRAM), self-selective chalcogenide-based memories, resistive random access memory (RRAM), and 3D XPoint memory (3DXP) and magnetoresistive random access memory (MRAM), etc.

[0003] More specifically, flash memory is a non-volatile memory that retains stored data and is characterized by very fast access times. In addition, it can be erased in blocks rather than one byte at a time. Each erasable memory block includes a plurality of non-volatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or multiple data lines. The cells are programmed and erased by manipulating the voltages on the access lines and data lines.

[0004] Non-volatile flash memory is one of the basic building blocks of modern electronic systems today, especially real-time operating systems (RTOS). The operation of non-volatile flash memory is managed by a controller that includes embedded firmware, and such a controller performs the required write / read / erase operations.

[0005] Memory cells are prone to defects, i.e., in very aggressive lithography nodes. Redundancy is used to bypass defective cells and repair memory architectures that fail during the test phase or exhibit failures in the field to achieve so-called instant redundancy. The root causes of defects can be different, i.e., depleted batteries, defective oxides in the batteries, defects in the physical cell connections, such as due to via breakage, shorted end cups, oxide defects, etc.

[0006] In NOR storage devices, redundancy is typically done on a column-by-column basis. Specifically, redundancy repairs local defects by changing the physical column that includes one or more defective cells to another physical column that is defect-free, and the redundant columns are typically located in the boundary regions of the memory array.

[0007] The implementation of redundancy can be accomplished by linking the defective column address and the target new address of the redundant column, such that when the defective column is addressed, the storage device enables the redundancy to store / read the content in a different redundant column that is defect-free.

[0008] Currently, complex semiconductor structure technologies known as system-on-a-chip (SoC) integrate at least one embedded non-volatile memory in the system. However, with current technologies, the embedded memory is becoming a large macro in the SoC, and increasing the size (e.g., beyond 128 Mbit) is ineffective. In other words, today's embedded memory shows the minimum non-integrable density.

[0009] In other words, when the lithography node is below the technology limit (e.g., below 28 nm), it becomes increasingly difficult to manage the embedded memory in the SoC.

[0010] The connection between the embedded memory and other parts of the SoC also raises defect problems related to the contact between the memory pads and the system.

[0011] Therefore, regardless of the redundancy strategy applied to the flash memory architecture, large connection devices as flash memories (also known as embedded flash memory replacements) within the SoC may have defects due to interconnectivity.

[0012] The existence of interconnect pad defects can completely endanger the operation of the SoC including the flash memory, thus wasting a large amount of money because the SoC, the embedded flash memory, and the package will be discarded, and the corresponding silicon cost will be completely wasted.

[0013] Therefore, a solution is needed for defects related to the interconnect pads of the embedded flash memory and the SoC, thereby allowing the repair of already stacked devices and improving the yield of the manufacturing process of such systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A A block diagram showing a flash memory sub-array including a sense amplifier and a boundary unit;

[0015] Figure 1B Shows Figure 1A An enlarged view of the details of the flash memory sub-array of

[0016] Figure 2A Shows a redundant register implementing single-pad interconnect redundancy according to an embodiment of the present disclosure;

[0017] Figure 2B Shows a redundant register implementing multi-pad interconnect redundancy according to an embodiment of the present disclosure;

[0018] Figure 2C Shows a flash memory architecture implementing interconnect redundancy using the redundant register of Figure 2A according to an embodiment of the present disclosure;

[0019] Figure 3A and3B shows different operating states of a selection circuit of a flash memory architecture that uses a redundant register to implement interconnect redundancy according to an embodiment of the present disclosure; Figure 2A

[0020] Figure 4 and 5 shows an exemplary method for managing interconnect redundancy of a memory architecture according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Referring to those figures, a memory architecture including a memory cell array will be disclosed herein, particularly a flash memory array provided with a selection circuit for implementing interconnect redundancy.

[0022] Figure 1A An example embodiment is a memory architecture 100 including a flash memory sub-array 110, which includes a plurality of sub-arrays all having the same structure.

[0023] More specifically, the flash memory sub-array 110 is connected to a sense amplifier 120, which is in turn connected to a boundary or Jtag unit 130, capable of managing input and output serial data SIN and SOUT, and input and output parallel data PIN and POUT respectively.

[0024] The output parallel data POUT is provided to a SoC (not shown) including the memory architecture 100. The memory architecture 100 is connected to the SoC using any packaging technology.

[0025] As Figure 1B shown, a low signal count interface 140 having the ability to modify the internal content of the flash memory sub-array 110, particularly a low signal count interface using functional pins and corresponding signals TDI, TDO, tms, tck, trst according to the Jtag protocol, may also be included within the memory architecture 100, between the sense amplifier 120 and the SoC, connected to the Jtag unit 130, and its parallel output POUT forms an interconnect channel 150 with the SoC.

[0026] As will be illustrated in the following description, the memory architecture 100 implements interconnect redundancy, which is capable of correcting defects related to the interconnect between the memory architecture 100 and the Soc including it. Redundancy is replicated for each sub-array of the memory architecture, and the sub-array output is an interconnect channel 150 with the SoC, not shown in the figure.

[0027] Specifically, the interconnect defect is related to a defective pad or the connection between defective pads, and the memory architecture 100 according to an embodiment of the present disclosure provides redundancy for all pads that may be defective or have defective connections.​

[0028] According to the subdivision of the memory architecture into multiple sub - arrays, 168 pads per channel are the current target implementation for embedding the flash memory architecture into the SoC. Appropriately, the present disclosure relates to a memory architecture 100 for managing one or more defects on any one of the 168 pads.

[0029] Figure 2A Schematically shown, to achieve interconnect redundancy, the memory architecture 100 appropriately includes a redundancy register 200. The redundancy register 200 is addressed using a Jtag port in the case of factory redundancy and addressed using a flash controller or a host in the case of field redundancy, so as to correctly set the redundancy with or without a low - pin - count interface 140 (such as a Jtag interface).

[0030] Specifically, as Figure 2A shown, for each extended page of the flash memory sub - array 110, the redundancy register 200 receives from the communication channel the bit - address of the addressed storage unit of the flash memory sub - array 110 connected to the corresponding addressed pad by a number of bits (e.g., 8 bits) sufficient to identify a defective pad, so as to be able to address 256 possible defective pads, which is sufficient for the exemplary embodiment of 168 pads per channel, and thus able to manage one defective pad. The pad strip of each flash memory sub - array 110 is represented as 210 in Figure 2A .

[0031] The redundancy register 200 stores information enabling redundancy using a Jtag interface; when field redundancy (also known as instant redundancy) is implemented and available, the register can be programmed at the factory and / or by the flash memory controller and / or the SoC. More specifically, when instant redundancy is implemented, Jtag and / or the SoC and / or the host can be used to program the register.

[0032] In addition, when latched, the address bus serves as the read address in the original data buffer associated with the original address buffer.

[0033] It can be clearly seen from the following description that the redundancy register 200 implements a logic for intercepting defects, which is always on and compares each flash memory sub - array 110 of the memory architecture 100 with any address used by the SoC in which it is embedded to ensure that data is correctly routed to the SoC.

[0034] When single - pad redundancy is implemented, according to Figure 2AIn the embodiment shown, the redundant register 200 includes a first part 220, a 1-bit redundancy flag (on / off) indicating the usage of redundancy, a second part 230 for storing the location or address of the defective pads among 168 pads, and a third part 240 for storing yet another location or address of the spare pads used as redundancy resources.

[0035] When implementing multi-pad redundancy, according to Figure 2B the embodiment for up to 4-pad redundancy shown, the redundant register 200 includes a first part 220, a 1-bit redundancy flag (on / off) indicating the usage of redundancy, a second part 230 including 4 (in the example described here) bit groups for storing four locations or addresses of the defective pads among 168 pads (for example, each group contains 8 bits to be able to address 256 possible combinations, thus addressing one of the 168 possible defective pads) and a third part 240 for storing yet another location or address of the four spare pads used as redundancy resources.

[0036] It can be noted that multi-pad redundancy is thus achieved by increasing the defective pad location field of the second part 230 and by increasing the redundancy resource bits of the third part 240; according to the example, referring to Figure 2B the embodiment shown, the defective pad location field is 8 bits, so the second part 230 is 8 bits multiplied by 4, i.e., the number of pads available for redundancy. Similarly, the redundancy resource bits are at most 4, and each bit can intercept a faulty pad in the channel according to the following logic:

[0037] Bit 0: Redundancy resource pad 0

[0038] Bit 1: Redundancy resource pad 1

[0039] Bit 2: Redundancy resource pad 2

[0040] Bit 3: Redundancy resource pad 3

[0041] More specifically, according to the single-pad redundancy embodiment of the present disclosure, only the spare pad is used, and the third part 240 is a 1-bit field, essentially another flag. In some embodiments, such a third part or another flag is not used, and the unique redundancy resource pad is directly activated; for example, the pad can be hardwired. According to the multi-pad redundancy embodiment, more than one spare pad is used, and the third part 240 is more than one bit. For example, a 4-bit field can implement up to four redundant locations or addresses of the spare pads, corresponding to the four 8-bit fields of the second part 230.

[0042] Therefore, it can be pointed out that the first part 220 of the redundant register 200 is a flag indicating that redundancy is enabled, the second part 230 of the redundant register 200 is the defective area of the pad, and the third part 240 of the redundant register 200 is the redundant resource field.

[0043] According to this embodiment, when a defective pad is found, its address is stored in the second part 230 and the redundancy flag of the first part 220 is enabled (turned on), so that one of the redundant pads enabled by another enable signal stored in the third part 240 is switched with the defective pad. In other words, when the redundancy flag of the first part 220 is turned on, the corresponding logic interception defect is always turned on, and any address used by each flash memory sub-array 110 is compared to replace the address of the storage unit corresponding to the pad found to be defective.

[0044] Specifically, the redundancy flag of the first part 220 is turned on, and the content of the third part 240 of the redundant resource is used to send data to the SoC.

[0045] During normal operation, the range of the pads is monitored and compared with the range of the defective pad position segments of the entire enabled redundant register; when addressing a defective position, a switch with redundant resources is executed, and the self-state of the redundancy flag of the first part 220 is checked: enabled or disabled, that is, turned on or off.

[0046] In the case of setting the enabled state (turned on), the redundant pad with the address stored in the third part 240 is routed using a multi-channel MUX to replace the defective pad with the address stored in the second part 230.

[0047] The redundant register 200 is replicated in each sub-array, and the contents of the corresponding parts 220, 230, and 240 are stored in the flash memory configuration area, because the corresponding stored data is only stored once as other setting data.

[0048] As already pointed out, according to the embodiment of the present disclosure, after the flash memory architecture 100 and the SoC in which it is embedded are powered on, the redundancy is always turned on, so as to continuously monitor the communication channels even in the case of taking 168 pads as an example in this description.

[0049] In the case of the multi-layer memory structure 100, the defective pad will replace all the layers or pages connected to the defective pad.

[0050] For example, in the case of the embedded flash memory replacement architecture, as Figure 2C schematically shown, the redundant register 200 (also denoted as Red_R) is usually divided into a high page 200H and a low page 200L.

[0051] According to the above-mentioned interconnection redundancy mechanism, if a defective pad is detected and the redundancy flag of the first part 220 is enabled (turned on), the redundancy register 200 is used to replace the original cell address 230H with the redundancy cell address 240H in the high page 200H, and replace the original cell address 230L with the redundancy cell address 240L in the low page 200L. If there are defects in the pads used, in terms of flexible TDI, pad redundancy applies to all extended pages of the sub-array and any data therein.

[0052] Specifically, when the redundancy flag 220 is enabled or turned on, the MUX 250 will receive the output parallel data POUT of the redundancy cells 240H and 240L instead of the output parallel data POUT of the original cells 230H and 230L. The following refers to Figure 3A and 3B to describe the function of the MUX 250.

[0053] As Figure 3A shown, the memory architecture 100 may specifically include a selection circuit 300 for implementing interconnection redundancy according to an embodiment of the present disclosure.

[0054] Specifically, the selection circuit 300 is connected to the pads of the memory architecture 100 and receives an address and an enable signal from the redundancy register 200. The pads are represented as the original pads OP and at least one redundant pad RP.

[0055] More specifically, the selection circuit 300 includes a first switch SW1 inserted between multiple data lines DL and the original pad OP and a second switch SW2 inserted between the data line DL and the redundant pad RP. The first switch SW1 is driven by a first redundancy signal RS1, which is the inverted value of the redundancy flag stored in the first part 220 of the redundancy register 200 obtained through an inverter INV, while the second switch SW2 is driven by a combination between the first redundancy signal RS1 and a second redundancy signal RS2 stored in the third part 240 of the redundancy register 200 obtained through a logic gate LG, and the logic gate LG is an AND gate.

[0056] In Figure 3A the example embodiment, the communication channel provides an address to the redundancy register 200, which corresponds to the bit found to be connected to the properly operating original pad OP, and its address AddOP is stored in the second part 230 of the redundancy register 200. Specifically, bit #4 (000……1000) of the storage page is connected to the "correct" pad, that is, the defect-free original pad OP.

[0057] In this case, the enable flag stored in the first part 220 is set to equal 1, such that the first redundant signal RS1 is set to equal 0 and the first switch SW1 is turned off by an inverted value equal to 1. Additionally, independent of the value of the second redundant signal RS2, since the first redundant signal RS1 is set to equal 0, the logic gate LG turns on the second switch SW2.

[0058] In this way, the data on the data line DL is provided to the correctly operating original pad OP.

[0059] In Figure 3B In an example embodiment of, the communication channel provides an address to the redundant register 200 that corresponds to the bit found to be connected to the defective original pad OP, the address AddOP of which is stored in the second part 230 of the redundant register 200. Specifically, bit #4 (000……1000) of the stored page is connected to the "bad" pad, i.e., the defective original pad OP.

[0060] In this case, the enable flag stored in the first part 220 is set to equal 0, such that the first redundant signal RS1 is set to equal 1 and the first switch SW1 is turned on by an inverted value equal to 0. Additionally, the value of the second redundant signal RS2 is set to equal 1, such that the logic gate LG, which also receives the first redundant signal RS1 set to equal 1, closes the second switch SW2.

[0061] In this way, the data on the data line DL is provided to the redundant pad RP, thus effectively bypassing the original pad OP that is not operating correctly.

[0062] The redundant register 200 and the selection circuit 300 thus form an interconnection redundancy management block included in the memory architecture 100.

[0063] Although Figure 3A and 3B The exemplary configurations shown in involve a single defective pad, but it is immediately verified whether the selection circuit 300 can implement the proposed interconnection redundancy for any number of defective pads (up to 168) by increasing the number of registers to store the defective pads and the new pads.

[0064] The memory architecture 100 can be included in, in particular embedded in, a system-on-chip (SoC) component, and the interconnection redundancy can be applied to the pads connected to the SoC.

[0065] Figure 4 An exemplary method 400 for managing the interconnection redundancy of a memory architecture 100 including a plurality of memory cell sub-arrays and a plurality of original pads OP is schematically shown, the method 400 including the following steps:

[0066] - Step 410: Verify whether one of the original pads OP is operating correctly; and

[0067] - Step 420: If the original pad OP is operating correctly, connect the original pad OP to a plurality of data lines DL; or

[0068] - Step 430: If the original pad OP is not operating correctly, connect the redundant pad RP to the data line DL.

[0069] More specifically, referring to Figure 5 , method 500 includes the following steps:

[0070] - Step 510: Store information enabling redundancy using a Jtag interface;

[0071] - Step 520: Store a redundancy flag in the first part 220 of the redundancy register 200 to indicate the usage of the redundant pad RP; a first redundancy signal RS1 is associated with the redundancy flag;

[0072] - Step 530: Store the address of the defective original pad OP to be switched with the redundant pad RP in the second part 230 of the redundancy register 200; and

[0073] - Step 540: Store in the third part 240 of the redundancy register 200 to address the redundant pad RP when the original pad OP is defective due to incorrect operation; a second redundancy signal RS2 is associated with the address stored in the third part 240.

[0074] It should be noted that the redundancy register 200 includes only one redundancy flag per flash memory sub - array 110. Specifically, in the case of multiple defective locations, the redundancy flag for enabling redundancy is not repeated.

[0075] In summary, the present disclosure provides a memory architecture including a plurality of sub - arrays, each sub - array having an interconnection redundancy mechanism implemented by a selection circuit connected to a redundancy register.

[0076] In this way, potential defects and / or lifetime defects can be instantaneously repaired by a firmware routine included in the SoC including the memory architecture that can correctly control the redundancy register and thus correctly control the selection circuit connected thereto.

[0077] It should be emphasized that the number of redundant pads used can be customized as needed by simply managing the addresses and enable flags to be stored.

[0078] Exemplary memory architectures that implement interconnect redundancy also improve the security of the memory and the SoC; in particular, interconnect redundancy allows errors caused by defective or defective-connected pads to be reset, thereby increasing the ECC coverage, and ECC protects the system from single defects.

[0079] In addition, for each sub-array of the memory architecture, the interconnect redundancy is appropriately replicated.

[0080] It should also be noted that redundant registers (especially those implemented in an embedded flash memory replacement device) are located in the SoC where the bits of the read page are rerouted elsewhere.

[0081] In this way, interconnect redundancy is a transparent strategy.

[0082] In addition, the redundant registers are addressed using a low signal count interface 140 or a Jtag interface, with or without flexible TDI, which is a programmable option to improve the operating performance of the entire memory architecture.

[0083] The size of the redundant registers will depend on the number of possible redundant pads, and full interconnect redundancy is theoretically possible.

[0084] In a practical implementation, considering the yield study and / or the pad topology, the number of possible redundant pads and defects that can be corrected is limited. In some embodiments, each channel (150 or 210) has its own redundant pad resources to repair one or more defective pads (among the 168 pads in the above example). In other embodiments, the redundant pad resources can be shared among different channels; for example, the spare pad resources for redundancy can be addressed to redundant defective pads in any interconnect channel of the system. For example, the redundant registers 200 of different channels can be marked as enabled for redundancy (in the first part 220), store the address of the failed pad (in the second part 230) and store (in the third part 240) the location or address of the spare pad used as a redundant resource, which is a shared resource.

[0085] Finally, it should be emphasized that the defective pads are also stored in the SoC so that the content of the defective pads in the redundant pads can be read instead of the content of the original pads.

[0086] In the above detailed description, reference has been made to the accompanying drawings which form a part thereof, and specific examples have been illustrated in the drawings. In the drawings, the same reference numerals describe substantially similar components in several views. Without departing from the scope of the present disclosure, other examples can be utilized and structural, logical and / or electrical changes can be made.

[0087] Like elements or components between different figures can be identified by using similar numbers. It should be understood that elements shown in various embodiments herein can be added, exchanged, and / or eliminated to provide multiple additional embodiments of the present disclosure. Further, as will be understood, the proportions and relative scales of the elements provided in the figures are intended to illustrate various embodiments of the present disclosure and should not be construed as restrictive.

[0088] As used herein, "a," "an," or "plural" may sometimes refer to one or more of such things. "Plural" things means two or more. As used herein, the term "coupled" may include electrical coupling, direct coupling, and / or direct connection (e.g., by direct physical contact) without an intermediate element or indirect coupling and / or connection using an intermediate element. The term coupling may also include two or more elements that cooperate or interact with each other (e.g., in a causal relationship).

[0089] Although specific examples have been shown and described herein, those of ordinary skill in the art will understand that arrangements calculated to achieve the same result can replace the specific embodiments shown. The present disclosure is intended to cover modifications or variations of one or more embodiments of the present disclosure. It should be understood that the above description is in an illustrative manner, rather than a restrictive manner. The scope of one or more examples of the present disclosure should be determined with reference to the appended claims and the full scope of equivalents given by such claims.

Claims

1. A memory architecture (100) comprising: - A plurality of memory cell sub - arrays (110), - A plurality of sense amplifiers (120) connected to the sub - arrays (110); - A plurality of original pads; - At least one redundant pad; - A plurality of data lines; and - A redundancy register (200) connected to the plurality of original pads, the at least one redundant pad, and the data lines, the redundancy register (200) being divided into a high page and a low page, wherein when it is determined that an addressed original pad is defective, the redundancy register (200) is configured to implement interconnection redundancy and connect the at least one redundant pad to the data lines by replacing the original cell address of the high page of the redundancy register with the redundant cell address of the high page of the redundancy register, and replacing the original cell address of the low page of the redundancy register with the redundant cell address of the low page of the redundancy register.

2. The memory architecture according to claim 1, wherein the redundant register comprises a first part (220) for indicating the usage of the at least one redundant pad by storing a redundant flag.

3. The memory architecture according to claim 2, wherein the redundant register further comprises a second part (230) for storing the address of the defective original pad to be switched with one of the redundant pads.

4. The memory architecture according to claim 3, wherein the redundant register further comprises a third part (240) for storing the address of the at least one redundant pad.

5. The memory architecture according to claim 4, further comprising a selection circuit (300) connected to the redundant register, the original pads, and the at least one redundant pad to implement the interconnection redundancy.

6. The memory architecture according to claim 5, wherein the selection circuit comprises: - A first switch inserted between one of the data lines and one of the original pads; - A second switch inserted between one of the data lines and the at least one redundant pad; - An inverter gate that receives a first redundant signal associated with the redundancy flag stored in the first part (220) of the redundancy register and provides an inverted value to command the first switch; - An AND logic gate that receives the first redundant signal and a second redundant signal associated with the address stored in the third part (240) of the redundancy register and provides a combined value to command the second switch.

7. The memory architecture according to claim 6, further comprising a MUX (250) that receives the address stored in the third part of the redundant register to replace the defective pad whose address is stored in the second part of the redundant register.

8. An interconnection redundancy management block, comprising: - An interconnection redundancy management block connected to a plurality of original pads, one or more redundant pads, and a plurality of data lines for memory cells, wherein the interconnection redundancy management block is divided into a high page and a low page; and - A selection circuit (300) connected to the redundancy register (200), the original pads, and the one or more redundant pads; wherein the interconnection redundancy management block is configured to replace a determined defective original pad with one of the one or more redundant pads by replacing the original cell address of the high page of the interconnection redundancy management block with the redundant cell address of the high page of the interconnection redundancy management block, and replacing the original cell address of the low page of the interconnection redundancy management block with the redundant cell address of the low page of the interconnection redundancy management block.

9. The interconnection redundancy management block according to claim 8, wherein the redundant register comprises: - A first part (220) for indicating the usage of at least one of the one or more redundant pads by storing a redundancy flag; - A second part (230) for storing the address of a defective original pad to be switched with one of the redundant pads;and - A third part (240) for storing the address of one of the one or more redundant pads.

10. The interconnect redundancy management block according to claim 9, wherein the selection circuit comprises: - A first switch inserted between one of the data lines and one of the original pads; - A second switch inserted between one of the data lines and one of the one or more redundant pads; - An inverter gate that receives a first redundant signal associated with the redundancy flag stored in the first part of the redundancy register and provides an inverted value to command the first switch; and - An AND logic gate that receives the first redundant signal and a second redundant signal associated with the address stored in the third part of the redundant register and provides a combined value to command the second switch.

11. The interconnect redundancy management block according to claim 10, further comprising a MUX (250), the MUX receiving the redundant pad address stored in the third part of the redundant register to replace the defective pad whose address is stored in the second part of the redundant register.

12. A method for managing interconnect redundancy of a memory architecture (100), the method comprising: - Determine the functionality of one of the plurality of original pads of the memory architecture (100) by means of a redundant register divided into a high page and a low page; And - In response to determining that the original pad is functional, connect the original pad to a plurality of data lines; or - If the original pad is not operating correctly, use interconnect redundancy to connect a redundant pad to the data lines by replacing the original cell address of the high page of the redundant register with the redundant cell address of the high page of the redundant register, and replacing the original cell address of the low page of the redundant register with the redundant cell address of the low page of the redundant register.

13. The method according to claim 12, further comprising: - Store a redundancy flag in the first part (220) of the redundant register (200) to indicate the usage of the redundant pad; - Store the address of the defective original pad to be switched with the redundant pad in the second part (230) of the redundant register (200); And - Store the address of the redundant pad in the third part (240) of the redundant register (200) to address the redundant pad when the original pad is defective due to incorrect operation.

14. A system-on-chip (SoC) component, comprising: - A plurality of memory cell sub-arrays (110), - A plurality of sense amplifiers (120) connected to the sub-arrays (110); - A plurality of original pads; - A plurality of redundant pads; - A plurality of data lines; and - A redundant register (200) connected to the plurality of original pads, the plurality of redundant pads, and the data lines, the redundant register (200) being divided into a high page and a low page; Wherein when it is determined that the addressed original pad is defective, the redundant register (200) implements interconnect redundancy and connects one of the plurality of redundant pads to the data lines by replacing the original cell address of the high page of the redundant register with the redundant cell address of the high page of the redundant register, and replacing the original cell address of the low page of the redundant register with the redundant cell address of the low page of the redundant register.

15. The SoC component according to claim 14, wherein the redundant register comprises: - A first part (220) for indicating the usage of one of the plurality of redundant pads by storing a redundancy flag.

16. The SoC component according to claim 15, further comprising a selection circuit (300), the selection circuit (300) being connected to the redundant register, the original pad and the redundant pad to implement the interconnect redundancy.

17. The SoC component according to claim 16, wherein the selection circuit (300) comprises: - A first switch inserted between the data line and one of the original pads; - A second switch inserted between the data line and one of the redundant pads; - An inverter gate that receives a first redundant signal associated with the redundancy flag stored in the first part (220) of the redundant register and provides an inverted value to command the first switch; - An AND logic gate that receives the first redundant signal and a second redundant signal associated with the address stored in the third part (240) of the redundant register and provides a combined value to command the second switch.

18. The SoC component according to claim 17, further comprising a MUX (250), the MUX receiving the redundant pad address stored in the third part of the redundant register to replace the defective pad whose address is stored in the second part of the redundant register.

19. The SoC component according to claim 14, wherein the redundant register comprises a second part for storing the address of the defective original pad to be switched with one of the redundant pads.

20. The SoC component according to claim 14, wherein the redundant register comprises a third part for storing the address of one of the redundant pads to address the one of the redundant pads.

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