Devices and methods for driving data lines in a memory array

Abstract

This disclosure relates to apparatus and methods for driving data lines in a memory array. In some examples, separate main I / O (MIO) lines can be used to write to different banks of the memory array. In some examples, separate MIO lines can be used to write to and read from different banks of memory. In some examples, the MIO lines of some banks can be used as shielding lines between the MIO lines of other banks of memory.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to semiconductor memory devices. In particular, this disclosure relates to volatile memories, such as dynamic random access memory (DRAM). Background Technology

[0002] Information can be stored as physical signals (e.g., charge on a capacitor element) in individual memory cells. For example, information can be written to a memory cell by charging or discharging a capacitor element. The stored information can be read from a memory cell by detecting the physical signal (e.g., sensing the amount of charge on a capacitor element). Memory cells are typically arranged in arrays of rows and columns. Memory cells in a column can be coupled to another access line (e.g., a word line), and memory cells in a row can be coupled to another access line (e.g., a bit line). Thus, each memory cell can be located at the intersection of a word line and a bit line. Memory cells can be accessed for reading and / or writing by activating the appropriate word line and bit line. In some applications, data from a memory cell can be provided from a bit line to a local data line, which in turn can provide data to a main data line (sometimes called a master input / output (I / O) line), which in turn provides data to a global data bus, which in turn provides data to the memory's output terminals.

[0003] As memory array capacity increases, the current required to drive the data lines may also increase. This can increase the memory's power consumption. Higher current may also necessitate the use of more expensive and / or larger components capable of handling higher currents. Therefore, it may be desirable to reduce the memory's current consumption. Summary of the Invention

[0004] In one aspect, this disclosure relates to an apparatus comprising: a memory array including a plurality of memory banks; a first plurality of main data lines coupled to at least a first subset of the plurality of memory banks and configured to receive read data and provide write data to the first subset of the plurality of memory banks; and a second plurality of main data lines coupled to a second subset of the plurality of memory banks and configured to provide write data to the second subset of the plurality of memory banks, wherein the length of the second plurality of main data lines is less than the length of the first plurality of main data lines.

[0005] In another aspect, this disclosure relates to an apparatus comprising: a memory array including a plurality of memory banks; a first plurality of main data lines coupled to the plurality of memory banks and configured to receive read data from the plurality of memory banks; and a second plurality of main data lines coupled to a subset of the plurality of memory banks and configured to provide write data to the subset of the plurality of memory banks.

[0006] In a further aspect, this disclosure relates to an apparatus comprising: a memory array including a plurality of memory banks; a first plurality of main data lines coupled to a first subset of the plurality of memory banks and configured to receive read data from the first subset of the plurality of memory banks and to provide write data to the first subset of the plurality of memory banks; a second plurality of main data lines coupled to a second subset of the plurality of memory banks and configured to receive read data from the second subset of the plurality of memory banks and to provide write data to the second subset of the plurality of memory banks, wherein the first subset of the plurality of memory banks and the second subset of the plurality of memory banks are mutually exclusive; and a selection circuit configured to selectively couple each of the first plurality of main data lines and each of the second plurality of main data lines to a corresponding data sense amplifier of a plurality of data sense amplifiers, wherein each data sense amplifier of the plurality of data sense amplifiers is shared by at least one of the first plurality of main data lines and at least one of the second plurality of main data lines. Attached Figure Description

[0007] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 is a block diagram of a portion of a semiconductor memory device.

[0009] Figure 3 is a block diagram of a sub-amplifier in a semiconductor memory device.

[0010] Figure 4 is a timing diagram of various signals within a semiconductor memory device during memory operations.

[0011] Figure 5 This is a block diagram of a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figure 6 This is a block diagram of a sub-amplifier of a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 7 This is a timing diagram of various signals within a semiconductor memory device during memory operation according to embodiments of the present disclosure.

[0014] Figure 8 This is a block diagram of a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 9 This is a timing diagram of various signals within a semiconductor memory device during memory operation according to embodiments of the present disclosure. Detailed Implementation

[0016] The following description of certain embodiments is merely exemplary in nature and is not intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the devices, systems, and methods, reference is made to the accompanying drawings, which form part of the invention and illustrate specific embodiments of the described devices, systems, and methods by way of illustration. These embodiments are described in great detail to enable those skilled in the art to practice the currently disclosed devices, systems, and methods, and it should be understood that other embodiments may be used and structural and logical changes may be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, detailed descriptions of certain features will not be discussed where they are obvious to those skilled in the art, so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be considered limiting, and the scope of this disclosure is defined only by the appended claims.

[0017] Memory arrays can be organized into one or more memory banks. Each memory bank can contain one or more memory cells for storing data. During a write operation, data to be written to a memory cell is supplied to the memory bank via a main data line (e.g., an MIO line). Similarly, during a read operation, data is received from the memory bank via the main data line. Typically, each main data line can supply or receive data from a subset of memory cells within each memory bank. For example, in some applications, each memory bank can be further divided into one or more mats. If the memory array has eight memory banks, during a write operation, the main data line can supply data to the mats in each of the eight memory banks. However, as the size and / or number of memory banks increases, the current consumption on the main data lines during storage operations also increases. In some applications, the current consumption may be particularly high during write operations when the write driver is available to drive the write data on the main data lines.

[0018] According to embodiments of this disclosure, a separate main data line can be used to provide data to different banks of a memory array for write operations. In these embodiments, the main data line (e.g., a main input / output line) can provide data to a subset of the banks (e.g., fewer than all banks). In some embodiments, some main data lines can receive read data from all banks while providing write data to a subset of the banks. In other embodiments, a separate main data line can be used to provide data to different banks of the memory array for both read and write operations. In some applications, using different main data lines for different banks can reduce memory current consumption during memory operations, such as write operations.

[0019] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor memory device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0020] Semiconductor memory device 100 includes a memory array 118. The memory array 118 is shown as comprising a plurality of memory cells. Figure 1 In one embodiment, the memory array 118 is shown as comprising eight memory banks BANK0-BANK7. In other embodiments, the memory array 118 may contain more or fewer memory banks. Each memory bank includes multiple word lines WL, multiple bit lines BL and / or BL, and multiple memory cells MC arranged at the intersections of the word lines WL and the bit lines BL and / or BL. The selection of word lines WL is performed by the row decoder 108, and the selection of bit lines BL and / or BL is performed by the column decoder 110. Figure 1 In this embodiment, row decoder 108 includes a corresponding row decoder for each memory bank, and column decoder 110 includes a corresponding column decoder for each memory bank. Bit lines BL and / or BL are coupled to a corresponding sense amplifier (SAMP) 126. Figure 1In the example shown, the sense amplifier 126 is a differential amplifier that receives differential signals from bit lines BL and / BL. Data read from the differential signals on bit lines BL or / BL is amplified by sense amplifier 126, and this differential signal is provided to sub-amplifier (SB) 128 via complementary local data lines (LIOT / B). Sub-amplifier 128 may provide differential signals to complementary master data lines (MIOT / B) or provide single-ended signals on master data lines (MIO). Master data lines may provide signals to read / write amplifier (RWAMP) 120. Read / write amplifier 120 provides read data to input / output (IO) circuitry 122 via the global data bus (GBUS). Conversely, write data received from IO circuitry 122 via the global data bus is provided from read / write amplifier 120 to sense amplifier 126 via master data line MIO, sub-amplifier 128, and complementary local data lines LIOT / B, and written to memory cells MC coupled to bit lines BL or / BL.

[0021] The read / write amplifier 120 may include one or more write drivers. Figure 1 (Not shown in the diagram) to drive write data on the main data lines during write operations. In some embodiments, the write driver of the read / write amplifier 120 can be enabled by an enable signal provided from the command decoder 106 and / or the column decoder 110. According to embodiments of this disclosure, different (e.g., separate) main data lines and write drivers can be used to write data to different banks of the memory array 118. In some examples, the main data lines can be driven by write drivers to write to BANK0-3 of the memory array 118, and another main data line driven by another write driver can be used to write to BANK4-7. Other partitions between banks of the memory array 118 can be used in other examples (e.g., main data lines for BANK0 and BANK1, main data lines for BANK2 and BANK3, main data lines for BANK4 and BANK5, and main data lines for BANK6 and BANK7). In some embodiments, the main data lines can be used by all banks for read operations. In other embodiments, different main data lines can be used for read and write operations to different banks of the memory array 118.

[0022] In some embodiments, the number of main data lines in the semiconductor memory device 100 may be greater than the number of main data lines in a means for providing data to all banks of memory in the memory array 118 during a write operation. As will be described in more detail herein, in some embodiments, some main data lines may be used as shielding lines located between the main data lines. In some applications, these main data lines may replace the shielding lines included in a conventional layout, and thus may at least partially reduce the increased layout area on the semiconductor memory device 100 due to the inclusion of additional main data lines.

[0023] The semiconductor memory device 100 may employ multiple external terminals, including: a command and address (C / A) terminal coupled to the command and address bus to receive command and address signals and chip select signals, a clock terminal for receiving clock CK and / CK, a data terminal DQ for providing data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ and VSSQ.

[0024] An external clock CK and / CK are provided to the clock terminal for input circuit 112. The external clocks can be complementary. Input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to command decoder 106 and internal clock generator 114. Internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to input / output circuit 122 to time the operation of circuits contained within input / output circuit 122, for example, to a data receiver to time the reception of write data.

[0025] A memory address can be provided to the C / A terminal. The memory address provided to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and provides the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 can also provide a decoded bank address BADD, which indicates the bank of memory array 118 containing the decoded row address XADD and column address YADD. Commands can be provided to the C / A terminal. Examples of commands include access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, as well as other commands and operations. Access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cell to be accessed.

[0026] These commands can be provided as internal command signals to the command decoder 106 via the command / address input circuit 102. The command decoder 106 includes circuitry that decodes the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 106 can provide row command signals for select word lines and column command signals for select bit lines.

[0027] The semiconductor memory device 100 can receive access commands as read commands. When an activation command and a read command are received, and the activation command and read command are provided in a timely manner to the bank address, row address, and column address, read data is read from the memory cells in the memory array 118 corresponding to the row address and column address. The command decoder 106 receives the activation and read commands and provides an internal command that causes the read data of the memory array 118 to be provided to the read / write amplifier 120. The read data is output to the outside via the data terminal DQ through the I / O circuit 122.

[0028] The semiconductor memory device 100 can receive access commands as write commands. When an activation command and a write command are received, and the activation command and write command are provided to the bank address, row address, and column address in a timely manner, write data provided to the data terminal DQ is written to the memory cells in the memory array 118 corresponding to the row address and column address. The activation and write commands are received by a command decoder 106, which provides an internal command causing the write data to be received by the data receiver in the I / O circuit 122. A write clock can also be provided to an external clock terminal to time the write data received by the data receiver of the I / O circuit 122. The write data is provided to the read / write amplifier 120 via the I / O circuit 122, and then provided to the memory array 118 by the read / write amplifier 120 to be written to the memory cell MC.

[0029] The memory cells of memory array 118 may need to be refreshed periodically to retain data in the memory cells MC. A refresh signal AREF can be provided to refresh control circuitry 116. Refresh control circuitry 116 provides a refresh row address RXADD to row decoder 108, which can refresh one or more word lines WL indicated by refresh row address RXADD. Refresh control circuitry 116 can control the timing of the refresh operation and can generate and provide refresh address RXADD. The refresh control circuitry 116 can be controlled to change the details of refresh address RXADD, or it can be operated based on internal logic.

[0030] Power supply potentials VDD and VSS are provided to the power supply terminals. These potentials VDD and VSS are then supplied to the internal voltage generator circuit 124. Based on the power supply potentials VDD and VSS provided to the power supply terminals, the internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc. Internal potential VPP is primarily used in the line decoder 108, internal potentials VOD and VARY are primarily used in the sense amplifier 126 contained in the memory array 118, and internal potential VPERI is used in many peripheral circuit blocks.

[0031] Power potentials VDDQ and VSSQ are also provided to the power supply terminals. These power potentials VDDQ and VSSQ are provided to the I / O circuit 122. In embodiments of this disclosure, the power potentials VDDQ and VSSQ provided to the power supply terminals may be the same as the power potentials VDD and VSS provided to the power supply terminals. In another embodiment of this disclosure, the power potentials VDDQ and VSSQ provided to the power supply terminals may be different from the power potentials VDD and VSS provided to the power supply terminals. The power potentials VDDQ and VSSQ provided to the power supply terminals are used in the I / O circuit 122 so that power supply noise generated by the I / O circuit 122 does not propagate to other circuit blocks.

[0032] The structure and operation of a conventional storage device will be described with reference to Figures 2 to 4.

[0033] Figure 2 is a block diagram of a portion of a semiconductor memory device. The semiconductor memory device 200 may include a memory array 202 containing multiple memory banks BK0-7. The memory array 202 can be coupled to a read / write amplifier 204 via main data lines 206, 208. The read / write amplifier 204 may include write drivers 210, 212, one write driver for each main data line 206, 208. During a write operation, the read / write amplifier 204 can receive data from the Global Data Bus (GBUS). The data can be driven by the write drivers 210, 212 onto the main data lines 206, 208 to be written to the appropriate memory banks BK0-7 of the memory array 202. The appropriate write drivers 210, 212 can be enabled by a write driver enable signal CWAE. During a read operation, the main data lines 206, 208 can provide read data to a data read amplifier 214, which amplifies the read data to provide it to the Global Data Bus. The appropriate data readout amplifier 214 can be enabled by the readout amplifier signal CDAE.

[0034] During a write operation, each master data line 206, 208 can provide data to a portion of each of the memory banks BK0-7. For example, each of the memory banks BK0-7 can be divided into eight mats (not shown). Master data line 206 can provide data to the first mat in each memory bank BK0-7, and master data line 208 can provide data to the second mat in each memory bank BK0-7. Similarly, during a read operation, each master data line 206, 208 can receive data from a portion of each of the memory banks BK0-7. Although only two master data lines 206, 208 are shown in Figure 2, the semiconductor memory device 200 can contain more master data lines. For example, the number of master data lines can be equal to the number of portions of each memory bank BK0-7 (e.g., the number of mats). Similarly, there can be multiple write drivers corresponding to the number of master data lines.

[0035] The main data lines 206 and 208 can be alternated with the shield lines 216 and 218. In some examples, the shield lines 216 and 218 can be coupled to a voltage source (e.g., VSS). Positioning the shield lines 216 and 218 between the main data lines 206 and 208 can reduce electromagnetic field effects or other interference between the main data lines 206 and 208.

[0036] In the semiconductor memory device 200, the main data lines 206 and 208 extend the entire length of the memory array 202 to access all memory banks BK0-7. Therefore, the current consumption of the main data lines 206 and 208 will be the same, regardless of which memory bank BK0-7 is written to.

[0037] Figure 3 is a block diagram of a sub-amplifier in a semiconductor memory device. Sub-amplifier 300 may be included in semiconductor memory device 200. During a write operation, sub-amplifier 300 may receive data MIO_DATA from main data line 312 (in some examples, the main data line may be main data line 206 and / or 208) and provide this data as a differential signal on local data lines LIOT, LIOB. Similarly, during a read operation, sub-amplifier 300 may receive data from memory cells as a differential signal from local data lines and provide this data as MIO_DATA to main data line 312.

[0038] Subamplifier 300 may include transistors 302, 304, and 306, series-coupled along local data line LIOT. Subamplifier 300 may further include transistors 308 and 310, series-coupled and further coupled to local data line LIOB. Transistors 302 and 310 may receive a write signal WSN at their respective gates. The write signal WSN may indicate a write operation. Transistor 306 may receive a read signal RS at its gate. The write signal WSN and the read signal RS may be provided by a command decoder of the semiconductor memory device including subamplifier 300. The gate of transistor 304 may be coupled to local data line LIOB, and the gate of transistor 308 may be coupled to local data line LIOT.

[0039] During a write operation, the write signal WSN can be active. The active state of the write signal WSN activates transistors 302 and 310. The read signal RS may be inactive. The inactive state of the read signal RS deactivates transistor 306. When transistors 302 and 310 are activated by the active write signal WSN, the data MIO_DATA on the main data line 312 can be provided as a differential signal on the local data lines LIOT and LIOB. Due to the cross-coupling of transistors 304 and 308, the local data line LIOT can provide the data MIO_DATA from the main data line 312, while the local data line LIOB can provide the complement of the data MIO_DATA.

[0040] During a read operation, the read signal can be active, which activates transistor 306. The write signal WSN may be inactive, which may deactivate transistors 302 and 310. The main data line can receive read data from local data lines LIOT and LIOB, and provides the read data as data MIO_DATA on the main data line 312.

[0041] Figure 4 is a timing diagram of various signals within the semiconductor memory device during memory operations. The signal states within the semiconductor memory device 200 during read and write operations are reflected in timing diagram 400. The first row of timing diagram 400 shows the clock signal (CLK) that can be received by the semiconductor memory device 200. The second row of timing diagram 400 shows the command (CMD) received by the semiconductor memory device 200. The third row of timing diagram 400 shows the state of the column select (CS) provided by the semiconductor memory device 200. The fourth row of timing diagram 400 shows the write driver enable signal (CWAE). The fifth row of timing diagram 400 shows the state of the master data line (MIO). The last row of timing diagram 400 shows the state of the data amplifier enable signal (CDAE).

[0042] At or around time T0, the semiconductor memory device may receive a write command W0. The write command W0 may instruct data to be written to memory bank BK0 of memory array 202. At least in part in response to the write command W0, the write drive enable signal CWAE may transition from an inactive (e.g., low) state to an active (e.g., high) state at or around time T1. Activating the CWAE signal enables write drivers 210 and / or 212 to drive data on the main data lines. Also at or around time T1, data to be written to memory bank BK0 may be provided on main data lines MIO (e.g., main data lines 206, 208). At or around time T2, at least in part in response to receiving the write command W0, the semiconductor memory device may provide a column select signal CS associated with the write command W0. At least in part in response to the column select signal CS, data may be driven from the main data lines to subamplifier 300, to the sense amplifier, and to the memory cells of memory bank BK0.

[0043] Around time T3, the semiconductor memory device 200 may receive a write command W4. The write command W4 may instruct data to be written to the memory bank BK4 of the memory array 202. At least partially in response to the write command W4, the write drive enable signal CWAE may remain active. Around time T4, the column select signal CS may switch to an inactive state. Around time T5, the data to be written to the memory bank BK4 may be provided on the main data line MIO. Around time T6, at least partially in response to receiving the write command W4, the semiconductor memory device may provide the column select signal CS associated with the write command W4 until around time T7. At least partially in response to the column select signal CS, data may be driven from the main data lines (e.g., main data lines 206, 208) to the sub-amplifier 300, to the sense amplifier, and to the memory cells of the memory bank BK4.

[0044] As shown in timing diagram 400, the semiconductor memory device can receive additional write commands. The write operation can be performed in a manner similar to that performed in response to write commands W0 and W4.

[0045] Around time T8, the semiconductor memory device 200 may receive a read command R0. The read command R0 may indicate that data should be read from memory bank BK0 of memory array 202. Around time T9, CWAE may transition to an inactive state, which may disable write drivers 210, 212. Around time T10, at least in part in response to the read command R0, the semiconductor memory device may provide a column select signal CS associated with the read command R0. At least in part in response to the column select signal CS, around time T11, data from memory cells of memory bank BK0 may be provided on the main data line MIO.

[0046] Also around time T11, the semiconductor memory device may receive a read command R4. Read command R4 indicates that data should be read from memory bank BK4 of memory array 202. Around time T12, the column select signal CS may switch to an inactive state. Around time T13, the data amplifier enable signal CDAE may switch to an active state (e.g., high). The CDAE signal enables data sense amplifier 214, which amplifies the data received from main data lines 206, 208 and provides the read data from memory bank BK0 to the global data bus. Around time T14, the CDAE signal may return to an inactive state (e.g., low), which disables data sense amplifier 214. Around time T15, at least in part in response to read command R4, the column select signal CS associated with read command R4 may be provided. At least in part in response to the column select signal CS, data from memory cells of memory bank BK4 may be provided on main data line MIO around time T16. Around time T17, the data amplifier enable signal CDAE can be switched to the active state. The CDAE signal enables the data read amplifier 214, which amplifies the data received from the main data lines 206 and 208 and provides the read data of memory bank BK4 to the global data bus. Around time T18, the CDAE signal can return to the inactive state, which disables the data read amplifier 214.

[0047] As shown in timing diagram 400, the semiconductor memory device can receive additional read commands. The read operation can be performed in a manner similar to the read operation performed in response to read commands R0 and R4.

[0048] As shown in timing diagram 400, when the main data line is used to provide write data to all banks of the memory array, the same write drive enable signal CWAE is activated for write operations on any bank. When the main data line is also used to receive read data from all banks, the same data amplifier enable signal CDAE is activated for read operations on all banks of the memory array.

[0049] In contrast to semiconductor memory device 200, in embodiments of this disclosure, a separate main data line can be used to provide data to different banks of the memory array for write operations. In some embodiments, the main data lines can be of different lengths (e.g., one shorter than the other). In some embodiments, the longer main data line can extend across all banks of the memory array. The longer main data line may or may not be coupled to all banks. The shorter main data line can extend over a subset of banks. In some embodiments, the shorter main data line can extend over a subset of banks that are closer to the read / write amplifier than other banks. In some embodiments, the shorter main data line is used for write operations on a subset of banks. In other embodiments, the shorter main data line is used for both read and write operations on a subset of banks. At least in part due to its shorter length, the shorter main data line can consume less current during read and / or write operations.

[0050] Figure 5 This is a block diagram of a portion of a semiconductor memory device according to embodiments of the present disclosure. In some embodiments, semiconductor memory device 500 may be included in semiconductor memory device 100. Semiconductor memory device 500 may include memory array 502, which includes a plurality of memory banks BK0-7. In some embodiments, memory array 502 may be included in memory array 118. Memory array 502 may be coupled to read / write amplifier 504 via main data lines 506, 508, 520, and 522. In some embodiments, read / write amplifier 504 may be included in read / write amplifier 120. Read / write amplifier 504 may include write drivers 510, 512, 524, and 526, one write driver for each main data line 506, 508, 520, and 522.

[0051] like Figure 5 As shown, main data lines 506 and 508 extend and / or couple to all memory banks BK0-7 of memory array 502. Conversely, main data lines 520 and 522 extend and / or couple to a subset of memory banks. In some embodiments, main data lines 520 and 522 may extend to a subset of memory banks closer to read / write amplifier 504 than the remaining memory banks, which may be further away from read / write amplifier 504. Figure 5 In the example shown, main data lines 520 and 522 extend to BK4-7 and are not coupled to memory bank BK0-3. According to embodiments of this disclosure, main data lines 506 and 508 can receive data from portions of all memory banks BK0-7 during read operations and provide data to memory bank BK0-3 during write operations. Main data lines 520 and 522 can provide data to portions of memory bank BK4-7 during write operations. In some examples, such as in... Figure 5In the example shown, main data lines 506 and 508 can provide write data to a subset of memory that is different from main data lines 520 and 522. That is, in some embodiments, the subsets can be mutually exclusive. In some embodiments, the subsets can partially overlap and can access a portion of the memory array 502. In some embodiments, main data lines 520 and 522 are not used for read operations.

[0052] Master data line 506 can receive data during a read operation from the same portion of the memory bank to which master data line 520 provides data during a write operation. Similarly, master data line 508 can receive data during a read operation from the same portion of the memory bank to which master data line 522 provides data during a write operation. For example, memory banks BK0-7 can each be divided into eight mats (not shown). Master data line 506 can receive data from the first mat of each memory bank BK0-7 during a read operation and provide data to the first mat of each memory bank BK0-3 during a write operation. Master data line 520 can provide data to the first mat of each memory bank BK4-7 during a write operation. Master data line 508 can receive data from the second mat of each memory bank BK0-7 during a read operation and provide data to the second mat of each memory bank BK0-3 during a write operation. Master data line 522 can provide data to the second mat of each memory bank BK4-7 during a write operation. Therefore, in some embodiments, semiconductor memory device 500 may include more main data lines than semiconductor memory device 200.

[0053] In some embodiments, such as in Figure 5 In the illustrated embodiment, the read / write amplifier 504 may include separate write drivers 510, 512, 524, and 526 for each of the main data lines 506, 508, 520, and 522. Write drivers 510 and 512 may be enabled by an enable signal CWAE_BK03, while write drivers 524 and 526 are enabled by a separate enable signal CWAE_BK47 during write operations to the respective memory bank. Therefore, in some embodiments, the semiconductor memory device 500 may include more word drivers and enable signal lines than the semiconductor memory device 200. In some embodiments, the enable signal may be provided by a command decoder (such as command decoder 106). In some embodiments, the enable signal may be provided via a column decoder (such as column decoder 110).

[0054] During a read operation, main data lines 506 and 508 can supply read data to the data read amplifier 514 of the read / write amplifier 504, which amplifies the read data for supply to the global data bus. The appropriate data read amplifier 514 can be enabled by the read data read amplifier signal CDAE. In some examples, the read data read amplifier signal CDAE can be provided by a command decoder and / or a column decoder.

[0055] although Figure 5 Only four main data lines 506, 508, 520, and 522 are shown, but the semiconductor memory device 500 may contain more main data lines. In some embodiments, the number of main data lines may be equal to twice the number of portions of the memory bank BK0-7 (e.g., the number of mats). For example, if the memory bank BK0-7 is divided into eight memory mats, there may be sixteen main data lines. In some embodiments, there may be multiple write drivers corresponding to the number of main data lines (e.g., if there are sixteen main data lines, there are sixteen word drivers).

[0056] In some embodiments, such as in Figure 5 In the illustrated embodiment, memory array 502 may include shielding lines 516 and 518, similar to shielding lines 216 and 218 in memory array 202. In some embodiments, shielding lines 516, 518 may be coupled to a voltage source (e.g., VSS). However, unlike shielding lines 216 and 218, shielding lines 516 and 518 may extend over a subset of memory banks BK0-7. Figure 5 In the example shown, shield lines 516 and 518 extend over memory cells BK0-3. Main data lines 520 and 522 could extend over memory cells BK4-7 located in the semiconductor memory device 200, instead of continuing shield lines 516 and 518 over the remaining memory cells. Figure 5As shown, shield lines 516 and 518 can be aligned with main data lines 520 and 522, respectively. Main data lines 520 and 522, which typically extend with shield lines 516 and 518, can reduce the increased layout area due to the additional main data lines 520 and 522. Main data lines 506 and 508 can alternate with shield lines 516 and 518 and main data lines 520 and 522 (e.g., arranged in an alternating pattern / mode). Positioning shield lines 516 and 518 between main data lines 506 and 508 can reduce electromagnetic field effects or other interference between main data lines 506 and 508. In some applications, shield lines 216 and 218 can reduce the shielding between main data lines 506 and 508 compared to the shielding between main data lines 206 and 206. However, the reduced shielding is still sufficient for the proper operation of the memory array 502. In some examples, the main data lines 520 and 522 may not be activated simultaneously with the main data lines 506 and 508, which can mitigate the impact of the reduced shielding lines 516 and 518.

[0057] During write operations to memory banks BK0-3, main data lines 506 and / or 508 may be driven by corresponding write drivers 510, 512 to provide write data received from the Global Data Bus (GBUS). In some applications, the current consumption of write operations to memory banks BK0-3 of memory array 502 may be the same as the current consumption of write operations to memory banks BK0-3 of memory array 202 of FIG. 2. During write operations to memory banks BK4-7, main data lines 520 and / or 522 may be driven by corresponding write drivers 524, 526. In some applications, the current consumption of write operations to memory banks BK4-7 of memory array 502 may be less than the current consumption of write operations to memory banks BK4-7 of memory array 202. The reduced current consumption may be at least partially due to the shorter length of main data lines 520, 522. However, as described above, semiconductor memory device 500 may include more write drivers than semiconductor memory device 200. Therefore, in some applications, the semiconductor memory device 500 may require a larger layout area for the read / write amplifier 504 than the read / write amplifier 204.

[0058] Figure 6 This is a block diagram of a sub-amplifier in a semiconductor memory device according to an embodiment of the present disclosure. In some embodiments, sub-amplifier 600 may be included in semiconductor memory device 500 and / or semiconductor memory device 100. For example, sub-amplifier 600 may be included in sub-amplifier 128. Sub-amplifier 600 may be included in a memory bank having separate main data lines for read and write operations. Figure 5In the example shown, sub-amplifier 600 may be included in memory bank BK4-7. In some embodiments, memory banks having the same main data line for read and write operations (e.g., Figure 5 The memory bank BK0-3 in the memory bank can use the sub-amplifier 300 shown in Figure 3.

[0059] Subamplifier 600 may include transistor 602 having a first node coupled to a local data line LIOT and a second node coupled to a main data line 612 (which may be main data lines 520 and / or 522 in some examples), which provides data MIOR_DATA for write operations. The gate of transistor 602 may receive a write signal WSN indicating a write operation. In some embodiments, the write signal may be provided by a command decoder, such as command decoder 106. In some examples, the write signal WSN may be provided to subamplifier 600 via a column decoder (such as column decoder 110) coupled to the command decoder. Subamplifier 600 may further include transistors 604 and 606 series coupled between another main data line 614 (which may be main data lines 506 and / or 508 in some examples) and a voltage source (e.g., ground, VSS), which provides data MIOR_DATA for read operations. Subamplifier 600 may further include transistors 608 and 610 series coupled between the local data line LIOB and a voltage source (e.g., ground, VSS). The gate of transistor 610 can also receive a write signal WSN. Transistor 606 can receive a read signal RS indicating a read operation at its gate. In some embodiments, the read signal RS can be provided by a command decoder and / or a column decoder. The gate of transistor 604 can be coupled to the local data line LIOB, and the gate of transistor 608 can be coupled to the local data line LIOT.

[0060] During a write operation, the write signal WSN can be active. The active state of the write signal WSN activates transistors 602 and 610. The read signal RS can be inactive. The inactive state of the read signal RS deactivates transistor 606. When transistors 602 and 610 are activated by the active write signal WSN, the data MIOW_DATA on the main data line 612 can be provided as a differential signal on the local data lines LIOT and LIOB. Due to the cross-coupling of transistors 604 and 608, the local data line LIOT can provide the data MIOW_DATA from the main data line 612, and the local data line LIOB can provide the complement of the data MIOW_DATA to the sense amplifier. Figure 6 (not shown in the image), such as Figure 1 The readout amplifier 126 is included.

[0061] During a read operation, the read signal can be active, which activates transistor 606. The write signal WSN can be inactive, which deactivates transistors 602 and 610. Another main data line 614 can receive read data from local data lines LIOT and LIOB and provide the read data as data MIOR_DATA to a data sense amplifier, such as data sense amplifier 514. Therefore, subamplifier 600 can couple local data lines LIOT and LIOB to main data line 612 during a write operation and to main data line 614 during a read operation.

[0062] Returning to sub-amplifier 300 in Figure 3, transistors 302 and 304 share a common node (e.g., source / drain). Conversely, transistors 602 and 604 have separate nodes due to their coupling to different main data lines 612 and 614. In some applications, the separate nodes of transistors 602 and 604 can allow sub-amplifier 600 to have a larger layout area than sub-amplifier 600.

[0063] Although in some embodiments, the semiconductor memory device 500 may include more write drivers and / or at least some larger sub-amplifiers (e.g., sub-amplifier 600), which may require more layout area, in some applications, the disadvantages of increased layout size can be offset by the advantages of reduced current consumption during at least some write operations.

[0064] Figure 7 This is a timing diagram of various signals within a semiconductor memory device during memory operations according to embodiments of the present disclosure. During read and write operations, the signal states within semiconductor memory device 100 and / or semiconductor memory device 500 can be reflected in the timing diagram 700 and will be referenced... Figure 1 and 5 The signals described in timing diagram 700. However, timing diagram 700 can reflect more than just... Figure 1 and 5 Operation of storage devices other than the specific storage device shown.

[0065] The first row of timing diagram 700 shows the clock signal (CLK). In some examples, the clock signal may be an internal clock signal generated by an internal clock generator (such as internal clock generator 114). The second row of timing diagram 700 shows the command (CMD). In some examples, the command CMD may be received by a command decoder (such as command decoder 106). In some examples, the command CMD may be provided to the storage device by another device (such as a storage controller (not shown)). The third row of timing diagram 700 shows the column select signal (CS) provided by a column decoder (such as column decoder 110). The column select signal CS may be issued in response to the command decoder receiving the command CMD. In some embodiments, the command decoder may provide the column decoder with a signal associated with the command CMD (e.g., an internal command), and may provide the column select signal CS at least in part in response to the signal provided by the command decoder. The fourth row of timing diagram 700 shows the state of the write driver enable signal (CWAE_BK03). The write driver enable signal CWAE_BK03 can be provided to write drivers coupled to the main data lines (such as write drivers 510 and 512), which are coupled to all banks of the memory array. The fifth row of timing diagram 700 shows the state of the write driver enable signal (CWAE_BK47). The write driver enable signal CWAE_BK47 can be provided to write drivers coupled to the main data lines (such as write drivers 524 and 526), ​​which are coupled to a subset of banks of the memory array. The sixth row of timing diagram 700 shows the state of the main data lines (MIOs) (such as main data lines 506 and 508) coupled to all banks of the memory array. The seventh row of timing diagram 700 shows the state of the main data lines (MIO47W) (such as main data lines 520 and 522) coupled to a subset of banks of the memory array. The last row of timing diagram 700 shows the state of the data amplifier enable signal (CDAE), which can be provided to the data sense amplifier (e.g., data sense amplifier 514). In some embodiments, various enable signals CWAE_BK03, CWAE_BK47 and / or CDAE can be provided by the command decoder and / or column decoder.

[0066] At or around time T0, a semiconductor memory device (e.g., semiconductor memory devices 100 and / or 500) may receive a write command W0. In some examples, the write command W0 may be received by a command decoder 106 from an external device (such as a memory controller). The write command W0 may indicate that data is to be written to bank BK0 of memory array 502 (and / or bank BK0 of memory array 118). At least in part in response to the write command W0, the write drive enable signal CWAE_BK03 may transition from an inactive (e.g., low) state to an active (e.g., high) state at or around time T1. Activating the CWAE_BK03 signal enables write drivers 510 and / or 512 to drive data on main data lines 506 and / or 508. Also at or around time T1, data to be written to bank BK0 / BANK0 may be provided on main data line MIO. At or around time T2, at least in part in response to receiving the write command W0, the column decoder may provide a column select signal CS associated with the write command W0. At least in part in response to the column select signal CS, data can be driven from the main data line (e.g., MIO, main data line 506 and / or 508) to the sub-amplifier (e.g., sub-amplifier 300 and / or sub-amplifier 128), to the sense amplifier 126, and to the memory cells of the memory bank BK0 / BANK0.

[0067] Around time T3, the semiconductor memory device may receive a write command W4. The write command W4 may instruct data to be written to memory banks BK4 / BANK4 of the memory array. Around time T4, the column select signal CS may transition to an inactive state. At least partially in response to the write command W4, the write drive enable signal CWAE_BK47 may transition to an active state, and CWAE_BK03 may transition to an inactive state. Activating the CWAE_BK47 signal enables write drivers 524 and 526, and deactivating the CWAE_BK03 signal disables write drivers 510 and 512. Around time T5, the data to be written to memory banks BK4 / BANK4 may be provided on the main data line MIO47W (e.g., main data lines 520 and / or 522). Around time T6, at least partially in response to receiving the write command W4, the column decoder may provide the column select signal CS associated with the write command W4 until around time T7. At least in part in response to the column select signal CS, data can be driven from the main data line MIO47W to subamplifiers 600 and / or 128, to the sense amplifier 126, and to the memory cells of memory bank BK4 / BANK4. At or around time T8, the CWAE_BK47 signal can transition to an inactive state (e.g., low), which disables write drivers 524 and 526.

[0068] As shown in timing diagram 700, the semiconductor memory device can receive additional write commands. Write operations to BK0-3 / BANK0-3 can be performed in a manner similar to write operations performed in response to write command W0, and write operations to BK4-7 / BANK4-7 can be performed in a manner similar to write operations performed in response to write command W4.

[0069] Around time T9, the command decoder may receive a read command R0. Read command R0 may indicate that data should be read from memory bank BK0 / BANK0 of the memory array. Around time T10, CWAE_BK03 may transition to an inactive state, which may disable write drivers 510, 512. Around time T11, at least in part in response to read command R0, the column decoder may provide a column select signal CS associated with read command R0. At least in part in response to column select signal CS, around time T12, data for memory cells of memory bank BK0 / BANK0 may be provided on main data line MIO (e.g., main data lines 506 and / or 508).

[0070] Around time T12, the command decoder can receive the read command R4. The read command R4 indicates that data should be read from memory bank BK4 / BANK4 of the memory array. Around time T13, the column select signal CS can be deactivated. Around time T14, the data amplifier enable signal CDAE can be activated (e.g., high). The CDAE signal enables the data readout amplifier 514, which amplifies the data received from the main data lines 506, 508 and provides the read data from memory bank BK0 / BANK0 to the global data bus. Around time T15, the CDAE signal can return to the deactivated state (e.g., low), which disables the data readout amplifier 514. Around time T16, at least in part in response to the read command R4, the column select signal CS associated with the read command R4 can be provided. At least in part in response to the command signal CS, data from the memory cells of memory bank BK4 / BANK4 can be provided on the main data line MIO around time T17. Around time T18, the data amplifier enable signal CDAE can be switched to the active state. The CDAE signal enables the data read amplifier 514, which amplifies the data received from the main data lines 506 and 508 and provides the read data from memory banks BK4 / BANK4 to the global data bus. Around time T19, the CDAE signal can return to the inactive state, which disables the data read amplifier 514.

[0071] As shown in timing diagram 700, the semiconductor memory device can receive additional read commands. The read operation can be performed in a manner similar to the read operation performed in response to read commands R0 and R4.

[0072] As shown in timing diagram 700, write operations on one set of memory banks (e.g., a subset) use different main data lines and activate different write driver enable signals than on another set of memory banks, unlike timing diagram 400, which uses the same write driver enable signal and main data lines for all write operations. Figure 7 In the example shown, write operations on memory banks BK0-3 / BANK0-3 use the main data line MIO and activate the write driver enable signal CWAE_BK03, while write operations on memory banks BK4-7 / BANK4-7 use the main data line MIO47W and activate the write driver enable signal CWAE_BK47. However, similar to that shown in timing diagram 400, read operations on all memory banks use the same main data line and activate the same data amplifier enable signal. For example, as shown... Figure 7 As shown, read operations on memory banks BK0-7 / BANK0-7 use the same main data line MIO.

[0073] Figure 8 This is a block diagram of a semiconductor memory device according to embodiments of the present disclosure. In some embodiments, semiconductor memory device 800 may be included in semiconductor memory device 100. Semiconductor memory device 800 may include memory array 802, which includes a plurality of memory banks BK0-7. In some embodiments, memory array 802 may be included in memory array 118. Memory array 802 may be coupled to read / write amplifier 804 via main data lines 806, 808, 820, and 822. In some embodiments, read / write amplifier 804 may be included in read / write amplifier 120. Read / write amplifier 804 may include write drivers 810, 812, 824, and 826, one write driver per main data line 806, 808, 820, and 822. In some embodiments, the main data lines 806, 808, 820, and 822 and the write drivers 810, 812, 824, and 826 of semiconductor memory device 800 may perform substantially the same operations as the corresponding components in semiconductor memory device 500 during write operations. In some embodiments, shielding wires 816 and 818 may be substantially the same as shielding wires 516 and 518. Therefore, no reference is provided. Figure 8 Provide a detailed description of these components.

[0074] In some embodiments, the main data lines coupled to a subset of the memory bank can receive data from the memory array during read operations, rather than just during write operations. For example, main data lines 820 and 822 can be coupled to memory bank BK4-7. During read operations, main data lines 820 and 822 can receive data from a portion of memory bank BK4-7 and supply read data to read / write amplifier 804, instead of main data lines 806 and 808. Using main data lines 820 and 822 for read operations can provide reduced current consumption for at least some read operations.

[0075] In some embodiments, the data sense amplifier 814 may be shared by two or more main data lines. For example, as Figure 8 As shown, main data lines 806 and 820 can share data sense amplifier 814, and main data lines 808 and 822 can also share data sense amplifier 814. In some embodiments, read / write amplifier 804 may include selection circuitry 828 to selectively couple main data lines to data sense amplifier 814. Figure 8 In the example shown, for each data sense amplifier 814, the selection circuit 828 may include a switch 830 for selectively coupling and decoupling main data lines 806, 808 to and from the data sense amplifier 814, and a switch 832 for selectively coupling and decoupling main data lines 820, 822 to and from the data sense amplifier 814. More generally, switch 830 may selectively couple and decouple the main data lines coupled to at least one subset of the memory banks BK0-7 of the memory array 802, and switch 832 may selectively couple and decouple the main data lines coupled to another subset of the memory banks BK0-7. Figure 8 In the example shown, main data lines 806 and 808 are coupled to at least memory bank BK0-3, and main data lines 820 and 822 are coupled to memory bank BK4-7. Switch 830 can be controlled by control signal CDAESEL_BK03, and switch 832 can be controlled by control signal CDAESEL_BK47. In some embodiments, the control signals can be provided by command decoders (such as command decoder 106) and / or column decoders (such as column decoder 110).

[0076] During a read operation corresponding to the address of memory bank BK0-3, control signal CDAESEL_BK03 can be active. In response to the active state, switch 830 can couple main data line 806 and / or main data line 808 to data sense amplifier 814. Control signal CDAESEL_BK47 can be deactivated. In response to the deactivated state, switch 832 can decouple main data lines 820 and 822 from data sense amplifier 814. Read data can be supplied from memory bank BK0-3 to data sense amplifier 814 via main data lines 806 and / or 808.

[0077] During a read operation corresponding to the address of memory bank BK4-7, control signal CDAESEL_BK03 can be inactive. In response to the inactive state, switch 830 can decouple main data lines 806 and 808 from data sense amplifier 814. Control signal CDAESEL_BK47 can be active. In response to the active state, switch 832 can couple main data lines 820 and / or 822 to data sense amplifier 814. Read data can be provided from memory bank BK4-7 to data sense amplifier 814 via main data lines 820 and / or 822.

[0078] although Figure 8 The example shown illustrates a selection circuit 828 including switches 830 and 832, but in other embodiments, the selection circuit 828 may include a single switch that selectively toggles between main data lines 806 and 820 (main data lines 808 and 822) based on the state of a control signal. Other suitable control logic for selectively coupling / decoupling to the main data lines of the data sense amplifier may also be used.

[0079] In semiconductor memory device 800, when main data lines 820 and 822 are used for both read and write operations, in some embodiments, the semiconductor memory device may include sub-amplifier 300 instead of sub-amplifier 600 because the memory bank provides data to and receives data from the same main data line. Therefore, in some embodiments, the sub-amplifiers of semiconductor memory device 800 may have a smaller layout area than the sub-amplifiers of semiconductor memory device 500. However, in some embodiments, the control logic may increase the layout requirements of semiconductor memory device 800 compared to semiconductor memory device 200 and / or semiconductor memory device 500. In some applications, for at least some of the read and write operations, the advantage of reduced current consumption may outweigh the disadvantage of increased layout area.

[0080] Figure 9This is a timing diagram of various signals within a semiconductor memory device during memory operations according to embodiments of the present disclosure. During read and write operations, the signal states within semiconductor memory device 100 and / or semiconductor memory device 800 can be reflected in timing diagram 900 and will be referenced... Figure 1 and 8 The signals described in timing diagram 900. However, timing diagram 900 can reflect more than just... Figure 1 and 8 Operation of storage devices other than the specific storage device shown.

[0081] The first row of timing diagram 900 shows the clock signal (CLK). In some examples, the clock signal may be an internal clock signal generated by an internal clock generator (such as internal clock generator 114). The second row of timing diagram 900 shows the command (CMD). In some examples, the command CMD may be received by a command decoder (such as command decoder 106). In some examples, the command CMD may be provided to the storage device by another device (such as a storage controller (not shown)). The third row of timing diagram 900 shows the column select signal (CS) provided by a column decoder (such as column decoder 110). The column select signal CS may be issued in response to the command decoder receiving the command CMD. In some embodiments, the command decoder may provide the column decoder with a signal associated with the command CMD (e.g., an internal command), and may provide the column select signal CS at least in part in response to the signal provided by the command decoder. The fourth row of timing diagram 900 shows the state of the write driver enable signal (CWAE_BK03). The write driver enable signal CWAE_BK03 can be provided to write drivers (such as write drivers 810 and 812) coupled to the main data lines, which are coupled to all banks of the memory array. The fifth row of timing diagram 900 shows the state of the write driver enable signal (CWAE_BK47). The write driver enable signal CWAE_BK47 can be provided to write drivers (such as write drivers 824 and 826) coupled to the main data lines, which are coupled to a subset of banks of the memory array. The sixth row of timing diagram 900 shows the state of the main data lines (MIO03) (such as main data lines 806 and 808) coupled to at least some banks of the memory array. The seventh row of timing diagram 900 shows the state of the main data lines (MIO47) coupled to a subset of banks of the memory array (such as main data lines 820 and 822). The eighth row of timing diagram 900 shows the state of the data amplifier enable signal (CDAE), which enables data sense amplifiers, such as data sense amplifier 814. The last few rows of timing diagram 900 show the states of switch control signals CDAESEL_BK03 and CDAESEL_BK47, which are provided to switches, such as switches 830 and 832, for selectively coupling the main data line to the data sense amplifier during read operations. In some embodiments, the enable signals CWAE_BK03, CWAE_BK47 and / or CDAE and / or control signals CDAESEL_BK03 and / or CDAESEL_BK47 may be provided by a command controller and / or a column decoder.

[0082] At or around time T0, a semiconductor memory device (e.g., semiconductor memory devices 100 and / or 800) may receive a write command W0. In some examples, the write command W0 may be received from an external device (such as a memory controller) by a command decoder 106. The write command W0 may indicate that data is to be written to memory bank BK0 of memory array 802 (and / or memory bank BK0 of memory array 118). At least in part in response to the write command W0, the write drive enable signal CWAE_BK03 may transition from an inactive (e.g., low) state to an active (e.g., high) state at or around time T1. Activating the CWAE_BK03 signal enables write drivers 810 and / or 812 to drive data on main data lines 806 and / or 808. Also at or around time T1, data to be written to memory bank BK0 / BANK0 may be provided on main data line MIO. At or around time T2, in at least a partial response to receiving a write command W0, the column decoder can provide a column select signal CS associated with the write command W0. In at least a partial response to the column select signal CS, data can be driven from the main data lines 806 and / or 808 to subamplifiers (e.g., subamplifier 300 and / or subamplifier 128), to the sense amplifier 126, and to the memory cells of memory bank BK0 / BANK0.

[0083] Around time T3, the semiconductor memory device may receive a write command W4. The write command W4 may instruct data to be written to memory banks BK4 / BANK4 of the memory array. Around time T4, the column select signal CS may transition to an inactive state. At least partially in response to the write command W4, the write drive enable signal CWAE_BK47 may transition to an active state, and CWAE_BK03 may transition to an inactive state. Activating the CWAE_BK47 signal enables write drivers 824 and 826, and deactivating the CWAE_BK03 signal disables write drivers 810 and 812. Around time T5, the data to be written to memory banks BK4 / BANK4 may be provided on the main data line MIO47W (e.g., main data lines 820 and / or 822). Around time T6, at least partially in response to receiving the write command W4, the column decoder may provide the column select signal CS associated with the write command W4 until around time T7. At least in part in response to the column select signal CS, data can be driven from the main data line MIO47W to subamplifiers 300 and / or 128, to the sense amplifier 126, and to the memory cells of memory bank BK4 / BANK4. At or around time T8, the CWAE_BK47 signal can transition to an inactive state (e.g., low), which disables write drivers 824 and 826.

[0084] As shown in timing diagram 900, the semiconductor memory device can receive additional write commands. Write operations to BK0-3 / BANK0-3 can be performed in a manner similar to write operations performed in response to write command W0, and write operations to BK4-7 / BANK4-7 can be performed in a manner similar to write operations performed in response to write command W4.

[0085] Around time T9, the command decoder may receive a read command R0. Read command R0 may indicate that data should be read from memory bank BK0 / BANK0 of the memory array. Around time T10, CWAE_BK03 may transition to an inactive state, which may disable write drivers 810, 812. Around time T11, at least in part in response to read command R0, the column decoder may provide a column selection signal CS associated with read command R0. Also around time T11, the switch control signal CDAESEL_BK03 may transition to an active state (e.g., high). Activating the CDAESEL_BK03 signal may cause a switch (e.g., switch 830) and / or other control logic to couple main data lines 806 and / or 808 to data sense amplifier 814. In at least a partial response to the column select signal CS, at or before time T12, data in the memory cells of memory bank BK0 / BANK0 can be provided on the main data line MIO (e.g., main data lines 806 and / or 808).

[0086] Also around time T12, the command decoder can receive the read command R4. The read command R4 indicates that data should be read from memory bank BK4 / BANK4 of the memory array. Around time T13, the column select signal CS can switch to an inactive state. Around time T14, the data amplifier enable signal CDAE can switch to an active state (e.g., high). The CDAE signal enables the data readout amplifier 814, which amplifies the data received from the main data lines 806, 808 and provides the read data from memory bank BK0 / BANK0 to the global data bus. Around time T15, the CDAE signal can return to an inactive state (e.g., low), which disables the data readout amplifier 814. Around time T16, at least in part in response to the read command R4, the column select signal CS associated with the read command R4 can be provided. At least partially in response to the column select signal CS, CDAESEL_BK03 can transition to an inactive (e.g., low) state, which can cause switches or other logic circuitry to decouple main data lines 806 and / or 808 from data sense amplifier 814 at or around time T16. Furthermore, at least partially in response to the column select signal CS, at or around time T16, the switch control signal CDAESEL_BK47 can transition from an inactive state to an active state, which can cause switches (e.g., switch 832) or other logic circuitry to couple main data lines 820 and / or 822 to data sense amplifier 814. Further, at least partially in response to the column select signal CS, data from memory cells of memory bank BK4 / BANK4 can be provided on main data line MIO at or around time T17. At or around time T18, the column select signal CS can transition to an inactive state. At or around time T19, the data amplifier enable signal CDAE can transition to an active state. The CDAE signal enables the data sense amplifier 814, which amplifies the data received from the main data lines 820 and 822 and provides read data from memory banks BK4 / BANK4 to the global data bus. Around time T20, the CDAE signal can return to an inactive state, which disables the data sense amplifier 814. Around time T21, the CDAESEL_BK47 signal can transition to an inactive state, causing the main data lines 520 and / or 522 to decouple from the data sense amplifier 814.

[0087] As shown in timing diagram 900, the semiconductor memory device can receive additional read commands. Read operations on memory banks BK0-3 / BANK0-3 can be performed in a manner similar to those performed in response to read command R0, and read operations on memory banks BK4-7 / BANK4-7 can be performed in a manner similar to those performed in response to read command R4.

[0088] As shown in timing diagram 900, similar to timing diagram 700, write operations on one set of memory banks use different main data lines and activate different write driver enable signals compared to write operations on another set of memory banks. Figure 9 In the example shown, write operations on memory banks BK0-3 / BANK0-3 use the main data line MIO03 and activate the write driver enable signal CWAE_BK03, while write operations on memory banks BK4-7 / BANK4-7 use the main data line MIO47 and activate the write driver enable signal CWAE_BK47. When read operations on all memory banks activate the same data amplifier enable signal, additional control signals are used to couple different main data lines to the data amplifier enable signal. Read operations on one set of memory banks activate different control signals than read operations on another set of memory banks. Figure 9 In the example shown, the read operation activation switch control signal CDAESEL_BK03 is used for memory bank BK0-3 / BANK0-3, while the read operation activation switch control signal CDAESEL_BK47 is used for memory bank BK4-7 / BANK4-7.

[0089] Therefore, in comparison Figure 9 and 7 Compared to Figure 4, in some embodiments, using separate main data lines for different memory banks for read and / or write operations allows for the use of more enable and / or control signals compared to using the same main data line for all memory banks for read and write operations. However, in some applications, the disadvantages of additional signal lines and the current requirements for providing additional signals may still be offset by the advantage of reducing the current consumption of at least some read and / or write operations.

[0090] As disclosed herein, a separate main data line can be used to provide data to different banks of a memory array for write and / or read operations. In some applications, using different main data lines for different banks can reduce memory current consumption during memory operations.

[0091] Of course, it should be understood that any of the examples, embodiments or processes described herein may be combined with one or more other examples, embodiments and / or processes, or may be separated and / or performed between separate devices or device parts, in accordance with this system, apparatus and method.

[0092] Finally, the foregoing discussion is intended only to illustrate the apparatus, system, and method of the present invention and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the apparatus, system, and method of the present invention have been described in particular detail with reference to exemplary embodiments, it should be understood that those skilled in the art can devise many modifications and alternative embodiments without departing from the broader and contemplated spirit and scope of the invention as set forth in the following claims. Accordingly, the specification and drawings are to be considered illustrative and are not intended to limit the scope of the appended claims.

Claims

1. A memory device comprising: a memory array comprising a plurality of memory banks, wherein each of the plurality of memory banks contains a plurality of mats, each mat containing a respective first mat; a first plurality of main data lines, each of the first plurality of main data lines coupled to at least a first subset of the plurality of memory banks, and each of the first plurality of main data lines configured to receive read data and provide write data to the first subset of the plurality of memory banks, wherein the first plurality of main data lines contains a first main data line; a second plurality of main data lines, each of the second plurality of main data lines coupled to a second subset of the plurality of memory banks, and each of the second plurality of main data lines configured to provide write data to the second subset of the plurality of memory banks, wherein a length of the second plurality of main data lines is less than a length of the first plurality of main data lines, wherein each of the first plurality of main data lines is further coupled to the second subset of the plurality of memory banks, and each of the first plurality of main data lines is further configured to receive read data from the second subset of the plurality of memory banks, wherein the second plurality of main data lines contains a second main data line, wherein the first main data line is configured to write data only to the respective first mat of the first subset of the plurality of memory banks, and wherein the second main data line is configured to write data only to the respective first mat of the second subset of the plurality of memory banks; a plurality of local data lines; a plurality of sub-amplifiers coupled between the plurality of local data lines and the first and second plurality of main data lines; a plurality of bit lines coupled to memory cells of the memory array; a plurality of sense amplifiers coupled between the local data lines and the bit lines; a global data bus coupled to the first and second plurality of main data lines; and input / output circuitry coupled to the global data bus.

2. The memory device of claim 1, wherein each of the second plurality of main data lines is further configured to receive read data from the second subset of the plurality of memory banks.

3. The memory device of claim 2, further comprising selection circuitry configured to selectively couple each of the first plurality of main data lines and each of the second plurality of main data lines to a corresponding data sense amplifier of a plurality of data sense amplifiers.

4. The memory device of claim 1, further comprising: a first plurality of write drivers coupled between the first plurality of main data lines and the global data bus, and enabled by a first write enable signal; and a second plurality of write drivers coupled between the second plurality of main data lines and the global data bus, and enabled by a second write enable signal.

5. The memory device of claim 1, wherein each of the first plurality of main data lines and each of the second plurality of main data lines are arranged in an alternating pattern over the memory array.

6. The memory device of claim 5, wherein the device further comprises a shield line aligned with the second plurality of main data lines extending over the first subset of the plurality of memory banks.

7. A memory device comprising: a memory array comprising a plurality of memory banks, wherein each of the plurality of memory banks contains a plurality of mats, each mat containing a respective first mat; a first plurality of main data lines, each of the first plurality of main data lines coupled to the plurality of memory banks and configured to receive read data from the plurality of memory banks, wherein the first plurality of main data lines contains a first main data line; a second plurality of main data lines, each of the second plurality of main data lines coupled to a subset of the plurality of memory banks and configured to provide write data to the subset of the plurality of memory banks, wherein each of the first plurality of main data lines is further configured to provide the write data to a remaining set of the plurality of memory banks, wherein the remaining set of the plurality of memory banks does not include the subset of the plurality of memory banks, wherein the second plurality of main data lines contains a second main data line, wherein the second main data line is configured to only write data to the respective first mat of the subset of the plurality of memory banks, and wherein the first main data line is configured to only write data to the respective first mat of the remaining set of the plurality of memory banks; a plurality of local data lines; a plurality of sub-amplifiers coupled between the plurality of local data lines and the first and second plurality of main data lines; a plurality of bit lines coupled to memory cells of the memory array; a plurality of sense amplifiers coupled between the local data lines and the bit lines; a global data bus coupled to the first and second plurality of main data lines; and input / output circuitry coupled to the global data bus.

8. The memory device of claim 7, further comprising a read / write amplifier coupled to the first and second plurality of main data lines, the read / write amplifier further coupled to the global data bus, wherein the remaining set of the plurality of memory banks is further from the read / write amplifier than the subset of the plurality of memory banks.

9. The memory device of claim 7, wherein each of the sub-amplifiers comprises: a first transistor having a first node coupled to a local data line of the plurality of local data lines and a second node coupled to a main data line of the second plurality of main data lines; and a second transistor having a first node coupled to a main data line of the first plurality of main data lines and a second node coupled to a third transistor. ​ 10. The memory device of claim 9, wherein the plurality of local data lines provide the write data to and provide read data from the subset of the plurality of memory banks.

11. The memory device of claim 9, wherein the sub-amplifiers are configured to couple the main data lines of the first plurality of main data lines to the local data lines during a read operation and to couple the main data lines of the second plurality of main data lines to the local data lines during a write operation.

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