Semiconductor memory device and control method of semiconductor memory device

Abstract

Embodiments of the present invention provide a semiconductor memory device capable of improving processing power and a control method for the semiconductor memory device. The semiconductor memory device of the embodiment includes a plurality of first memory cells (MT), word lines (WL), and a control circuit (17). In the first programming cycle of the first mode, after performing the first programming by applying a first voltage (VSV) to the word line, the control circuit (17) boosts the second voltage (VCG_SV) applied to the word line (WL) while repeatedly performing the first verification until the number of disconnected cells of the first memory cells falls below a threshold. Based on the first voltage (VSV) and the number of times the first verification is repeated, a third voltage (VPGM_SV) is determined. In the first second programming cycle of the second mode, the third voltage (VPGM_SV) is applied to the word line (WL) to perform the second programming.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on August 2, 2017, with application number 201710651020.9 and title "Semiconductor Memory Device and Memory System".

[0003] [Related Applications]

[0004] This application claims priority to Japanese Patent Application No. 2017-42499 (filed on March 7, 2017). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0005] Embodiments of the present invention relate to a semiconductor memory device and a memory system. Background Technology

[0006] As a semiconductor memory device, NAND (Not AND) type flash memory is known. Summary of the Invention

[0007] The embodiments of the present invention provide a semiconductor memory device and memory system that can improve processing power.

[0008] The semiconductor memory device of the embodiment includes: a first memory cell group including a plurality of first memory cells; word lines commonly connected to the plurality of first memory cells; and control circuitry controlling a write operation, the write operation having a first mode of repeatedly performing a first programming cycle including a first programming and a first verification, and a second mode of repeatedly performing a second programming cycle including a second programming and a second verification. When the control circuitry executes the first and second modes sequentially, in the first programming cycle, after performing first programming by applying a first voltage to the word lines, it repeatedly performs first verification while increasing the second voltage applied to the word lines until the number of disconnected cells of the first memory cells becomes below a threshold. Based on the first voltage and the number of times the first verification is repeated, a third voltage lower than the first voltage is determined. In the first second programming cycle, after performing second programming by applying a third voltage to the word lines, a fourth voltage lower than the second voltage is applied to the word lines to perform second verification. Attached Figure Description

[0009] Figure 1 This is a block diagram of the memory system according to the first embodiment.

[0010] Figure 2 This is a block diagram of the semiconductor memory device according to the first embodiment.

[0011] Figure 3This is a circuit diagram of the memory cell array included in the semiconductor memory device of the first embodiment.

[0012] Figure 4 This is a cross-sectional view of the memory cell array included in the semiconductor memory device of the first embodiment.

[0013] Figure 5 This is a block diagram of the readout amplifier module included in the semiconductor memory device of the first embodiment.

[0014] Figure 6 This is a threshold distribution diagram of the memory cell transistors included in the semiconductor memory device of the first embodiment.

[0015] Figure 7 This is an explanatory diagram of the sampling mode in the semiconductor memory device according to the first embodiment.

[0016] Figure 8 It is the offset table provided by the semiconductor memory device of the first embodiment.

[0017] Figure 9 This is a flowchart illustrating the write operation in the semiconductor memory device of the first embodiment.

[0018] Figure 10 This is a flowchart illustrating the write operation in the semiconductor memory device of the first embodiment.

[0019] Figure 11 This is a timing diagram showing the voltage of the select word line during a write operation in the semiconductor memory device of the first embodiment.

[0020] Figure 12 This is a timing diagram showing the voltage of the select word line during a write operation in the semiconductor memory device of the first embodiment.

[0021] Figure 13 This is a flowchart illustrating the writing process in the semiconductor memory device of the first example of the second embodiment.

[0022] Figure 14 This is a flowchart illustrating the writing process in the semiconductor memory device of the second example of the second embodiment.

[0023] Figure 15 This is a flowchart illustrating the writing process in the semiconductor memory device of the third example of the second embodiment.

[0024] Figure 16 This is a cross-sectional view of the NAND string in the fourth example of the second embodiment of the semiconductor memory device.

[0025] Figure 17This is a flowchart illustrating the writing process in the semiconductor memory device of the fourth example of the second embodiment.

[0026] Figure 18 This is a flowchart illustrating the write operation in the memory system of the third embodiment.

[0027] Figure 19 This is a timing diagram showing the instruction sequence in the case where the controller of the memory system in the third embodiment does not specify a register.

[0028] Figure 20 This is a timing diagram showing the instruction sequence in the case of the controller designation register provided by the memory system of the third embodiment.

[0029] Figure 21 This is a flowchart illustrating the write operation in the memory system of the fourth embodiment.

[0030] Figure 22 This is an explanatory diagram showing the sampling mode in the semiconductor memory device of the first variation example. Detailed Implementation

[0031] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In this description, common reference numerals will be used to label common parts in all drawings.

[0032] 1. First Implementation Method

[0033] The semiconductor memory device and memory system according to the first embodiment will be described. Hereinafter, a three-dimensional stacked NAND flash memory formed by stacking memory cell transistors on a semiconductor substrate will be used as an example for description as a semiconductor memory device.

[0034] 1.1 Regarding the composition

[0035] 1.1.1 Overall Structure of the Memory System

[0036] First, use Figure 1 The overall configuration of the memory system in this embodiment will be described.

[0037] like Figure 1 As shown, the memory system 1 includes a NAND flash memory 100 and a controller 200. The controller 200 and the NAND flash memory 100 can be combined to form a semiconductor storage device, for example, a memory card such as an SDTM card or an SSD (solid state drive).

[0038] The NAND flash memory 100 has multiple memory cell transistors and stores data non-volatilely. The NAND flash memory 100 is connected to the controller 200 via a NAND bus and operates based on commands from the controller 200. More specifically, the NAND flash memory 100 transmits and receives, for example, 8-bit input / output (I / O) signals with the controller 200 via data lines DQ0 to DQ7. The I / O signals include, for example, data, address, and instruction signals. Additionally, the NAND flash memory 100 receives, for example, a chip enable signal CEn, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from the controller 200. Furthermore, the NAND flash memory 100 sends a ready / busy signal R / Bn to the controller 200.

[0039] The chip enable signal CEn is used to enable the NAND flash memory 100, and is activated, for example, at a Low ("L") level. The instruction latch enable signal CLE indicates that the input / output signal I / O is an instruction, and is activated, for example, at a High ("H") level. The address latch enable signal ALE indicates that the input / output signal I / O is an address, and is activated, for example, at an "H" level. The write enable signal WEn is used to input received signals into the NAND flash memory 100, and is activated, for example, at a "L" level whenever instructions, addresses, or data are received from the controller 200. Therefore, whenever WEn is toggled, input / output signals I / O are input into the NAND flash memory 100. The read enable signal REn is used to enable the controller 200 to read data from the NAND flash memory 100. The read enable signal REn is activated, for example, at a "L" level. The ready / busy signal R / Bn is a signal that indicates whether the NAND flash memory 100 is in a busy state (whether it is able to receive instructions from the controller 200 or not). For example, when the NAND flash memory 100 is in a busy state, it is set to the "L" level.

[0040] The controller 200 responds to commands from the host device 2, instructing the NAND flash memory 100 to perform data reading, writing, deletion, etc. Additionally, the controller 200 manages the memory space of the NAND flash memory 100.

[0041] The controller 200 includes a host interface circuit 210, an internal memory (RAM) 220, a processor (CPU) 230, a buffer memory 240, a NAND interface circuit 250, and an ECC circuit 260.

[0042] The host interface circuit 210 is connected to the host device 2 via the controller bus and is responsible for communication with the host device 2. The host interface circuit 210 transmits commands and data received from the host device 2 to the processor 230 and the buffer memory 240. In addition, the host interface circuit 210 transmits data in the buffer memory 240 to the host device 2 in response to commands from the processor 230.

[0043] The NAND interface circuit 250 is connected to the NAND flash memory 100 via the NAND bus and is responsible for communication with the NAND flash memory 100. The NAND interface circuit 250 transmits commands received from the processor 230 to the NAND flash memory 100. Furthermore, during write operations, the NAND interface circuit 250 transfers write data from the buffer memory 240 to the NAND flash memory 100. Conversely, during read operations, the NAND interface circuit 250 transfers data read from the NAND flash memory 100 to the buffer memory 240.

[0044] Processor 230 controls the operation of the entire controller 200. For example, when processor 230 receives a write command from host device 2, it responds by outputting the write command to NAND flash memory 100. The same applies to read and delete operations. Furthermore, processor 230 performs various processes, such as wear averaging, to manage NAND flash memory 100. Moreover, processor 230 performs various operations. For example, processor 230 performs data encryption or randomization processes.

[0045] ECC circuit 260 performs error correction (ECC: Error Checking and Correcting) processing on the data.

[0046] The built-in memory 220 is, for example, a semiconductor memory such as DRAM (Dynamic Random Access Memory), and is used as the operating area of ​​the processor 230. Furthermore, the built-in memory 220 stores firmware and various management tables used to manage the NAND flash memory 100.

[0047] 1.1.2 Regarding the composition of semiconductor memory devices

[0048] Next, use Figure 2 The configuration of the NAND flash memory 100 will be described.

[0049] like Figure 2As shown, the NAND flash memory 100 includes a memory cell array 11, a sense amplifier module 12, a line decoder 13, an input / output circuit 14, a register 15, a logic control circuit 16, a sequencer 17, a ready / busy control circuit 18, and a voltage generation circuit 19. Furthermore, in Figure 2 In the example, to simplify the explanation, a portion of the connection between the blocks is shown.

[0050] The memory cell array 11 contains blocks BLK0 to BLKn (n is a natural number greater than or equal to 1). A block BLK is a collection of multiple non-volatile memory cell transistors associated with bit lines and word lines. Each memory cell transistor can store multiple bits of data using an MLC (Multi-Level Cell) method.

[0051] The readout amplifier module 12 outputs the data DAT read from the memory cell array 11 to the controller 200 via the input / output circuit 14. In addition, the readout amplifier module 12 transmits the write data DAT received from the controller 200 via the input / output circuit 14 to the memory cell array 11.

[0052] Additionally, the sense amplifier module 12 includes a counter CT and multiple sense amplifier units (not shown) disposed on each bit line. The counter CT counts the number of disconnected units of the read data, that is, the number of memory cell transistors in the disconnected state, and transmits the count result to the sequencer 17. Details regarding the sense amplifier module 12 will be described below.

[0053] The line decoder 13 selects the word lines corresponding to the memory cell transistors that perform read and write operations. Furthermore, the line decoder 13 applies the required voltages to the selected word lines and the non-selected word lines, respectively.

[0054] The input / output circuit 14 transmits and receives, for example, 8-bit input / output signals (I / O0 to I / O7) with the controller 200 via data lines DQ0 to DQ7. For example, the input / output circuit 14 transmits the write data DAT contained in the input / output signal I / O received from the controller 200 to the sense amplifier module 12. In addition, the input / output circuit 14 sends the sense data DAT transmitted from the sense amplifier module 12 as an input / output signal I / O to the controller 200.

[0055] Register 15 includes a status register 15A, an address register 15B, and an instruction register 15C. Status register 15A stores status information STS. Additionally, status register 15A transmits the status information STS to input / output circuit 14 according to the instructions of sequencer 17. Address register 15B receives address ADD from input / output circuit 14 and stores it. Furthermore, address register 15B transmits the column address CA and row address RA contained in address ADD to sense amplifier module 12 and row decoder 13, respectively. Instruction register 15C receives instruction CMD from input / output circuit 14 and stores it. Furthermore, instruction register 15C transmits instruction CMD to sequencer 17.

[0056] The logic control circuit 16 receives the chip enable signal CEn, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn from the controller 200, and controls the input / output circuit 14 and the sequencer 17 according to these control signals.

[0057] The sequencer 17 controls the operation of the entire NAND flash memory 100. Specifically, the sequencer 17 controls the read amplifier module 12, the line decoder 13, and the voltage generation circuit 19, etc., based on the instruction CMD transmitted from the instruction register 15C, to perform data writing and reading operations. The sequencer 17 can sample the programming voltage during the writing operation and calculate the offset value of the programming voltage based on the result. The programming voltage refers to the voltage applied to the select word line when writing data. The operation of calculating the offset value will be explained below.

[0058] Additionally, the sequencer 17 includes a register REG. Register REG, for example, has a table (hereinafter referred to as the "offset table") relating to the offset values ​​of the programming voltage. The sequencer 17 refers to the offset table to set the optimal programming voltage. Furthermore, the offset table can be rewritten via parameter write operations, such as setting a feature.

[0059] The ready / busy control circuit 18 generates a ready / busy signal R / Bn based on the operating state of the sequencer 17 and sends the signal to the controller 200. The ready / busy signal R / Bn is generated by the ready / busy control circuit 18 controlling the switching on / off of the transistor Tr connected to its output.

[0060] The voltage generation circuit 19 generates various voltages based on the instructions of the sequencer 17. Furthermore, the voltage generation circuit 19 supplies the generated voltages to the memory cell array 11, the sense amplifier module 12, and the line decoder 13, etc.

[0061] 1.1.3 Regarding the composition of the memory cell array

[0062] Next, use Figure 3 The configuration of the storage cell array 11 will be described. Figure 3 The example represents block BLK0, but the composition of other blocks BLK is the same.

[0063] like Figure 3 As shown, block BLK0 contains, for example, four string cells SU (SU0 to SU3). Furthermore, the number of string cells SU contained in one block BLK is arbitrary. Each string cell SU contains multiple NAND strings 20. Each NAND string 20 contains, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2. Hereinafter, without limiting the memory cell transistors MT0 to MT7, they will be referred to as memory cell transistors MT. The memory cell transistor MT has a control gate and a charge storage layer, and non-volatilely stores data.

[0064] Furthermore, the memory cell transistor MT can be a MONOS type with an insulating film used in the charge storage layer, or an FG type with a conductive layer used in the charge storage layer. In this embodiment, the MONOS type will be used as an example for explanation. Additionally, the number of memory cell transistors MT is not limited to 8; it can be 16, 32, 64, 128, etc., and the number is not limited. Furthermore, the number of transistors ST1 and ST2 can be arbitrary, as long as there is one or more of each.

[0065] The memory cell transistor MT is connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2. More specifically, the current paths of memory cell transistors MT0 to MT7 are connected in series. Furthermore, the drain of memory cell transistor MT7 is connected to the source of select transistor ST1, and the source of memory cell transistor MT0 is connected to the drain of select transistor ST2.

[0066] The gates of the selection transistors ST1 in each of the string units SU0 to SU3 are connected to the selection gate lines SGD0 to SGD3, respectively. Similarly, the gates of the selection transistors ST2 in each of the string units SU0 to SU3 are connected to the selection gate lines SGS0 to SGS3, respectively. Hereinafter, selection gate lines SGD0 to SGD3 are not limited to selection gate lines SGD, and selection gate lines SGS0 to SGS3 are not limited to selection gate lines SGS. Furthermore, the selection gate lines SGS0 to SGS3 of each string unit SU can also be connected in a common manner.

[0067] The control gates of the memory cell transistors MT0 to MT7 located in block BLK are all connected to word lines WL0 to WL7. Hereinafter, word lines WL0 to WL7 will not be limited to word lines WL.

[0068] The drains of the select transistors ST1 of each NAND string 20 located within the string cell SU are connected to different bit lines BL0 to BL(L-1) (where L is an integer greater than or equal to 2). Hereinafter, without limitation, bit lines BL0 to BL(L-1) are referred to as bit lines BL. Each bit line BL is connected in a common manner to one NAND string 20 located within each string cell SU across multiple blocks BLK. Furthermore, the sources of multiple select transistors ST2 are connected in a common manner to the source line SL. In other words, the string cell SU is a collection of NAND strings 20 connected to different bit lines BL and connected to the same select gate lines SGD and SGS. Additionally, a block BLK is a collection of multiple string cells SU that share the word line WL. Furthermore, the memory cell array 11 is a collection of multiple blocks BLK that share the bit line BL.

[0069] Data write and read operations are performed comprehensively on the memory cell transistors MT connected to any word line WL in any string cell SU. Hereinafter, the group of memory cell transistors MT selected comprehensively during data write and read operations is called a "memory cell group MCG". Furthermore, the set of 1 bit of data written to or read from one memory cell group MCG is called a "page".

[0070] Data deletion can be performed in blocks (BLKs) or smaller. Deletion is described, for example, in U.S. Patent Application No. 13 / 235,389, entitled "Non-Volatile Semiconductor Memory Device," filed September 18, 2011. It is also described in U.S. Patent Application No. 12 / 694,690, entitled "Non-Volatile Semiconductor Storage Device," filed January 27, 2010. Furthermore, it is described in U.S. Patent Application No. 13 / 483,610, entitled "Non-Volatile Semiconductor Memory Device and Data Erase Method Thereof," filed May 30, 2012. The entire contents of these patent applications are incorporated herein by reference.

[0071] Furthermore, the configuration of the memory cell array 11 can also be other configurations. That is, the configuration of the memory cell array 11 is described, for example, in U.S. Patent Application No. 12 / 407,403 entitled "Three-dimensional stacked non-volatile semiconductor memory" filed on March 19, 2009. Additionally, U.S. Patent Application No. 12 / 406,524, entitled "Three-dimensional stacked non-volatile semiconductor memory," filed March 18, 2009; U.S. Patent Application No. 12 / 679,991, entitled "Non-volatile semiconductor memory device and method of manufacturing the same," filed March 25, 2010; and U.S. Patent Application No. 12 / 532,030, entitled "Semiconductor memory and method of manufacturing the same," filed March 23, 2009, are also described herein. The entire contents of these patent applications are incorporated herein by reference.

[0072] 1.1.4 Cross-sectional configuration of the memory cell array

[0073] Next, use Figure 4 The cross-sectional configuration of the storage cell array 11 will be described. Figure 4 The examples show the cross-sections of string units SU0 and SU1, and the structures of string units SU2 and SU3 are also the same. Furthermore, in Figure 4 The interlayer insulating film is omitted.

[0074] like Figure 4 As shown, a plurality of source line contacts LI are provided along a first direction D1 parallel to the semiconductor substrate 30 and extending along a second direction D2 perpendicular to the first direction D1. A string cell SU is arranged between two source line contacts LI. The source line contacts LI connect the semiconductor substrate 30 to a source line SL (not shown) disposed above the NAND string 20. Furthermore, the arrangement of the source line contacts LI and the NAND string 20 can be arbitrarily set. For example, multiple string cells SU can be arranged between two source line contacts LI. Furthermore, in Figure 4In the example, for the sake of simplicity, the case where multiple NAND strings 20 are arranged in a column along the second direction D2 in a single string unit SU is shown. The arrangement of the NAND strings 20 in a single string unit SU can be arbitrarily set. For example, they can be arranged side by side in two columns along the second direction D2, or they can be arranged in a zigzag configuration of four columns.

[0075] In each string cell SU, the NAND string 20 is formed along a third direction D3 perpendicular to the semiconductor substrate 30. More specifically, an n-type well 31 is formed in the surface region of the semiconductor substrate 30. Furthermore, a p-type well 32 is formed in the surface region of the n-type well 31. Additionally, an n-type well 32 is formed in a portion of the surface region of the p-type well 32. + A p-type diffusion layer 33. Furthermore, above the p-type well 32, ten wiring layers 34, which function as select gate line SGS, word line WL, and select gate line SGD, are sequentially deposited via interlayer insulating films (not shown).

[0076] Furthermore, a pillar-shaped semiconductor layer 35 is formed, penetrating the 10 wiring layers 34 and reaching the p-type well 32. A tunneling insulating film 36, a charge storage layer 37, and a barrier insulating film 38 are sequentially formed on the side of the semiconductor layer 35. The semiconductor layer 35 is, for example, made of polysilicon. The tunneling insulating film 36 and the barrier insulating film 38 are, for example, made of silicon oxide. The charge storage layer 37 is, for example, made of silicon nitride. Hereinafter, the pillar formed by the semiconductor layer 35, the tunneling insulating film 36, the charge storage layer 37, and the barrier insulating film 38 will be referred to as the "memory pillar MP". The semiconductor layer 35 functions as a current path for the NAND string 20 and serves as a channel for forming each transistor. Furthermore, the upper end of the semiconductor layer 35 is connected to a wiring layer (not shown) that functions as a bit line BL. The memory pillar MP and the wiring layer 34 form the memory cell transistor MT, and the select transistors ST1 and ST2.

[0077] exist Figure 4 In this example, the diameter of the upper surface (opening) of the memory pillar MP is larger than the diameter of the bottom surface that contacts the semiconductor substrate 30. Furthermore, the side surface of the memory pillar MP is tilted at an angle of 90 degrees or less relative to the plane of the semiconductor substrate 30 (hereinafter, this shape is referred to as a "conical shape"). In this case, corresponding to the shape of the memory pillar MP, the cell size of the memory cell transistors MT (MT0 to MT7) on each wiring layer 34 (layer) is different. More specifically, in Figure 4 In the example, the cell size of memory cell transistor MT0 becomes the smallest, and the cell size of memory cell transistor MT7 becomes the largest.

[0078] If the cell sizes are different, then there may be cases where the optimal value of the programming voltage applied to the select word line WL during a write operation is different.

[0079] Furthermore, the shape of the memory cylinder MP is not limited to a conical shape. For example, the memory cylinder MP can be a cylinder with the same diameter at the top and bottom surfaces, and the diameter of the bottom surface can also be larger than the diameter of the top surface.

[0080] Furthermore, in Figure 4 In this example, the wiring layer 34, which serves as the selection gate line SGD and SGS, is provided with one layer, but multiple layers can also be provided.

[0081] The source line contact LI has a line shape along the second direction D2. The source line contact LI is made of polysilicon, for example. Furthermore, the bottom surface of the source line contact LI is connected to n. + The diffusion layer 33 has its upper surface connected to the wiring layer (not shown) that functions as the source line SL.

[0082] 1.1.5 Composition of the Readout Amplifier Module

[0083] Next, use Figure 5 The configuration of the readout amplifier module 12 will be explained. Figure 5 This is the circuit diagram for the readout amplifier module 12. (Example) Figure 5 As shown, the sense amplifier module 12 includes sense amplifier units SAU (SAU0 to SAU(L-1)) disposed on each bit line BL.

[0084] Each sense amplifier unit (SAU) is connected to the counter (CT) in a manner that enables data transmission and reception. Furthermore, each sense amplifier unit (SAU) includes a sense circuit (SA), latch circuits (SDL, ADL, BDL, CDL, and XDL). These sense circuits (SA, SDL, ADL, BDL, CDL, and XDL) are connected to each other in a manner that enables data transmission and reception.

[0085] During a read operation, the read circuit SA reads the data that has been read to the corresponding bit line BL and determines whether the read data is "0" or "1". Conversely, during a write operation, a voltage is applied to the bit line BL based on the data stored in the latch circuit SDL.

[0086] The latch circuits SDL, ADL, BDL, and CDL temporarily store read and written data. For example, the ADL, BDL, and CDL are used for multi-value operations where each memory cell transistor stores more than 2 bits of data. Furthermore, the number of latch circuits can be arbitrarily set, for example, based on the amount of data (number of bits) that the memory cell transistor can store.

[0087] A latch circuit XDL is provided in each sense amplifier unit (SAU) and is used for inputting and outputting data between the sense amplifier unit (SAU) and the controller 200. Data received from the controller 200 is transmitted via the latch circuit XDL to latch circuits SDL, ADL, BDL, or CDL. Additionally, data from latch circuits SDL, ADL, BDL, and CDL is transmitted to the controller 200 via the latch circuit XDL.

[0088] 1.2 Threshold distribution of memory cell transistors

[0089] Next, use Figure 6 The threshold distribution obtainable by the memory cell transistor MT in this embodiment will be described. Hereinafter, this embodiment will describe the case where the memory cell transistor MT can store 4 bits (2 bits) of data, but the data that can be stored is not limited to 4 bits. In this embodiment, the memory cell transistor MT can also store, for example, 8 bits (3 bits) of data, as long as it can store 4 bits (2 bits) or more of data.

[0090] like Figure 6 As shown, the threshold voltage of each memory cell transistor MT takes a discrete value from one of four distributions. These four distributions are named "Er" level, "A" level, "B" level, and "C" level in ascending order of threshold value.

[0091] The "Er" level, for example, corresponds to the data deletion state. Furthermore, the threshold voltage included in the "Er" level is less than the voltage VCG_AV and can have either a positive or negative value.

[0092] The “A” through “C” levels correspond to the state where charge is injected into the charge storage layer and data is written. The threshold voltages included in each distribution have, for example, positive values. The threshold voltage included in the “A” level is above VCG_AV and below VCG_BV (where VCG_BV > VCG_AV). The threshold voltage included in the “B” level is above VCG_BV and below VCG_CV (where VCG_CV > VCG_BV). The threshold voltage included in the “C” level is above VCG_CV and below VREAD and VPASS (VREAD (or VPASS) > VCG_CV). Furthermore, VREAD and VPASS are the voltages applied to the non-select bit line WL during data read and write operations, respectively.

[0093] As described above, each memory cell transistor MT has any one of four threshold distributions, thus yielding four states. These states are assigned in binary notation from "00" to "11", allowing each memory cell transistor MT to store 2 bits of data. Hereinafter, these 2 bits of data will be referred to as the upper bit and the lower bit, respectively. Furthermore, the set of upper bits that are written (or read) in total within the memory cell group MCG is called the upper page, and the set of lower bits is called the lower page.

[0094] In addition, Figure 6 The example provided illustrates a discrete distribution of four voltage levels, but this distribution represents an ideal state, such as immediately after data is written. Therefore, in reality, adjacent voltage levels may overlap. For instance, after data is written, interference may cause the upper end of the "Er" level to overlap with the lower end of the "A" level. In such cases, data correction techniques, such as ECC, are used.

[0095] 1.3 Write Action

[0096] Next, the write operation will be explained. The write operation generally includes programming and programming verification. And, by repeatedly performing the combination of programming and programming verification (hereinafter referred to as the "programming loop"), the threshold voltage of the memory cell transistor MT is raised to the target level.

[0097] Programming refers to the action of increasing the threshold voltage by injecting electrons into the charge storage layer (or maintaining the threshold voltage by disabling injection). Hereinafter, the action of increasing the threshold voltage will be referred to as "0" writing. Conversely, the action of maintaining the threshold voltage will be referred to as "1" writing or "disabling writing".

[0098] Programming verification involves reading the data after programming and determining whether the threshold voltage of the memory cell transistor MT has reached the target level. Hereinafter, the case where the threshold voltage of the memory cell transistor MT reaches the target level will be referred to as "verification passed," and the case where the target level is not reached will be referred to as "verification failed."

[0099] The write operation in this embodiment has two modes, referred to as "normal mode" and "sampling mode". The sequencer 17 selects the sampling mode when optimizing the programming voltage applied to the word line WL. Hereinafter, the initial value of the programming voltage is denoted as VPGM, and the optimized programming voltage is denoted as VPGM_SV.

[0100] Normal mode is the typical write sequence, repeatedly performing a programming loop and writing data. In the first programming iteration of normal mode, the voltage VPGM_SV is used as the programming voltage optimized in sampling mode. Each subsequent programming loop increases the programming voltage. Hereinafter, the boosted voltage in normal mode will be denoted as DVP.

[0101] Sampling mode is a write sequence used to determine the optimal programming voltage. Hereinafter, the write operation in sampling mode will be simply referred to as "sampling". In sampling mode, programming is performed using a voltage higher than the programming voltage applied in the first programming cycle of normal mode. Hereinafter, the programming voltage applied to the select word line WL in the first programming cycle of sampling mode will be denoted as VSV. Voltages VSV, VPGM, and VPGM_SV are related as VSV > VPGM_SV > VPGM. For example, voltage VSV is a high voltage such that the threshold voltage offset of the memory cell transistor MT changes from the "Er" level to the "B" level during a single programming operation. Furthermore, the optimization of the programming voltage, i.e., the offset voltage VOS, is determined based on the threshold voltage offset of the memory cell transistor MT at this time. Voltages VPGM, VPGM_SV, and VOS are related as VPGM_SV = VPGM + VOS.

[0102] 1.3.1 About Sampling Mode

[0103] Next, use Figure 7 The sampling mode is explained in detail.

[0104] like Figure 7 As shown, when the sequencer 17 is programmed, for example, it performs a "0" write using voltage VSV on memory cell transistors MT that write data at the "C" level (hereinafter referred to as "C write"). For example, the number of memory cell transistors MT that perform "C write" is randomized to about 1 / 4 of the data length. At this time, memory cell transistors MT that write data at the "Er" level, "A" level, and "B" level (hereinafter referred to as "Er write", "A write", and "B write" respectively) are set to be disabled for writing. As a result, for example, the threshold voltage of multiple memory cell transistors MT that perform "C write" increases from the "Er" level to the "B" level. Furthermore, the memory cell transistors MT that are set to be written to "0" only need to be memory cell transistors MT that write data at a level higher than the threshold voltage (e.g., "B" level) using voltage VSV for "0" write.

[0105] The programming verification process differs between sampling mode and normal mode. More specifically, in sampling mode, the sequencer 17 counts the number of disconnected units during programming verification and repeatedly performs the verification while increasing the read voltage at equal intervals until the number of disconnected units falls below a predetermined number.

[0106] Hereinafter, the repetition of programming verification within a programming loop will be referred to as a "verification loop". Furthermore, the programming verification in each verification loop will be referred to as verification number 1 to M (M being an integer greater than or equal to 1) corresponding to the number of verification loops. Furthermore, the read voltage applied to the selection word line WL during the first verification in the sampling mode will be denoted as VCG_SV, and the boost voltage of VCG_SV will be denoted as DVCG. More specifically, for example, the line decoder 13 applies a voltage (VCG_SV + DVCG) to the selection word line WL during the second verification, and applies a voltage (VCG_SV + 2·DVCG) to the selection word line WL during the third verification. Similarly, the line decoder 13 applies a voltage (VCG_SV + (M - 1)·DVCG) to the selection word line WL during the Mth verification.

[0107] Furthermore, in sampling mode, during the first verification, if the number of disconnected cells is less than a predetermined number (i.e., insufficient writing), the sequencer 17 repeatedly performs a programming loop while increasing the programming voltage until the number of disconnected cells temporarily exceeds the predetermined number. Hereinafter, the boost voltage of the voltage VSV in sampling mode will be denoted as DSV. Also, during the first verification, if the number of disconnected cells exceeds the predetermined number, the sequencer 17 repeats the verification loop until the number of disconnected cells falls below the predetermined number. In this case, the verification loop is repeated at least twice.

[0108] The sequencer 17 determines the offset voltage VOS based on the read voltage when the number of disconnected units falls below a predetermined number, which is the number of verification cycles. Furthermore, the sequencer 17 sets the optimal programming voltage VPGM_SV based on the offset voltage VOS. The voltage VPGM_SV and the voltage VOS are related as VPGM_SV = VPGM + VOS.

[0109] In addition, the sequencer 17 may also have the functions of adjusting the voltage value and application period of voltage VSV, the specified number of disconnection units, and the voltage values ​​of voltage DSV, voltage VCG_SV and voltage DVCG_SV. For example, the controller 200 may also make changes using Set Feature.

[0110] 1.3.2 About the Offset Table

[0111] Next, use Figure 8The offset table will be explained. In this embodiment, the sequencer 17 has an offset table related to the number of programming loops and the readout voltage (number of verification loops) during sampling mode. Furthermore, the sequencer 17 determines the offset voltage VOS based on the offset table. Figure 8 The example represents a table where the programming loop is set to 2 times and the verification loop is set to 5 times, but it is not limited to this. The number of programming loops and the number of programming verifications in the sampling mode can be set arbitrarily.

[0112] like Figure 8 As shown, for example, when the programming loop is 1 time and the verification loop is 2 times, voltage VOS1_2 is set as the offset voltage VOS. Similarly, when the verification loops are 3, 4, and 5 times, voltages VOS1_3, VOS1_4, and VOS1_5 are set as offset voltages VOS, respectively. Likewise, when the programming loop is 2 times, voltages VOS2_2 to VOS2_5 are set corresponding to the number of verification loops. With the same number of programming loops, the more verification loops, the smaller the offset voltage VOS. For example, voltages VOS1_2 to VOS1_5 have a relationship of VOS1_2 > VOS1_3 > VOS1_4 > VOS1_5. Furthermore, with the same number of verification loops, the more programming loops, the larger the offset voltage VOS. For example, voltages VOS1_2 and VOS2_2 have a relationship of VOS1_2 < VOS2_2. Furthermore, the step widths between voltages VOS1_2 to VOS1_5 and voltages VOS2_2 to VOS2_5 can be the same or different.

[0113] 1.3.3 Overall Flow of Write Operations in Semiconductor Memory Devices

[0114] Next, use Figure 9 and Figure 10 The overall process of writing operations in semiconductor memory devices is explained. Figure 9 and Figure 10 The example illustrates the case where the normal mode is selected when the same word line WL of the same block BLK as the previous write operation is chosen, and the sampling mode is selected when a different word line WL is chosen. Furthermore, the conditions for selecting the sampling mode can be arbitrarily set. For example, the sequencer 17 can perform a write operation based on the normal mode after each application of the sampling mode to set the programming voltage VPGM_SV. Alternatively, the sequencer 17 can also select the sampling mode based on instructions sent by the controller 200.

[0115] like Figure 9As shown, firstly, the NAND flash memory 100 receives a write command (instruction CMD, address ADD, and data DAT) from the controller 200 (step S10). More specifically, the input / output circuit 14 of the NAND flash memory 100 transmits the received instruction CMD, address ADD, and data DAT to the instruction register 15C, address register 15B, and sense amplifier module 12, respectively. The address register 15B sends the column address CA to the sense amplifier module 12 and the row address RA to the row decoder 13. When the instruction CMD is stored in the instruction register 15C, the ready / busy control circuit 18, corresponding to the control of the sequencer 17, sets the ready / busy signal from "H" level to "L" level.

[0116] Sequencer 17 selects a sampling mode when the selected word line WL is different from the previous one (step S11_Yes) (step S12). More specifically, for example, sequencer 17 selects a sampling mode when the selected block BLK is different from the previous one, or when the selected block BLK is the same as the previous one but the selected word line WL is different from the previous one.

[0117] On the other hand, sequencer 17 selects normal mode (step S13) if the selected word line WL is the same as the previous one (step S11_No). For example, if the string unit SU is different from the previous one but the selected word line WL is the same as the previous one, or if the memory cell group MCG is the same as the previous one, sequencer 17 selects normal mode. When normal mode is selected, sequencer 17 sets the programming voltage VPGM_SV used in the previous write operation as the first programming voltage. The programming voltage VPGM_SV used in the previous operation is stored, for example, in the register REG within sequencer 17.

[0118] When the sampling mode is selected (step S12), the sequencer 17 sets the voltage VSV as the programming voltage (step S14).

[0119] Sequencer 17 performs programming using voltage VSV (step S15). More specifically, sequencer 17 sets the memory cell transistor MT to be written to "0" and sets the memory cell transistors MT to be disabled for writing "Er" to "B". The sense amplifier module 12 applies, for example, voltage VSS to the bit line BL corresponding to the memory cell transistor MT written to "C", and voltage VBL (>VSS) to the bit line BL corresponding to the memory cell transistors MT written to "Er" to "B". The line decoder 13 applies voltage VSV to the select word line WL in the select block BLK and voltage VPASS to the other non-select word lines WL. Voltage VPASS is the voltage that sets the memory cell transistor MT to the ON state regardless of its threshold voltage. Voltage VPASS has a relationship of VPASS < VPGM < VSV. Therefore, the threshold voltage of the memory cell transistor MT written to "C" increases.

[0120] Next, the sequencer 17 performs programming verification (step S16). More specifically, the line decoder 13 applies the first verification readout voltage VCG_SV to the select word line WL and the voltage VREAD to the non-select word line WL. The voltage VREAD is the voltage that keeps the memory cell transistor MT on regardless of the data being saved, and is related as VREAD(>VCG_CV)>VCG_SV. For example, if the threshold voltage of the memory cell transistor MT to be read is higher than the voltage VCG_SV, the memory cell transistor MT is in the off state; if the threshold voltage is lower than the voltage VCG_SV, the memory cell transistor MT is in the on state. In this state, the readout amplifier module 12 reads the current flowing through each bit line BL and reads the data of the memory cell transistor MT, while the counter CT counts the number of disconnected cells.

[0121] If the number of disconnected cells exceeds a predetermined number (step S17_Yes), sequencer 17 boosts the read voltage to DVCG. More specifically, for example, sequencer 17 sets a voltage (VCG_SV+DVCG) as the read voltage in the second verification. Next, sequencer 17 returns to step S16 and repeats the verification loop until the number of disconnected cells falls below the predetermined number.

[0122] If the number of disconnected units is less than or equal to a predetermined number (step S17_No), the sequencer 17 checks whether the read voltage has been boosted. In other words, the sequencer 17 checks whether the number of disconnected units in the first verification cycle is less than or equal to a predetermined number.

[0123] Without boosting the read voltage (step S19_No), sequencer 17 boosts the programming voltage to voltage DSV (step S20). More specifically, for example, sequencer 17 sets the voltage (VSV+DSV) as the second programming voltage. Next, sequencer 17 returns to step S15 and performs programming again. Sequencer 17 repeats the programming loop in sampling mode until it reaches a state where the verification loop will be repeated at least twice.

[0124] like Figure 10 As shown, when the read voltage is boosted (step S19_yes), that is, when the verification cycle is repeated at least twice, the sequencer 17 determines that the sampling is performed normally, and sets the programming voltage VPGM_SV based on the number of verification cycles (read voltage) and the number of programming cycles (step S21).

[0125] Next, sequencer 17 switches to normal mode and continues the write operation (step S22).

[0126] After transitioning to normal mode in step S22 or selecting normal mode in step S13, the sequencer 17 performs programming in normal mode (step S23). More specifically, the sequencer 17 sets the memory cell transistors MT for writing "A" to "C" to be "0" written, and sets the memory cell transistors MT for writing "Er" to be disabled for writing. The sense amplifier module 12 applies, for example, a voltage VSS to the bit line BL corresponding to the memory cell transistors MT for writing "A" to "C", and applies a voltage VBL (>VSS) to the bit line BL corresponding to the memory cell transistor MT for writing "Er". The decoder 13 applies a voltage VPGM_SV to the select word line as the first programming voltage in normal mode.

[0127] Next, the sequencer 17 performs programming verification (step S24). More specifically, for example, in the case of performing programming verification at the "A" level, the line decoder 13 applies voltage VCG_AV to the select word line. Furthermore, in programming verification in normal mode, multiple levels of programming verification can also be performed. In this case, the intervals of the readout voltages corresponding to each level can also be different. For example, in the case of performing verification at "A" to "C" levels, the voltage difference between voltage VCG_AV and voltage VCG_BV, and the voltage difference between voltage VCG_BV and voltage VCG_CV, can be different.

[0128] If the verification is successful (step S25_Yes), sequencer 17 ends the writing operation.

[0129] If the verification fails (step S25_No), the sequencer 17 checks whether the number of programming loops in the normal mode has reached the preset number of times (step S26).

[0130] When the programming loop reaches the specified number of times (step S26_Yes), the sequencer 17 ends the writing operation and reports the content of the writing operation that was not completed normally (status information STS) to the controller 200.

[0131] If the programming cycle has not reached the specified number of iterations (step S26_No), the sequencer 17 increases the programming voltage DVP in the next programming cycle (step S27). More specifically, for example, the sequencer 17 sets the voltage (VPGM_SV+DVP) as the second programming voltage in normal mode. Next, the sequencer 17 returns to step S23 and performs programming again.

[0132] Sequencer 17 repeats the programming loop until the number of programming loops in either verification or normal mode reaches the specified number.

[0133] 1.3.4 Specific example of selecting the word line voltage during a write operation

[0134] Next, use Figure 11 and Figure 12 A specific example of the voltage of the select word line WL during a write operation is explained. Figure 11 The example represents the case where the programming loop is executed once in sampling mode and then transitioned to normal mode. Figure 12 The example represents the case where the programming loop is executed twice in sampling mode before transitioning to normal mode.

[0135] First, let's explain the case where the programming loop is executed once in sampling mode.

[0136] like Figure 11 As shown, first, sequencer 17 selects the sampling mode. In the first programming loop of the sampling mode, sequencer 17 performs the first programming based on the sampling mode (“S_Pg1”). At this time, line decoder 13 applies voltage VSV to the select word line WL.

[0137] Next, sequencer 17 performs the first programming verification (“S_Pv1”) based on the sampling pattern. Figure 11The example illustrates the case where the verification loop is repeated 5 times. In the first verification (“1st Vfy”), the line decoder 13 applies a voltage VCG_SV to the select word line WL. Furthermore, each time the verification loop is repeated, the line decoder 13 boosts the voltage applied to the select word line WL by a voltage DVCG. More specifically, the line decoder 13 applies a voltage (VCG_SV + DVCG) to the select word line WL in the second verification (“2nd Vfy”), and applies a voltage (VCG_SV + 2·DVCG) to the select word line WL in the third verification (“3rd Vfy”). Furthermore, the line decoder 13 applies a voltage (VCG_SV + 3·DVCG) to the select word line WL in the fourth verification (“4th Vfy”), and applies a voltage (VCG_SV + 4·DVCG) to the select word line WL in the fifth verification (“5th Vfy”).

[0138] The sequencer 17 determines the offset voltage VOS based on the sampling results and calculates the corrected programming voltage VPGM_SV. Furthermore, when the normal mode is selected, the sequencer 17 omits the preceding actions.

[0139] Next, sequencer 17 transitions to normal mode. In the first programming loop of normal mode, sequencer 17 performs the first programming based on normal mode (“N_Pg1”). At this time, line decoder 13 applies a voltage VPGM_SV to the select word line WL.

[0140] Next, sequencer 17 performs the first programming verification (“N_Pv1”) based on the normal mode. Figure 11 The example illustrates the case of performing programming verification at the "A" level. Line decoder 13 applies a voltage VCG_AV to the select word line WL that is lower than the voltage VCG_SV in sampling mode and corresponds to the programming verification at the "A" level.

[0141] Next, sequencer 17 performs a second programming based on normal mode (“N_Pg2”) in the second programming loop in normal mode. At this time, line decoder 13 applies a voltage (VPGM_SV+DVP) to the select word line WL after boosting the voltage VPGM_SV to the voltage DVP.

[0142] Next, sequencer 17 performs a second verification (“N_Pv2”) based on the normal mode. Figure 11 The example illustrates the case of performing programming verification at "A" and "B" levels. The line decoder 13 applies the voltage VCG_AV corresponding to the programming verification at "A" level to the select word line WL, and then applies the voltage VCG_BV corresponding to the programming verification at "B" level.

[0143] Next, sequencer 17 performs the third programming based on normal mode (“N_Pg3”) in the third programming loop in normal mode. At this time, line decoder 13 applies a voltage (VPGM_SV+2·DVP) to the select word line WL after boosting the voltage (VPGM_SV+DVP) to the voltage DVP.

[0144] Sequencer 17 repeats the programming loop in normal mode until the verification or programming loop reaches the specified number of times.

[0145] Next, we will explain the case where the program is executed twice in sampling mode.

[0146] like Figure 12 As shown, first, sequencer 17 selects the sampling mode. Sequencer 17 performs the first programming based on the sampling mode (“S_Pg1”) in the first programming loop of the sampling mode. At this time, line decoder 13 applies voltage VSV to the select word line WL.

[0147] Next, sequencer 17 performs the first programming verification (“S_Pv1”) based on the sampling pattern. Figure 12 In the example, since the count of disconnected units is below the specified number, sequencer 17 ends the programming verification in one step.

[0148] Next, sequencer 17 performs a second programming based on the sampling mode (“S_Pg2”) in the second programming loop of the sampling mode. At this time, line decoder 13 applies a voltage (VSV+DSV) to the select word line WL after the voltage VSV is boosted to the voltage DSV.

[0149] Next, sequencer 17 performs a second programming verification (“S_Pv2”) based on the sampling pattern. Figure 12 The example illustrates the case where the verification loop is repeated three times. In the first verification (“1st Vfy”), the line decoder 13 applies a voltage VCG_SV to the select word line WL. Furthermore, each time the verification loop is repeated, the line decoder 13 boosts the voltage applied to the select word line WL to a voltage DVCG. More specifically, the line decoder 13 applies a voltage (VCG_SV + DVCG) to the select word line WL in the second verification (“2nd Vfy”) and a voltage (VCG_SV + 2·DVCG) to the select word line WL in the third verification (“3rd Vfy”).

[0150] The sequencer 17 determines the offset voltage VOS based on the sampling results and calculates the corrected programming voltage VPGM_SV.

[0151] Next, sequencer 17 transitions to normal mode. Write operations in normal mode are... Figure 11 Since they are the same, the explanation is omitted.

[0152] 1.4 Effects of this implementation method

[0153] If the configuration of this embodiment is adopted, the processing power of the semiconductor memory device and memory system can be improved. The effects will be explained in detail below.

[0154] For example, in a three-dimensional stacked NAND flash memory, the cell size of the transistors MT within each memory cell of a NAND string varies depending on the layer. In this case, the optimal programming voltage for each memory cell transistor MT, or each word line WL, is different.

[0155] One method for optimizing the programming voltage is to write data into other memory cell groups (MCGs), determine the programming voltage at which the threshold voltage of the memory cell transistor MT reaches a target level (e.g., "A" level), and apply that programming voltage. However, in this case, optimization takes time because the programming cycle (programming and verification) is repeated until the programming voltage reaches the target level. Furthermore, it is impossible to optimize the programming voltage for the memory cell transistor MT that is actually being written to.

[0156] In contrast, in this embodiment, the semiconductor memory device has two write modes: a sampling mode and a normal mode. When the sampling mode is selected, the semiconductor memory device can apply a higher programming voltage than the programming voltage used in the first programming iteration of the normal mode to the select word line WL. Furthermore, within a programming cycle, the semiconductor memory device can repeatedly perform programming verification while simultaneously increasing the read voltage at equal intervals until the number of disconnected cells falls below a predetermined number. Moreover, the semiconductor memory device can optimize the programming voltage based on the programming voltage in the sampling mode and the number of times programming verification is repeated (read voltage). Therefore, compared to the method of repeatedly performing programming and programming verification to determine the optimal programming voltage, the semiconductor memory device can reduce the number of programming cycles required for programming voltage optimization. This shortens the time required for programming voltage optimization, thereby improving the processing power of the semiconductor memory device and the memory system.

[0157] Furthermore, in this embodiment, an optimized programming voltage is used in normal mode, thereby reducing the number of programming cycles required before the threshold voltage of the memory cell transistor MT reaches the required level. Therefore, the processing time for write operations can be shortened.

[0158] Furthermore, in this embodiment, by sampling, the memory cell transistor MT that is used to write data at a level higher than the threshold voltage of the memory cell transistor MT is designated as the target, and programming ("0" write) is performed. Therefore, a normal mode write operation can be performed using an optimized programming voltage after the sampling mode ends.

[0159] Furthermore, in this embodiment, the optimized programming voltage value (the voltage value of voltage VPGM_SV) can be pre-stored in, for example, the REG register within the sequencer 17. Therefore, when the stored programming voltage value can be used, the sampling mode can be omitted, thereby suppressing the increase in the processing time of the write operation.

[0160] Furthermore, register REG can store two or more voltage values ​​of VPGM_SV calculated in the sampling mode. Alternatively, multiple registers REG can be set up to store the voltage value of VPGM_SV for each sampling mode. For example, sequencer 17 can perform a sampling mode for each word line WL and store the voltage value of VPGM_SV corresponding to each word line WL in one register REG or multiple registers REG. In this case, the voltage value of VPGM_SV used in normal mode is the voltage value of VPGM_SV stored in the register REG associated with the sampling mode.

[0161] 2. Second Implementation Method

[0162] Next, the semiconductor memory device and memory system according to the second embodiment will be described. In the second embodiment, four examples are shown where the sequencer 17 selects a sampling mode during the write operation. Hereinafter, only the differences from the first embodiment will be described.

[0163] 2.1 Case 1

[0164] First, use Figure 13 Let's take the first example as an example. In the first example, the sampling mode was selected when a different block BLK was chosen than the previous one. Figure 13 It is different from the first embodiment. Figure 9 and Figure 10 A flowchart that more simply illustrates the overall process of the write operation in the NAND flash memory 100.

[0165] like Figure 13 As shown, firstly, the NAND flash memory 100 receives a write command from the controller 200 (step S10).

[0166] If the selected block BLK is different from the previous one (step S30_Yes), the sequencer 17 selects the sampling mode and performs sampling (step S31). The details of the sampling operation are the same as in the first embodiment. Figure 9 and Figure 10 Steps S12 and S14 to S1422 are the same. For example, if the deviation from the optimal value of the programming voltage is large between blocks BLK, the sequencer 17 performs sampling in each block BLK. The sampling result sets the programming voltage VPGM_SV for the sequencer 17.

[0167] If the selected block BLK is the same as the previous one (step S30_No), the sequencer 17 uses the programming voltage VPGM_SV stored in the register REG.

[0168] Next, sequencer 17 selects normal mode and performs writing (step S32). The writing operation in this case is the same as in the first embodiment. Figure 9 and Figure 10 Steps S23 to S27 are the same.

[0169] 2.2 Case 2

[0170] Next, use Figure 14 The second example will be explained. In the second example, the sampling mode is selected when the serial cell SU0 is selected. The following explanation will only cover the differences from the first example.

[0171] like Figure 14 As shown, unlike the first example, sequencer 17 performs sampling (step S31) when serial cell SU0 is selected (step S33_Yes). For example, in this example, the write order in the selected block BLK is the order of serial cells SU0~SU3 of word line WL0, serial cells SU0~SU3 of word line WL1, ..., serial cells SU0~SU3 of word line WL7. Therefore, sampling is performed when serial cell SU0 is selected for a certain word line WL (step S33_Yes), and when serial cells SU1~SU3 are selected (step S33_No), the optimized programming voltage VPGM_SV when serial cell SU0 is selected is used.

[0172] In addition, in this example, the sampling mode can also be selected when the serial unit SU0 of block BLK0 is selected.

[0173] 2.3 Example 3

[0174] Next, use Figure 15 The third example will be explained. In the third example, the sampling mode was selected when a different memory cell group (MCG) was chosen than in the previous example. The following explanation will only cover the differences from the first and second examples.

[0175] like Figure 15 As shown, unlike examples 1 and 2, sequencer 17 performs sampling (step S31) when the selected memory cell group MCG is different from the previous one (step S34_Yes). For example, when the lower page is written in the same memory cell group MCG and then the upper page is written, or when the column address CA is different in the same page, the same memory cell group MCG is selected.

[0176] 2.4 Case 4

[0177] Next, we will explain the fourth example. In the fourth example, the memory cell transistors MT within the NAND string 20 are divided into multiple word line WL units (hereinafter referred to as "zones ZN"), and the sampling mode is selected when different zone ZNs are selected. Hereinafter, we will only explain the differences from the first to the third examples.

[0178] 2.4.1 Regarding Zone ZN

[0179] First, use Figure 16 Explanation of zone ZN. Figure 16 The first embodiment is Figure 4 The diagram is extracted from the memory cylinder MP and wiring layer 34.

[0180] like Figure 16 As shown, the sequencer 17 divides the word lines WL0 to WL7 into, for example, four zones ZN0 to ZN3 for management. Figure 16 In the example, word lines WL0 and WL1 belong to zone ZN0, word lines WL2 and WL3 belong to zone ZN1, word lines WL4 and WL5 belong to zone ZN2, and word lines WL6 and WL7 belong to zone ZN3. Furthermore, the zone ZN setting can be changed arbitrarily. For example, word lines WL0 to WL3 can be set to zone ZN0, and word lines WL4 to WL7 can be set to zone ZN1.

[0181] 2.4.2 Overall Flow of Write Operations in Semiconductor Memory Devices

[0182] Next, use Figure 17 The overall process of writing operations in semiconductor memory devices is explained.

[0183] like Figure 17 As shown, unlike examples 1 to 3, sequencer 17 performs sampling (step S31) when region ZN is different from the previous one (step S35_yes).

[0184] 2.5 Effects of this implementation method

[0185] The first to fourth examples of this embodiment can be applied to the first embodiment. Furthermore, the first to fourth examples can be combined as much as possible. For example, the second example can be combined with the third example, and if the same memory cell group MCG as before is selected in the string cell SU0, the normal mode is selected.

[0186] 3. Regarding the third implementation method

[0187] Next, the semiconductor memory device and memory system according to the third embodiment will be described. The third embodiment will describe the case where the controller 200 selects the write mode in the NAND flash memory 100. Hereinafter, only the differences from the first and second embodiments will be described.

[0188] 3.1 Overall process of write operations in a memory system

[0189] First, use Figure 18 The overall process of the write operation in memory system 1 is described. Figure 18 In the example, controller 200 selects the sampling mode without selecting the same row address RA as the previous one.

[0190] like Figure 18 As shown, firstly, the controller 200 receives a write command from the host device 2 (step S100).

[0191] The processor 230 of the controller 200 determines the address ADD (row address RA and column address CA) to write the data (step S101).

[0192] For example, if the processor 230 selects the same row address RA as the previous write (address ADD) stored in the built-in memory 220 (step S102_Yes), it selects the normal mode and issues a write command. Next, the processor 230 sends a write command (write command, address ADD, and data DAT) to the NAND flash memory 100 via the NAND interface circuit 250 (step S103).

[0193] In this way, the sequencer 17 selects the normal mode and begins the write operation based on the write command received from the controller 200 (step S105). In this case, the write operation in the NAND flash memory 100 is similar to that in the first embodiment. Figure 9 and Figure 10 The write operation after step S13 is the same.

[0194] On the other hand, if the processor 230 selects the same row address RA as before (step S102_Yes), it selects the sampling mode and issues a sampling instruction. Next, the processor 230 sends a write command containing the sampling instruction (sampling instruction, write instruction, address ADD, and data DAT) to the NAND flash memory 100 via the NAND interface circuit 250 (step S104).

[0195] In this way, the sequencer 17 selects a sampling mode and begins the write operation based on the sampling instruction received from the controller 200 (step S106). In this case, the write operation in the NAND flash memory 100 is similar to that in the first embodiment. Figure 9 and Figure 10 The write operation after step S12 is the same. After the sequencer 17 calculates the programming voltage VPGM_SV by sampling, it switches to normal mode and continues the write operation.

[0196] Furthermore, when the sequencer 17 stores multiple registers REG, the processor 230 selects the appropriate register REG and sends a write command. More specifically, in normal mode, the processor 230 selects the register REG that stores the voltage value VPGM_SV corresponding to the selected page and sends a write command. In this case, regarding the write operation in the NAND flash memory 100, the voltage value VPGM_SV stored in the selected register REG is used for the write operation, similar to that in the first embodiment. Figure 9 and Figure 10 The write operation following step S13 is the same. Additionally, in sampling mode, the processor 230 selects the register REG storing the sampling results and the sampling mode, and sends a write command. In this case, the voltage value VPGM_SV calculated in sampling mode is stored in the selected register REG, and the voltage value VPGM_SV stored in the unselected register REG is not updated.

[0197] 3.2 Controller actions related to write operations

[0198] Next, use Figure 19 and Figure 20 Two examples of the actions of the controller 200 during a write operation are explained. Figure 19 The example represents a write operation when the controller 200 does not specify the REG register and selects the sampling mode. Figure 20 The example represents a write operation when the controller 200 specifies the REG register and selects the sampling mode.

[0199] First, the case where the controller 200 does not specify the register REG will be explained. For example, if the sequencer 17 contains one register REG and the register REG can only store one voltage VPGM_SV, the controller 200 does not specify the register REG.

[0200] like Figure 19 As shown, firstly, the processor 230 outputs the sampling instruction "YYh" for notifying the execution of sampling and the instruction "80h" for notifying the execution of writing to the NAND flash memory 100, and activates the instruction latch enable signal CLE as "H" level.

[0201] Next, processor 230 outputs the address "ADD" and activates the address latch enable signal ALE at the "H" level. Furthermore, in Figure 19 In the example, the address is shown in one loop, but multiple loops can be used to send column address CA and row address RA, etc.

[0202] Next, the processor 230 outputs the programming data "DAT" for the required number of loops.

[0203] Then, the processor 230 outputs the write instruction "10h" indicating that the write operation will be performed, and activates the instruction latch enable signal CLE as "H" level.

[0204] These instructions, addresses, and data are stored, for example, in register 15 of the NAND flash memory 100.

[0205] The sequencer 17 selects the sampling mode in response to the sampling command "YYh". In addition, the sequencer 17 starts the writing operation in response to the write command "10h", and the NAND flash memory 100 becomes busy (R / Bn = "L").

[0206] When the write operation is completed, the NAND flash memory 100 becomes ready, and the ready / busy signal R / Bn returns to the "H" level.

[0207] Next, the case where the controller 200 specifies the REG register will be explained. For example, if the sequencer 17 contains multiple REG registers, the controller 200 specifies the REG register corresponding to the selected page.

[0208] like Figure 20As shown, firstly, the processor 230 outputs the instruction "ZZ1h" to specify the REG register, the instruction "ZZ2h" to specify the write mode and the TEG register, and the instruction "80h" to notify the execution of the write operation to the NAND flash memory 100, and activates the instruction latch enable signal CLE at the "H" level. For example, the instruction ZZ2h is a 1-cycle signal, using 1 bit of the 8 bits of data in "ZZ2h" to select the sampling mode or normal mode, and using the remaining bits to select the REG register to be used. Furthermore, the instruction "ZZ2h" can also be an address or data.

[0209] Next, with Figure 19 Similarly, processor 230 outputs address "ADD", programming data "DAT", and write instruction "10h" indicating write execution.

[0210] 3.3 Effects of this implementation method

[0211] As long as the configuration of this embodiment is used, the same effects as those of the first and second embodiments can be obtained.

[0212] Furthermore, in this embodiment, the case where the processor 230 selects the sampling mode when the row address RA is the same has been described, but it is not limited to this. The processor 230 may also perform the sampling mode selection operation performed by the sequencer 17 as described in the first and second embodiments. Furthermore, the first to third embodiments may be combined, and the controller 200 and the NAND flash memory 100 may select the sampling mode under different conditions.

[0213] 4. Fourth Implementation Method

[0214] Next, the semiconductor memory device and memory system according to the fourth embodiment will be described. The fourth embodiment describes the case where the controller 200 selects and samples the number of rewrites (the number of times write / delete operations are repeated) corresponding to the selected block BLK. Hereinafter, only the differences from the first to third embodiments will be described.

[0215] 4.1 Overall process of write operations in a memory system

[0216] use Figure 21 The overall process of the write operation in memory system 1 is described. Figure 21 In the example, controller 200 selects the sampling mode corresponding to the number of rewrites performed after the previous sampling.

[0217] like Figure 21 As shown, firstly, the controller 200 receives the write from the host device 2 (step S100).

[0218] The processor 230 of the controller 200 determines the address ADD (row address RA and column address CA) to write the data (step S101).

[0219] The processor 230 refers to, for example, a rewrite count table stored in the built-in memory 220 (step S107). The rewrite count table stores, for example, the number of rewrites after sampling for each block BLK. Furthermore, the rewrite count stored in the write table can be in word line (WL) units or string unit (SU) units, and can be arbitrarily set. Alternatively, the rewrite count table can store, for example, the total number of rewrites since factory release. In this case, sampling can be performed each time a predetermined number of times (e.g., 1000 times, 5000 times, ...) is reached. Furthermore, it could also be a deletion count table storing the deletion count for each block BLK.

[0220] If the number of rewrites is less than the predetermined number (step S107_Yes), similarly to the third embodiment, the processor 230 selects the normal mode and issues a write command. Next, the processor 230 sends a write command to the NAND flash memory 100 (step S103).

[0221] In this way, sequencer 17 selects normal mode and begins the writing operation (step S105).

[0222] On the other hand, if the number of rewrites exceeds the predetermined number (step S107_No), similarly to the third embodiment, the processor 230 selects a sampling mode and issues a sampling instruction and a write instruction. Next, the processor 230 sends a write command containing the sampling instruction to the NAND flash memory 100 (step S104).

[0223] In this way, sequencer 17 selects the sampling mode and begins the writing operation (step S106).

[0224] 4.2 Effects of this implementation method

[0225] As long as the configuration of this embodiment is used, the same effects as those of the first to third embodiments can be obtained.

[0226] Furthermore, with the configuration of this embodiment, even if the characteristics of the memory cell transistor MT deteriorate due to repeated writing and deletion, the optimal programming voltage can still be set. Therefore, the processing power of the semiconductor memory device and memory system can be improved.

[0227] 5. Examples of variations, etc.

[0228] The semiconductor memory device of the embodiment includes: a first memory cell group (MCG) including a plurality of first memory cells (MT); word lines (WL) commonly connected to the plurality of first memory cells; and control circuitry (corresponding to sequencer 17) for controlling a write operation, the write operation comprising: a first mode (sampling mode) for repeatedly performing a first programming cycle including a first programming and a first verification; and a second mode (normal mode) for repeatedly performing a second programming cycle including a second programming and a second verification. When the control circuit executes the first and second modes in sequence, in the first programming cycle, after performing the first programming by applying the first voltage (VSV) to the word line, the first verification is repeated while boosting the second voltage (VCG_SV) applied to the word line until the number of disconnected cells of the first memory cell becomes below the threshold. Based on the first voltage and the number of times the first verification is repeated, a third voltage (VPGM_SV) lower than the first voltage is determined. In the first second programming cycle, after performing the second programming by applying the third voltage to the word line, a fourth voltage (VCG_AV) lower than the second voltage is applied to the word line to perform the second verification.

[0229] By applying the described embodiments, a semiconductor memory device capable of improving processing power can be provided.

[0230] Furthermore, the implementation method is not limited to the described method and various variations are possible.

[0231] 5.1 Example of the first variation

[0232] For example, this implementation can also be applied to a memory cell transistor MT capable of storing 8 bits (3 bits) of data. Using Figure 22 An example will be described below. Hereinafter, only the example described in the first embodiment will be considered. Figure 7 Explain the different points.

[0233] like Figure 22 As shown, sequencer 17, for example, sets the memory cell transistors MT for writing "D" to "G" to the target and performs a "0" write using voltage VSV. At this time, the memory cell transistors MT for writing "Er" to "C" to the target are disabled for writing. This results in a significant shift, for example, when the threshold voltage of multiple memory cell transistors MT for writing "D" to "G" to the target reaches the "C" level. In this case, voltage VCG_SV is set to, for example, a voltage higher than voltage VCG_CV and lower than voltage VCG_DV.

[0234] 5.2 Other variations

[0235] For example, the embodiments can be combined as much as possible. For example, the first embodiment can be combined with the fourth embodiment.

[0236] Furthermore, in the aforementioned embodiment, the readout amplifier module 12 can be either a current readout type or a voltage readout type.

[0237] Furthermore, the embodiments described are not limited to three-dimensional stacked NAND flash memory, but can also be applied to planar NAND flash memory in which memory cells are arranged on a semiconductor substrate. Furthermore, they are not limited to NAND flash memory, but can also be applied to semiconductor memory devices that use other types of memory.

[0238] Furthermore, the so-called "connection" in the above-described embodiments also includes a state in which other objects, such as transistors or resistors, are interposed between the two to ground them.

[0239] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other ways and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. The embodiments or variations thereof are included in the scope or spirit of the invention and are included within the scope of the invention as described in the claims and its equivalents.

[0240] Furthermore, in various embodiments related to this invention, it may also be described as follows. For example, the memory cell transistor MT can store 2 bits (4 bits) of data, and when the threshold level for storing any one of the 4 bits is set from low to high as Er level (delete level), A level, B level, and C level,

[0241] (1) In the reading action,

[0242] The voltage applied to the word line selected for the readout operation at level "A" is, for example, between 0 and 0.55V. It is not limited to this and can also be set to any range of 0.1 to 0.24V, 0.21 to 0.31V, 0.31 to 0.4V, 0.4 to 0.5V, and 0.5 to 0.55V.

[0243] The voltage applied to the word line selected for the read operation at the "B" level is, for example, between 1.5 and 2.3V. It is not limited to this and can also be set to any range of 1.65 to 1.8V, 1.8 to 1.95V, 1.95 to 2.1V, and 2.1 to 2.3V.

[0244] The voltage applied to the word line selected for the read operation at the "C" level is, for example, between 3.0V and 4.0V. It is not limited to this and can also be set to any range of 3.0 to 3.2V, 3.2 to 3.4V, 3.4 to 3.5V, 3.5 to 3.6V, and 3.6 to 4.0V.

[0245] The time (tR) of the readout action can be set to any range of 25μs to 38μs, 38μs to 70μs, or 70μs to 80μs.

[0246] (2) As mentioned above, the write action includes programming and verification actions. In the write action,

[0247] The voltage applied to the selected word line when the programming action is first performed is, for example, between 13.7 and 14.3V. It is not limited to this; for example, it can also be set to any range between 13.7 and 14.0V and between 14.0 and 14.6V.

[0248] You can also change the voltage applied first to the selected word line when writing the odd-numbered word line and the voltage applied first to the selected word line when writing the even-numbered word line.

[0249] When the programming action is set to ISPP (Incremental Step Pulse Program) mode, the boost voltage can be, for example, around 0.5V.

[0250] The voltage applied to the unselected word line can be set, for example, between 6.0 and 7.3V. It is not limited to this; for example, it can also be set between 7.3 and 8.4V, or even below 6.0V.

[0251] The applied voltage can also be changed depending on whether the non-selected word line is the odd-numbered word line or the even-numbered word line.

[0252] The time (tProg) for the write operation can be set to any range of 1700μs~1800μs, 1800μs~1900μs, or 1900μs~2000μs.

[0253] (3) In the deletion action,

[0254] The voltage initially applied to the well formed on the semiconductor substrate and on which the memory cell is disposed is, for example, between 12V and 13.6V. This is not a limitation; for example, it can be any range of 13.6V to 14.8V, 14.8V to 19.0V, 19.0V to 19.8V, or 19.8V to 21V.

[0255] The time (tErase) for the deletion action can be set to any range, such as 3000–4000 μs, 4000–5000 μs, or 4000–9000 μs.

[0256] (4) The memory cell is constructed with a charge storage layer disposed on a semiconductor substrate (silicon substrate) with a tunneling insulating film having a thickness of 4 to 10 nm. This charge storage layer can also be a composite structure of an insulating film such as SiN or SiON with a thickness of 2 to 3 nm and polycrystalline silicon with a thickness of 3 to 8 nm. Alternatively, a metal such as Ru can be added to the polycrystalline silicon. An insulating film is placed above the charge storage layer. This insulating film, for example, has a silicon oxide film with a thickness of 4 to 10 nm sandwiched between a lower High-k film with a thickness of 3 to 10 nm and an upper High-k film with a thickness of 3 to 10 nm. Examples of High-k films include HfO. Furthermore, the thickness of the silicon oxide film can be thicker than that of the High-k film. A control electrode with a thickness of 30 nm to 70 nm is formed on the insulating film with a work function adjustment material having a thickness of 3 to 10 nm. Here, the work function adjustment material is a metal oxide film such as TaO or a metal nitride film such as TaN. The control electrode can be W, etc.

[0257] In addition, air gaps can be formed between storage cells.

[0258] [Explanation of Symbols]

[0259] 1. Memory System

[0260] 2. Main unit

[0261] 11-cell array

[0262] 12 Readout Amplifier Module

[0263] 13-line decoder

[0264] 14 Input / Output Circuit

[0265] 15 registers

[0266] 15A Status Register

[0267] 15B Address Register

[0268] 15C Instruction Register

[0269] 16 Logic Control Circuits

[0270] 17 Sequencers

[0271] 18 Ready / Busy Control Circuits

[0272] 19 Voltage Generation Circuit

[0273] 20 NAND string

[0274] 30 Semiconductor Substrates

[0275] 31n type well

[0276] 32p type well

[0277] 33n + Type diffusion layer

[0278] 34 wiring layers

[0279] 35 semiconductor layers

[0280] 36 tunneling insulation film

[0281] 37 charge storage layer

[0282] 38 Barrier Insulating Film

[0283] 100NAND flash memory

[0284] 200 controller

[0285] 210 Host Interface Circuit

[0286] 220 Built-in memory

[0287] 230 processor

[0288] 240 Buffer Memory

[0289] 250NAND interface circuit

[0290] 260ECC circuit

Claims

1. A control method of a semiconductor storage device, characterized by Controlling a semiconductor memory device, the semiconductor memory device comprising: The first storage unit group contains multiple first storage units; Word lines are commonly connected to the plurality of first memory cells; and A control circuit controls a write operation, the write operation comprising: a first mode, executing a first programming loop including a first programming and a first verification at least once; And in the second mode, repeat the second programming loop, which includes the second programming and the second verification; The control method for the semiconductor memory device includes: When the first mode and the second mode are executed sequentially, In the first programming loop, The first programming is performed by applying a first voltage to the word line. While increasing the second voltage applied to the word line, the first verification is repeated until the number of disconnected cells in the first memory cell falls below a threshold. A third voltage lower than the first voltage is determined based on the first voltage and the number of times the first verification is repeated; In the first instance of the second programming loop, The second programming is performed by applying the third voltage to the word line. The second verification is performed by applying a fourth voltage, which is lower than the second voltage, to the word line.

2. The control method for a semiconductor memory device according to claim 1, characterized in that: In the first programming cycle, the first programming cycle is repeated while the first voltage is boosted until the number of disconnected units exceeds the threshold in the first verification during the first verification in which the second voltage is applied to the word line.

3. The control method for a semiconductor memory device according to claim 1 or 2, characterized in that: In the first programming cycle, the first verification is repeated while the second voltage is increased by the first voltage amount each time.

4. The control method for a semiconductor memory device according to claim 1 or 2, characterized in that: The semiconductor memory device further includes a second memory cell group, which comprises a plurality of second memory cells; and After the write operation to the first storage cell group, the write operation to the second storage cell group is performed. In the write operation to the second memory cell group, the first mode is not executed, but the second mode is executed using the third voltage.

5. A control method for a semiconductor memory device, characterized in that... The semiconductor memory device includes: The first storage unit group contains multiple first storage units; The second storage unit group contains multiple second storage units; The first word line is commonly connected to the plurality of first memory cells and the plurality of second memory cells; and The control circuit controls the write operation, which includes: In Mode 1, the first programming loop, which includes the first programming and the first verification, is executed at least once. The second mode involves repeating the second programming loop, which includes the second programming and the second verification; and The control circuit is: When performing the write operation on the plurality of first storage units, In the first programming loop, The first programming is performed by applying a first voltage to the first word line. The first verification is performed multiple times by applying multiple second voltages, each lower than the first voltage, to the first word line until the number of disconnected cells in the first memory cell falls below a threshold. A third voltage higher than the second voltage is determined based on the first voltage and the number of times the first verification is performed; In the first instance of the second programming loop, The second programming is performed by applying the third voltage to the first word line. The second verification is performed by applying a fourth voltage, which is lower than the highest of the plurality of second voltages, to the first word line.

6. The control method for a semiconductor memory device according to claim 5, characterized in that... It also has: A plurality of first selection transistors are connected to the plurality of first memory cells; A plurality of second selection transistors are connected to the plurality of second memory cells; The first selection gate line is connected to the plurality of first selection transistors; and A second selection gate line is connected to the plurality of second selection transistors; and When the control circuit performs the write operation on the second memory cell group after the write operation on the first memory cell group, In the write operation to the second memory cell group, the first mode is not executed, but the second mode is executed using the third voltage.

7. The control method for a semiconductor memory device according to claim 6, characterized in that... It also has: A plurality of third memory cells are connected to the plurality of first memory cells and the plurality of first selection transistors; A plurality of fourth memory cells are connected to the plurality of second memory cells and the plurality of second selection transistors; and The second word line is commonly connected to the plurality of third memory cells and the plurality of fourth memory cells; When the control circuit performs the write operation on the third memory cell group after the write operation on the second memory cell group, In the write operation to the third storage cell group, the second mode is executed after the first mode is executed; When the control circuit performs the write operation on the fourth memory cell group after the write operation on the third memory cell group, In the write operation to the fourth storage cell group, the first mode is not executed but the second mode is executed.

8. A semiconductor memory device, characterized in that... include: A storage cell array having multiple storage cell groups, each storage cell group containing multiple storage cells, the multiple storage cell groups including: a first storage group containing a first storage cell; and a second storage group containing a second storage cell; The first word line is connected to each of the first memory cells; The second word line is connected to each of the second memory cells; and The control circuit is configured to: execute a first write operation targeting the first memory cell in a first mode, wherein in the first mode, the control circuit performs at least a first programming operation on the first memory cell, followed by multiple first verification operations to verify the first programming operation; and then execute in a second mode, wherein in the second mode, the control circuit performs a second programming operation on the first memory cell, followed by a second verification operation to verify the second programming operation, wherein... The programming voltage applied to the first word line during the second programming operation is less than the programming voltage applied to the first word line during the first programming operation and is adjusted based on the number of first verification operations.

9. The semiconductor memory device according to claim 8, wherein: The programming voltage applied to the first word line during the second programming operation is further adjusted based on the number of first programming operations performed during the first mode.

10. The semiconductor memory device according to claim 9, wherein: The programming voltage applied to the first word line during the second programming operation is: a first voltage when the number of the first programming operations is N1 and the number of the first verification operations is N2, and a second voltage when the number of the first programming operations is N1 and the number of the first verification operations is N3, and if N2 < N3, the first voltage is greater than the second voltage, and if N2 > N3, the first voltage is less than the second voltage.

11. The semiconductor memory device according to claim 9, wherein: The programming voltage applied to the first word line during the second programming operation is: a third voltage when the number of the first programming operations is N4 and the number of the first verification operations is N5, and a fourth voltage when the number of the first programming operations is N6 and the number of the first verification operations is N5, and if N4 > N6, the third voltage is greater than the fourth voltage, and if N4 < N6, the third voltage is less than the fourth voltage.

12. The semiconductor memory device according to claim 8, characterized in that... The control circuit is configured to: Execute the second write operation according to whether the second write operation targets the first storage unit, the second write operation being the next write operation after the first write operation.

13. The semiconductor memory device according to claim 12, characterized in that... The control circuit is configured to: If the second write operation does not target the first storage unit, execute the second write operation in the first mode and then in the second mode.

14. The semiconductor memory device according to claim 12, characterized in that... The control circuit is configured to: Store the programming voltage applied to the first word line during the second programming operation, and if the second write operation targets the first storage unit, execute the second write operation in the third mode, in which the control circuit performs a third programming operation on the first storage unit and then performs a third verification operation to verify the third programming operation, where The programming voltage applied to the first word line during the third programming operation is the same as the stored programming voltage.

15. The semiconductor memory device according to claim 8, characterized in that... The control circuit is configured to: Execute the second write operation according to whether the second write operation targets a storage unit connected to the first word line or a different word line located in the same word line region as the first word line, the second write operation being the next write operation after the first write operation.

16. The semiconductor memory device according to claim 8, characterized in that... The control circuit is configured to: The second write action is performed depending on whether the target of the second write action is a storage cell located in the same block as the first storage cell. The second write action is the next write action after the first write action.

17. The semiconductor memory device according to claim 8, characterized in that... The control circuit is configured as follows: The second write action is performed depending on whether the target of the second write action is a storage cell with the same row address as the first storage cell. The second write action is the next write action after the first write action.

18. The semiconductor memory device according to claim 8, characterized in that... The control circuit is configured as follows: The second write action is executed based on whether the target of the second write action is a storage unit that has been rewritten more than the rewrite threshold number. The second write action is the next write action after the first write action.

19. A semiconductor memory device, characterized in that... include: A storage cell array having multiple storage cell groups, each storage cell group containing multiple storage cells connected to a common word line; and The control circuit is configured to perform the first write operation and the second write operation consecutively by means of the following: At least a first programming action is performed on the memory cell targeted by the first write action, followed by multiple first verification actions to verify the first programming action. A second programming action is performed on the memory cell targeted by the first write action, followed by a second verification action to verify the second programming action. The programming voltage applied during the second programming operation is stored in the word line connected to the memory cell targeted by the first write operation, and The second write operation is performed based on whether the conditions for using the stored programming voltage are met.

20. The semiconductor memory device according to claim 19, characterized in that: The programming voltage applied during the second programming action is less than the programming voltage applied during the first programming action, and is adjusted based on the number of first verification actions.

21. The semiconductor memory device according to claim 20, characterized in that: When it is determined that the second write operation satisfies the conditions for using the programming voltage of the memory, a third programming operation is performed on the memory cell targeted by the second write operation, followed by a third verification operation to verify the third programming operation. The programming voltage used during the third programming action is the same as the stored programming voltage.

22. The semiconductor memory device according to claim 20, characterized in that: When it is determined that the second write operation does not meet the conditions for using the programming voltage of the memory, at least a third programming operation is performed on the memory cell targeted by the second write operation, followed by multiple third verification operations to verify the third programming operation, and A fourth programming action is performed on the storage cell targeted by the second write action, followed by a fourth verification action to verify the fourth programming action.

23. The semiconductor memory device according to claim 19, characterized in that... The condition is one of the following: The storage cell targeted by the second write operation is the same as the storage cell targeted by the first write operation; The word line connected to the memory cell targeted by the second write operation is the same as the word line connected to the memory cell targeted by the first write operation; The word line connected to the memory cell targeted by the second write operation is in the same region as the word line connected to the memory cell targeted by the first write operation; The row address of the memory cell targeted by the second write action is the same as the row address of the memory cell targeted by the first write action; and The number of rewrites performed on the storage cell targeted by the second write action is less than the rewrite threshold number.

24. A method for performing a write operation on a group of memory cells of a semiconductor memory device, the memory cells being connected to a common word line, the method comprising: (a) Perform at least a first programming action on the memory cell, followed by multiple first verification actions to verify the first programming action; (b) Perform a second programming action on the storage unit, followed by a second verification action to verify the second programming action; (c) The programming voltage applied during the second programming operation is stored in the word line connected to the memory cell; and (d) After completing the first write operation including steps (a), (b) and (c), the next write operation is performed based on whether the second write operation satisfies the conditions for using the stored programming voltage.

25. The method according to claim 24, characterized in that: The programming voltage applied during the second programming action is less than the programming voltage applied during the first programming action, and is adjusted based on the number of first verification actions.

26. The method according to claim 25, characterized in that... Also includes: When it is determined that the second write operation satisfies the conditions for using the programming voltage of the memory, a third programming operation is performed on the memory cell targeted by the second write operation, followed by a third verification operation to verify the third programming operation. The programming voltage used during the third programming action is the same as the stored programming voltage.

27. The method according to claim 25, characterized in that: When it is determined that the second write operation does not meet the conditions for using the stored programming voltage, At least a third programming action is performed on the memory cell targeted by the second write action, followed by multiple third verification actions to verify the third programming action, and A fourth programming action is performed on the storage cell targeted by the second write action, followed by a fourth verification action to verify the fourth programming action.

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