Memory device testing and associated methods, devices, and systems

Abstract

Memory device testing and associated methods, devices, and systems are disclosed. A method can include reading from a plurality of memory addresses of a memory array of the memory device and identifying each memory address of the plurality of addresses as pass or fail. The method can further include, for each identified fail, storing data associated with the identified fail in a buffer of the memory device. In addition, the method can include transferring at least some of the data associated with each identified fail to a tester external to the memory device without transferring address data associated with each identified pass to the tester.

Description

[0001] CLAIM

[0002] This application claims the benefit of the filing date of U.S. Patent Application Serial No. 16 / 919,922, filed July 2, 2020, entitled “MEMORY DEVICE TESTING, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS.” TECHNICAL FIELD

[0003] Embodiments of the present disclosure generally relate to memory device testing. More specifically, various embodiments relate to methods of testing memory devices, and related devices and systems. More specifically, some embodiments relate to processing, storing, and / or communicating memory device test data to a tester. BACKGROUND

[0004] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are a variety of different types of memory, including, for example, random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), double data rate memory (DDR), low power double data rate memory (LPDDR), phase change memory (PCM), and flash memory.

[0005] Memory devices typically include a plurality of memory cells that are capable of holding an electrical charge representative of a data bit. Typically, these memory cells are arranged in a memory array. Data can be written to or retrieved from a memory cell by selectively activating the memory cell via an associated word line driver. SUMMARY

[0006] Various embodiments of the present disclosure can include a method of testing a memory device. The method can include reading from a plurality of memory addresses of a memory array of the memory device, and identifying each memory address of the plurality of addresses as either passing or failing. The method can further include, for each identified failure, storing data associated with the identified failure in a buffer of the memory device. In addition, the method can include communicating at least some of the data associated with each identified failure to a tester external to the semiconductor die without communicating address data associated with each identified pass to the tester.

[0007] According to another embodiment of the disclosure, an apparatus can include a memory array and a buffer coupled to the memory array. The apparatus can further include circuitry coupled to the memory array and the buffer and configured to read data from a plurality of memory addresses of the memory array. The circuitry can also be configured to compare the read data to known test data. In addition, the circuitry can be configured to identify each memory address of the plurality of memory addresses as pass or fail in response to the comparison. Also, the circuitry can be configured to store data associated with each identified fail in the buffer for each identified fail. The circuitry can further be configured to transfer at least some of the data associated with each identified fail to an external tester without transferring address data associated with each identified pass to the external tester.

[0008] Additional embodiments of the disclosure include a system. The system can include a test apparatus and at least one memory device operably coupled to the test apparatus. The memory device can include a memory array comprising a plurality of memory addresses. The memory device can also include a first-in-first-out (FIFO) cache and at least one circuit. The at least one circuit can be configured to identify each memory address of the plurality of memory addresses as pass or fail in response to at least one test operation. The at least one circuit can also be configured to store a plurality of fail data bits associated with each identified fail in the FIFO cache for each identified fail. In addition, the at least one circuit can be configured to transfer at least some of the plurality of fail data bits associated with each identified fail to the test apparatus without transferring address data associated with each identified pass to the test apparatus. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a block diagram of an exemplary memory device according to at least one embodiment of the disclosure.

[0010] Figure 2 depicts an exemplary system including a memory device and a tester.

[0011] Figure 3 depicts an exemplary system including a tester, a memory device, and a buffer according to various embodiments of the disclosure.

[0012] Figure 4A and 4B is an exemplary illustration depicting a snapshot of data within a buffer of a memory device according to one or more embodiments of the disclosure.

[0013] Figure 5 A timing diagram showing an exemplary test operation is depicted in accordance with various embodiments of the present disclosure.

[0014] Figure 6 is a flowchart of an exemplary method of testing a memory device in accordance with various embodiments of the present disclosure.

[0015] Figure 7 is a simplified block diagram of a system in accordance with various embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] Semiconductor memory devices typically include an array of memory cells. Memory cells in the array are selected for reading and writing by row and column address signals input to the memory device. The row and column address signals are processed by address decode circuitry to select a row line and a column line in the array to access a desired one or more memory cells (i.e., at one or more identified memory addresses).

[0017] In the manufacture of semiconductor memory devices, integrated circuits are formed on a wafer, which typically includes a plurality of integrated circuits. The functionality of the integrated circuits is then tested or probed while the circuits are still on the wafer. Each wafer is then cut into dies or dies using a diamond saw. Each die represents one integrated circuit. Dies that do not pass wafer testing will be discarded or reworked to restore functionality to the circuit. Dies that pass wafer-level testing are typically mounted on a lead frame and the dies are encapsulated with a plastic compound to form a semiconductor device. However, the dies can be mounted and encapsulated at a later time after further testing of the dies.

[0018] An electrical test is then typically performed on each device. Following this initial testing, an aging test is typically performed on each of the devices. The aging test involves testing the devices at an elevated temperature, typically in excess of 100 degrees Celsius, for a length of time typically in excess of 24 hours. The environmental stress applied to the devices during the aging test is much greater than the stress the devices would typically encounter under normal operation. Thus, the aging test can identify defects in the devices that can cause early failure of the semiconductor devices. The aging test typically does not test the devices at the maximum operating speed of the devices and other discrete tests cannot be performed on the devices. Thus, the devices are typically subjected to another series of electrical tests.

[0019] One conventional method of testing a memory device is for an external test device (also referred to herein as a "tester") to write data into each memory cell of the memory device, read data from each memory cell, and compare the input with the output. Such a comparison can reveal cells that failed to store data correctly. Despite the defective memory cells, to salvage the semiconductor memory device, and thus improve the overall yield of the manufacturing process, redundancy is typically implemented. Redundant memory cells are located in the memory array, and the memory array can be associated with multiple redundant memory cells. When a defective memory cell is detected in the array, the redundancy decoding circuitry associated with the redundant memory cells can be programmed (e.g., via fuses, antifuses, or other programming techniques) to respond to the address of the defective memory cell. When the address of the defective memory cell is selected for access, the redundant memory cell can be accessed (e.g., read from or written into) instead of the defective memory cell.

[0020] During at least some testing phases, a large number of electrical tests are performed on a large number of integrated circuits on a wafer or on a large number of packaged semiconductor devices via an integrated circuit tester. Due to the large number, test time for a production run of semiconductor memory devices can be long, which can increase manufacturing costs.

[0021] As described more fully below, various embodiments disclosed herein relate to testing a memory device, and more particularly to processing test data, storing test data in a buffer, and / or transferring test data to a tester. More particularly, according to some embodiments, a method of testing a memory device can include reading from a plurality of memory addresses of a memory array of the memory device, and identifying each memory address of the plurality of addresses as pass or fail. The method can further include, for each identified fail, storing data associated with the identified fail in a buffer of the memory device. In addition, the method can include transferring at least some of the data associated with each identified fail to a tester external to the memory device without transferring address data associated with each identified pass to the tester. Compared to conventional methods, devices, and systems, various embodiments of the present disclosure can reduce test time and / or reduce usage of input / output (I / O) resources of the memory device and / or associated memory system.

[0022] Although various embodiments are described herein with reference to memory devices, the present disclosure is not so limited, and embodiments can be generally applicable to microelectronic devices that can or can not include semiconductor devices and / or memory devices. Embodiments of the present disclosure will now be explained with reference to the accompanying drawings.

[0023] Figure 1A block diagram including an exemplary memory device 100 according to various embodiments of the present disclosure. The memory device 100 can include, for example, DRAM (dynamic random access memory), SRAM (static random access memory), SDRAM (synchronous dynamic random access memory), DDR SDRAM (double data rate DRAM, such as DDR4 SDRAM, etc.), or SGRAM (synchronous graphics random access memory). The memory device 100, which can be integrated on a semiconductor die, can include an array of memory cells 102.

[0024] In Figure 1 In embodiments, the array of memory cells 102 is shown to include eight banks BANK0-7. More or fewer banks can be included in the array of memory cells 102 of other embodiments. Each bank includes a plurality of access lines (word lines WL), a plurality of data lines (bit lines BL) and / BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL and / BL. Selection of the word lines WL can be performed by a row decoder 104, while selection of the bit lines BL and / BL can be performed by a column decoder 106. In Figure 1 In embodiments, the row decoder 104 can include a respective row decoder for each bank BANK0-7, while the column decoder 106 can include a respective column decoder for each bank BANK0-7.

[0025] The bit lines BL and / BL are coupled to respective sense amplifiers SAMP. Read data from the bit lines BL or / BL can be amplified by the sense amplifiers SAMP and transmitted through complementary local data lines (LIOT / B), transmission gates (TG), and complementary main data lines (MIOT / B) to a read / write amplifier 108. Conversely, write data output from the read / write amplifier 108 can be transmitted through the complementary main data lines MIOT / B, transmission gates TG, and complementary local data lines LIOT / B to the sense amplifiers SAMP and written into the memory cells MC coupled to the bit lines BL or / BL.

[0026] The memory device 100 can generally be configured to receive various inputs (e.g., from an external controller) via various terminals, such as address terminals 110, command terminals 112, clock terminals 114, data terminals 116, and data mask terminals 118. The memory device 100 can include additional terminals, such as power supply terminals 120 and 122.

[0027] During intended operation, one or more command signals COM received via command terminals 112 can be transferred to command decoder 150 via command input circuit 152. Command decoder 150 can include circuitry configured to generate various internal commands via decoding of the one or more command signals COM. Examples of internal commands include an activate command ACT and a read / write signal R / W.

[0028] Further, one or more address signals ADD received via address terminals 110 can be transferred to address decoder 130 via address input circuit 132. Address decoder 130 can be configured to provide a row address XADD to row decoder 104 and a column address YADD to column decoder 106. Although command input circuit 152 and address input circuit 132 are shown as separate circuits, in some embodiments, address signals and command signals can be received via common circuitry.

[0029] Activate command ACT can include a pulse signal activated in response to a command signal COM (e.g., an activate command) indicative of a row access. In response to activate signal ACT, row decoder 104 specifying a memory bank address can be activated. As a result, a word line WL specified by row address XADD can be selected and activated.

[0030] Read / write signal R / W can include a pulse signal activated in response to a command signal COM (e.g., a read command or a write command) indicative of a column access. In response to read / write signal R / W, column decoder 106 can be activated and a bit line BL specified by column address YADD can be selected.

[0031] In response to activate command ACT, read signal, row address XADD, and column address YADD, data can be read from a memory cell MC specified by row address XADD and column address YADD. The read data can be output via sense amplifier SAMP, transfer gate TG, read / write amplifier 108, input / output circuit 162, and data terminals 116. Further, in response to activate command ACT, write signal, row address XADD, and column address YADD, write data can be provided to memory cell array 102 via data terminals 116, input / output circuit 162, read / write amplifier 108, transfer gate TG, and sense amplifier SAMP. The write data can be written to a memory cell MC specified by row address XADD and column address YADD.

[0032] A clock signal CK and / CK can be received via clock terminals 114. Clock input circuitry 170 can generate an internal clock signal ICLK based on the clock signals CK and ICK. The internal clock signal ICLK can be communicated to various components of the memory device 100, such as command decoder 150 and internal clock generator 172. Internal clock generator 172 can generate an internal clock signal LCLK, which can be communicated to input / output circuitry 162 (e.g., to control the timing of operation of input / output circuitry 162). Further, a data mask terminal 118 can receive one or more data mask signals DM. When the data mask signals DM are activated, the corresponding data can be inhibited from being overwritten.

[0033] As described more fully below, according to some embodiments, the memory device 100 can include control circuitry 109 and a buffer 111. In some embodiments, during testing of the memory device 100, the control circuitry 109 and / or other circuitry of the memory device 100 can be configured to read data from a plurality of memory addresses of the memory cell array 102, compare the read data to known test data (e.g., data written to the memory cell array 102 and / or known data (e.g., data stored in one or more internal registers)), and responsive to the comparison, identify each of the plurality of memory addresses as either pass or fail. In other words, memory addresses associated with defective (“bad”) memory cells can be identified as “fail,” while memory addresses associated with functional (“good”) memory cells can be identified as “pass.” Further, the control circuitry 109 and / or other circuitry of the memory device 100 can be configured to, for each identified fail, store data associated with the identified fail in the buffer 111, and communicate at least some of the data associated with each identified fail to an external tester Figure 1 (not shown in FIG. 1, see Figure 3 ), without communicating address data associated with each identified pass to the external tester.

[0034] Figure 2An exemplary system 200 including a memory device 202 and a tester 204 is depicted. Generally, during testing of the memory device 202, data associated with both pass and fail bits (i.e., data associated with both pass and fail memory addresses) (e.g., 1 bit per memory cell or a group of compressed cells (e.g., up to 138X)) is transferred from the memory device 202 to the tester 204 via input / output (I / O) lines 210. Further, in this example, the tester 204 requires sufficient memory to record both pass and fail bits. As will be appreciated, generally, a majority of bits of a memory device are “good” (i.e., pass) bits. For example, in one case (e.g., in a worst case scenario), only 1 read out of 3729 reads (e.g., less than 0.027%) can result in a fail. Thus, as will be appreciated, during testing of the memory device 202, a majority of the data transferred from the memory device 202 to the tester 204 via the I / O lines 210 is associated with pass bits (“pass data”). It should also be appreciated that the transfer of large amounts of data via the I / O lines 210 limits the efficiency of the testing process (e.g., limits read speed) and undesirably uses I / O resources of the memory device 202 and / or associated memory system.

[0035] In some conventional memory device testing methods, such as global column repair (GCR), each column plane of a memory array of a memory device can generate a plurality (e.g., 8) of bits. If each bit generated via the column plane has a first state (e.g., “0”), the column plane “passes” the test (i.e., the column plane does not contain any defective memory cells), whereas if the column plane generates one or more bits having a second state (e.g., “1”), the column plane “fails” the test (i.e., the column plane contains one or more defective memory cells). Further, each row of the memory array can contain a plurality of redundant memory cells accessible via a redundant column select (RCS) line. Further, if one or more memory cells accessible via a column select line X of a row of column planes fail, the one or more memory cells accessible via the column select line X can be replaced with one or more memory cells accessible via a column select address X of a redundant column plane.

[0036] Global column repair can provide yield and / or die size advantages. However, global column repair can introduce some issues related to timing and / or size requirements. Furthermore, if error correction codes (ECC) are used (i.e., for correcting individual bits, “single-bit tolerance”), full visibility (i.e., 1X visibility) may be required to determine which specific bits failed. As will be understood, this additional visibility can increase the amount of data per failure, even more than current global column repair schemes. Other conventional test solutions may limit the amount of data and / or speed that can be read from a single die (e.g., due to shared I / O lines (e.g., on a burn-in board (BIB))).

[0037] As described above, the various embodiments disclosed herein relate to processing, storing, and / or reading test data, wherein data associated with failed memory addresses is read (e.g., read from a memory device to a tester), and it is not necessary to read data associated with passed addresses. Therefore, compared to conventional methods, apparatuses, and systems, the various embodiments can reduce the amount of data transferred from the memory device to the tester. Consequently, compared to conventional methods, apparatuses, and systems, the various embodiments can reduce the time and / or I / O resources required for reading data during test operations.

[0038] Figure 3 An exemplary system 300 according to various embodiments of the present disclosure is depicted, the system including a memory device 302 and a tester 304 (also referred to herein as a "test device"). The memory device 302 may include a memory array (e.g., Figure 1 The memory cell array 302) 306. Furthermore, the memory device 302 includes a buffer 308. In at least some embodiments, the buffer 308, also referred to herein as a “cache,” may be a first-in, first-out (FIFO) buffer. As will be understood from the embodiments disclosed herein, the buffer 308 may contain sufficient memory to store data relating to failed bits (also referred to herein as “failed memory addresses” or “failed memory cells”) of the memory array 306, and in at least some embodiments, the buffer 308 may not necessarily store data relating to passed bits (also referred herein as “passed memory addresses” or “passed memory cells”) of the memory array 306. For example, the size of the buffer 308 may depend on the buffer overflow risk (e.g., buffer overflow risk per die). In some embodiments, the semiconductor die 312 may include the memory device 302 and the buffer 308. Furthermore, although the buffer 308 is shown as being within the memory device 302, this disclosure is not limited thereto, and in some embodiments, the buffer 308 may be external to the memory device 302 (e.g., and located on the semiconductor die 312).

[0039] Memory device 302 can further include control circuitry (e.g., control circuitry 109 of Figure 1 According to various embodiments of the present disclosure, control circuitry 309 and / or other circuitry of memory device 302 can identify each of a plurality of memory addresses of memory array 306 as either passing or failing (e.g., in response to one or more write and / or read operations). In other words, memory addresses associated with defective (“bad”) memory cells can be identified as “failing,” while memory addresses associated with functional (“good”) memory cells can be identified as “passing.” Moreover, control circuitry 309 and / or other circuitry of memory device 302 can be configured to, for each identified failing, store data associated with the identified failing (e.g., the address of the failing memory cell, encoded data identifying the failing address, and / or which bits of the address failed) in buffer 308 and communicate at least some of the data associated with each identified failing (i.e., via I / O lines 310) to tester 304. According to various embodiments, there is no need to communicate address data associated with each identified passing (i.e., data associated with and / or identifying passing addresses or cells) to tester 304.

[0040] According to some embodiments, failing data (e.g., data containing memory address information and / or which bits of a memory address failed) can be buffered on buffer 308. For example, one address per read can be stored in buffer 308. In some non-limiting examples, failing data can contain all information for an associated read, including pre-fetch failing information. Alternatively or additionally, failing data can contain an encoded representation of failing and / or failing counts. Moreover, in these and other embodiments, multiple read compression or column plane compression can be used. In other words, failing data information can be encoded and recorded in buffer 308. Moreover, in some embodiments, additional information about failing can be stored as separate bits (e.g., to allow multiple addresses to be combined into one failing register). However, this can increase the chance of failing occurring in both locations and losing the specific information associated with the failing (e.g., due to a collision). The potential collision can be weighed against the increased testing time (i.e., no risk of collision).

[0041] Further, in response to a pass read (i.e., a read operation associated with no at least one defective memory cell), additional pass data (e.g., associated with the previous pass) can be transferred from the memory device 302 (e.g., from the buffer 308) to the tester 304 (e.g., via the at least one input / output (I / O) circuit). Further, in some embodiments, as described more fully below, some of the pass data (e.g., address information) can be serially transferred from the memory device 302 (e.g., from the buffer 308) to the tester 304. In other embodiments, as also described more fully below, the tester 304 can be configured to align the pass data with associated addresses based on the order in which the pass data is received.

[0042] A non-limiting exemplary method of testing a memory device, including processing, storing, and transferring fail data to a tester, will now be described in more detail with reference to Figure 3 , 4A , 4B, and 5. In a first exemplary method of processing, storing, and transferring fail data (also referred to herein as“Method A”), address information is not stored in the buffer 308 or transferred from the memory device 302 to the tester 304. Rather, each pass and fail is indicated or represented in a data stream (e.g., a burst of data or a continuous data stream), which can be stored on the buffer 308 and transferred to the tester 304. Further, the tester 304 is configured to align address information with the data received from the buffer 308. In other words, the tester 304 is configured to synchronize incoming data with a particular memory address associated with a previously issued read command. In other words, the tester 304 can send a read command to the memory device 302 for a particular memory address, and in response thereto, the memory device 302 can send a data stream (e.g., a burst of data) associated with the particular memory address. Further, as described more fully below, information contained in the data stream can enable the tester 304 to track which memory address is associated with the fail data.

[0043] More specifically, the tester 304 can issue a read command for a particular memory address, which can include, for example, 128 bits. Data can be read from the memory array 306 and compared to known data (e.g., data written to the memory array 306 or data from an internal register) to identify fail and / or pass bits. If at least one bit of the 128 bits fails (i.e., at least one memory element fails (“a fail event”)), a data burst (also referred to herein as a “burst of data”) can begin with a fail indicator bit (e.g., binary “1”), and the remainder of the data burst can identify which bits of the 128 bits failed. Further, if each bit of the 128 bits passes, the data burst can begin with a pass indicator bit (e.g., binary “0”), and the remainder of the data burst can include a count value representing the number of consecutive pass bits (e.g., since the last fail). In other words, the count value (i.e., binary value) can indicate the number of consecutive passes (e.g., since the last fail event).

[0044] A more specific example (i.e., of Method A) will now be described. Note that in this example, five read commands are issued, addresses 0 and 4 fail (i.e., addresses 0 and 4 are associated with defective (“bad”) memory elements), and addresses 1, 2, and 3 pass (i.e., addresses 1, 2, and 3 are associated with operational (“good”) memory elements). Further, in this example, the tester 304 can issue one read command at a time, or can combine more than one read command. In this example, at least one of the 128 bits of address 0 fails (i.e., at least one memory element fails), and thus, the memory device 302 sends a data burst that starts with a fail indicator bit (“1”), and the remainder of the data burst (e.g., N bits) can identify which of the 128 bits of address 0 failed. Upon receiving the data burst, the tester 304 can align the data burst with address 0. Further, in this example, each of the 128 bits of address 1 passes, and thus, the memory device 302 sends a data burst that starts with a pass indicator bit (“0”). The data burst further contains a count of the number of consecutive passes (e.g., since the last fail or since the first read). More specifically, in this example, the second data burst can contain “0…1”, where “0” is the pass indicator bit, and “1” is a binary representation of one (1) “pass” since the last fail event (i.e., for address 0). Further, the third data burst can contain “0…10”, where “0” is the pass indicator bit, and “10” is a binary representation of two (2) “passes” since the last fail event (i.e., for address 0). Also, in this example, the fourth data burst can contain “0…11”, where “0” is the pass indicator bit, and “11” is a binary representation of three (3) consecutive “passes” since the last fail event (i.e., for address 0). Further, the fifth data burst can contain “1…XX”, where “1” is the fail indicator bit, and “XX” identifies which of the bits of address 4 failed.

[0045] As will be appreciated by one of ordinary skill in the art, based on the order of the read commands issued by the tester 304 and the order of the data bursts received at the tester 304, the tester 304 can determine which memory address should be associated with which data burst.

[0046] As will be appreciated, a buffer overflow can occur if the amount of data sent to the buffer 308 exceeds the storage capacity of the buffer 308. According to some embodiments, a buffer overflow can be considered a "pass" and, in response to a buffer overflow, a data burst can begin with a pass indicator bit (e.g., "0") and the count value (i.e., provided with the data burst) can be incremented, as described above. In some embodiments, in response to an overflow or to prevent an overflow, additional "fails" can be considered "passes" (i.e., if the buffer 308 is full) and / or a multi-read compression scheme can be employed. In some embodiments, a test flow can be designed such that a fortuitous overflow and associated false passers (i.e., fail bits that are ignored during a buffer overflow) can be captured by accessing the array in a different order in subsequent tests. Also, in some embodiments, one of the bits of the pass register (the MSB or the next bit after the initial zero) can be used to indicate that an overflow exists and the tester (e.g., the tester 304) can treat the passer count as all fails or the tester can retest the portion.

[0047] As described above, data can be transferred from the buffer 308 to the tester 304 in data bursts or continuous data streams. More specifically, in some embodiments, data can be transferred in data bursts in response to a read from the tester 304. In these embodiments, the tester 304 can be able to write to the memory device 302 between reads. According to other embodiments in which data is transferred in a continuous stream (e.g., a single continuous stream), an internal register (i.e., an internal register of the memory device 302) can write to the memory device 302.

[0048] In various embodiments, multiple read operations (e.g., issued by the tester 304) can be combined (e.g., "XORed" together bit by bit in multi-read compression) and attributed to the same address register in the buffer 308. Further, in at least some embodiments, prefetch data can be compressed (e.g., via encoding) prior to being stored in the buffer 308. For example, 128 bits of prefetch data can be compressed to, for example, 16 bits (e.g., for global column repair), 8 bits, or any other suitable value.

[0049] Figure 4A and 4B are exemplary illustrations depicting snapshots of data within the buffer 308 according to various embodiments of the present disclosure. More specifically, Figure 4A depicts a snapshot of data within the buffer 308 at some time (e.g., time = ti), and Figure 4B depicts a snapshot of data within the buffer 308 at a subsequent time (e.g., time = t2).

[0050] Figure 4AThe table 400 is depicted as containing a plurality of rows, where each row contains a burst count (BC), an indicator bit (i.e., for the fail / pass (F / P) column), and a number of bits of fail information or pass count. For example, for bit count 0, the indicator bit is "1" (i.e., indicating a fail), and each "V" represents valid fail data. For bit count 1, the indicator bit is "0" (i.e., indicating a pass), and the count of the number of consecutive passes is "000000011" (i.e., indicating 4 consecutive passes since the last fail). Further, for bit count 2, the indicator bit is "1" (i.e., indicating a fail), and each "V" represents valid fail data. For bit count 3, the indicator bit is "0" (i.e., indicating a pass), and the count of the number of consecutive passes is "000000001" (i.e., indicating 1 pass since the last fail).

[0051] Figure 4A The table 410 is further depicted as containing exemplary bits within a serial data output register (e.g., a register of the buffer 308 of the tester 304). As will be appreciated, the data from the table 400 (i.e., the data from the bottom row of the table 400 (i.e., bit count = 0)) can be transferred to the serial data output register before being transferred (e.g., to the tester 304). In this example, the first bit of the serial data output register is the indicator bit (e.g., "1" indicating a fail), while the "V" represents valid fail data. Figure 3

[0052] Figure 4B The table 400' is depicted as containing a plurality of rows, where each row contains a burst count (BC), an indicator bit (i.e., for the fail / pass (F / P) column), and a number of bits of fail information or pass count. Figure 4B The table 410' is further depicted as containing exemplary bits within a serial data output register (e.g., a register of the buffer 308 of the tester 304). As will be appreciated, the data from the table 400' (i.e., the data from the bottom row of the table 400' (i.e., bit count = 0)) is now shown in the serial data output register of the table 410'. Figure 3 Figure 4B Figure 4A

[0053] ​​​​A second exemplary method of handling, storing, and / or transferring fail data (also referred to herein as“Method B”) will now be described. In this exemplary method, multiple read commands can occur, including internal and external read commands. More specifically, in response to one or more internal read commands (i.e., read commands internal to the memory device 302), data can be read from the memory array 306 and compared to known data (e.g., data written to the memory array 306 or data from internal registers) to identify each of a plurality of memory addresses of the memory array 306 as either passing (“pass addresses”) or failing (“fail addresses”). In response to the identification of fail addresses, fail data can be stored in the buffer 308, which in this embodiment can include full read address information and prefetch information for the fail addresses. For example, the fail address information can be encoded (e.g., 2X compression (XOR), 4X, 8X, but not limited thereto), or can include IX representation (i.e., full visibility). Further, in response to another read command (e.g., an external read command), the next fail address in the buffer 308 can be transferred (e.g., in a data burst) to the tester 304. In some embodiments, during the external read command, one or more additional internal read commands for one or more other memory addresses of the memory array 306 can occur, and any address information for any identified fail addresses can be added to the buffer 308.

[0054] In this embodiment, as described above, full address information (i.e., the actual memory address of the failing memory element) can be stored in the buffer 308 and transferred to the tester 304. Thus, in this embodiment, the tester 304 is not required to determine which memory address should be associated with the received fail data. In other words, in this embodiment, because the tester 304 receives memory address information for the fail addresses, the tester 304 is not required to determine and track which address is associated with the received fail data.

[0055] It should be noted that in this embodiment, because the data burst includes full address information (i.e., the fail address and which bits failed), the length of the data burst can be longer than a conventional compressed read. For example, for a 16G memory device, 34 bits can be required to represent each read address using an encoded column plane approach and encoded prefetch bits. In this example, 7 bits of the 34 bits can be prefetch bits, while 1 bit can be an indicator bit.

[0056] Further, in various embodiments, multiple read operations can be combined (e.g., XORed together bit by bit in multi-read compression) and attributed to the same address register in the buffer 308. These embodiments can require longer data bursts and can increase the risk of collisions, but can reduce the number of external reads (i.e., reads to the buffer 308).

[0057] Figure 5 is a timing diagram 500 illustrating exemplary operations of the above-described method B. The timing diagram 500 includes a clock signal 502, a plurality of commands 504, and data 506 output from a memory device (e.g., the memory device 302 of Figure 3 , to a tester (e.g., the tester 304 of Figure 3 ). As will be appreciated, the data 506 includes full address information for the fails, including bank group (BG), bank (B), row (R), and column (C) data. It should be noted that the data 506 is an exemplary data set, and in some embodiments, more or less data can be included in the data burst.

[0058] Another exemplary method (also referred to herein as “method C”) for processing, storing, and / or communicating fail data will now be described. In this exemplary method, the buffer 308 includes a serial FIFO buffer (e.g., a unit serial buffer). In this embodiment, data can be read from the memory array 306 and compared to known data (e.g., data written to the memory array 306 or data from internal registers) to identify each of a plurality of memory addresses of the memory array 306 as either a pass (“pass address”) or a fail (“fail address”). In response to a fail address, fail data is stored in the buffer 308. In this embodiment, the fail data, which can be encoded (e.g., 2X, 4x, 8X) or decoded (IX), need not include full address information.

[0059] Further, in this embodiment, at least two bits are communicated from the memory device 302 to the tester 304 in response to a read command. The first bit transmitted from the memory device 302 to the tester 304 includes an indicator bit that indicates whether the memory address associated with the read command is a pass or a fail. For example, if the memory address fails, the first bit (i.e., the indicator bit) communicated from the memory device 302 to the tester 304 can include a “1,” and if the memory element passes, the first bit (i.e., the indicator bit) communicated from the memory device 302 to the tester 304 can include a “0.” The second bit transmitted to the tester 304 can include the next bit of the fail data from the buffer 308.

[0060] More specifically, for example, if address 0 is read (e.g., a first read operation) and fails, the first bit transmitted to the tester 304 (i.e., in response to the read) will be a “1” and the second bit transmitted to the tester 304 will be the fail data associated with address 0 and stored in the buffer 308. Continuing with this example, if address 1 is then read (e.g., a second read operation) and address 1 also fails, the first bit transmitted to the tester 304 (i.e., in response to the second read operation) will be a “1” and the second bit transmitted to the tester 304 will be the next bit of the fail data stored in the buffer 308 (e.g., the fail data associated with address 0). Continuing with this example, if address 3 is then read (e.g., a third read operation) and address 3 passes, the first bit transmitted to the tester 304 (i.e., in response to the third read operation) will be a “0” and the second bit transmitted to the tester 304 will be the next bit of the fail data stored in the buffer 308 (e.g., the fail data associated with address 0).

[0061] In this embodiment, the tester 304 is configured to synchronize incoming data with a particular memory address. In other words, the tester 304 can issue a read command for a particular memory address and the next bit received (i.e., the first bit in response to the read command) indicates whether the particular memory address passed or failed. In other words, the tester 304 can send a read command to the memory device 302 for a particular memory address and, in response, the memory device 302 can transmit data associated with the particular memory address. Moreover, as described more fully below, information contained in the data can enable the tester 304 to track which memory address is associated with the fail data.

[0062] As will be appreciated, in this embodiment, the "pass through" allows the tester 304 to "catch up" and receive the fail data associated with the previous fail address. As an example, if address 0 is read (e.g., a first read operation) and fails, the first bit transmitted to the tester 304 (i.e., in response to the read) will be a "1" and the second bit transmitted to the tester 304 will be the fail data associated with address 0 and stored in the buffer 308. Further, if each of addresses 1-10 are read and pass (e.g., in response to 10 read operations), the first bit in each bit sequence transmitted to the tester 304 in response to each of the 10 reads will be a "0" and the second bit in each bit sequence transmitted to the tester 304 in response to each of the 10 reads will be the next bit of the fail data in the buffer 308 (i.e., the fail data associated with address 0). Thus, the "pass through" allows data associated with a previous fail to be transmitted from the memory device 302 to the buffer 308. It should be noted that if the buffer 308 is empty, the second bit of the bit sequence transmitted to the tester 304 (i.e., in response to one or more of the 10 read commands) can be 0. In this embodiment, data is transferred to the tester 304 in response to read commands, thus other operations (e.g., write operations) can occur (e.g., between read operations).

[0063] In at least this embodiment, the tester 304 can know that each fail can contain a known number of bits. Thus, in response to a fail, the tester 304 can count the data bits (second bits of the burst) and associate the bits with the first fail address until all of the data bits for that fail have been transferred. If another fail occurs during the transfer time, it can be assumed that the fail information for the next fail will start flowing immediately (i.e., during the second bit). The tester 304 can associate the data with the second fail address (i.e., based on when the first bit failed in testing). If no additional fails occur during the transfer of the fail data, the tester 304 can not record any data bits and the tester 304 can wait for the next fail (i.e., first bit is 1). In response to another fail, the tester 304 can again count the data bits and associate the data bits with the fail. Thus, generally, the first bit indicates the address based on which address was read to create the fail. The address is stored in a buffer (e.g., FIFO) on the tester 304 and when the data is received, the tester 304 applies the address to the data.

[0064] As will be appreciated, various embodiments described herein (e.g., Method A, Method B, and / or Method C) can reduce test time (e.g., at burn-in) and can allow for reading at a maximum design support test clock. Further, various embodiments can allow for IX visibility (e.g., for reading ECC conflict bits). In these embodiments, data can be compared to data in on-die registers to achieve IX visibility (e.g., using an XOR comparison). Further, some embodiments disclosed herein can allow for other repair schemes that are not currently feasible due to reduced compression. Also, some embodiments can allow for additional data compression (e.g., bank group compression). Further, in embodiments in which memory built-in self-test (MBIST) contains a separate clock (e.g., an internal oscillator), a faster clock can be run on a slower tester and data streams can be output at a slower speed. Also, various embodiments can allow for spanning multiple clocks at each address bit during repair testing (e.g., running at a faster test clock) (e.g., to reduce test time at burn-in).

[0065] Figure 6 is a flow diagram of an exemplary method 600 of testing a memory device in accordance with various embodiments of the present disclosure. The method 600 can be arranged in accordance with at least one embodiment described in the present disclosure. In some embodiments, the method 600 can be performed by a memory device 100 such as Figure 1 the memory device 100 of FIG. 1, Figure 3 the system 300 of FIG. 3, Figure 3 the memory device 302 of FIG. 3, Figure 7 the memory system 700 of FIG. 7, or another device or system. Although shown as a discrete block, individual blocks can be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0066] The method 600 can begin at block 602, where data can be read from a plurality of memory addresses of a memory array of a memory device, and the method 600 can proceed to block 604. For example, with reference to Figure 3 in response to a read command (e.g., issued by the tester 304 of FIG. 4), data can be read from a plurality of memory addresses of the memory array 306.

[0067] At block 604, each memory address of the plurality of addresses can be identified as pass or fail, and the method 600 can proceed to block 606. For example, data read from memory addresses of the memory array 306 can be compared to known data (e.g., data written to the memory array 306 or data from internal registers) to identify each memory address of the plurality of memory addresses as a pass address or a fail address.

[0068] At block 606, for each identified fail, data associated with the identified fail can be stored in a buffer on the memory device, and the method 600 can proceed to block 608. For example, the data associated with each identified fail can be stored in the buffer 308 of Figure 3 In some embodiments, an indicator bit and fail data for each fail bit that identifies the identified fail or a count indicating a number of consecutive identified passes can be stored in the buffer. In other embodiments, a memory address of the identified fail can be stored in the buffer. In yet other embodiments, data for each fail bit that identifies the identified fail can be stored in the buffer.

[0069] At block 608, at least some of the data associated with each identified fail can be transferred from the memory device to the tester without transferring address data associated with each identified pass. For example, with reference to Figure 3 In some embodiments, an indicator bit and fail data for each fail bit that identifies the identified fail or a count indicating a number of consecutive identified passes can be stored in the buffer. In other embodiments, a memory address of the identified fail can be stored in the buffer. In yet other embodiments, data for each fail bit that identifies the identified fail can be stored in the buffer.

[0070] Modifications, additions, or omissions can be made to the method 600 without departing from the scope of the present disclosure. For example, the operations of the method 600 can be implemented in differing order. Additionally, the outlined operations and actions are provided as examples, and some operations and actions can be optional, combined into fewer operations and actions, or expanded into additional operations and actions without detracting from the essence of the disclosed embodiments.

[0071] A system is also disclosed. According to various embodiments, the system can include a tester and one or more memory devices (e.g., the memory device 100 of Figure 1 ). Figure 7 is a simplified block diagram of a memory system 700 implemented in accordance with one or more embodiments described herein. The memory system 700, which can include, for example, a memory test system, includes a plurality of memory devices 702 and a tester 704, which can include, for example, the tester 304 (see Figure 3), as described herein. Tester 704 can be operably coupled with memory devices 702, where each memory device 702 can include or can be coupled to circuitry for performing one or more embodiments disclosed herein.

[0072] Various embodiments of the present disclosure can include a method of testing a memory device. The method can include reading from a plurality of memory addresses of a memory array of the memory device and identifying each memory address of the plurality of addresses as either passing or failing. The method can further include, for each identified fail, storing data associated with the identified fail in a buffer of the memory device. In addition, the method can include transferring at least some of the data associated with each identified fail to a tester external to the semiconductor die without transferring address data associated with each identified pass to the tester.

[0073] According to another embodiment of the present disclosure, an apparatus can include a memory array and a buffer coupled to the memory array. The apparatus can further include circuitry coupled to the memory array and the buffer and configured to read data from a plurality of memory addresses of the memory array. The circuitry can also be configured to compare the read data to known test data. In addition, the circuitry can be configured to identify each memory address of the plurality of memory addresses as either passing or failing in response to the comparison. Moreover, the circuitry can be configured to, for each identified fail, store data associated with the identified fail in the buffer. The circuitry can further be configured to transfer at least some of the data associated with each identified fail to an external tester without transferring address data associated with each identified pass to the external tester.

[0074] Additional embodiments of the present disclosure include a system. The system can include a testing device and at least one memory device operably coupled to the testing device. The memory device can include a memory array comprising a plurality of memory addresses. The memory device can also include a first-in-first-out (FIFO) cache and at least one circuit. The at least one circuit can be configured to, in response to at least one testing operation, identify each memory address of the plurality of memory addresses as either passing or failing. The at least one circuit can also be configured to, for each identified fail, store a plurality of fail data bits associated with the identified fail in the FIFO cache. In addition, the at least one circuit can be configured to transfer at least some of the plurality of fail data bits associated with each identified fail to the testing device without transferring address data associated with each identified pass to the testing device.

[0075] As is customary, the various features shown in the accompanying drawings may not be drawn to scale. The illustrations presented in this disclosure are not intended to be actual views of any particular device (e.g., apparatus, system, etc.) or method, but are merely idealized representations used to describe various embodiments of this disclosure. Therefore, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Additionally, some drawings may be simplified for clarity. Therefore, the drawings may not depict all components of a given device (e.g., apparatus) or all operations of a particular method.

[0076] As used herein, the terms "apparatus" or "memory device" may include, but are not limited to, devices having only memory. For example, an apparatus or memory device may include memory, a processor, and / or other components or functions. For example, an apparatus or memory device may include a system-on-a-chip (SoC).

[0077] As used herein, unless otherwise specified, the term “semiconductor” shall be interpreted broadly to include microelectronic and MEMS devices (e.g., magnetic storage, optical devices, etc.) that may or may not operate using semiconductor functions.

[0078] The terms used herein, particularly in the appended claims (e.g., the body of the appended claims), are generally expected to be “open” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “having at least”, the term “includes” should be interpreted as “including but not limited to”, etc.).

[0079] Furthermore, if a specific number of the introduced claim statements are required, such intent will be explicitly stated in the claims, and if no such statements are present, such intent does not exist. For example, to aid understanding, appended claims may use the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that introducing a claim statement with the indefinite article “a (a / an)” would limit any particular claim containing this introduced claim statement to an embodiment containing only one of such statements, even if the same claim contains the introductory phrases “one or more” or “at least one” and the indefinite article (e.g., “a (a / an)”) (e.g., “a (a / an)” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles used to introduce claim statements. As used herein, “and / or” includes any and all combinations of one or more of the related listed items.

[0080] Also, even if a specific number of an introduced claim recitation is explicitly recited, it should be understood that such recitation should be interpreted to mean at least the recited number (e.g., reciting "two widgets" means at least two widgets or two or more widgets). Moreover, when a claim recitation similar in structure to "at least one of A, B and C" is used, it will be understood that each of the items A, B, and C can be individually used precluding the use of A, B and C collectively, unless otherwise indicated. For example, the use of "A and / or B" will be understood to include A alone, B alone, or A and B together.

[0081] Also, any disjunctive word or phrase presenting two or more alternative terms, whether in

[0082] In addition, the use of the terms "first," "second," "third," etc. do not necessarily imply a specified order or quantity. Generally, the terms "first," "second," "third," etc. are used as generic identifiers to distinguish between different elements having the same name. If the terms "first," "second," "third," etc. are used to imply a specific order or quantity, those terms will be unambiguously indicated. Furthermore, the use of the terms "first," "second," "third," etc. to identify different elements does not imply a specific number of elements. The use of the terms "first," "second," "third," etc. to identify different elements does not imply a specific number of elements.

[0083] The embodiments of the disclosure described above and illustrated in the drawings are not intended to limit the scope of the disclosure, which is encompassed by the claims below and their legal equivalents. Any equivalent embodiments are within the scope of the disclosure. Indeed, various modifications of the disclosure, in addition to those described herein, will become apparent to those skilled in the art from the description. Such modifications are also intended to fall within the scope of the appended claims and equivalents thereof.

Claims

1. A method of testing a memory device, comprising: reading from a plurality of memory addresses of a memory array of the memory device; identifying each memory address of the plurality of memory addresses as either passing or failing; for each identified fail, storing data associated with the identified fail in a buffer of the memory device; and transmitting at least some of the data associated with each identified fail to a tester external to the memory device without transmitting address data associated with each identified pass to the tester.

2. The method of claim 1, wherein storing the data associated with each identified fail comprises, for each identified fail, storing a fail indicator bit and fail data identifying each fail bit of the identified fail.

3. The method of claim 2, wherein transmitting comprises transmitting the fail indicator bit and the fail data from the buffer to the tester.

4. The method of claim 2, further comprising, for each identified pass, storing a pass indicator bit and a count indicating a number of consecutively identified passes.

5. The method of claim 4, further comprising transmitting the pass indicator bit and the count from the buffer to the tester.

6. The method of claim 1, wherein storing the data associated with each identified fail comprises, for each identified fail, storing a memory address of the identified fail.

7. The method of claim 6, wherein transmitting comprises transmitting the memory address of the identified fail from the buffer to the tester.

8. The method of claim 1, wherein storing the data associated with each identified fail comprises, for each identified fail, storing fail information identifying each fail bit of the identified fail.

9. The method of claim 8, wherein transmitting comprises transmitting a pass indicator bit or a fail indicator bit and at least a next bit of the fail information stored in the buffer to the tester.

10. An apparatus, comprising: a memory array; a buffer coupled to the memory array; and circuitry coupled to the memory array and the buffer and configured to: read data from a plurality of memory addresses of the memory array; compare the read data to known test data; in response to the comparison, identify each memory address of the plurality of memory addresses as either passing or failing; for each identified fail, store data associated with the identified fail in the buffer; and transmit at least some of the data associated with each identified fail to an external tester without transmitting address data associated with each identified pass to the external tester.

11. The apparatus of claim 10, wherein the buffer comprises a first-in-first-out (FIFO) buffer.

12. The apparatus of claim 10, wherein the circuitry is further configured to: store, for each identified fail, a fail indicator bit and fail information for each fail bit identifying the identified fail; transfer the fail indicator bit and the fail information from the buffer to the external tester; store, for each identified pass, a pass indicator bit and a count indicating a number of consecutive identified passes; and transfer the pass indicator bit and the count from the buffer to the external tester.

13. The apparatus of claim 10, wherein the circuitry is further configured to: store, for each identified fail, a memory address of the identified fail; and transfer the memory address of the identified fail from the buffer to the external tester.

14. The apparatus of claim 10, wherein the buffer comprises a serial buffer.

15. The apparatus of claim 14, wherein the circuitry is further configured to: store, for each identified fail, fail information for each fail bit identifying the identified fail in the serial buffer; and transfer a pass or fail indicator bit and at least a next bit of the fail information stored in the serial buffer to the external tester.

16. A system comprising: a test apparatus; and at least one memory apparatus operably coupled to the test apparatus and comprising: a memory array comprising a plurality of memory addresses; a first-in-first-out (FIFO) cache; and at least one circuit configured to: identify each memory address of the plurality of memory addresses as a pass or a fail in response to at least one test operation; store, for each identified fail, a plurality of fail data bits associated with the identified fail in the FIFO cache; and transfer at least some of the fail data bits associated with each identified fail to the test apparatus without transferring address data associated with each identified pass to the test apparatus.

17. The system of claim 16, wherein the at least one circuit is further configured to: store, for each identified fail, a first indicator bit and fail data for each fail bit identifying the identified fail in the FIFO cache; transfer the first indicator bit and the fail data to the test apparatus; store, for each identified pass, a second, different indicator bit and a count value indicating a number of consecutive identified passes in the FIFO cache; and transfer the second, different indicator bit and the count value to the test apparatus.

18. The system of claim 16, wherein the at least one circuit is configured to transfer the at least some of the plurality of fail data bits in a data burst or a single data stream.

19. The system of claim 16, wherein: in response to a first read command, the at least one circuit is configured to store the identified failed memory addresses in the FIFO cache; and in response to a second read command, the at least one circuit is configured to transfer the identified failed memory addresses to the test device.

20. The system of claim 16, wherein the at least one circuit is further configured to: for each identified fail, store data identifying each fail bit of the identified fail in the FIFO cache; and transfer a pass or fail indicator bit and at least a next one of the plurality of fail data bits stored in the FIFO cache to the test device.

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