Patterning method

Abstract

The present invention provides a patterning method, comprising the following steps: sequentially forming a doped polysilicon layer, a core layer, and an undoped polysilicon layer on a target layer; patterning the undoped polysilicon layer to form a polysilicon pattern; performing a first etching process using the polysilicon pattern as a mask to remove a portion of the core layer and form a core pattern; performing a second etching process to remove the polysilicon pattern; performing an atomic layer deposition process to form a spacer material on the core pattern and the doped polysilicon layer; removing a portion of the spacer material to form spacers on the sidewalls of the core pattern; and removing a portion of the core pattern and the doped polysilicon layer below it.

Description

Technical Field

[0001] The present invention relates to a patterning method. Background Art

[0002] With technological advancements, all types of electronic products are trending toward becoming thinner, lighter, and smaller. This trend is driving the shrinking critical dimensions of semiconductor devices, making photolithography increasingly challenging. In existing photolithography processes, methods for reducing critical dimensions include using optical devices with larger numerical apertures (NA), shorter exposure wavelengths (such as EUV), or interfacial media other than air (such as water immersion). As the resolution of existing photolithography processes approaches their theoretical limits, manufacturers have begun turning to double-patterning (DP) methods to overcome optical limitations and increase the integration density of semiconductor devices.

[0003] However, in the current double patterning method, the spacer on the sidewall of the core pattern has a poor roughness. Therefore, the current double patterning method still faces some challenges. Summary of the Invention

[0004] The present invention provides a patterning method, which can improve the roughness of the spacer on the sidewall of the core pattern, so that the target pattern formed subsequently has better sidewall uniformity.

[0005] The present invention provides a patterning method comprising the following steps. A doped polysilicon layer, a core layer, and an undoped polysilicon layer are sequentially formed on a target layer. The undoped polysilicon layer is patterned to form a polysilicon pattern. A first etching process is performed using the polysilicon pattern as a mask to remove a portion of the core layer and form a core pattern. A second etching process is performed to remove the polysilicon pattern. An atomic layer deposition process is performed to form a spacer material on the core pattern and the doped polysilicon layer. A portion of the spacer material is removed to form spacers on the sidewalls of the core pattern. A portion of the core pattern and the doped polysilicon layer thereunder are removed.

[0006] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1N FIG. 4 is a cross-sectional schematic diagram of a manufacturing process of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0008] The present invention will be more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. Identical or similar reference numerals denote identical or similar components, and detailed descriptions will not be repeated in the following paragraphs.

[0009] Figures 1A to 1N The figure is a cross-sectional schematic diagram illustrating the manufacturing process of a semiconductor structure according to one embodiment of the present invention. This semiconductor structure may be a control gate (CG) of a memory device, but the present invention is not limited thereto. In other embodiments, this semiconductor structure may also be a contact window of a memory device, an active area (AA) of a dynamic random access memory (DRAM), an interconnect structure of a logic device, or a combination thereof.

[0010] Please refer to Figure 1A This embodiment provides a method for fabricating a semiconductor structure, comprising the following steps. First, a target layer 100 is provided. In some embodiments, the target layer 100 may be a polysilicon layer, which may be used as a control gate of a memory device. However, the present invention is not limited thereto. In other embodiments, the target layer 100 may also be a metal layer (e.g., a tungsten layer), a silicon substrate, a dielectric layer, or a combination thereof.

[0011] Next, a nitride layer 102, an oxide layer 104, a doped polysilicon layer 106, a core layer 108, an undoped polysilicon layer 110, a hard mask layer 112, and a photoresist pattern 118 are sequentially formed on the target layer 100. In one embodiment, the nitride layer 102 may be silicon nitride with a thickness of 1 nm to 1000 nm. The oxide layer 104 may be a plasma enhanced tetraethyl orthosilicate (PETEOS) layer with a thickness of 1 nm to 1000 nm. The doped polysilicon layer 106 may be formed by an ion implantation process using dopants with a thickness of 1 nm to 1000 nm. In this embodiment, the dopants may be N-type and / or P-type dopants, such as BF 2+ 、B + 、F + 、P +or a combination thereof. The core layer 108 may be a low-pressure tetraethyl orthosilicate (LPTEOS) layer, any silicon oxide, or a combination thereof, and has a thickness of 1 nm to 1000 nm. The undoped polysilicon layer 110 may be an intrinsic polysilicon layer, and has a thickness of 1 nm to 1000 nm. The hard mask layer 112 may include a carbide layer 114 and an anti-reflective layer 116 located on the carbide layer 114. The material of the carbide layer 114 includes spin-on-carbon (SoC); and the material of the anti-reflective layer 116 includes silicon oxynitride. The thickness of the hard mask layer 112 is 1 nm to 1000 nm. The photoresist pattern 118 may include a positive photoresist or a negative photoresist, and has a thickness of 1 nm to 1000 nm.

[0012] It is worth noting that in this embodiment, the doped polysilicon layer 106 and the undoped polysilicon layer 110 have different doping concentrations. Specifically, the doping concentration of the doped polysilicon layer 106 can be greater than the doping concentration of the undoped polysilicon layer 110. Therefore, this embodiment can increase the etch selectivity between the doped polysilicon layer 106 and the undoped polysilicon layer 110 in the subsequent second etching process to prevent the underlying doped polysilicon layer 106 from being removed. Please refer to the following paragraphs for details.

[0013] Please refer to Figure 1B and Figure 1C Using the photoresist pattern 118 as a mask, the hard mask layer 112 and the undoped polysilicon layer 110 are patterned to form a polysilicon pattern 210 and a hard mask pattern 212 (which includes a carbide pattern 214 and an anti-reflective pattern 216). In one embodiment, the core layer 108 can be considered an etch stop layer in the aforementioned patterning process. In this case, the top surface of the core layer 108 is exposed at the polysilicon pattern 210 and the hard mask pattern 212. The photoresist pattern 118 and the hard mask pattern 212 are then removed.

[0014] Please refer to Figures 1C to 1E , using the polysilicon pattern 210 as a mask, a first etching process is performed to remove a portion of the core layer 108 and form a core pattern 208. Specifically, the first etching process includes a dry etching step to form an opening 10 in the core layer 108a. In this case, Figure 1DAs shown, the sidewalls 108s of the core layer 108a are flush with the sidewalls 210s of the polysilicon pattern 210a. The first etching process also includes a wet etching step to trim the core layer 108a so that the sidewalls 208s of the core pattern 208 are recessed relative to the sidewalls 210s of the polysilicon pattern 210. From another perspective, the opening 10 is expanded to the opening 12, so that the width of the core pattern 208 is smaller than the width of the core layer 108a. In one embodiment, the doped polysilicon layer 106 can be considered as an etch stop layer in the above-mentioned first etching process. That is, in the above-mentioned first etching process, most of the core layer 108 is removed, while the doped polysilicon layer 106 is not removed or only a small amount is removed.

[0015] Please refer to Figures 1E to 1F , a second etching process is performed to remove the polysilicon pattern 210a. In one embodiment, the second etching process may be a wet etching process, which includes using an etching solution of ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH) or a combination thereof. In the second etching process, the etching rate of the polysilicon pattern 210a is greater than the etching rate of the doped polysilicon layer 106. That is, in the second etching process, the polysilicon pattern 210a is completely removed, while the doped polysilicon layer 106 is not removed or is only slightly removed. Figure 1F As shown, the opening 12 may extend downward to form a recess 14 on the doped polysilicon layer 106. However, the present invention is not limited thereto. In other embodiments, the top surface of the doped polysilicon layer 106 exposed in the opening 12 may also be a flat surface. In this embodiment, in the second etching process described above, the etching selectivity ratio between the doped polysilicon layer 106 and the polysilicon pattern 210a is 15 to 100 to ensure that the polysilicon pattern 210a is completely removed while the doped polysilicon layer 106 remains and covers the underlying oxide layer 104.

[0016] Please refer to Figure 1G, an atomic layer deposition (ALD) process is performed to form a spacer material 120 on the core pattern 208 and the doped polysilicon layer 106. The spacer material 120 conformally covers the surface of the core pattern 208 and the surface of the doped polysilicon layer 106. In the present embodiment, the spacer material 120 can be a dielectric material, such as ALD silicon nitride, any silicon nitride (for example, chemical vapor deposition (CVD) silicon nitride), or a combination thereof. This ALD silicon nitride not only has better step coverage but also has better surface uniformity. Specifically, the surface roughness of the spacer material 120 of the present embodiment can be less than 3nm. This surface roughness can be regarded as the height difference between the highest point and the lowest point on the surface of the spacer material 120. In some embodiments, the spacer material 120 can have a uniform thickness, which is 1nm to 100nm.

[0017] Please refer to Figure 1G and Figure 1H , removing a portion of the spacer material 120 to form spacers 220 on the sidewalls of the core pattern 208. Specifically, the spacer material 120 on the top surface of the core pattern 208 and the top surface of the doped polysilicon layer 106 can be removed by an anisotropic etching process (e.g., reactive ion etching (RIE)). In one embodiment, the spacer 220 includes a first sidewall 220s1 and a second sidewall 220s2 opposing each other. The first sidewall 220s1 contacts the sidewall of the core pattern 208 and is perpendicular to the bottom surface of the core pattern 208. The second sidewall 220s2 is away from the sidewall of the core pattern 208 and is inclined relative to the bottom surface of the core pattern 208. In this embodiment, the inclined second sidewall 220s2 can be a curved surface.

[0018] Please refer to Figure 1I A dielectric layer 122, a mask layer 124, and a photoresist pattern 126 are sequentially formed on the core pattern 208. In one embodiment, the dielectric layer 122 may be a spin-on carbon (SoC) layer, which fills the opening 12 and extends to cover the top surface of the core pattern 208. The mask layer 124 may be a spin-on silicon anti-reflective layer (SOSA) with a thickness of 1 nm to 100 nm. The photoresist pattern 126 may include a positive photoresist or a negative photoresist with a thickness of 1 nm to 1000 nm.

[0019] It is worth noting that in this embodiment, the photoresist pattern 126 covers the first portion 208a of the core pattern 208, but does not cover the second portion 208b of the core pattern 208. The sidewall of the photoresist pattern 126 may correspond to the opening 12. Figure 1IAs shown, the width W1 of the first portion 208a may be greater than the width W2 of the second portion 208b. In one embodiment, the ratio of the width W1 to the width W2 is 1 to 10,000.

[0020] Please refer to Figure 1I and Figure 1J , using the photoresist pattern 126 as a mask, remove a portion of the mask layer 124 and a portion of the dielectric layer 122 to expose the second portion 208b and the spacer 220b on its sidewall. Figure 1J As shown, the photoresist pattern 126 is also removed.

[0021] Please refer to Figure 1J and Figure 1K , the second portion 208b of the core pattern 208 is removed to form an opening 16 between the spacers 220b. The opening 16 exposes the top surface of the doped polysilicon layer 106. In this case, Figure 1K As shown, the mask layer 124 is also removed, and the first portion 208 a and the spacer 220 a are still covered by the dielectric layer 122 .

[0022] Please refer to Figure 1K and Figure 1L , remove the dielectric layer 122 covering the first portion 208a and the spacer 220a. In this case, Figure 1L As shown, the first portion 208a still exists between the spacers 220a.

[0023] Please refer to Figure 1L and Figure 1M , using the first portion 208a, the spacers 220a and the spacers 220b as masks, a portion of the doped polysilicon layer 106 is removed to form a polysilicon pattern 206. In one embodiment, the oxide layer 104 can be regarded as an etch stop layer in the above-mentioned removal process. In this case, the top surface of the oxide layer 104 is exposed on the polysilicon pattern 206. Figure 1M As shown, the polysilicon pattern 206 includes a first portion 206a and a second portion 206b. The first portion 206a of the polysilicon pattern 206 is located directly below the first portion 208a of the core pattern 208 and the spacers 220a. The width W3 of the first portion 206a may be the sum of the widths of the first portion 208a of the core pattern 208 and the spacers 220a. The second portion 206b of the polysilicon pattern 206 is located directly below the spacers 220b. The width W4 of the second portion 206b is smaller than the width W3 of the first portion 206a.

[0024] Please refer to Figure 1M and Figure 1NAfter removing the first portion 208a of the core pattern 208, the spacers 220a and 220b, the polysilicon pattern 206 is used as a mask to remove a portion of the oxide layer 104 to form an oxide pattern 204. In this case, the oxide pattern 204 exposes the top surface of the nitride layer 102, as shown in FIG. Figure 1N As shown. The oxide pattern 204 includes a first portion 204a and a second portion 204b. The width W5 of the first portion 204a is greater than the width W6 of the second portion 204b. From another perspective, the layout density (or pattern density) of the second portion 204b may be greater than the layout density (or pattern density) of the first portion 204a. Therefore, the first portion 204a can be used as a layout for a peripheral circuit; while the second portion 204b can be used as a layout for a memory array. In an alternative embodiment, the width W5 of the first portion 204a of the oxide pattern 204 is greater than the width W1 of the first portion 208a of the core pattern 208 (as shown in FIG. 2 ). Figure 1I ); and the width W6 of the second portion 204b of the oxide pattern 204 is less than the width W2 of the second portion 208b of the core pattern 208. In other words, after the self-aligned double patterning (SADP) method of this embodiment, the layout density (or pattern density) of the semiconductor structure can be increased or decreased to achieve more flexible layout design.

[0025] Furthermore, after forming the oxide pattern 204, the underlying nitride layer 102 and the target layer 100 may be patterned to form a target pattern (not shown). The target pattern may replicate the oxide pattern 204. In this case, the layout density (or pattern density) of the target pattern may be greater or less than the layout density (or pattern density) of the core pattern 208.

[0026] In summary, the embodiment of the present invention can form a doped polysilicon layer and an undoped polysilicon layer below and above the core layer, respectively, to increase the etching selectivity of the doped polysilicon layer and the undoped polysilicon layer in the second etching process. Therefore, in the second etching process, the upper undoped polysilicon layer can be completely removed while retaining the lower doped polysilicon layer. In addition, the embodiment of the present invention can form a spacer material through an atomic layer deposition (ALD) process to obtain a spacer with better morphology on the sidewall of the core pattern. In this case, when the spacer is used as a mask to remove the lower target layer, a target pattern with better sidewall morphology can be formed.

[0027] Although the present invention has been disclosed above by way of embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A patterning method comprising: forming a doped polysilicon layer, a core layer, and an undoped polysilicon layer in sequence on the target layer, wherein the doping concentration of the doped polysilicon layer is greater than the doping concentration of the undoped polysilicon layer; patterning the undoped polysilicon layer to form a polysilicon pattern; Using the polysilicon pattern as a mask, performing a first etching process to remove a portion of the core layer and form a core pattern; performing a second etching process to remove the polysilicon pattern; performing an atomic layer deposition (ALD) process to form a spacer material on the core pattern and the doped polysilicon layer; removing a portion of the spacer material to form a spacer on the sidewall of the core pattern; as well as A portion of the core pattern and the doped polysilicon layer thereunder are removed.

2. The patterning method according to claim 1, wherein forming the doped polysilicon layer comprises performing an ion implantation process using a dopant, wherein the dopant comprises BF 2+ 、B + 、F + 、P + or a combination thereof.

3. The patterning method according to claim 1 , wherein performing the first etching process comprises: performing a dry etching step to form an opening in the core layer; as well as A wet etching step is performed to trim the core layer to enlarge the opening and make the sidewall of the core pattern concave relative to the sidewall of the polysilicon pattern. 4 . The patterning method according to claim 1 , wherein a material of the core layer comprises low-pressure tetraethyl orthosilicate, silicon oxide, or a combination thereof. 5 . The patterning method according to claim 1 , wherein in the second etching process, an etching rate of the polysilicon pattern is greater than an etching rate of the doped polysilicon layer. The patterning method according to claim 1 , wherein the second etching process comprises using an etching solution of NH 4 OH, TMAH, or a combination thereof. The patterning method according to claim 1 , wherein the spacer material comprises ALD silicon nitride or CVD silicon nitride.

8. The patterning method according to claim 1, further comprising: Using the spacer and the doped polysilicon layer thereunder as masks, a portion of the target layer is removed to form a target pattern. 9 . The patterning method according to claim 8 , wherein a pattern density of the target pattern is greater than a pattern density of the core pattern.

Images