Method and apparatus for testing a continuous approximation register analog-to-digital converter

Abstract

Embodiments of the present disclosure relate to methods and apparatus for testing a successive approximation register analog-to-digital converter. An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step size selector. During testing of the ADC, the bit step size selector selects a number of bits to test for a next analog test voltage based on a digital value within an integer increment value of a most recent digital value for a most recent analog test voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of analog-to-digital converters and more particularly to testing analog-to-digital converters. Background Art

[0002] Integrated circuits often include analog-to-digital converters (ADCs). These converters receive an analog voltage and output a digital value representing the analog voltage. Typically, before an ADC is put into operation, it is tested for the expected range of input analog voltages. This testing process helps confirm that the ADC will provide digital values ​​for the entire input voltage range. Summary of the Invention

[0003] In one embodiment of the present disclosure, a method includes testing an analog-to-digital converter using a plurality of monotonically increasing input test voltages within an input test voltage range. The method includes storing an integer value in a bit step selector of the analog-to-digital converter and identifying a first digital value corresponding to a most recent input test voltage using the analog-to-digital converter during testing. The method includes identifying a most significant bit that changed between a first digital value and a second digital value, the second digital value being within an integer value of the first digital value. The method includes testing a next input test voltage within the input test voltage range by adjusting only bits of the first digital value that have a significance equal to or less than the most significant bit that changed between the first digital value and the second digital value.

[0004] In one embodiment, a method includes testing a successive approximation analog-to-digital converter using a monotonically increasing input test voltage from an input test voltage range. The method includes storing integer values ​​in a bit step selector of the analog-to-digital converter. The method includes using the bit step selector to identify a set of digital values ​​to be tested for a next input test voltage based on a most significant bit that changes between a first digital value and a second digital value, the second digital value being within an integer value of the first digital value. The first digital value corresponds to a most recent input test voltage. The method includes testing the next input test voltage by providing only the set of digital values ​​from a successive approximation register of the analog-to-digital converter.

[0005] In one embodiment, an integrated circuit includes an analog-to-digital converter. The analog-to-digital converter includes a successive approximation register configured to output digital values, each digital value including a plurality of bits. The analog-to-digital converter includes a digital-to-analog converter coupled to the successive approximation register and configured to receive the digital values and generate an analog output voltage representing the digital values. The analog-to-digital converter includes a comparator coupled to the digital-to-analog converter and configured to compare the analog output voltage to an analog test voltage during a test. The analog-to-digital converter includes a bit step size selector coupled to the successive approximation register and configured to store an integer value to identify a nearest digital value corresponding to a nearest analog test voltage and select a number of bits to be tested by the successive approximation register for a next analog test voltage based on a first digital value and a second digital value, the second digital value being within the integer value from the first digital value. The first digital value corresponds to the nearest analog test voltage. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a block diagram of an integrated circuit including an analog-to-digital converter according to one embodiment;

[0007] Figure 2 shows a chart of test voltage ranges and corresponding digital values for the voltage ranges according to one embodiment;

[0008] Figure 3 shows aspects of bit step size selection for testing an analog-to-digital converter according to one embodiment;

[0009] Figure 4 shows aspects of bit step size selection for testing an analog-to-digital converter according to one embodiment;

[0010] Figure 5 is a flowchart of a process for testing an analog-to-digital converter according to one embodiment; and

[0011] Figure 6 is a flowchart of a process for testing an analog-to-digital converter according to one embodiment. DETAILED DESCRIPTION

[0012] Figure 1 is a block diagram of an integrated circuit 100 according to one embodiment. The integrated circuit 100 includes an analog-to-digital converter (ADC). The ADC 102 is configured to efficiently and effectively test itself prior to entering a standard mode of operation. As set forth in greater detail below, the ADC 102 utilizes a testing process that reduces the number of bit tests to be performed during testing. The result is that the analog-to-digital converter takes less time and computational resources to complete testing prior to use.

[0013] In one embodiment, the ADC 102 includes a successive approximation register (SAR) 104, a digital-to-analog converter (DAC) 106, a comparator 108, a digital output 110, and a bit step selector 112. The components of the ADC 102 cooperate to convert an input analog voltage to a digital value during standard operation. During testing or initialization of the ADC 102, the components of the ADC 102 cooperate to test the ADC 102’s ability to provide digital values for an expected input voltage range. In particular, as set forth in greater detail below, the bit step selector 112 facilitates testing of the ADC 102 with a substantially reduced number of bit tests than conventional testing schemes. To facilitate understanding of the bit step selector 112, it is beneficial to first describe some details of other aspects of the ADC 102.

[0014] The ADC 102 is an N-bit ADC. For a given input voltage V IN , the ADC 102 outputs a digital value having N bits. The number of bits, N, determines the resolution of the ADC 102. The higher the number of bits, the higher the resolution in distinguishing different input voltages. The lower the number of bits, the lower the resolution in distinguishing different input voltages. For example, if the expected input voltage range is 5V, and the number of bits is 1, then the resolution of the ADC 102 is 2.5V. This means that each possible digital value covers a range of 2.5V. The digital value 0 can represent any voltage between 0V and 2.5V. The digital value 1 can represent any voltage between 2.5V and 5V. If the number of bits is 2, then the resolution of the ADC 102 is 1.25V. This means that each possible digital value covers a range of 1.25V. The digital value 00 can represent any input voltage between 0V and 1.25V. The digital value 01 can represent any input voltage between 1.25V and 2.5V. The digital value 10 can represent any input voltage between 2.5V and 3.75V. The digital value 11 can represent any input voltage between 3.75V and 5V. Thus, as the number of bits increases, each digital output represents a smaller range of input values.

[0015] During standard operation, the SAR 104 outputs a series of digital values. The SAR 104 includes N binary outputs, labeled B N-1 -B0. Each of the N outputs corresponds to a bit of a digital value that can represent an analog voltage. B N-1 represents the most significant bit, and B0represents the least significant bit. The operation of the SAR 104 can be best understood in conjunction with the operation of the DAC 106 and the comparator 108.

[0016] DAC 106 is coupled to SAR 104 and comparator 108. DAC 106 includes N inputs coupled to N outputs of SAR 104. Each input receives one of the binary values ​​from SAR 104. DAC 106 includes an output coupled to an inverting terminal of comparator 108. DAC 106 outputs an analog voltage V OUT , the analog voltage V OUT corresponds to the digital value represented by each of the N binary outputs from SAR 104. DAC 106 also receives a reference voltage V REF . Reference voltage V REF can correspond to the maximum expected input voltage V IN .

[0017] In one embodiment, during standard operation of ADC 102, SAR 104 outputs a series of digital values. For each digital value, DAC 106 outputs an analog output voltage V OUT The comparator 108 receives an input voltage V IN If V IN Greater than V OUT , the comparator outputs a high voltage value. If V IN Less than V OUT , the comparator 108 outputs a low voltage value. The output of the comparator 108 is coupled to the input of the SAR 104. The SAR 104 uses the output voltage V OUT The SAR 104 is used to determine when the SAR 104 has output the correct digital value. When the SAR 104 outputs the correct digital value, the SAR 104 causes the end of conversion signal (EOC) to go high. The SAR 104 also receives a clock signal that is used to regulate the operation of the SAR 104.

[0018] Digital output 110 includes N outputs, each corresponding to one of the outputs of SAR 104. Although not described in Figure 1 , but the digital output circuit 110 receives the digital value from the SAR 104. The digital output circuit 110 also receives the EOC signal from the SAR 104. When the EOC signal goes high, it indicates that the SAR 104 has output the output voltage for the input voltage V IN The digital output circuit 110 latches its digital output to provide a digital value that is identified by the SAR 104 as representing the input voltage V IN The output of the digital output circuit 110 is a digital value representing the correct digital value of the analog input voltage V IN The output of the ADC 102 is digitally converted.

[0019] In one embodiment, during standard operation, when ADC 102 receives a new input voltage VIN At this time, the SAR 104 outputs a series of N digital values. Each of the N digital values identifies the correct value of one of the bits. The first digital value determines the value of the most significant bit B N-1 . The second digital value determines the value of the second most significant bit B N-2 . The final digital value determines the value of the least significant bit B0. In the first digital value, the most significant bit B N-1 is set to 1 and all the remaining bits B N-2 -B0 are set to 0. The DAC 106 generates an output voltage V OUT corresponding to this digital value. In fact, V OUT for this digital value can equal half of the reference voltage V REF . If V OUT is greater than V IN for this digital value, the comparator 108 will output a low voltage value and the SAR 104 will fix the most significant bit B N-1 to 0. If V OUT is less than V IN , the comparator 108 will output a high voltage value and the SAR 104 will fix the most significant bit B N-1 to 1. The SAR 104 will output a second digital value with B N-1 having the value identified after testing the first digital value, B N-2 switched to 1, and all the remaining bits having a value of 0. If V OUT is greater than V IN for this second digital value, the comparator 108 will output a low voltage value and the SAR 104 will fix B N-2 to 0. If V OUT is less than V IN , the comparator 108 will output a high voltage value and the SAR 104 will fix the bit B N-2 to 1. The SAR 104 will then output a digital value for testing the next most significant bit B N-3 . In the third digital value, B N-1 and B N-2 have the values determined after testing the first two digital values, B N-3 is 1, and all the remaining bits are 0. This testing process continues for each next most significant bit until the final digital value tests the least significant bit B0.

[0020] After the value of the least significant bit B0 is identified, the SAR 104 causes the EOC to go high. When the EOC goes high, the digital output circuit 110 latches each of its digital outputs to the bit value identified via the sequence of digital values output by the SAR 104. Thus, the digital output circuit 110 outputs the analog input voltage VIN Corresponding Digital Value. Although a particular process for identifying the correct digital value of the analog input voltage has been set forth above, other processes may be utilized without departing from the scope of this disclosure.

[0021] As previously mentioned, before ADC 102 can be used in standard operation, it must be tested to ensure that ADC 102 can provide digital values ​​over the entire expected input voltage range. If ADC 102 is not functioning properly, ADC 102 may output digital values ​​that do not correspond correctly to the analog input voltage. For example, a malfunctioning ADC may output a digital value that does not correspond to the analog input voltage. IN The first digital value and the higher second input voltage V IN Therefore, testing the ADC 102 before implementation can ensure that the ADC 102 correctly outputs digital values ​​over the entire expected input voltage range. Figure 2 Numerical values ​​corresponding to the expected input range are shown.

[0022] Figure 2 A graph 200 of input test voltages and a table 202 of bit values ​​are shown according to one embodiment. Figure 1 and 2 , graph 200 shows a monotonically increasing input test voltage over time. The test voltage starts at 0V and continues to the maximum expected voltage V FS Although graph 200 shows a smooth curve of the test voltage over time, in practice, the voltage may be increased in steps.

[0023] Because ADC 102 is an N-bit ADC, there are 2^N possible digital values. Table 202 shows that each digital value corresponds to a specific test voltage. In practice, each input value can correspond to a small range of test voltages.

[0024] Traditional SAR ADCs provide a voltage range from 0V to the expected maximum voltage V FS The conventional SAR ADC is tested over a monotonically increasing test voltage range. Thus, a conventional SAR ADC will generate a digital value for each of a series of monotonically increasing analog test voltages. A conventional SAR ADC tests each bit for each analog test voltage. For example, a conventional SAR ADC may test each input test voltage by generating N digital values ​​to determine the value of each bit, as described above with respect to the standard operating mode of ADC 102. Thus, there are a large number of digital values ​​to be tested for each input test voltage.

[0025] return Figure 1In one embodiment, the ADC 102 overcomes the shortcomings of conventional SAR ADCs by providing a testing process that tests a significantly smaller number of digital values. The ADC 102 includes a bit step selector 112. The bit step selector is coupled to the SAR 104 and controls the number of digital values that will be tested by the SAR 104 for each input test voltage. The bit step selector 112 controls the SAR 104 so that, throughout the test voltage range during testing of the ADC 102, the SAR 104 tests a much smaller number of digital values.

[0026] In one embodiment, when the SAR 104 identifies the correct digital value for a test voltage during testing, the bit step selector 112 uses that digital value to determine which digital values will be tested for the next test voltage. The bit step selector 112 uses the fact that the test voltages are monotonically increasing during testing to reduce the overall number of test digital values. In particular, because the test voltages are monotonically increasing, the bit step selector 112 can limit the range of digital values to be tested for the next test voltage based on the digital value of the most recent previous test voltage. In most cases, it is wasteful to test every bit for every test voltage. If the digital value of the most recent test voltage is known, then the number of bits to be tested for the next test voltage can be selected based on the digital value of the most recent previous test voltage.

[0027] In one embodiment, the bit step selector 112 selects or is provided with a delta (δ) value to be used during testing. The δ value can be referred to interchangeably herein as an integer value. The δ value is an integer that is less than the total number of bits of the ADC 102. The δ value indicates the number of adjacent digital values that will be used to determine the number of bits to be tested for the next test voltage.

[0028] In one embodiment, the bit step selector 112 identifies a digital value that is δ value distance from the digital value identified for the most recent test voltage. The bit step selector 112 compares the most recent digital value to the digital value that is δ value distance from the most recent digital value. The bit step selector 112 identifies the most significant bit that changes between the most recent digital value and the digital value that is δ value distance from the most recent digital value. The bit step selector 112 causes the SAR 104 to test the digital value for the next test voltage by changing only the bits corresponding to the most significant bit that changed in that comparison and lower. In other words, all bits that are more significant than the most significant bit that changed will be fixed at the value that is δ value distance from the digital value found for the most recent test voltage. The result is that, in most cases, a much smaller number of digital values will be tested for each test voltage.

[0029] In one example, the ADC 102 is an 8-bit ADC. This means that there are 2^8 or 256 possible digital values. If a number is assigned to each digital value, then the digital value 00000000 corresponds to the number 0 and the digital value 11111111 corresponds to the number 255. If the delta value is chosen to be 4, then for the nearest test voltage corresponding to the digital value of 120, the number of bits to be tested for the next test voltage is based on a comparison of the digital value of 120 to the digital value of 124 (120+4). Specifically, the number of bits to be tested for the next test voltage is based on the most significant bits that change between 120 and 124. The 8-bit binary digital value of 120 is 01111000. The 8-bit binary digital value of 124 is 01111100. The most significant bit is the leftmost digit and the least significant bit is the rightmost digit. In this case, 5 of the most significant bits (01111) do not change between 120 and 124. The sixth bit (0 in 120 and 1 in 124) is the most significant bit that changes between the binary values of 120 and 124. Thus, the bit step size selector 112 will specify that 5 of the most significant bits from the previous digital value will not change when testing the next test voltage. Only the 3 least significant bits are tested. This can be seen as the bit step size selector 112 effectively providing a value of 01111XXX to the SAR 104 and telling the SAR 104 to determine the value of the 3 final bits XXX. Thus, the SAR 104 will only test three digital values instead of testing 8 digital values for the next test voltage.

[0030] In one embodiment, the bit step size selector 112 identifies a first digital value that is the delta value beyond the digital value identified for the nearest test voltage and a digital value that is the delta value after the nearest digital value. The bit step size selector 112 compares the digital value that is the delta value after the nearest digital value to the digital value that is the delta value before the nearest digital value for the nearest test voltage. The bit step size selector 112 identifies the most significant bit that changes between the digital value that is the delta value after the nearest test value and the digital value that is the delta value before the nearest test value. The bit step size selector 112 causes the SAR 104 to test the digital value for the next test voltage by changing only those bits corresponding to the most significant bit that changes in the comparison and lower significance bits. In other words, all bits of higher significance than the changed most significant bit will be fixed to the value from the digital value that is the delta value from the digital value found for the nearest test voltage.

[0031] In one example, the ADC 102 is an 8-bit ADC. If the delta value is selected to be 4, then for the most recent test voltage corresponding to a digital value of 120, the number of bits to be tested for the next test voltage is based on a comparison of the digital value of 116 (120 - 4) and the digital value of 124 (120 + 4). Specifically, the number of bits to be tested for the next test voltage is based on the most significant bit that changes between the binary digital values of 116 to 124. The 8-bit binary digital value of 116 is 01110100. The 8-bit binary digital value of 124 is 01111100. The most significant bit is the leftmost digit and the least significant bit is the rightmost digit. In this case, 4 most significant bits (0111) do not change between 116 to 124. The fifth bit (0 in 120 and 1 in 124) is the most significant bit that changes between the binary values of 116 to 124. Thus, the bit step size selector 112 will specify that the 4 most significant bits from the previous digital value will not change when testing the next test voltage. Only the 4 least significant bits are tested. This can be viewed as the bit step size selector 112 effectively providing a value of 0111XXXX to the SAR 104 and telling the SAR 104 to determine the value of the 3 final bits XYZ. Thus, the SAR 104 will only test three digital values instead of testing 8 digital values for the next test voltage.

[0032] In one embodiment, the bit step size selector 112 includes an exclusive OR (XOR) logical operator. The bit step size selector 112 performs the above-described comparison by performing an XOR operation on two digital values. The bit step size selector 112 identifies the most significant bit that changes based on the XOR operation. For example, if the bit step size selector 112 compares a digital value that is delta values after the most recent digital value and a digital value that is delta values before the most recent digital value, the bit step size selector 112 provides these two values to the XOR operator. The XOR operator performs an XOR operation on these two digital values. If the bit step size selector 112 compares the most recent digital value to a digital value that is delta values before, the bit step size selector 112 provides these two values to the XOR operator. The XOR operator performs an XOR operation on these two digital values. Other logical operations or comparisons can be utilized by the bit step size selector 112 to determine which bits the SAR 104 will test without departing from the scope of the present disclosure.

[0033] The delta value can be selected according to desired performance. A smaller delta value will result in a faster testing process. This is because a smaller delta value will result in fewer digital values being tested throughout the testing process. Thus, various delta values can be selected without departing from the scope of the present disclosure.

[0034] In one embodiment, the bit step selector 112 receives the delta value from a circuit external to the bit step selector 112. For example, another circuit component of the integrated circuit 100 or a circuit external to the integrated circuit 100 may provide the delta value to the bit step selector 112. The bit step selector 112 may then test the ADC 102 based on the provided delta value. In this case, the bit step selector 112 may store the delta value in a memory that can be overwritten in the future if a new delta value is selected.

[0035] Figure 3 A portion of a table 300 showing digital values ​​for ADC 102 according to one embodiment is shown. Figure 3 In the example shown, ADC 102 is a 13-bit ADC. The bits are labeled B0-B 12 . B 12 is the most significant bit. B0 is the least significant bit. In a 13-bit ADC, there are 8192 possible digital values. Figure 3 An example is shown where the digital value of the most recent test voltage is 4073 (binary 0111111101001) and an example is shown where the digital value of the most recent test voltage is 4092 (binary 0111111111100). In these examples, the delta value is 4. However, other delta values ​​may be selected without departing from the scope of this disclosure.

[0036] For a digital value of 4073 and a delta value of 4, 4077 is the delta value preceding 4073. 4077 is represented in binary as 01111111101001. To select the range of digital values ​​to be tested for the next test voltage, bit step selector 112 identifies the most recent digital value (4073) and the digital value preceding the most recent digital value by a delta value (4077). Bit step selector 112 performs an XOR operation on the binary values ​​of 4073 and 4077. For any bits that are identical between the two values, the XOR operation returns 0. For any bits that differ between the two digital values, the XOR operation returns 1. Bit step selector 112 identifies the most significant bit that differs between the two digital values. Bit step selector 112 then causes SAR 104 to retain the value from the previous digital value for any bits that are more significant than the most significant bit that changed, and only test bits whose significant bits are less than or equal to the most significant bit that changed in the XOR operation. In this case, bit B2 is the most significant bit that changed. Therefore, for the next test voltage, the bit step selector 112 will force the SAR 104 to test only bits B2, B1, and B0 instead of all 13 bits.

[0037] For a digital value of 4092 and a delta value of 4, 4096 is the delta value preceding 4092. 4096 is represented in binary as (1000000000000). To select the range of digital values ​​to be tested for the next test voltage, the bit step selector 112 identifies the most recent digital value (4092) and the digital value preceding the most recent digital value by a delta value (4096). The bit step selector 112 performs an XOR operation on the binary values ​​of 4092 and 4096. In this case, bit B 12 is the most significant bit that changes. Therefore, for the next test voltage, the bit step selector 112 will force the SAR 104 to test bit B. 12 -B0, i.e., all bits. The reason that the bit step selector 112 will cause the SAR 104 to test all bits in this position is that the value 4096 is between 0 and the maximum value of 8192. It is the most significant bit (B 12 ) changes from 0 to 1. Therefore, for very few digital values, including a delta value of 4096, all bits will be tested. However, this still represents a huge improvement over conventional SAR ADCs that test all bits for all test voltages.

[0038] Figure 4 Table 400 shows digital values ​​for ADC 102 according to one embodiment. Figure 4 In the example shown, ADC 102 is a 13-bit ADC. The bits are labeled B0-B 12 . B 12 is the most significant bit. B0 is the least significant bit. In a 13-bit ADC, there are 8192 possible digital values. Figure 4 An example in which the digital value of the most recent test voltage is 4073 (0111111101001 in binary) and an example in which the digital value of the most recent test voltage is 4092 are shown. In these examples, the delta value is 4.

[0039] For digital value 4073 and a delta value of 4, 4077 is the delta value before 4073 and 4069 is the delta value after 4073. 4077 is represented in binary as 0111111101001. 4069 is represented in binary as 0111111100101. To select the range of digital values that will be tested for the next test voltage, bit step selector 112 identifies the most recent digital value (4073) and the digital value that is delta values before the most recent digital value (4077) and the digital value that is delta values after the most recent digital value (4069). Bit step selector 112 performs an XOR operation on the binary values of 4069 and 4077. For any bits that are the same between the two values, the XOR operation will return 0. For any bits that are different between the two digital values, the XOR operation will return 1. Bit step selector 112 identifies the most significant bit that is different between the two digital values. Bit step selector 112 then causes SAR 104 to retain the value from the previous digital value for any bits that are more significant than the most significant bit that changed and only test the bits that are less than or equal to the most significant bit that changed in the XOR operation. In this case, bit B3 is the most significant bit that changed. Therefore, for the next test voltage, bit step selector 112 will force SAR 104 to only test bits B3-B0.

[0040] For digital value 4092 and a delta value of 4, 4096 is the delta value before 4092 and 4088 is the delta value after 4092. 4096 is represented in binary as 1000000000000. 4088 is represented in binary as 0111111111000. To select the range of digital values that will be tested for the next test voltage, bit step selector 112 identifies the most recent digital value (4092) and the digital value that is delta values before the most recent digital value (4096) and the digital value that is delta values after the most recent digital value (4088). Bit step selector 112 performs an XOR operation on the binary values of 4088 and 4096. In this case, bit B 12 is the most significant bit that changed. Therefore, for the next test voltage, bit step selector 112 will force SAR 104 to test bits B 12 -B0, i.e., all bits.

[0041] Figure 5is a flowchart of a method for testing an ADC according to one embodiment. At 502, 500 includes testing an analog-to-digital converter using a plurality of monotonically increasing input test voltages over an input test voltage range. At 504, method 500 includes storing an integer value in a bit step selector of the analog-to-digital converter. At 506, method 500 includes identifying, using the analog-to-digital converter during the testing, a first digital value corresponding to a most recent input test voltage. At 508, method 500 includes identifying a most significant bit that changes between the first digital value and a second digital value that is within the integer value from the first digital value. At 510, method 500 includes testing a next input test voltage over the input test voltage range by adjusting only bits of the first digital value having significance equal to or less than the most significant bit that changes between the first digital value and the second digital value.

[0042] Figure 6 is a flowchart of a method 600 for testing an ADC according to one embodiment. At 602, method 600 includes testing a successive approximation analog-to-digital converter using monotonically increasing input test voltages from an input test voltage range. At 604, method 600 includes storing an integer value in a bit step selector of the analog-to-digital converter. At 606, method 600 includes identifying, using the bit step selector, a set of digital values to test for a next input test voltage based on a most significant bit that changes between a first digital value to a second digital value that is within the integer value from the first digital value, where the first digital value corresponds to a most recent input test voltage. At 608, method 600 includes testing the next input test voltage by providing only digital values within the set of digital values from successive approximation registers of the analog-to-digital converter.

[0043] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the used terminology can not be interpreted as limiting the claim to the specific embodiments disclosed in the specification and the claims and should be interpreted not to exclude other embodiments that can be apparent to a person skilled in the art. Accordingly, the claims are not limited to the disclosed embodiments and examples.

Claims

1. A method for testing an analog-to-digital converter, comprising: testing the analog-to-digital converter using a plurality of monotonically increasing input test voltages within an input test voltage range; storing an integer value in a bit step selector of the analog-to-digital converter; identifying, during testing, using the analog-to-digital converter, a first digital value corresponding to a most recent input test voltage; identifying a most significant bit that changes between the first digital value and a second digital value, the second digital value being within the integer value from the first digital value; as well as The next input test voltage within the input test voltage range is tested by adjusting only bits of the first digital value having a significance equal to or less than the most significant bit that changes between the first digital value and the second digital value.

2. The method of claim 1 , wherein identifying the most significant bit of a change comprises: An exclusive-OR operation is performed on the first digital value and the second digital value.

3. The method of claim 1 , wherein identifying the most significant bit of a change comprises: An exclusive-OR operation is performed on the second digital value and a third digital value, wherein the second digital value is the integer value preceding the first digital value, and wherein the third digital value is the integer value following the first digital value. The method of claim 1 , wherein the analog-to-digital converter is a successive approximation register analog-to-digital converter.

5. The method according to claim 1, further comprising: The most significant bit that is changed is identified using the bit step selector.

6. The method according to claim 5, further comprising: The next input test voltage is tested using a successive approximation register coupled to the bit step selector.

7. A method for testing an analog-to-digital converter, comprising: Testing a successive approximation analog-to-digital converter using a monotonically increasing input test voltage from an input test voltage range; storing an integer value in a bit step selector of the analog-to-digital converter; identifying, using the bit step selector, a set of digital values ​​to be tested for a next input test voltage based on a most significant bit that changes between a first digital value and a second digital value that is within the integer value from the first digital value, wherein the first digital value corresponds to a most recent input test voltage; as well as The next input test voltage is tested by providing only the set of digital values ​​from a successive approximation register of the analog-to-digital converter.

8. The method according to claim 7, further comprising: The bit step selector is used to identify the most significant bit that is changed by enabling the bit step selector during testing of the analog-to-digital converter.

9. The method of claim 8, wherein identifying the most significant bit comprises: An exclusive-OR operation is performed on the first digital value and the second digital value.

10. The method of claim 8, wherein identifying the most significant bit comprises: An exclusive-OR operation is performed on the second digital value and a third digital value, wherein the second digital value is the integer value preceding the first digital value, and wherein the third digital value is the integer value following the first digital value.

11. The method according to claim 7, further comprising: The integer value is received from circuitry external to the analog-to-digital converter.

12. An integrated circuit comprising an analog-to-digital converter, the analog-to-digital converter comprising: a successive approximation register configured to output digital values, each digital value comprising a plurality of bits; a digital-to-analog converter coupled to the successive approximation register and configured to receive the digital value and generate an analog output voltage representative of the digital value; a comparator coupled to the digital-to-analog converter and configured to compare the analog output voltage to an analog test voltage during testing; as well as a bit step selector coupled to the successive approximation register and configured to store an integer value to identify a most recent digital value corresponding to a most recent analog test voltage and to select a number of bits to be tested by the successive approximation register for a next analog test voltage based on a first digital value and a second digital value that is within the integer value from the first digital value, wherein the first digital value corresponds to the most recent analog test voltage. 13 . The integrated circuit of claim 12 , wherein the bit step selector comprises logic circuitry configured to select the number of bits based on the integer value and the first digital value.

14. The integrated circuit of claim 13, wherein the logic circuit comprises an exclusive-OR operator configured to perform an exclusive-OR operation on two or more digital values. 15 . The integrated circuit of claim 14 , wherein the bit step selector is configured to select the number of bits to be tested based on the XOR operation.

16. The integrated circuit of claim 14, wherein the XOR operator performs the XOR operation on the second digital value and a third digital value, wherein the third digital value is the integer value after the first digital value, and wherein the second digital value is the integer value before the first digital value.

17. The integrated circuit of claim 12, wherein the bit step selector is configured to receive the integer value from a user of the analog-to-digital converter.

18. The integrated circuit of claim 12, wherein the bit step selector is configured to receive the integer value from a circuit external to the analog-to-digital converter.

19. The integrated circuit of claim 12, wherein the analog-to-digital converter is configured to operate in a standard operating mode and a test mode, wherein the bit step selector selects the number of bits only during the test mode.

20. The integrated circuit of claim 19, wherein in the standard operating mode, the comparator receives analog input voltages and the successive approximation register tests all bits for each analog input voltage.

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