A parallel accelerated LZ77 decoding method and device

Abstract

The present application discloses a parallel accelerated LZ77 decoding method and device, including: controlling the LZ77 decoder to read multiple data units to be decoded, and combining the multiple data units to be decoded to obtain different combined data pairs; the type of the data unit to be decoded is the original character or distance length pair compressed by the LZ77 algorithm, and the combined data pair is a combination of the original character and the distance length pair; according to the type of the data unit to be decoded in the combined data pair, the LZ77 decoder is controlled to decode and output the corresponding target data, and the target data is processed by the data copy module and written into the on-chip RAM cache to obtain the decoded data. The present application reads multiple data units to be decoded at the same time, solves the problem of excessive serial copy delay, and adds an on-chip RAM cache at the same time, greatly reduces the access frequency to the off-chip memory, effectively reduces the memory access delay and memory access bandwidth pressure, and improves the decompression performance.

Description

Technical Field

[0001] The present invention relates to the technical field of data decompression, and in particular to a parallel accelerated LZ77 decoding method and device. Background Art

[0002] In the combination library of various data compression and decompression algorithms, multiple compression algorithms are often used to achieve higher compression rates according to different compression stages. The LZ77 algorithm is widely used as a compression algorithm based on repetitive compression stages as a compression algorithm with good balance between performance and compression rate. However, due to the limitations of the compression principle of the LZ77 algorithm, a large number of data copy operations are involved in the decoding process, and due to the sequential nature of the data, that is, the subsequent copy depends on all the data in the 0~MAX_D data domain before the data pointer at the copy time, all copy processes must be strictly executed in sequence. At present, various optimization methods and special programming can be used to accelerate the serial process in software implementation, but the essence is not out of the inefficient process of serial sequential execution, which also limits the overall performance of the compression algorithm decompression process with the LZ77 compression algorithm as one of the compression components.

[0003] Therefore, how to reduce the data dependency caused by a large amount of data copying during the LZ77 decoding process and improve the serial efficiency of the decoding process are technical problems that need to be solved urgently by those skilled in the art. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a parallel accelerated LZ77 decoding method and apparatus, and provide corresponding equipment and storage media, which can simultaneously read multiple data units to be decoded, solve the problem of excessive serial copy delay, and add on-chip RAM cache to greatly reduce the access frequency to off-chip memory, effectively reduce memory access delay and memory access bandwidth pressure, and improve decompression performance. The specific scheme is as follows:

[0005] The first aspect of the present application provides a parallel accelerated LZ77 decoding method, comprising:

[0006] Controlling the LZ77 decoder to read a plurality of data units to be decoded, and respectively combining the plurality of data units to be decoded to obtain different combined data pairs; wherein the type of the data unit to be decoded is an original character or a distance length pair compressed by the LZ77 algorithm, and the combined data pair is a combination of the original character and the distance length pair;

[0007] According to the type of the data unit to be decoded in the combined data pair, the LZ77 decoder is controlled to decode and output corresponding target data, and the target data is processed by the data copy module and then written into the on-chip RAM cache to obtain decoded data.

[0008] Optionally, the controlling the LZ77 decoder to read a plurality of data units to be decoded, and respectively combining the plurality of data units to be decoded to obtain different combined data pairs, comprises:

[0009] Control the LZ77 decoder to read two data units to be decoded and the distance data in the target data output in the previous clock cycle, and respectively combine multiple data units to be decoded and the distance data to obtain different combined data pairs; wherein the type of the data unit to be decoded is the original character or distance length pair compressed by the LZ77 algorithm, and the combined data pair is a combination of the original character, the distance length pair and the distance data.

[0010] Optionally, controlling the LZ77 decoder to decode and output corresponding target data according to the type of the to-be-decoded data unit in the combined data pair includes:

[0011] When the combined data pair is (original character, original character), the LZ77 decoder is controlled to decode and output the lower 8 bits of each original character in the combined data pair;

[0012] When the combined data pair is (original character, distance data), the LZ77 decoder is controlled to decode and output the lower 8 bits of the original character in the combined data pair;

[0013] When the combined data pair is a distance-length pair, controlling the LZ77 decoder to decode and output the distance-length pair in the combined data pair;

[0014] When the combined data pair is (distance length pair, original character), the LZ77 decoder is controlled to decode and output the distance length pair in the combined data pair and the lower 8 bits of the original character;

[0015] When the combined data pair is (distance length pair, distance data), the LZ77 decoder is controlled to decode and output the distance length pair in the combined data pair.

[0016] Optionally, when the combined data pair is (original character, distance data) or (distance length pair, distance data), after controlling the LZ77 decoder to decode and output the lower 8 bits of the original character in the combined data pair or the distance length pair in the combined data pair, the method further includes:

[0017] The distance data in the combined data pair is output to the next clock cycle, so that the LZ77 decoder in the next clock cycle reads the distance data and respectively combines the multiple data units to be decoded and the distance data to obtain different combined data pairs.

[0018] Optionally, the processing the target data by the data copy module and then writing the data into an on-chip RAM cache includes:

[0019] The lower 8 bits of the original character output by decoding are written to the tail of the on-chip RAM queue through the data copy module;

[0020] And / or read the distance data in the distance length pair decoded and output from the tail of the current on-chip RAM queue forward by the length data amount of the length data in the distance length pair decoded and output through the data copy module, and write the read data to the tail of the current on-chip RAM queue.

[0021] Optionally, after the target data is processed by the data copy module and written into an on-chip RAM cache to obtain decoded data, the method further includes:

[0022] The decoded data in the on-chip RAM buffer is copied to the off-chip memory in each clock cycle by a burst signal data transmission method.

[0023] Optionally, before copying the decoded data in the on-chip RAM cache to the off-chip memory by means of burst signal data transmission, the method further includes:

[0024] Determine whether the write position is consistent with the copy position of the decoded data from the on-chip RAM cache to the off-chip memory. If not, execute the step of copying the decoded data on the on-chip RAM cache to the off-chip memory through the data transmission mode of the burst signal.

[0025] Optionally, the parallel accelerated LZ77 decoding method further includes:

[0026] The plurality of data units to be decoded are decoded by setting a plurality of LZ77 decoders.

[0027] A second aspect of the present application provides a parallel accelerated LZ77 decoding device, comprising:

[0028] A data unit combination module is used to control the LZ77 decoder to read multiple data units to be decoded, and respectively combine the multiple data units to be decoded to obtain different combined data pairs; wherein the type of the data unit to be decoded is an original character or a distance length pair compressed by the LZ77 algorithm, and the combined data pair is a combination of the original character and the distance length pair;

[0029] The decoding output module is used to control the LZ77 decoder to decode and output corresponding target data according to the type of the data unit to be decoded in the combined data pair, and write the target data into the on-chip RAM cache after processing it through the data copy module to obtain decoded data.

[0030] Optionally, the parallel accelerated LZ77 decoding device further includes a pipeline processing module for controlling the operations between various modules using pipeline technology.

[0031] A third aspect of the present application provides an electronic device, comprising a processor and a memory; wherein the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the aforementioned parallel accelerated LZ77 decoding method.

[0032] A fourth aspect of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are loaded and executed by a processor, the aforementioned parallel accelerated LZ77 decoding method is implemented.

[0033] In the present application, the LZ77 decoder is first controlled to read multiple data units to be decoded, and the multiple data units to be decoded are respectively combined to obtain different combined data pairs; wherein the type of the data unit to be decoded is the original character or distance length pair obtained by compression of the LZ77 algorithm, and the combined data pair is a combination of the original character and the distance length pair; then the LZ77 decoder is controlled to decode and output the corresponding target data according to the type of the data unit to be decoded in the combined data pair, and the target data is processed by the data copy module and written into the on-chip RAM cache to obtain the decoded data. It can be seen that the present application solves the problem of excessive serial copy delay by controlling the LZ77 decoder to read multiple data units to be decoded, and then the multiple data units to be decoded are respectively combined to obtain different combined data pairs including the original character and the distance length pair. On this basis, the corresponding target data is decoded and output according to the type of the data unit to be decoded in the combined data pair, thereby improving the decompression performance. At the same time, an on-chip RAM cache is added, and the target data is processed by the data copy module and written into the on-chip RAM cache, which greatly reduces the access frequency to the off-chip memory and effectively reduces the memory access delay and the memory access bandwidth pressure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0035] Figure 1 A flow chart of a parallel accelerated LZ77 decoding method provided by this application;

[0036] Figure 2 A schematic diagram of an existing compression / decompression process provided for this application;

[0037] Figure 3 A schematic diagram of the length distance pair decoding principle provided by this application;

[0038] Figure 4 A specific parallel accelerated LZ77 decoding architecture diagram provided for this application;

[0039] Figure 5 A specific parallel accelerated LZ77 decoding method flow chart provided in this application;

[0040] Figure 6 A schematic diagram of the structure of a parallel accelerated LZ77 decoding device provided by this application;

[0041] Figure 7 A structural diagram of a parallel accelerated LZ77 decoding electronic device provided in this application. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] At present, in software implementation, various optimization methods and special programming can be used to accelerate the serial process, but the essence is not out of the inefficient process of serial sequential execution, which also limits the overall performance of the compression algorithm decompression process with the LZ77 compression algorithm as one of the compression components. In view of the above technical defects, the present application provides a parallel accelerated LZ77 decoding scheme, which solves the problem of excessive serial copy delay by controlling the LZ77 decoder to read multiple data units to be decoded, and then combines multiple data units to be decoded to obtain different combination data pairs including original characters and distance length pairs. On this basis, the corresponding target data is decoded and output according to the type of the data unit to be decoded in the combined data pair, thereby improving the decompression performance. At the same time, an on-chip RAM cache is added, and the target data is processed by the data copy module and written into the on-chip RAM cache, which greatly reduces the access frequency to the off-chip memory and effectively reduces the memory access delay and the memory access bandwidth pressure.

[0044] Figure 1 A flow chart of a parallel accelerated LZ77 decoding method provided in an embodiment of the present application. Figure 1 As shown, the parallel accelerated LZ77 decoding method includes:

[0045] S11: Control the LZ77 decoder to read multiple data units to be decoded, and respectively combine the multiple data units to be decoded to obtain different combined data pairs; wherein the type of the data unit to be decoded is the original character or distance length pair compressed by the LZ77 algorithm, and the combined data pair is a combination of the original character and the distance length pair.

[0046] In this embodiment, the LZ77 decoder is first controlled to read multiple data units to be decoded, and then the multiple data units to be decoded are respectively combined to obtain different combined data pairs; wherein the type of the data unit to be decoded is the original character or distance length pair compressed by the LZ77 algorithm, and the combined data pair is a combination of the original character and the distance length pair. It is not difficult to understand that the LZ77 algorithm is a data compression algorithm published by Ziv and Lempel in 1977. The LZ77 algorithm includes a dynamic window and a pre-read buffer. The dynamic window is a historical buffer, which is used to store the relevant information of the first n bytes of the historical input string. The pre-read buffer is used to store the m bytes to be input. In the historical buffer, the best matching string among the m characters to be input is searched, including the original character and the distance length pair. If the length of the matching string is greater than the minimum matching length, then a pair of <length (length), distance (distance)> arrays is output. The length (length) is the length of the matched data, and the distance (distance) indicates how many bytes back in the historical input string this matching data can be found. For ease of description, this embodiment represents the original character as LITERAL and the distance length pair as (LEN, D).

[0047] Taking the zlib / gzip compression and decompression algorithm as an example, the LZ77+Huffman combined algorithm is used to compress and decompress the data stream. The compression / decompression process is as follows: Figure 2As shown. This embodiment mainly focuses on the "LZ77decompress" stage in the decompression process. After the compressed data is decompressed by the Huffman decompression algorithm, it becomes an LZ77 encoded stream consisting of LITERAL original data and (LEN, D) length distance data pairs. After input into the LZ77 decoder, the original data stream is decompressed, wherein LITERAL and (LEN, D) can also be understood as the data unit form obtained by compression by the LZ77 algorithm. The LZ77 decoding process can be simply described as the following process: the LZ77 encoded stream is read in sequence in units of unsigned short type. If the current data is less than 256, the lower 8 bits of the data are intercepted and written to the output buffer output as the decoding result. If the current data is equal to 256, the current LZ77 decoding process ends. If the current data is greater than 256, it means that the current data and the next unit data form a (LEN+256, D) data pair. According to the read LEN and D, the LEN length data at a distance of D from the current buffer position of the output is written to the output buffer output as the decoding result, as shown Figure 3 shown.

[0048] In this embodiment, based on the above-mentioned LZ77 decoding implementation process, the LZ77 decoder is controlled to read the two data units to be decoded in parallel as unsigned short types, so as to realize heterogeneous parallel acceleration of the LZ77 decompression process. The combination result between the two data units to be decoded, that is, the combined data pair, includes (LITERAL, LITERAL), (LITERAL, LEN), (LEN, D), (D, LITERAL), (D, LEN), (LITERAL, END), (D, END), (END, *), etc.

[0049] S12: Control the LZ77 decoder to decode and output corresponding target data according to the type of the data unit to be decoded in the combined data pair, and process the target data through the data copy module and write it into the on-chip RAM cache to obtain decoded data.

[0050] In this embodiment, the LZ77 decoder is controlled to decode and output the corresponding target data according to the type of the data unit to be decoded in the combined data pair, and the target data is processed by the data copy module and written into the on-chip RAM cache to obtain the decoded data. By performing decoding and data copying in parallel on the FPGA (Field-Programmable Gate Array) hardware circuit design, the situation where one or more (LEN, D) data pairs are mixed with LITERAL during the LZ77 decoding process is processed. For the combined data pairs in various forms, the LZ77 decoder needs to perform corresponding decoding processing, which can be specifically parameterized in the LZ77 decoding process in step S11. For LITERAL, the lower 8-bit decoding output can be directly intercepted, and for (LEN, D), the LEN length data at a distance D before the current buffer position of output can be written into the output cache output as the decoding result, and the same applies to other situations.

[0051] On this basis, the target data output by decoding is input into the data copy module to perform pipeline copying, such as Figure 4 As shown. A 2^M (>max distance) Byte on-chip RAM cache is set in the data copy module, and all copied data are exchanged with the off-chip memory through the cache. Specifically, the decoded data on the on-chip RAM cache in each clock cycle is copied to the off-chip memory through a burst signal (burst) data transmission method. Furthermore, in this embodiment, the decoding module can take out the data to be copied from the corresponding position of the RAM on demand in a circular queue access manner, insert the decoded output into the tail of the RAM queue, and at the same time, the RAM data is burst copied from the head of the queue to the off-chip memory for storage, and RAM space is freed up to facilitate the storage of subsequent decoded data. The decoding process of this embodiment, data reading, decoding, copying, exporting and other processes are completely pipelined, and the execution of each process depends on the previous level of data drive, without loop data dependence, and the processing delay of the entire decompression process is compressed to a single process delay time.

[0052] In addition, the above steps are implemented based on the design of a decoder. According to the on-chip resources and memory access pressure, multiple incoherent data decoders can be replicated to implement parallel decoding, thereby further improving the LZ77 decompression efficiency. For example, multiple LZ77 decoders can be set to decode multiple data units to be decoded. That is, according to the on-chip resources and performance and power consumption requirements, multiple parallel LZ77 decompression processes are added, and there is no correlation between the decompressed data, which linearly expands the overall throughput performance of the LZ77 decompression. On this basis, the above decoding process is carried out in a pipeline, that is, multiple instructions are run concurrently using pipeline technology, thereby improving time efficiency. The pipeline technology refers to a quasi-parallel processing implementation technology in which multiple instructions overlap to perform operations during program execution.

[0053] It can be seen that the embodiment of the present application first controls the LZ77 decoder to read multiple data units to be decoded, and combines the multiple data units to be decoded to obtain different combined data pairs; wherein the type of the data unit to be decoded is the original character or distance length pair compressed by the LZ77 algorithm, and the combined data pair is a combination of the original character and the distance length pair; then the LZ77 decoder is controlled to decode and output the corresponding target data according to the type of the data unit to be decoded in the combined data pair, and the target data is processed by the data copy module and written into the on-chip RAM cache to obtain the decoded data. The embodiment of the present application solves the problem of excessive serial copy delay by controlling the LZ77 decoder to read multiple data units to be decoded, and then combines the multiple data units to be decoded to obtain different combined data pairs including the original character and the distance length pair. On this basis, the corresponding target data is decoded and output according to the type of the data unit to be decoded in the combined data pair, thereby improving the decompression performance. At the same time, an on-chip RAM cache is added, and the target data is processed by the data copy module and written into the on-chip RAM cache, which greatly reduces the access frequency to the off-chip memory and effectively reduces the memory access delay and memory access bandwidth pressure.

[0054] Figure 5 A specific parallel accelerated LZ77 decoding method flow chart provided in the embodiment of the present application. Figure 5 As shown, the parallel accelerated LZ77 decoding method includes:

[0055] S21: Control the LZ77 decoder to read two data units to be decoded and distance data in the target data output in the previous clock cycle, and respectively combine a plurality of the data units to be decoded and the distance data to obtain different combined data pairs.

[0056] In this embodiment, the LZ77 decoder is controlled to read two data units to be decoded and the distance data in the target data output in the previous clock cycle, and a plurality of the data units to be decoded and the distance data are respectively combined to obtain different combined data pairs. At this time, the type of the data unit to be decoded is the original character or the distance length pair compressed by the LZ77 algorithm, and the combined data pair is a combination of the original character, the distance length pair and the distance data.

[0057] The LZ77 decoder reads possible data unit combinations such as (LITERAL, LITERAL), (LITERAL, LEN), (LEN, D), (LEN, D, LITERAL), (LEN, D, LEN), (LITERAL, END), (LEN, D, END), (END, *) from the input end, and the LZ77 decoder obtains the legacy output of the decoder of the previous clock cycle: a LEN data unit. Since the LEN data must be followed by a D data, the data read at the input end of the decoding unit can only be (D, LITERAL), (D, LEN) or empty data. At this time, the LZ77 decoder reads two data units to be decoded at one time, and combines them with the remaining data of the previous clock cycle to form data modes such as (LITERAL, LITERAL), (LITERAL, LEN), (LEN, D), (LEN, D, LITERAL), (LEN, D, LEN), (LITERAL, END), (LEN, D, END), and (END, *), and performs targeted decoding processing on each combination form, and sends the processed data to the data copy module and the decoder of the next clock cycle respectively.

[0058] S22: When the combined data pair is (original character, original character), the LZ77 decoder is controlled to decode and output the lower 8 bits of each original character in the combined data pair; when the combined data pair is (original character, distance data), the LZ77 decoder is controlled to decode and output the lower 8 bits of the original character in the combined data pair; when the combined data pair is a distance-length pair, the LZ77 decoder is controlled to decode and output the distance-length pair in the combined data pair; when the combined data pair is (distance-length pair, original character), the LZ77 decoder is controlled to decode and output the distance-length pair in the combined data pair and the lower 8 bits of the original character; when the combined data pair is (distance-length pair, distance data), the LZ77 decoder is controlled to decode and output the distance-length pair in the combined data pair.

[0059] In this embodiment, when the combined data pair is (LITERAL, LITERAL), the LZ77 decoder is controlled to decode and output the lower 8 bits of each original character in the combined data pair, that is, the lower 8 bits of the two data units are directly intercepted and output to the data copy module, and an empty data flag is output to the post-decoder, and the post-decoder is the next clock cycle decoder. When the combined data pair is (LITERAL, LEN), the LZ77 decoder is controlled to decode and output the lower 8 bits of the original character in the combined data pair, that is, the lower 8 bits of the LITERAL data are intercepted and output to the data copy module, and LEN is output to the post-decoder. When the combined data pair is (LEN, D), the LZ77 decoder is controlled to decode and output the distance length pair in the combined data pair, that is, the (LEN, D) data pair is directly output to the data copy module, and an empty data flag is output to the post-decoder. When the combined data pair is (LEN, D, LITERAL), the LZ77 decoder is controlled to decode and output the distance length pair in the combined data pair and the lower 8 bits of the original character, that is, the (LEN, D) data pair is directly output to the data copy module, the lower 8 bits of the LITERAL data are intercepted and output to the data copy module, and an empty data flag is output to the post-decoder. When the combined data pair is (LEN, D, LEN), the LZ77 decoder is controlled to decode and output the distance length pair in the combined data pair, that is, the (LEN, D) data pair is directly output to the data copy module, and LEN is output to the post-decoder. It is not difficult to understand that for the (LITERAL, END) data pair, the lower 8 bits of the LITERAL data are intercepted and output to the data copy module, and the end instruction is broadcast; for the (LEN, D, END) data pair, the (LEN, D) data pair is directly output to the data copy module, and the end instruction is broadcast; for the (END, *) data pair, the end instruction is broadcast.

[0060] S23: Write the lower 8 bits of the original character output by decoding into the tail of the on-chip RAM queue through the data copy module.

[0061] S24: read the distance data in the distance length pair output by decoding from the tail of the current on-chip RAM queue forward by the length data amount of the length data in the distance length pair output by decoding through the data copy module, and write the read data to the tail of the current on-chip RAM queue.

[0062] S25: Determine whether the write position is consistent with the copy position of the decoded data from the on-chip RAM cache to the off-chip memory. If not, copy the decoded data on the on-chip RAM cache to the off-chip memory through a burst signal data transmission method.

[0063] In this embodiment, for the LITERAL and (LEN, D) combined data processed by the LZ77 decoder, on the one hand, the lower 8 bits of the original character output by the decoder are written to the tail of the on-chip RAM queue through the data copy module, and on the other hand, the distance data in the distance length pair output by the decoder is read from the position of the length data in the distance length pair output by the decoder from the tail of the current on-chip RAM queue, and the read data is written to the tail of the current on-chip RAM queue. Specifically, the data copy module reads data sequentially from the data queue sent by the LZ77 decoder, writes the LITERAL data directly into the on-chip RAM cache, and for the (LEN, D) data, reads the LEN length data cyclically and in parallel from the "current RAM queue tail position-D" position, and writes the read data in parallel to the tail of the RAM queue.

[0064] At the same time, during the writing process, it is necessary to check whether the current writing position is equal to the RAM position to be copied to the off-chip memory. If they are equal, wait until the data is copied to the off-chip memory before continuing to execute. That is, it is necessary to determine whether the writing position is consistent with the copy position of the decoded data from the on-chip RAM cache to the off-chip memory. If not, the decoded data on the on-chip RAM cache is copied to the off-chip memory through the data transmission method of the burst signal. It should be noted that in each clock cycle, the data in the RAM cache is exported to the off-chip memory in a burst manner according to the preset parallelism. If the length of the data to be exported is 0 or less than the burst length, it waits in a loop. Among them, the parallelism N can be flexibly set to be greater than or equal to the preset output throughput / operating frequency according to the on-chip resources and performance requirements. On the premise of ensuring that no data overwriting occurs (the cached data that has not yet been written to the off-chip memory is not overwritten), the read-in data is written in parallel to the on-chip RAM cache.

[0065] It can be seen that the embodiment of the present application proposes a heterogeneous parallel LZ77 decoding method based on FPGA to address the data dependency caused by a large amount of data copying in the LZ77 decoding process and the serial inefficiency of the decoding process. The serial part of the decoding process is partially processed in parallel to reduce the processing delay between each data copy process, while reducing the data access delay caused by repeated random memory access operations.

[0066] See also Figure 6 As shown, the embodiment of the present application also discloses a parallel accelerated LZ77 decoding device, including:

[0067] The data unit combination module 11 is used to control the LZ77 decoder to read multiple data units to be decoded, and respectively combine the multiple data units to be decoded to obtain different combined data pairs; wherein the type of the data unit to be decoded is the original character or the distance length pair compressed by the LZ77 algorithm, and the combined data pair is a combination of the original character and the distance length pair;

[0068] The decoding output module 12 is used to control the LZ77 decoder to decode and output corresponding target data according to the type of the data unit to be decoded in the combined data pair, and write the target data into the on-chip RAM cache after processing through the data copy module to obtain decoded data. It can be seen that the embodiment of the present application.

[0069] In some specific embodiments, the data unit combination module 11 is specifically used to control the LZ77 decoder to read two data units to be decoded and the distance data in the target data output in the previous clock cycle, and respectively combine multiple data units to be decoded and the distance data to obtain different combined data pairs; wherein the type of the data unit to be decoded is the original character or distance length pair compressed by the LZ77 algorithm, and the combined data pair is a combination of the original character, the distance length pair and the distance data.

[0070] In some specific embodiments, the decoding output module 12 specifically includes:

[0071] A first output unit, used for controlling the LZ77 decoder to decode and output the lower 8 bits of each original character in the combined data pair when the combined data pair is (original character, original character);

[0072] A second output unit, used for controlling the LZ77 decoder to decode and output the lower 8 bits of the original character in the combined data pair when the combined data pair is (original character, distance data);

[0073] A third output unit, configured to control the LZ77 decoder to decode and output the distance length pair in the combined data pair when the combined data pair is a distance length pair;

[0074] A fourth output unit, used for controlling the LZ77 decoder to decode and output the distance length pair in the combined data pair and the lower 8 bits of the original character when the combined data pair is (distance length pair, original character);

[0075] a fifth output unit, configured to control the LZ77 decoder to decode and output the distance length pair in the combined data pair when the combined data pair is (distance length pair, distance data);

[0076] A first writing unit is used to write the lower 8 bits of the original character output by decoding into the tail of the on-chip RAM queue through the data copy module;

[0077] The second writing unit is used to read the distance data in the distance length pair output by decoding from the tail of the current on-chip RAM queue forward by the position of the length data in the distance length pair output by decoding through the data copy module, and write the read data to the tail of the current on-chip RAM queue.

[0078] In some specific embodiments, the parallel accelerated LZ77 decoding device further includes:

[0079] A legacy output module, used for outputting the distance data in the combined data pair to the next clock cycle after the second output unit or the fifth output unit, so that the LZ77 decoder in the next clock cycle reads the distance data and respectively combines the plurality of data units to be decoded and the distance data to obtain different combined data pairs;

[0080] A data copy module, used for copying the decoded data in the on-chip RAM cache to the off-chip memory in each clock cycle through a burst signal data transmission mode;

[0081] The pipeline processing module is used to control the operations between various modules using pipeline technology.

[0082] Furthermore, an embodiment of the present application also provides an electronic device. Figure 7 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0083] Figure 7 The present invention provides a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the parallel accelerated LZ77 decoding method disclosed in any of the aforementioned embodiments.

[0084] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0085] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon may include an operating system 221, a computer program 222 and data 223, etc. The storage method can be temporary storage or permanent storage.

[0086] The operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, so as to realize the operation and processing of the massive data 223 in the memory 22 by the processor 21, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the parallel accelerated LZ77 decoding method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks. The data 223 can include decoded data units collected by the electronic device 20.

[0087] Furthermore, an embodiment of the present application also discloses a storage medium, in which a computer program is stored. When the computer program is loaded and executed by a processor, the steps of the parallel accelerated LZ77 decoding method disclosed in any of the aforementioned embodiments are implemented.

[0088] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0089] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0090] The above is a detailed introduction to the parallel accelerated LZ77 decoding method, device, equipment and storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A parallel accelerated LZ77 decoding method, It is characterized in that include: Control the LZ77 decoder to read multiple data units to be decoded, and respectively combine the multiple data units to be decoded to obtain different combined data pairs; wherein the type of the data unit to be decoded is the original character or distance length pair compressed by the LZ77 algorithm, and the combined data pair is a combination of the original character and the distance length pair; the distance length pair is composed of length data and distance data; the distance data represents the byte distance between the historical input string and the current matching string, and the current matching string is a string that matches the historical input string; Control the LZ77 decoder to decode and output corresponding target data according to the type of the data unit to be decoded in the combined data pair, and process the target data through the data copy module and write it into the on-chip RAM cache to obtain decoded data; The target data is the lower 8 bits of the original character in the combined data pair, or the distance length pair in the combined data pair.

2. The parallel accelerated LZ77 decoding method according to claim 1, It is characterized in that The controlling LZ77 decoder reads a plurality of data units to be decoded, and respectively combines the plurality of data units to be decoded to obtain different combined data pairs, including: Control the LZ77 decoder to read two data units to be decoded and the distance data in the target data output in the previous clock cycle, and respectively combine multiple data units to be decoded and the distance data to obtain different combined data pairs; wherein the type of the data unit to be decoded is the original character or distance length pair compressed by the LZ77 algorithm, and the combined data pair is a combination of the original character, the distance length pair and the distance data.

3. The parallel accelerated LZ77 decoding method according to claim 2, It is characterized in that The step of controlling the LZ77 decoder to decode and output corresponding target data according to the type of the to-be-decoded data unit in the combined data pair comprises: When the combined data pair is (original character, original character), the LZ77 decoder is controlled to decode and output the lower 8 bits of each original character in the combined data pair; When the combined data pair is (original character, distance data), the LZ77 decoder is controlled to decode and output the lower 8 bits of the original character in the combined data pair; When the combined data pair is a distance-length pair, controlling the LZ77 decoder to decode and output the distance-length pair in the combined data pair; When the combined data pair is (distance length pair, original character), the LZ77 decoder is controlled to decode and output the distance length pair in the combined data pair and the lower 8 bits of the original character; When the combined data pair is (distance length pair, distance data), the LZ77 decoder is controlled to decode and output the distance length pair in the combined data pair.

4. The parallel accelerated LZ77 decoding method according to claim 3, It is characterized in that When the combined data pair is (original character, distance data) or (distance length pair, distance data), after controlling the LZ77 decoder to decode and output the lower 8 bits of the original character in the combined data pair or the distance length pair in the combined data pair, the method further includes: The distance data in the combined data pair is output to the next clock cycle, so that the LZ77 decoder in the next clock cycle reads the distance data and respectively combines the multiple data units to be decoded and the distance data to obtain different combined data pairs.

5. The parallel accelerated LZ77 decoding method according to claim 3, It is characterized in that The processing of the target data by the data copy module and writing the data into the on-chip RAM cache comprises: The lower 8 bits of the original character output by decoding are written to the tail of the on-chip RAM queue through the data copy module; And / or through the data copy module, starting from the position of the length data in the distance length pair decoded and output forward from the tail of the current on-chip RAM queue, read the distance data in the distance length pair decoded and output, obtain the read-in data, and write the read-in data to the tail of the current on-chip RAM queue.

6. The parallel accelerated LZ77 decoding method according to any one of claims 1 to 5, It is characterized in that After the target data is processed by the data copy module and written into the on-chip RAM cache to obtain decoded data, the method further includes: The decoded data in the on-chip RAM buffer is copied to the off-chip memory in each clock cycle by a burst signal data transmission method.

7. The parallel accelerated LZ77 decoding method according to claim 6, It is characterized in that Before copying the decoded data in the on-chip RAM cache to the off-chip memory by means of burst signal data transmission in each clock cycle, the method further includes: Determine whether the write position is consistent with the copy position of the decoded data from the on-chip RAM cache to the off-chip memory. If not, execute the step of copying the decoded data on the on-chip RAM cache to the off-chip memory through the data transmission mode of the burst signal.

8. The parallel accelerated LZ77 decoding method according to claim 1, It is characterized in that Also includes: The plurality of data units to be decoded are decoded by setting a plurality of LZ77 decoders.

9. A parallel accelerated LZ77 decoding device, It is characterized in that include: A data unit combination module is used to control the LZ77 decoder to read multiple data units to be decoded, and to combine the multiple data units to be decoded to obtain different combination data pairs; wherein the type of the data unit to be decoded is the original character or distance length pair compressed by the LZ77 algorithm, and the combination data pair is a combination of the original character and the distance length pair; the distance length pair is composed of length data and distance data; the distance data represents the byte distance between the historical input string and the current matching string, and the current matching string is a string that matches the historical input string; A decoding output module is used to control the LZ77 decoder to decode and output corresponding target data according to the type of the data unit to be decoded in the combined data pair, and write the target data into the on-chip RAM cache after processing through the data copy module to obtain decoded data; the target data is the lower 8 bits of the original character in the combined data pair, or the distance length pair in the combined data pair.

10. The parallel accelerated LZ77 decoding device according to claim 9, It is characterized in that It also includes a pipeline processing module for controlling the operations between various modules using pipeline technology.

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