Memory device with improved sensing structure

Abstract

The present disclosure relates to a memory device having an improved sensing structure and comprising: a memory array including a plurality of memory cell subarrays and constructed in a memory block; a sense amplifier coupled to the memory cell; a modified JTAG cell coupled in parallel to the output of the sense amplifier and serially interconnected in a scan chain structure, thereby integrating the JTAG structure and the sense amplifier. The scan chain structure associated with each subarray is interconnected to form a unique chain as a boundary scan register. In addition, the boundary scan register is a test structure for testing the interconnection of the sense amplifier.

Description

Technical Field

[0001] The present invention relates to memory devices, and more particularly, to memory devices or components that allow replacement of embedded memory portions in SoC devices and are constructed with improved sensing circuitry to enable digital testing of sense amplifiers to be performed. Background Art

[0002] A system on a chip or SoC is a semiconductor integrated circuit that integrates all components of a computer or other electronic system. These components typically include a central processing unit (CPU), memory portions, input / output ports, and auxiliary storage components, all on a single semiconductor substrate.

[0003] SoC devices can contain digital, analog, mixed-signal, and often RF signal processing functions, depending on the application. When they are integrated on a single electronic substrate, SoC devices can consume much less power and occupy much less area than multi-chip designs with equivalent functionality. Today, SoC devices are very common in mobile computing, embedded systems, and the Internet of Things.

[0004] Especially in the automotive field, it is necessary to process SoC devices, including controllers, memory and connections to many external sensors and actuators. In addition, the controllers of these SoC devices need to have a long life and extremely high reliability, and work with the memory part embedded in the SoC device with low initial latency and the highest possible throughput.

[0005] Non-volatile flash memories are one of the fundamental building blocks of today's modern electronic systems, including SoC devices for automotive applications, especially for real-time operating systems, or RTOS. Their performance in terms of speed, consumption, variability, non-volatility, and the increasing importance of system reconfigurability has driven the integration of flash memories in system-on-chip devices.

[0006] However, flash integration introduces many issues that require careful design at both the system and circuit / technology levels. From a system perspective, the choice of the type of flash memory to be integrated in an SoC device involves several aspects; the most important of which are their yield, cost, power consumption, reliability, and performance requirements, depending on the specific application and requirements.

[0007] Furthermore, embedded memory in SoC devices is difficult to manage when lithography nodes are below 28 nm, for example, and when embedded macro flash may be the largest portion of the SoC. Summary of the invention

[0008] In one aspect, the present application provides a memory device having an improved sensing structure and comprising: a memory array including a plurality of memory cell sub-arrays and constructed in a memory block; a sense amplifier coupled to the memory cells; and a modified JTAG cell coupled in parallel to the output of the sense amplifier and interconnected in series in a scan chain structure, thereby integrating the JTAG structure and the sense amplifier.

[0009] On the other hand, the present application provides a memory device, which is constructed as an independent semiconductor device and includes at least one memory array and at least one JTAG logic interface part, which is used to interact with a system on chip (SoC) structure through at least one communication channel, and includes: a memory array, which includes a plurality of memory cell sub-arrays and is constructed in a memory block; a sense amplifier, which is coupled to the memory cell and the communication channel; a modified JTAG cell, which is coupled in parallel to the output of the sense amplifier and is serially interconnected in a scan chain structure, thereby integrating the JTAG structure and the sense amplifier.

[0010] On the other hand, the present application provides an integrated semiconductor device, which includes a system on chip (SoC) structure and a structurally independent memory device, wherein the SoC structure and the memory device both include interconnect pads and are coupled in a face-to-face manner to connect corresponding interconnect pads, and wherein the memory device includes: a memory array, which includes a plurality of memory cell sub-arrays and is constructed in a memory block; a sense amplifier coupled to the memory cell and the communication channel; a modified JTAG cell, which is coupled in parallel to the output of the sense amplifier and is serially interconnected in a scan chain structure, thereby integrating the JTAG structure and the sense amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram and perspective view of a system-on-chip device according to the present disclosure and including a memory component that replaces an embedded memory portion of a previous SoC device;

[0012] Figure 2 is a schematic diagram of a memory component according to the present disclosure;

[0013] Figure 3 Show Figure 2 A schematic diagram of a portion of a non-volatile memory component including a layout configuration according to the present disclosure;

[0014] Figure 4 is a schematic diagram of a memory block formed by a plurality of rows of a memory array according to one embodiment of the present disclosure;

[0015] Figure 5 yes Figure 4 A schematic diagram of an extended memory page in a memory row of a memory block of;

[0016] Figure 6 yes Figure 3 A schematic diagram of details of a memory portion shown in FIG.

[0017] Figure 7 is a schematic diagram of the connections between a general memory cell and a corresponding sense amplifier including a modified JTAG cell according to the present disclosure;

[0018] Figure 8 schematically illustrates a more detailed internal structure of a memory component according to the present disclosure;

[0019] Fig. 9 is Figure 6 and 7 A schematic diagram of a JTAG unit shown in and modified according to the present disclosure;

[0020] Fig.10 shows the use of a boundary scan cell configured in accordance with IEEE Standard No. 1149.1 but including Fig. 9 Schematic diagram of the standard structural architecture of a modified JTAG unit. DETAILED DESCRIPTION

[0021] With reference to those figures, apparatus and methods relating to non-volatile memory devices or components and host devices for such memory devices will be disclosed herein.

[0022] According to an embodiment of the present disclosure, a separate memory device or component 100 is implemented using technology specifically used to manufacture flash memory devices. This new memory component 100 is associated with and connected to a SoC structure 110 that overlaps with a portion of this structure, while the corresponding semiconductor area of ​​the SoC structure is used for other logic circuits and for providing support for the overlapping structure independent memory portion.

[0023] Disclosed herein is a non-volatile memory structure 100 that can improve access time. In any case, the system on chip 110 and the associated memory devices are implemented on respective dies obtained by different lithographic processes.

[0024] like Figure 1As shown, according to the present disclosure, the memory component 100 is constructed as a separate device implemented in a single die using technology specifically used to manufacture flash memory devices. The memory component 100 is an independent structure, but it is absolutely associated with a host device or SoC structure. More specifically, the memory device 100 is associated with and connected to the SoC structure 110 that partially overlaps such a structure, and the corresponding semiconductor area of ​​the SoC structure is used for other logic circuits and for providing support for the partially overlapping structure independent memory device 100, for example, through a plurality of guide pillars 130 or other similar alternative connections (e.g., ball grids) or using a flip chip-like technology.

[0025] To mount the chip to external circuitry (e.g., a circuit board or another chip or wafer), the chip is flipped so that its top side is facing down, and the pads are aligned with each other so that its pads align with matching pads on the external circuit. The solder is then reflowed to complete the interconnect.

[0026] The final configuration will be a face-to-face interconnected SoC / Flash array, where the sense amplifier will be connected to the SoC in a direct memory access configuration.

[0027] Ultimately, the memory device is manufactured according to the needs of the user and its range of values ​​may vary according to the available technology, for example from at least 128 Mbit to 512 Mbit or even higher, without any limitation to the rights of the applicant. More precisely, the proposed external architecture allows to go beyond the limits of the current eFlash (i.e. embedded Flash technology) and thus allows the integration of larger memories, since it can be 512 Mbit and / or 1 Gbit and / or more, depending on the memory technology and the technology node.

[0028] In one embodiment of the present disclosure, the memory component 100 of the SoC structure 110 includes at least a memory portion and a logic circuit portion for interacting with the memory portion and the SoC structure 110. The logic circuit 140 is integrated in the SoC structure 110 to cooperate with the logic circuit portion of the memory component 100.

[0029] More generally, the memory component 100 has a tiny size compared to the larger size of the SoC structure 110, and the term "partially overlapping" means that the memory component 100 only partially or incompletely covers the area of ​​the SoC structure 110. However, larger size memory components 100 can also be supported and can be interconnected with the pads of the SoC structure to maintain the position and misalignment of its interconnects or interconnect pads.

[0030] In one embodiment of the present disclosure, the arrangement of the pads of the memory component 100 has been implemented on the surface of the memory component 100. More precisely, the pads are arranged above the array so that when the memory component 100 is turned upside down, its pads face the corresponding pads of the SoC structure 110. The semiconductor area 120, which is partially occupied by the embedded non-volatile memory in the well-known system-on-chip device, is dedicated to the housing of the interconnect pads corresponding to the pads of the memory component 100.

[0031] Alternatively, if face-to-face coupling is employed, a stack of memory components of the same size may be overlapped to achieve a stacked structure, wherein each individual component is addressed by the logic circuitry of the SoC structure 110 through a corresponding identification address.

[0032] The semiconductor area 120, which was previously partially occupied by embedded memory in known solutions, is now used to implement additional functions and prepare the semiconductor device for Logic Over Pads technology. The expression "Logic Over Pads" means providing logic circuitry overlapping some connection pads located inside the first or base layer represented by the finished semiconductor product, i.e., SoC structure 110. In the case of extending the memory in the SoC, the technology will provide pads above the memory in the SoC silicon and flash array.

[0033] Thus, memory component 100 represents an upper layer coupled and interconnected to base SoC structure 110 , but has a greater capacity and may cover a semiconductor area that is larger than semiconductor area 120 .

[0034] In addition, in order to make the SoC structure 110 operate better, Figure 1 The logic circuit portion 140 of the memory component 100 (which in well-known SoC devices contains a modified finite state machine or RISC controller) has been removed from the SoC and reorganized in association with the memory component 100. Therefore, in order to support the write and erase phases performed on the larger memory component 100, the modified finite state machine or RISC 140 has been migrated into the memory component 100.

[0035] The separation and optimization of the logic circuit portion further allows the functionality of the entire SoC structure 110 to be enhanced, thereby obtaining an independent semiconductor memory component 100 coupled to the SoC structure 110 .

[0036] Thus, this independent semiconductor memory component 100 comprises at least the memory portion, preferably a non-volatile memory portion, and the associated modification finite state machine 140, which are incorporated into a semiconductor product coupled to the SoC structure 110. In this case, the logic embedded in the SoC is the read logic: data acquisition, data correction, elaboration and execution.

[0037] As will become apparent from the following disclosure, the memory component 100 with the interface logic JTAG TAP is provided with DMA capability using a modified JTAG unit along with flexible TDI, secure access, address buffers and other features for handling communications with the SoC fabric 110 .

[0038] Now, more specifically referring to Figure 2 The main structure of the memory component 200 according to the embodiment of the present disclosure will be disclosed. Figure 2 The mark 200 corresponds to Figure 1 The mark is 100.

[0039] The memory component 200 includes at least: I / O circuits 205, a micro-sequencer 203, a memory cell array 290, a voltage and / or current reference generator 210, a charge pump architecture 202, an address decoder 208, a sense amplifier 209 and corresponding latches, service logic for connecting all parts of the memory, and a command user interface 204, such as a CUI block.

[0040] Memory cell array 290 includes non-volatile flash memory cells.

[0041] In one embodiment of the present disclosure, the memory component 200 implements a direct memory access type of memory to replace the embedded memory array of a known SoC device.

[0042] Furthermore, the proposed concept enables implementation of the memory component 200 in a "known good die" (KGD) form factor or bare die, which allows the sense amplifier outputs (except for the intermediate latch structures) to be directly connected to the controller of the SoC structure.

[0043] The strategy to achieve the KGD form factor is based on leveraging existing infrastructure for testing and burn-in of traditional packaged components. This minimizes the amount of hardware, tools, or inserts that add cost to the bare die product.

[0044] Figure 3 The internal structure of the memory module 100 or 200 is shown in more detail. Figure 3 In the example, the memory device is used to correspond to Figure 2 The reference numeral 300 of the reference numeral 200 is indicated by the numeral 300 , and the memory array 290 is indicated by the numeral 320 .

[0045] The JTAG interface 350 is used to test the memory component 300, so that the test tool can be reused. Therefore, the memory component 300 also includes a JTAG logic 350. This JTAG interface 350 will be referred to later. Figure 8 More details disclosed.

[0046] In more detail, the memory array includes at least one JTAG interface 350 for receiving standard JTAG signals as input: TMS, TCK, TDI and data from the memory page. According to an embodiment of the present disclosure, the extended TDI is used as a flexible TDI. The flexibility is because the number of parallel bits that work as TDI depends on the selected register, i.e. K (four in the example) lines of the instruction register, M lines of the address register, N lines of the data register, etc., and TDI comes from the JTAG protocol, which uses TDI as a name on the signal used to fill the register.

[0047] The JTAG interface 350 generates data, address and control signals as outputs, which are transferred to the memory address decoder 340 and the internal flash controller 310 to perform modification, test and verification operations.

[0048] The activities of the decoder 340 are accomplished by a charge pump 330 that is configured to keep the voltages and timing of the array secret. The decode stage drives the data lines while the charge pump provides a high voltage that is routed in the selected data line by the address decoder.

[0049] This decoder 340 addresses the selected memory block. The address decoder is connected to the array to select the correct data lines, i.e., rows and columns for each superpage. Reading, modifying and any other operation uses the address decoder to correctly address the bytes in the memory array.

[0050] The interconnect also includes a JTAG interface 350 and control pins for testing and other purposes. The core of the SoC device 110 can access the JTAG interface 350 by using some internal pads 370. Such pads are high-speed and can support the highest frequencies. More specifically, the high-speed pads 370 are used for the fast read path of the SoC 110, while the slow path 380 is dedicated to the test phase. The JTAG unit is part of the fast path, but the JTAG interface uses the slower path.

[0051] According to the present disclosure, the memory component 300 is equipped with a controller 310 (hereinafter referred to as a flash array controller) of a flash array 320. The flash array controller 310 has an architecture that allows some flash array resources to be used together with the SoC controller without compromising the confidentiality of specific information stored therein (e.g., algorithms, flash array voltages, currents, and more general process information) and ensuring end-customer return management. This is achieved by adopting a dedicated structure in which a user can write his own firmware in a first area and can interact with the controller's internal firmware located in a different second area.

[0052] Thus, the memory component 100 and the host or SoC 110 have been coupled to the interface using a very high degree of parallelism. This feature can also be used to improve performance, for example, for loading instruction registers and (general) data registers.

[0053] The need for extremely low initial latency and high throughput motivates the following per-subarray addressing scheme.

[0054] As will be disclosed in more detail subsequently, each memory block is connected to a corresponding amplifier, and the sense amplifiers of the read interface 360 ​​are connected to the SoC device 110 using a modified JTAG cell. The communication channel between the flash array blocks and the SoC device 110 is represented by a control and status bus.

[0055] The output of the read interface 360 ​​is represented by an extended page containing a combined string of data cells + address cells + ECC cells, which will be referred to later. Figure 5 The write operation also drives these three components of the extended page (data unit + address unit + ECC unit); the ECC and address units act as a safety mechanism to ensure a low error probability.

[0056] In the examples disclosed herein, the total number of bits will involve N+M+R bits, for example, 168 pads per channel in the embodiments disclosed herein.

[0057] The memory component 300 uses interconnect pads and logic circuit portions to implement interconnection with the SoC structure 110 .

[0058] The final configuration will be a face-to-face interconnect SoC / Flash array where the sense amplifiers of the memory component 300 will be connected to the SoC in a direct memory access configuration. The interconnect also contains a JTAG interface and control pins for testing and other purposes.

[0059] In this way, the number of pads required for interconnection can be kept relatively small.

[0060] According to the present disclosure, the memory component 300 is equipped with a controller 310 of the flash array 320 (hereinafter referred to as the flash array controller), which has an architecture that allows sharing some flash array resources with the SoC controller without compromising the confidentiality of specific information stored therein (e.g., algorithms, flash array voltages, currents, and more general process information) and ensures end-customer return management.

[0061] The memory array 320 of the memory component 300 is structured as a collection of sub-arrays 390. The scan chains can be connected to form a unique shift register for proper testing of the interconnects.

[0062] This architecture is very scalable, where expanding and / or reducing the density of the final device is simply a matter of mirroring the processing subarrays and providing the corresponding interconnects in a very scalable manner. The memory can also be scaled to increase the memory size of each subarray without increasing the number of channels of the SoC.

[0063] Direct memory access reduces the resulting latency that the SoC may experience when reading data.

[0064] Now looking more closely at the internal structure of memory component 100 or 200 or 300 , it should be noted that the architecture of memory array 320 is structured as a collection of sub-arrays 390 .

[0065] Each sub-array 390 is independently addressable within the memory device 300. Each sub-array 390 contains a plurality of memory blocks 460 (in Figure 4 described in more detail in ).

[0066] In this way, with smaller sectors compared to known solutions, the access time is significantly reduced and the overall throughput of the memory component is improved. The reduction in initial latency time is at the block level, because the row and column lines, the latency associated with the read path and the external communication have been optimized. The initial latency is the time required to get the first valid data after the address is issued.

[0067] In the embodiment disclosed herein, the memory array 320 is constructed with a number of sub-arrays 390 corresponding to a number of cores of the associated SoC 110 and thus corresponding to a number of corresponding communication channels. For example, at least four memory sub-arrays 390 are provided, one for each communication channel having a corresponding core of the SoC 110.

[0068] The host device or system on chip 110 normally includes more than one core, and each core is coupled to a corresponding bus or channel for receiving and transmitting data to the memory components 100, 200 or 300. We will make a general reference to K buses of N data bits.

[0069] Thus, in this embodiment, each sub-array 390 can access a corresponding channel to communicate with a corresponding core of the system on chip 110. The results of the memory blocks are driven directly to the SoC without the use of high power output buffers and optimized paths.

[0070] This architecture is very scalable, where expanding and / or reducing the density of the final device is simply a matter of mirroring the subarrays and making connections or increasing the number of blocks per subarray (ie, available per-core density).

[0071] In an embodiment of the present disclosure, each independently addressable location of a block of each memory sub-array 390 is associated with an extended page 450 (in Figure 4 ) addressing, which will also be defined hereinafter by the term superpage, meaning a double-extended page.

[0072] As a non-limiting example, this extended page 450 includes a string that includes a first set of at least N bits (for example, one hundred and twenty-eight (128) bits) and at least a second set of M bits (for example, twenty-four (24) address bits), and a final or third set of at least R bits (for example, sixteen (16) ECC bits) for I / O data exchange with the SoC device 110. The M address bits (in the example, twenty-four address bits) are sufficient to address up to 2 gigabits of available memory space.

[0073] like Figure 4 As shown in , each block 460 of each memory sub-array 390 is constructed with a row 435 containing at least 16 double words, each double word being N bits (i.e., 128 bits) per page plus M address bits and R ECC syndrome spare bits, thereby forming a memory page with N+M+R 168 bits. This architecture is similar to a DRAM-like scheme that prepares multiple addresses simultaneously. For example, each double word containing N+M+R bits can contain 168 bits plus 168 bits to form the super page mentioned above.

[0074] Those skilled in the art will appreciate that larger or smaller memory devices may be constructed with an increased number of memory sub-arrays 390, thereby expanding or reducing the density of the resulting memory device 100. For example, larger memory devices may be obtained by mirroring the sub-arrays 390 and providing corresponding interconnects in a very scalable manner.

[0075] exist Figure 4 The combined string of data units + address units + ECC units forming an extended or super page 450 schematically shown in the figure enables implementation of a secure coverage of the bus consistent with the standard requirements of rule ISO26262, because the ECC covers the entire bus communication (data units + address units), and the presence of the address units provides confidence that the data comes entirely from the controller addressed location (i.e., in the case where ADD == ADD0).

[0076] The R ECC units allow the host controller to understand if data and address content is corrupted.

[0077] The implementation of this mechanism ensures that the read operation of the memory is optimized.

[0078] According to the present disclosure, the output of the sense amplifier SA prepares a double extended page at a time, ie, a super page 450, including a plurality of bits given by a double combination of the above three sets of data bits, address bits, and ECC bits, according to the size of the memory array.

[0079] In the specific but non-limiting example disclosed herein, each extended page 450 contains at least 168 bits, obtained by combining the above three groups of N+M+R=128+24+16 data, address and ECC bits, and each super page is formed by several extended pages (i.e., a group of 168x 2 bits).

[0080] As a non-limiting numerical example only, each row of memory block 460 contains sixteen extended pages. Thus, the resulting row contains 2688 bits, from the combination of sixteen independently addressable extended pages each containing 168 bits, in other words, from the combination of eight super pages.

[0081] In an embodiment of the present disclosure, the output of the general subarray 390 is configured to combine the following sequence: N data units plus M address units plus R ECC units. In this non-limiting example, the total amount of bits will involve 168 pads per channel, such as Figure 5 As shown in the example.

[0082] The combined string of data cells + address cells + ECC cells enables safe coverage of the bus consistent with standard requirements, because the ECC covers the entire bus communication (data cells + address cells), and the presence of the address cells provides confidence that the data comes completely from the location addressed by the controller.

[0083] The sense amplifier SA of each sub-array 390 is connected to the scan chain of the modified JTAG cell 700, thereby connecting all outputs of one sub-array 390 together, as shown in FIG. Figure 6 and 7 as shown in .

[0084] The present disclosure relates to a memory device having an improved sensing structure and comprising:

[0085] - a memory array comprising a plurality of memory cell sub-arrays and structured in a memory block;

[0086] - a sense amplifier coupled to the memory cell;

[0087] - A modified JTAG cell coupled in parallel to the output of the sense amplifier and interconnected in series in a scan chain structure, thereby integrating the JTAG structure and the sense amplifier.

[0088] The scan chain structures associated with each sub-array are interconnected to form a unique chain as a boundary scan register.In addition, a boundary scan register is a test structure for testing the interconnection of the sense amplifiers.

[0089] Figure 6A schematic diagram of a memory portion is shown, wherein a sub-array 390 is architected to service at least one channel of a SoC structure 110 associated with a memory component 100 , 200 , or 300 .

[0090] In this Figure 7 , an example is shown in which modified JTAG cells 700 associated with a sub-array 390 may be interconnected to form a unique scan chain 1000 for quickly checking the integrity of pad interconnects.

[0091] Due to the memory architecture of the present disclosure, it is possible to switch from a parallel mode for retrieving data and addresses from the memory sub-array 390 to a serial mode for checking the interconnection between the memory component 100 and the associated SoC device 110. In addition, the SoC 110 has the ability to read once a '1' and once a '0' to perform testing, and can also analyze the memory results, using the scan chain to scan the data.

[0092] It should also be noted that each sub-array 390 includes address registers connected to data buffer registers, similar to the architecture used in DRAM memory devices, ie, DDRX type in 3DXP or as LPDDRx.

[0093] In the following paragraphs of this disclosure, it will be apparent that the output of the sense amplifier SA of each sub-array 390 is latched by internal circuitry in order to allow the sense amplifier to perform another internal read operation, thereby preparing a second nibble or a second group of 168 bits. This second nibble is transferred to the output of the flash array 320 using an additional enable signal (i.e., an internal clock signal or an ADV signal; ADV=address data valid. In this case, the signal is load_data[1:0], depending on the addressed flip-flop), which transfers the content read at the sense amplifier level to the host device or SoC device 110.

[0094] In other words, the internal sense amplifiers prepare two extended pages 450, and when the first page is ready to be shifted (i.e., shifted out), the read phase of the second page associated with the same address is performed internally. This allows five to eight double words to be prepared (in this example), which is typical in RTOS applications. In any case, the disclosed structure can be extended to enable multi-page reads when shifting out the read pages.

[0095] The sense amplifier SA is directly connected to the modified JTAG cell 700 (which will be disclosed in more detail later) so as to integrate the JTAG structure and the sense amplifier into a single circuit portion. This can reduce the delay in propagating the output of the memory array to the SoC 110 as much as possible.

[0096] Just to report numerical examples based on the embodiments disclosed herein, we can note that each address in the address buffer is connected to a data buffer, which contains, for example, N data bits (i.e., 128 bits). However, the SoC may need up to 2*N bits at a time (i.e., 256 bits, without address bits and ECC), so the data buffer will be replicated to be able to shift, assuming address 0 of subarray 0 is used:

[0097] The first group of N bits in the first pass: data 0_0_H[127:0]+ADD+ECC

[0098] The second group of N bits in the second pass: data 0_0_L[127:0]+ADD+ECC

[0099] The above indications are standard readings used, for example, for security purposes and data integrity / correction purposes.

[0100] In one embodiment, the address buffer is implemented using a modified JTAG unit 620, as we will see below.

[0101] In one embodiment of the present disclosure, each sub-array 390 is independently addressable within the memory device 100 .

[0102] The JTAG unit 620 operates as follows: Figure 6 and 7 Connect as shown in:

[0103] PIN: Output of the sense amplifier

[0104] POUT: data I / O to the corresponding SoC

[0105] SIN: is the serial IN input connected to the SOUT of the previous sense amplifier

[0106] SOUT: is the serial output connected to SIN of the next sense amplifier

[0107] The use of serial input and output scan chain 600 formed by interconnected JTAG cells 620 has several advantages:

[0108] - Capability to test successful interconnection between SoC and Direct Memory Access (DMA) memory;

[0109] - Ability to perform digital testing of sense amplifiers, since cell 620 can act as a program load to store data inside the array;

[0110] -Can act as a second level latch.

[0111] We will see later in this disclosure that when the first set of data bits (extended page) is ready to be transferred to the parallel output POUT of the sense amplifier, there is an internal latch coupled to the sense amplifier that can trigger the read data of the subsequent portion of the remaining data bits (the second extended page).

[0112] Still reference Figure 6 and 7 As an example, we can consider the interconnections of each JTAG cell 620: PIN is coupled to the output of a sense amplifier; POUT is coupled to the corresponding data I / O of the host device 110 (i.e., the system on chip); SIN is the serial IN input connected to SOUT of the previous sense amplifier, and SOUT is the serial output connected to SIN of the next sense amplifier.

[0113] For example, Figure 7 The schematic example of FIG. 1 shows a schematic diagram and a universal memory cell MC located at the intersection of a memory cell row and a memory cell column in a cell matrix of a universal subarray so that the cell can be addressed accordingly. A practical implementation may contain additional circuits from the cell to the SA output, but for the purposes of this disclosure, they are not shown as irrelevant.

[0114] Sense amplifiers SA are coupled to the columns of memory cells as part of the read circuitry used when reading data from the memory array. Generally, one memory word is read at a time comprising the extended page 450 described above, and in this example we will refer to a memory page comprising data+address+ECC bits.

[0115] As is well known, the role of the sense amplifier SA is to sense the low power signal from the array row. The low voltage value representing the logic data bit (1 or 0, depending on the convention) stored in the memory cell MC is amplified to a recognizable logic level so that the data can be correctly interpreted by the logic circuit part outside the memory.

[0116] In the examples disclosed herein, the output of each sense amplifier SA is coupled to a modified JTAG cell 620 so as to integrate the JTAG structure and the sense amplifier.

[0117] In the non-limiting example disclosed herein, the output amplifier OA is inserted between the sense amplifier SA and the JTAG cell 700 .

[0118] Due to the memory architecture of the present disclosure, it is possible to switch from a parallel mode for retrieving data and addresses from the memory sub-array 390 to a serial mode for checking the interconnection between the memory component 210 and the associated host device. In addition, the SoC has the power to read once a '1' and once a '0' to perform the test, and can also analyze the memory results, using the scan chain to scan the data.

[0119] The transition from parallel mode to serial mode is managed by the JTAG interface 350. However, implementation of these dual mode operations is achieved through the specific structure of the modified JTAG unit 620 disclosed below.

[0120] Figure 8 Show Figure 3 300, but in more detail illustrating aspects of data exchange. Figure 3 The JTAG interface 800 of the interface 350 is indicated as receiving as input the standard JTAG signals: TMS, TCK, TDI and data from an N-bit memory page received on K buses. These data and the TDI signal can be considered as flexible TDI. The flexibility is because the number of parallel bits that work as TDI depends on the selected register, i.e., four lines for the instruction register, eight lines for the address register, 128 lines for the data register, etc., and the TDI comes from the JTAG protocol, which uses TDI as a name on the signal used to fill the register.

[0121] This control and JTAG interface 800 generates data, address and control signals as outputs which are transferred to the memory address decoder 820 and the internal flash controller to perform the modify operation.

[0122] The decoder activity is accomplished by a charge pump 840 that is configured to manage the array's voltage and timing confidentially.

[0123] This decoder 820 is coupled to a read interface 860 that communicates with the host or SoC device 110 through a control and status bus.

[0124] The output of the read interface 860 is represented by an extended page containing a combined string of data cells+address cells+ECC cells.

[0125] In the examples disclosed herein, the total amount of bits would involve 168 pads per channel in the embodiments disclosed herein.

[0126] Now more specifically refer to Fig. 9 Schematic example, which shows a modification according to the present disclosure and the same as the previous reference Figure 6 and 7 The modified JTAG unit 620 corresponds to the disclosed JTAG unit 900 .

[0127] The JTAG cell 900 has a first parallel input PIN terminal and a first serial input SIN terminal for receiving corresponding signals Pin and Sin. In addition, the JTAG cell 900 has a first parallel output terminal POUT and a first serial output terminal SOUT. The scan chain 600 allows the output of the entire 168 bits x2, because the first group is read directly from the output, and the second group is prepared later.

[0128] like Fig.10 As shown in , the JTAG unit 900 can be regarded as a block having two input terminals PIN and SIN and two output terminals POUT and SOUT. The input terminal PIN is a parallel input, while the input terminal SIN is a serial input. Similarly, the output terminal POUT is a parallel output, while the output terminal SOUT is a serial output.

[0129] Due to the serial input and output, a test process can be performed to check that there are no faulty connections between the memory component 100 and the associated system on chip 110. Due to the parallel input and output, the same JTAG cell is used as a data buffer to complete the read phase through the sense amplifier SA.

[0130] The JTAG cell 900 comprises a boundary scan basic cell 980 , which contains several latches 901 and 902 and several multiplexers 951 and 952 : a first input multiplexer 951 and a second output multiplexer 952 .

[0131] The boundary scan basic unit 980 is indicated as Fig.10 The dashed box in , and is a dual-input unit, where the serial input corresponds to SIN and the parallel input corresponds to PIN, and is also a dual-output unit, where the serial output corresponds to SOUT and the parallel output corresponds to POUT.

[0132] The first multiplexer 951 receives a parallel input signal Pin from a first parallel input terminal PIN on a first input “0” and receives a serial input signal Sin from a first serial input terminal SIN on a second input “1”.

[0133] This first multiplexer 951 is driven by the control signal ShiftIR (called the instruction register signal) and has an output MO1. The unit 900 has two parallel outputs, namely MO1 and MO2. The serial output is driven from SOUT when the JTAG clock arrives. SOUT is connected to a JTAG latch close to the multiplexer that receives the following selector signal: Mode Controller (Serial / Parallel). Basically, the output of the latch connected to the input '1' of this multiplexer MO2 is also SOUT.

[0134] The first multiplexer output MO1 is connected to a first input of a first latch 901 which receives a clock signal ClockDR at a second input terminal.

[0135] The first latch 901 is chain-connected to the second latch 902 , wherein a first output of the first latch 901 is connected to a first input of the second latch 902 .

[0136] It is important to note that the output of the first latch 901 is also the serial output SOUT of the entire JTAG cell 900 .

[0137] The second input terminal of the second latch 902 receives the signal UpdateDR.

[0138] The second latch 902 has an output connected to an input of the second multiplexer 952 (specifically, the second input thereof).

[0139] This second multiplexer 952 is controlled by a mode control signal which allows switching the entire JTAG unit 900 from serial mode to parallel mode and from parallel mode to serial mode.

[0140] In one embodiment of the present disclosure, the JTAG unit 900 further includes several additional latches 921 and 922 disposed between the parallel input pins and the second multiplexer 952. These additional latches 921 and 922 are latches for direct reading (i.e., the first group of data bits) and shadow reading (i.e., the second group of 128 data bits) (not considering the address bits and ECC, i.e., a total of 168 bits). In other words, the JTAG unit 900 includes a boundary scan unit 980 and at least the additional latches 921 and 922.

[0141] We will refer to these additional latches hereinafter as third latch 921 and fourth latch 922. In other embodiments, longer latch chains may be used.

[0142] More specifically, the third latch 921 and the fourth latch 922 are connected in a small pipeline configuration, where the third latch 921 receives the parallel input signal Pin from the first parallel input terminal PIN on a first input and receives the signal Data_Load[0] corresponding to the previously mentioned AVD signal and the first data load on a second input.

[0143] The fourth latch 922 receives the output of the third latch 921 on a first input and receives a signal Data_Load[1] (always the AVD signal) corresponding to subsequent data loading on a second input.

[0144] The output of the fourth latch 922 is connected to a first input “0” of a second multiplexer 952 , which generates an output signal for a parallel output terminal POUT at its output terminal MO2 .

[0145] Compared to a conventional JTAG cell, the JTAG cell 900 of the present disclosure may be considered a modified JTAG cell because, in addition to the boundary scan cell 980 , there are two additional latches, namely, a third latch 921 and a fourth latch 922 .

[0146] Now, we have to imagine a JTAG cell 900 coupled to the output of each sense amplifier SA of the memory sub-array 390. As usual, the memory array provides one sense amplifier for each column of memory cells, such as Figure 7 shown.

[0147] In an embodiment of the present disclosure, all JTAG cells 900 coupled to the sense amplifiers of the memory sub-arrays will be considered as data buffers containing a page of data, in this example containing at least one hundred and twenty-eight (128) bits (always without address bits and ECC bits), for reading the combined memory page from four sub-arrays 390 at a time.

[0148] However, as previously mentioned, the communication channel between the memory component and the SoC structure may require up to 256 bits at a time (i.e., two combined extended memory pages = one super page), but in the present disclosure, 2x16 plus 2x24 bits are also required. The JTAG unit 900 has been modified to replicate only the internal latches to be able to shift the first or higher portion of the 168 bits of data to be read with the second or lower portion of the data to be read. Obviously, in this context, "higher" means the portion of data loaded before, and "lower" means the portion of data loaded after.

[0149] Those skilled in the art will appreciate that where it is desired to increase the number of bits transferred to the SoC fabric via the communication channel, the number of internal latches of the modified JTAG unit 900 may be increased. For example, the above fabric may be scaled accordingly depending on the page size required by a particular implementation of the memory controller.

[0150] Just to explain the way data are transferred in the data buffer, we have to imagine that when data is loaded into one of the two latches 921 or 922, the other latch is in standby state but is ready to receive the subsequent data portion.

[0151] Thus, a first portion containing 168 bits (including address bits and ECC bits) is transferred to the SoC structure for a first data elaboration, while the read phase is not stopped because another portion of 168 bits is ready to be loaded into the latches at a subsequent clock signal.

[0152] In this example, each data buffer contains 168 modified JTAG cells 900, and a common Data_Load[1:0] is a signal generated to allow capturing of the entire 168 bits x2, ie, eight double words DW (each double word having four subarrays) according to the proposed implementation.

[0153] When a read operation is performed in a specific data buffer, the signal generation is controlled internally, and the signal is controlled by the SoC structure to allow the read phase to be performed using 168 bits of parallelism.

[0154] The main benefit of this memory architecture is that each buffer can contain an entire double word DW, leaving the sense amplifier free to read another memory location.

[0155] The presence of the modified JTAG cell 900 as the output of the sense amplifier is particularly important because it allows:

[0156] a. Using boundary scan as a method of checking the interconnection between the SoC 110 and the flash array component 100, 200 or 300;

[0157] b. Implementing direct memory access by directly connecting the sense amplifier to the controller;

[0158] c. Allow the sense amplifier to prepare the second 128-bit wide page plus address plus ECC and write close to the page.

[0159] According to some embodiments, a boundary scan test architecture including the modified JTAG cell 900 may be employed, thereby obtaining a new and unique boundary scan test architecture, as in Fig.10 Therefore, for this test, only one output driver is required, which is obtained using the signal TCK and the data stored in the cell. The scan chain test requires the SoC 110 to test the output of the scan chain.

[0160] As is known in this specific technical field, boundary scan is a family of test methodologies designed to solve many test problems: from chip level to system level, from logic cores to interconnections between cores, and from digital circuits to analog or mixed-mode circuits.

[0161] The boundary scan test architecture 1000 provides a means to test the interconnections between the integrated circuits 100 and 110 on the board without using physical test probes. It adds a boundary scan cell 900, such as Fig.10 As shown, multiplexers and latches are included and are associated with each pin or pad on the device.

[0162] In other words, each primary input signal and primary output signal of a complex semiconductor device, such as memory component 100 or host device 110, is supplemented with a multi-purpose memory element called a boundary scan cell, which together form a serial shift register 1050 around the device boundary.

[0163] Initially, these boundary scan cells were introduced as a means to test individual semiconductor devices. The original motivation for including boundary scan cells in semiconductor devices was to test the presence, orientation, and bonding of devices in place on a circuit board.

[0164] According to the present disclosure, boundary scan cells 900 are used to test the interconnections between integrated circuits that work together (e.g., system-on-chip 110 and associated memory components 100, 200, or 300), as is the case with the present disclosure.

[0165] The collection of boundary scan cells is configured as a parallel input or parallel output shift register, and the boundary scan path is not affected by the functions of the host device. The required digital logic is contained within the boundary scan register. Obviously, the external JTAG FSM interacts with the cells, i.e., shiftDR, shiftIR, UpdateDR, etc. are driven by the JTAG logic 350.

[0166] To very briefly summarize the function of the boundary scan cell, it can be said that each cell 900 is constructed to capture data on its parallel input PI; update the data to its parallel output PO; serially scan the data from its serial output SO to its nearby serial input SI. Additionally, each cell behaves transparently in the sense that the data passed from PI to PO.

[0167] Fig.10 A schematic diagram showing a standard architecture using boundary scan cells configured according to the IEEE Standard No. 1149.1. However, according to the present disclosure, the boundary scan cells used in architecture 1000 are the modified JTAG cells 900 previously referenced Fig. 9 disclosed.

[0168] The JTAG interface is a special interface added to the chip. According to this embodiment, two, four, or five pins are added to allow for the expansion of JTAG as needed according to this implementation.

[0169] The connector pins are: TDI (Test Data Input); TDO (Test Data Output); TCK (Test Clock); TMS (Test Mode Select) and optionally TRST (Test Reset).

[0170] The TRST pin is an optional active-low reset for the test logic, usually asynchronous, but sometimes synchronous, depending on the chip. If the pin is not available, then the test logic can be reset by using TCK and TMS to switch to a reset state synchronously. Note that resetting the test logic does not necessarily mean resetting anything else. There are usually some processor-specific JTAG operations that can reset all or part of the chip being debugged.

[0171] Since only one data line is available, the protocol is serial. The clock input is at the TCK pin. One data bit is clocked in at TDI and out to TDO on each rising edge of the TCK clock. Different instructions can be loaded. Instructions for a typical IC might read the chip ID, sample an input pin, drive (or float) an output pin, manipulate chip functionality, or bypass (transfer from TDI to TDO to logically shorten a chain of multiple chips).

[0172] As with any timed signal, data presented to TDI must be valid for some chip-specific setup time before the associated (here, rising) clock edge and for some hold time after. TDO data is valid for some chip-specific time after the falling edge of TCK.

[0173] Figure 8 A set of four dedicated test pins are shown - test data input (TDI), test mode select (TMS), test clock (TCK), test data output (TDO) - and one optional test pin test reset (TRST).

[0174] These pins are collectively referred to as the Test Access Port (TAP). However, the architecture 1000 includes a finite state machine, named TAP controller 1070, which receives as input three signals: TCK, TMS, and TRST. TAP controller 1070 is a 16-state final state machine FSM that controls each step of the operation of the boundary scan architecture 1000. Each instruction to be executed by the boundary scan architecture 1000 is stored in instruction register 1020.

[0175] Fig.10 A plurality of boundary scan cells 900 are shown on the primary input and primary output pins of the device. The cells 900 are connected internally to form a serial boundary scan register 1050. In other words, the modified JTAG cells 900 serve as building blocks of the boundary scan architecture 1000.

[0176] Data may also be shifted in a serial pattern around boundary scan shift register 1050 , starting at a dedicated device input pin called “test data input (TDI)” and terminating at a dedicated device output pin called “test data output (TDO)” at the output of multiplexer 1060 .

[0177] The test clock TCK is selectively sent to each register depending on the TAP state and to the register select; the feeding of the TCK signal is performed via a dedicated device input pin and the operation mode is controlled by a dedicated "Test Mode Select (TMS)" serial control signal.

[0178] The instruction register (IR) 1020 contains n bits (where n≥2) and is implemented to hold each current instruction, but can be extended to handle flexible TDI.

[0179] According to the IEEE 1149 standard, the architecture is equipped with the following: a 1-bit bypass register 1040 (Bypass); an optional 32-bit identification register 1030 (Ident), which can be loaded with a permanent device identification code.

[0180] At any time, only one register can be connected between TDI and TDO (e.g., IR, Bypass, Boundary Scan, Ident, or even some appropriate register inside the core logic). The selected register is identified by the decoded output of the IR. Some instructions are mandatory, such as Extest (Boundary Scan register selected), while other instructions are optional, such as the Idcode instruction (Ident register selected).

[0181] The parallel load operation is called a "capture" operation, where data is captured by the instruction into the selected register cell. Capture causes the value of the signal on the device input pin to be loaded into the input cell, and causes the value of the signal passed from the core logic to the device output pin to be loaded into the output cell.

[0182] The parallel offload operation is called an "update" operation to freeze the register contents. Basically, it latches the contents of the executable shadow registers within the BS unit. This update allows the shift register to be ready for future incoming data / instructions. Additionally, the PAUSE instruction allows the data to be saved in the registers even if the update is not completed.

[0183] Depending on the nature of the input scan cell, the signal value already present in the scan cell will be passed to the core logic.

[0184] Now, in one embodiment of the present disclosure, the boundary scan architecture 1000 is provided with another or more than one additional register 1080, which is dedicated to managing the memory component 100. This additional register 1080 can also be defined by the user. The IEEE 1532 standard allows this extension.

[0185] The composition of registers incorporated into the boundary scan architecture 1000 of the present disclosure has been omitted so as not to limit the present disclosure with undue information.

[0186] As previously disclosed, and to summarize the principles of the present disclosure, in some embodiments of the present disclosure, the output of the general subarray 390 is formed by combining the following sequence: data unit plus address unit plus ECC unit. In this non-limiting example, the total amount of bits will involve 168 pads per channel, e.g. Figure 5 as shown in .

[0187] The combined string of data cells + address cells + ECC cells enables safe coverage of the bus consistent with standard requirements, because the ECC covers the entire bus communication (data cells + address cells), and the presence of the address cells provides confidence that the data comes completely from the location addressed by the controller.

[0188] The sense amplifiers SA of each subarray 390 are connected to the scan chain of modified JTAG cells 900, thereby connecting together all outputs of one subarray 390. In addition, modified JTAG cells 900 associated with subarrays 390 can be interconnected to form a unique chain for quickly checking the integrity of pad interconnects.

[0189] Due to the memory architecture of the present disclosure, it is possible to switch from a parallel mode for retrieving data and addresses from the memory sub-array 390 to a serial mode for checking the interconnection between the memory component 100 and the associated SoC device 110. In addition, the SoC has the power to read once a '1' and once a '0' to perform the test, and can also analyze the memory results, using the scan chain to scan the data.

[0190] As an operation, error correction is left to the SoC 110; additional bits are provided to the controller to store any possible ECC syndromes associated with the page. The ECC unit enables the SoC controller to understand if data and address content is corrupted.

[0191] To write and erase the memory cells of array 320, a dedicated logic circuit portion is provided, which includes a simplified reduced instruction set computer (RISC) controller or a modified finite state machine, or logic circuits for processing programming and erasing algorithms.

[0192] In addition, the JTAG interface 350 is used as a conventional user interface to modify the array and provide read addresses to the memory blocks. The JTAG interface 350 is also used for testing of the memory component 100, so that the test tools can be reused. Therefore, the memory component 100 (or 200 or 300) also includes JTAG logic.

[0193] Direct memory access reduces the final latency that the SoC may experience when reading data. In addition, the final latency is also reduced due to the block size, the distribution of sense amplifiers between blocks, the selection of comparison thresholds in the sense amplifiers, and the optimized paths.

[0194] Although specific examples have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover modifications or variations of one or more embodiments of the present disclosure. It should be understood that the above description is by way of illustration and not by way of limitation. The scope of one or more examples of the present disclosure should be determined with reference to the attached claims and the full range of equivalents given by these claims.

Claims

1. A memory device, comprising: a memory array comprising a plurality of memory cell sub-arrays and structured in a memory block, in: Each sub-array corresponds to a different core of a system-on-chip (SoC) structure; and each core coupled to a different respective channel for receiving data at the memory device and transmitting data from the memory device; a sense amplifier coupled to the memory cell; A modified JTAG cell is coupled in parallel to the output of the sense amplifier and interconnected in series in a scan chain structure, thereby integrating the JTAG structure and the sense amplifier.

2. The memory device according to claim 1, in: The scan chain structures associated with each sub-array are interconnected to form a unique chain as a boundary scan register; and The boundary scan register includes a test structure for testing interconnections of the sense amplifier.

3. The memory device of claim 1 , wherein the modified JTAG cell comprises: serial and parallel input and output, and A latch is interposed between the parallel input and output, the latch being used to load a memory page prior to reading a subsequent memory page from the sub-array.

4. The memory device of claim 1, wherein the scan chain structure comprises a data buffer configured to include memory data pages at a time when reading different data pages from the memory array.

5. The memory device of claim 4, wherein the memory data page comprises N data cells, M address cells, R ECC cells, and at least one hundred sixty eight (168) bits.

6. The memory device according to claim 1, in: The output of the general sub-array is configured to combine N data cells, M address cells, and R ECC cells; and N+M+R is 168 bits or larger.

7. The memory device of claim 1, wherein the sense amplifier is connected to the SoC structure through the scan chain structure in a direct memory access configuration.

8. A memory device comprising: Memory array; A JTAG logic interface portion configured to interact with a system-on-chip (SoC) structure through a communication channel and comprising: A memory array comprising a plurality of memory cell sub-arrays and structured in a memory block, wherein: Each sub-array corresponds to a different core of the SoC structure; and each core coupled to a different respective communication channel for receiving data at the memory device and transmitting data from the memory device; a sense amplifier coupled to the memory cell and the communication channel; A modified JTAG cell is coupled in parallel to the output of the sense amplifier and interconnected in series in a scan chain structure, thereby integrating the JTAG structure and the sense amplifier.

9. The memory device of claim 8, wherein the scan chain structures associated with each sub-array are interconnected to form a unique chain as a boundary scan register.

10. The memory device of claim 8, wherein the modified JTAG cell includes serial and parallel inputs and outputs, and a latch interposed between the parallel inputs and outputs.

11. The memory device of claim 8, wherein latches are inserted between parallel inputs and outputs of the modified JTAG cell to load a memory page before a subsequent memory page is read from a sub-array.

12. The memory device according to claim 8, in: The scan chain structure includes a data buffer configured to contain memory data pages at a time while reading different data pages from the memory array; and The memory data page includes N data units, M address units, R ECC units, and at least one hundred sixty eight (168) bits.

13. The memory device of claim 8, wherein the output of the subarray is formed by combining a sequence comprising: N data cells plus M address cells plus R ECC cells.

14. The memory device of claim 8, wherein the output of the subarrays is formed by combining sequences comprising at least 168 bits.

15. An integrated semiconductor device comprising: A system-on-chip (SoC) structure includes an interconnect pad; and A memory device comprising an interconnect pad, wherein the memory device is coupled to the SoC structure via the interconnect pad in a face-to-face manner, and wherein the memory device include: A memory array comprising a plurality of memory cell sub-arrays and structured in a memory block, wherein: Each sub-array corresponds to a different core of the SoC structure; and each core coupled to a different respective communication channel for receiving data at the memory device and transmitting data from the memory device; a sense amplifier coupled to the memory cell and a communication channel; A modified JTAG cell is coupled in parallel to the output of the sense amplifier and interconnected in series in a scan chain structure, thereby integrating the JTAG structure and the sense amplifier.

16. The integrated semiconductor device of claim 15, wherein the memory array comprises non-volatile memory cells and is connected to the SoC structure in a direct memory access configuration.

17. The integrated semiconductor device of claim 15, wherein the memory device includes a scan chain structure associated with each subarray that is interconnected to form a unique chain as a boundary scan register, wherein the boundary scan register is a test structure for testing interconnections of the sense amplifier.

18. The integrated semiconductor device of claim 15, wherein the scan chain structure comprises a data buffer configured to include at least one memory data page at a time when reading different data pages from the memory array.

19. The integrated semiconductor device of claim 15, wherein the memory device structure is independent of the SoC structure.

20. The integrated semiconductor device of claim 15, wherein the modified JTAG cell includes serial and parallel inputs and outputs, and latches interposed between the parallel inputs and outputs, the latches being used to load a memory page prior to reading a subsequent memory page from a sub-array.

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