Semiconductor package substrate fine pitch metal bump and reinforcement structure

Abstract

Semiconductor package substrates and processing sequences are described. In embodiments, a package substrate includes a build-up structure and a patterned metal contact layer partially embedded within and protruding from the build-up structure. The patterned metal contact layer can include an array of surface mount (SMT) metal bumps in a chip mounting region, a metal dam structure, or a combination thereof.

Description

Technical Field

[0001] The embodiments described herein relate to semiconductor packaging, and more specifically, to metal bumps and mechanical reinforcement structures. Background Technology

[0002] Miniaturization is a trend in the semiconductor industry driving the production of thinner, smaller form factors. Coreless substrates, especially those with materials based on Ajinomoto laminate (ABF), have been used in the industry to produce thin dielectric layers without glass-textured reinforcement structures. However, from a mechanical point of view, such thin substrates are inherently weaker, especially due to the lack of a thick core.

[0003] Furthermore, advanced flip-chip packaging substrates require finer bump pitches to support smaller wafer node technologies. In some implementations, due to yield and tooling limitations, conventional solder on-padded (SOP) surface finishing tends to support bump pitches greater than 100 μm. Surface mount (SMT) metal bumps have been introduced into the industry to accommodate finer bump pitches, where the SMT metal bumps on the packaging substrate serve as functional via landing pads for die connections. Summary of the Invention

[0004] This invention describes a packaging substrate for forming a patterned metal substrate layer and a method for manufacturing the same. The patterned metal substrate layer includes an SMT metal bump array, a metal dike structure, or a combination thereof, wherein the patterned metal substrate layer is partially embedded within and protrudes from a stacked structure. According to embodiments, the SMT metal bumps and metal dike structures may have distinctive straight sidewalls for the portion of the patterned metal substrate layer embedded in the stacked structure and for the portion of the patterned metal substrate layer extending above the topmost surface of the stacked structure laterally adjacent to the SMT metal bumps or metal dike structure.

[0005] The patterned metal substrate layer according to the implementation plan can be revealed using a back-etching technique, wherein the back-etching operation can be performed before or after the formation of the surface finishing layer. Attached Figure Description

[0006] Figure 1 This is a close-up cross-sectional side view of a package substrate including a stacked structure and a patterned metal contact layer according to an embodiment, wherein the patterned metal contact layer is partially embedded in and protrudes from the stacked structure.

[0007] Figure 2 This is a schematic top view illustration of various metal embankment structures according to the implementation plan.

[0008] Figure 3AThis is a close-up cross-sectional side view of a semiconductor package according to an embodiment, the semiconductor package including devices mounted on a package substrate manufactured using a post-etching surface finishing technique.

[0009] Figure 3B This is a close-up cross-sectional side view of a semiconductor package according to an embodiment, the semiconductor package including devices mounted on a package substrate manufactured using a surface finishing technique prior to etching back.

[0010] Figure 4 This is a flowchart illustrating a method for manufacturing a packaging substrate using post-etch-back surface finishing technology and pre-etch-back surface finishing technology, according to an implementation scheme.

[0011] Figures 5A-5G This is a schematic cross-sectional side view of the manufacturing sequence of surface finishing after etching according to the implementation plan.

[0012] Figures 6A-6G This is a schematic cross-sectional side view of the manufacturing sequence of surface finishing prior to the etching process according to the implementation plan.

[0013] Figures 7A-7C This is a schematic cross-sectional side view of an SMT metal bump manufactured according to the surface finishing manufacturing sequence following the etching process, as per the implementation plan.

[0014] Figures 8A-8C This is a schematic cross-sectional side view of an SMT metal bump manufactured according to the surface finishing manufacturing sequence prior to etchback, as per the implementation plan.

[0015] Figures 9A-9B This is a close-up cross-sectional side view of a package substrate variant according to an embodiment, the package substrate variant including a metal embankment structure protruding above an SMT metal bump array.

[0016] Figures 10A-10G It is used to form according to the implementation plan. Figure 9A A schematic cross-sectional side view of the manufacturing sequence of surface finishing after the re-etching of the structure.

[0017] Figures 11A-11G It is used to form according to the implementation plan. Figure 9B A schematic cross-sectional side view of the manufacturing sequence of surface finishing after the re-etching of the structure.

[0018] Figures 12A-12B This is a close-up cross-sectional side view of a package substrate variant according to an embodiment, the package substrate variant including trenches formed in a stacked structure between an SMT metal bump array and a metal dike structure.

[0019] Figures 13A-13FIt is used to form according to the implementation plan. Figure 12A A schematic cross-sectional side view of the manufacturing sequence of surface finishing after the re-etching of the structure.

[0020] Figures 14A-14F It is used to form according to the implementation plan. Figure 12B A schematic cross-sectional side view of the manufacturing sequence of surface finishing after the re-etching of the structure. Detailed Implementation

[0021] The implementation describes the semiconductor packaging substrate processing sequence and structure, in which surface mount (SMT) metal bumps and reinforcement structures can be formed simultaneously to achieve both fine bump pitch and structural reinforcement.

[0022] It has been observed that SMT metal bumping technology faces challenges in achieving precise and robust bump diameters and heights, particularly for applications with multiple dies of large size in multi-chip modules (MCMs). An SMT metal bump structure according to an embodiment is fabricated using a processing sequence in which the SMT metal bumps (also referred to herein simply as metal bumps) are revealed after etching (thinning) the package substrate stack structure. According to an embodiment, the metal bumps can be formed via a lithography process that causes the metal bumps to be embedded in a dielectric layer, such as the top dielectric layer (encapsulation) used for the package substrate stack structure. For example, this could be a coreless substrate. A metal seed etching is then performed, which does not erode the sidewalls of the metal bumps (pads) and maintains the pad dimensions as designed. Furthermore, no additional copper plating post-processing is required. Various surface finishing techniques can be combined with the formation of the metal bumps, such as electroless nickel-palladium immersion gold (ENEPIG), organic solderability protectants (OSP), etc.

[0023] It has been observed that electronic failures can occur in thin package substrates (such as coreless substrates) during thermal cycling, drop testing, etc., due to via or trace cracking at die corners. Inconsistent die underfill volume around die corners has also been observed. The reinforcement structure according to the embodiment can mechanically reinforce the package substrate at designated locations to resist mechanical stress and manufacturing and reliability issues under harsh conditions. Furthermore, the reinforcement structure can confine the underfill material flow at designated locations and maintain its shape (e.g., rounded corners). For example, the reinforcement structure can maintain sufficient underfill material at die corners to cover at least 50% of the die silicon thickness. The reinforcement structure can also be designed to accommodate different types of underfill materials through various types of surface finishing or post-processing (e.g., Ni / Au, Ni, grain size, and metal-organic coatings). Importantly, the reinforcement structure can be formed simultaneously with SMT metal bump patterning, thereby providing an integrated method and structure for fine-pitch die attachment and package substrate reinforcement.

[0024] Various embodiments are described with reference to the accompanying drawings. However, certain embodiments may be practiced without one or more of these specific details or in combination with other known methods and constructions. In the following description, numerous specific details such as particular configurations, dimensions, and processes are shown to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the embodiments. The phrase "an embodiment" as used throughout the specification means that a particular feature, structure, construction, or characteristic described in connection with an embodiment is included in at least one embodiment. Therefore, the repeated use of the phrase "in an embodiment" throughout the specification does not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, construction, or characteristic may be combined in any suitable manner in one or more embodiments.

[0025] As used herein, the terms “above,” “over,” “to,” “between,” “across,” and “on” can refer to the relative position of one layer with respect to other layers. A layer being “above,” “over,” “across,” or “on” with respect to another layer, or being “in contact” with another layer, can mean directly contacting other layers or having one or more intermediary layers. A layer being “between” multiple layers can mean directly contacting those multiple layers or having one or more intermediary layers.

[0026] Now for reference Figure 1 A close-up cross-sectional side view of a packaging substrate 100 is provided, the packaging substrate including a stacked structure 110 and a patterned metal contact layer 120 partially embedded in and protruding from the stacked structure 110. It should be understood that... Figure 1 This illustration shows only a portion of the package substrate 100 illustrating several related features. As shown, the patterned metal contact layer 120 includes an array of surface mount (SMT) metal bumps 122 in landing regions 123A, 123B, etc. The SMT metal bumps 122, according to an embodiment, can serve as landing pads, and their size and spacing are set depending on the device structure to be mounted. For example, the size of the SMT metal bumps 122 in landing region 123A can be set to receive a chip (or die) such as a SoC chip. The SMT metal bumps 122 in landing region 123B can be larger and their size can be set to receive a chip-scale package (CSP). The patterned metal contact layer 120 may additionally include a metal embankment structure 124 in a support region 125. This metal embankment structure 124 may be formed laterally adjacent to the SMT metal bumps 122 in landing regions 123A, 123B.

[0027] The stacked structure 110 may include one or more dielectric layers 114 and metal wiring layers 114. Through-holes 116 may be used to connect the metal wiring layers 114. Through-holes 116 may also be used to connect the metal wiring layers 114 to STM metal bumps 122 and contact pads 118 on the back side of the package substrate 100. For example, contact pads 118 may be used to receive solder bumps (e.g., ball grid arrays) for mounting onto a circuit board. Still referring to... Figure 1 The stacked structure 110 may include a top dielectric layer 115 embedded therein, with a patterned metal contact layer 120 therein. Alternatively, the metallization layer may be embedded within multiple layers of the stacked structure 110.

[0028] The stacked structure 110 according to the embodiment can be formed using thin-film processing techniques. For example, the stacked structure 110 can be formed using a semi-additive ABF process, which includes lamination and curing steps of ABF resin, laser via opening formation, and copper plating to form vias 116 and a metal wiring layer 114. According to the embodiment, dielectric layers 112 and 115 can be non-glass-reinforced organic materials. Furthermore, the encapsulation substrate 100 can be a coreless substrate. The metal dike structure 124 according to the embodiment can provide structural integrity to the encapsulation substrate 100 without requiring additional mechanical support from a core or glass-reinforced structure. However, the metal dike structure 124 according to the embodiment does not preclude the incorporation of a core or glass-reinforced structure.

[0029] See now Figure 2 Schematic top-view illustrations of various metal dike structures according to embodiments are provided. In one embodiment, the metal dike structure 124 includes multiple parallel metal lines 124A extending parallel to the edge 202 of a device 200 mounted on an array of SMT metal bumps 122. In another embodiment, the metal dike structure 124 includes an array or metal plane 124C of repeating geometries 124B adjacent to corners of the device 200 mounted on the SMT metal bump array. In yet another embodiment, the metal dike structure 124 may laterally surround (e.g., completely laterally surround) the array of SMT metal bumps 122 in a chip mounting region. Multiple metal dike structures are possible.

[0030] In one aspect, the metal dike structure 124 can provide mechanical integrity to the package substrate 100 due to bending and thermal cycling, and the additional metal dike structure can serve to accommodate the underlying filler material for devices (e.g., chips, CSPs) mounted on the package substrate. For example, metal lines 124A can be used as reinforcing ribs. Metal dike structures, such as honeycomb structures, metal planes, grids, etc., can also be customized at the corners of devices (e.g., chips, CSPs) in the shade. Specifically, stress has been observed to concentrate at the corners of mounted devices (e.g., chips, CSPs), leading to trace cracking. Figure 2In the specific embodiment shown, the metal embankment structure 124 is located directly below the corner of the installed device 200.

[0031] The arrangement of the metal embankment structure 124 and the mounted device 200 can also be characterized by various exclusion zones (KOZ1, KOZ2, KOZ3). For example, the metal line 124A can be positioned at a lateral distance from the edge 202 of the mounted device 200 defined by KOZ1. The distal edge of the metal embankment structure 124 can be defined by KOZ2. Additionally, KOZ3 can be defined by intruding into the metal embankment structure 124 below the mounted device 200 closest to the nearest SMT metal bump 122. For example, this distance can be less than 800 μm on the distribution side. Shielding the metal embankment structure 124 below the corners of the mounted device 200 can help retain the underlying filler material and / or provide a denser mechanical support structure in these high-stress areas.

[0032] By integrating various surface trimming layers or post-processing, the surface energy of the metal dike structure can be further designed to accommodate different types of underlying filler materials. In some embodiments, for both the SMT metal bump 122 and the metal barrier structure 124, the patterned metal contact layer 120 may include the same bulk metal layer and the same surface trimming layer above the bulk metal layer. Using an etch-back manufacturing technique according to the embodiment, both the SMT metal bump and the metal dike structure 124 may have distinctive straight sidewalls for embedding within the stack structure and for extending above the topmost surface 117 of the laterally adjacent stack structure. The final structural features of the SMT metal bump and the metal dike structure 124 may depend on whether the etch-back is performed before or after surface trimming. Additional structures may also be added, including forming trenches in the stack structure between the SMT metal bump array and the metal dike structure, and raising the metal dike structure so that it protrudes above the SMT metal bump array.

[0033] Figure 3A This is a close-up cross-sectional side view of a semiconductor package according to an embodiment, the semiconductor package including a device 200 mounted on a package substrate manufactured using a post-etching surface finishing technique. Figure 3B This is a close-up cross-sectional side view of a semiconductor package according to an embodiment, the package including a device 200 mounted on a package substrate manufactured using a surface finishing technique prior to etching back. See also Figures 3A-3BBoth, including contact elements 212 (e.g., studs, pads, etc.), the device 200 is mounted on SMT metal bumps 122 and underfilled with underfill material 210. The device 200 can be bonded using, for example, solder bumps 214. A metal dam structure 124 can be used to hold the underfill material 210 below and along the device edge, and can prevent further diffusion of the underfill material 210 across the surface of the package substrate. In an embodiment, the underfill material is wicked along the device edge, such that the underfill height (t) along the device edge... h Covering device 200 thickness (t) t At least 50% of the thickness of a silicon die, for example, at least 50% of the thickness of a silicon die.

[0034] The patterned metal contact layer 120 according to the embodiment can be a multi-layer structure. As shown, the patterned metal contact layer 120 may include a bulk metal layer 142 (e.g., copper) and a surface trimming layer 144 above the bulk metal layer 142. The surface trimming layer may also be a multi-layer structure. The specific embodiment shown illustrates an ENEPIG structure including a chemically plated nickel layer 146 and a chemically plated palladium immersion gold layer 148. According to the embodiment, each SMT metal bump 122 includes a straight sidewall 132 for a portion 132A of the SMT metal bump embedding in the stack structure, and a portion 132B of the SMT metal bump extending above the topmost surface 117 of the stack structure laterally adjacent to the SMT metal bump 122. Similarly, each metal embankment structure 124 includes a straight sidewall 134 for a portion 134A of the metal embankment structure 124 embedded in a stacked structure, and a portion 134B of the metal embankment structure extending above the top surface 117 of the stacked structure laterally adjacent to the metal embankment structure 124.

[0035] See now for details. Figure 3A For both the SMT metal bump 122 and the metal embankment structure 124, the top surface 143 of the bulk metal layer 142 extends over the topmost surface 117 of the adjacent stack structure. Additionally, for both the SMT metal bump 122 and the metal embankment structure 124, straight sidewalls 132 and 134 are defined by the bulk metal layer 142, and the surface trimming layer 144 covers the top surface 143 of the bulk metal layer 142 and the straight sidewalls 132 and 134B of portions 132B and 134B of the SMT metal bump 122 and the metal embankment structure 124, respectively, which extend over the topmost surface 117 of the adjacent stack structure. Thus, the bulk metal layer 142 (e.g., copper) is completely encapsulated by the stack structure and the surface trimming layer 144.

[0036] See now for details.Figure 3B Each SMT metal bump 122 and each metal embankment structure 124 has straight sidewalls 132, 134 spanning a bulk metal layer 142 and a surface trimming layer 144. As shown, the bulk metal layer 142 of each SMT metal bump 122 and each metal embankment structure 124 is fully embedded in the stack structure and covered by the surface trimming layer 144. Additionally, each surface trimming layer 144 for each SMT metal bump 122 and each metal embankment structure 124 is partially embedded in the stack structure and extends partially above the topmost surface 117 of the adjacent stack structure. For example, this may have a nickel layer 146.

[0037] See still Figures 3A-3B According to the embodiment, the bottom filler material 210 may extend or flash outward from the device 200 and cover some, but not all, of the adjacent metal dike structures 124. Thus, multiple metal dike structures 124, such as parallel lines or repeating geometric patterns, can be used to support each other. Alternatively, the multiple metal dike structures 124 may be used to provide mechanical support rather than to accommodate the bottom filler material 210. Furthermore, the metal dike structures 124 may be located in the shadow of the device 200 such that they are at least partially located below (and inside) the side edges or corners(s) of the device 200.

[0038] Figure 4 This is a flowchart illustrating a method for manufacturing a packaging substrate using post-etch-back surface finishing technology and pre-etch-back surface finishing technology, according to an implementation scheme. Figures 5A-5G This is a schematic cross-sectional side view of the manufacturing sequence of surface finishing after etching according to the implementation plan. Figures 6A-6G This is a schematic cross-sectional side view illustrating the surface finishing manufacturing sequence prior to etching according to the implementation plan. For clarity and brevity, the description is also... Figure 4 Flowcharts and Figures 5A-5G and Figures 6A-6G The order shown.

[0039] At operation 4010, a patterned metal substrate layer 305 is formed on the carrier substrate 300. For example, the patterned metal substrate layer 305 may include a bulk metal layer 142 and a barrier layer 150. Figures 5A-5B and 6A to Figure 6BAs shown, this can be achieved by forming a seed layer 302 (e.g., copper) on a carrier substrate 300, followed by forming a dry film photoresist 310 and electroplating a barrier layer 150 and a bulk metal layer 142. In an embodiment, the barrier layer 150 may be formed of a material used as an etch stop during the removal of the seed layer 302. The barrier layer 150 also serves as a temporary layer that facilitates etch-back techniques. As shown, the total height of the barrier layer 150 and the bulk metal layer 142 may be less than the total thickness of the dry film photoresist 310 to control the SMT metal bump height. However, subsequent planarization operations are also possible. See now for the appendix. Figure 5C and Figure 6C The dry film photoresist 310 is removed, and at operation 4020, a stacked structure is formed on the patterned metal substrate layer 305. In the specific embodiment shown, only a single top dielectric layer 115 of the stacked structure is shown, but it is possible to form... Figure 1 The complete stacked structure. At this stage, the patterned metal substrate layer 305 is embedded in the stacked structure (e.g., the top dielectric layer 115).

[0040] See now Figures 5D-5E and Figures 6D-6E At operation 4030, the carrier substrate 300 and the seed layer 302 are removed. A barrier layer 150 protects the bulk copper metal layer 142 during the removal of the copper seed layer 302. The barrier layer 150 is then removed, thereby creating an opening 151 or recess in the stacked structure. At this stage, the bulk metal layer 142 is recessed into the interior of the stacked structure.

[0041] The thickness of the bulk metal layer 142 can depend on the specific processing sequence. For example, in Figures 5A-5G In the sequence shown, the barrier layer 150 may have the minimum thickness required to function as an etching barrier. Figures 6A-6G In the sequence shown, however, the barrier layer 150 can be thicker, and removing the barrier layer can leave a recess in the stacked structure above the bulk metal layer 142 sufficient to form the surface finishing layer 144. Similarly, the relative thickness of the bulk metal layer 142 can depend on the processing sequence.

[0042] exist Figure 5F In the illustrated surface finishing fabrication sequence following etchback, the thickness of the stacked structure (e.g., top dielectric layer 115) is reduced at operation 4050 such that the top surface 143 of the bulk metal layer 142 protrudes from the stacked structure (e.g., above the topmost surface 117 of the stacked structure). In one embodiment, the etchback is a plasma dry etching or wet chemical etching technique. For example, this could include CF4 chemical reaction or chemical mechanical polishing (CMP). A surface finishing layer 144 can then be formed on the exposed bulk metal layer 142 at operation 4052, such as... Figure 5G As shown.

[0043] exist Figure 6G In the surface finishing manufacturing sequence shown prior to the etching back, a surface finishing layer 144 is then formed on the bulk metal layer 142. This exposed bulk metal layer is located within an opening 151 (recess) created in the stacked structure due to the removal of the barrier layer 150. In an embodiment, the surface finishing layer 144 completely encompasses the opening 151 to control its shape and height. At operation 4062, the thickness of the stacked structure (e.g., the top dielectric layer 115) is reduced such that the top surface 149 of the surface finishing layer 144 protrudes from the stacked structure, and the top surface 143 of the bulk metal layer 142 is embedded in the stacked structure, as shown. Figure 6G As shown. In one embodiment, the back etching is a plasma dry etching or wet chemical etching technique. For example, this may include CF4 plasma chemical reaction or CMP.

[0044] For both the post-etchback surface finishing manufacturing sequence and the pre-etchback surface finishing manufacturing sequence, the seed layer 302 etching operation does not erode the sidewalls of the bulk metal layer 142, or in this respect, the sidewalls within the bulk metal layer become recesses or openings 151 in the stacked structure (e.g., the top dielectric layer 115). This maintains the pad dimensions as designed according to both sequences.

[0045] Figures 7A-7C This is a schematic cross-sectional side view of an SMT metal bump 122 manufactured according to the surface finishing manufacturing sequence after etch-back, as per the implementation plan. Figures 8A-8C This is a schematic cross-sectional side view of an SMT metal bump 122 manufactured according to the surface finishing manufacturing sequence prior to etchback, as per the implementation plan.

[0046] See Figure 7A The structure illustrates the opening 151 formed at operation 4040 after the removal of the barrier layer 150. Electrical and physical connections between the bulk metal layer 142 and vias 116 formed in one or more dielectric layers 115, 112 are also shown. Figure 7B The top surface 143 of the bulk metal layer 142, which protrudes above the top surface 117 of the stacked structure after back etching at operation 4050, is shown. Figure 7C A surface trimming layer 144 is shown formed at operation 4052, which may also encapsulate the bulk metal layer 142 to provide chemical protection. The metal dike structure 124 can be similarly treated, with a similar physical arrangement.

[0047] See Figure 8A The structure shows an opening 151 formed at operation 4040 after the removal of the barrier layer 150. It should be noted that the bulk metal layer 142 is larger than... Figure 7AThe thickness is thinner, and the recesses or openings 151 are deeper. Electrical and physical connections between the bulk metal layer 142 and vias 116 formed in one or more dielectric layers 115, 112 are also shown. Figure 8B The surface trimming layer 144 is formed at operation 4060. As shown, the opening 151 may not be completely filled. This helps to maintain the same dimensions of the SMT metal bumps 122. Figure 8C The image shows an SMT metal bump 122 after etch-back at operation 4062. As shown, a surface trimming layer 144 re-encapsulates the bulk metal layer 142 to provide chemical protection. The metal dike structure 124 can be similarly treated, with a similar physical arrangement.

[0048] See now Figures 9A-9B A close-up cross-sectional side view of a package substrate variant according to an embodiment is provided, the package substrate variant including a metal dike structure protruding above an SMT metal bump array. Figure 9A It is based on the surface finishing manufacturing sequence after the use of the implementation plan (such as...). Figures 10A-10G It is manufactured using the provided (materials). Figure 9B It is based on the surface finishing manufacturing sequence before the use of the implementation plan (such as...). Figures 11A-11G The provided packaging substrate is used for manufacturing. The variations in the packaging substrate and processing sequence are consistent with those already referenced. Figures 1-8C The structures and processing sequences shown and described have similarities. Therefore, for clarity and brevity, the following description focuses on specific variations rather than shared features and processes.

[0049] See Figure 9A and Figure 9B The metal embankment structure 124 is shown protruding above the array of SMT metal bumps 122. Furthermore, this stacked structure, or more specifically, the top dielectric layer 115, protrudes into the interior portion of the metal embankment structure 124. Here, the top surface 119 of the stacked structure located within the metal embankment structure 124 is higher than the topmost surface 117 of the stacked structure that is adjacent laterally to both the metal embankment structure 124 and the SMT metal bumps 122. In both structures, the metal embankment structure 124 may have a characteristic inverted U-shape or horseshoe shape embedded within the stacked structure.

[0050] See now for the appendix. Figures 10A-10B and Figures 11A-11B The processing order is similar to the previous one. Figure 5A and Figure 6AThe process begins as shown and described, including forming a seed layer 302 on a carrier substrate 300. A patterned dam layer 304 is then formed over the seed layer 302. In one embodiment, the dam layer 304 is a conductive layer and may be a metallic layer. For example, the dam layer 304 is a copper-plated layer. The dam layer 304 can be formed by forming a patterned resist layer in which an opening 306 is shown, followed by electroplating, and then stripping the resist layer to form the dam layer 304 and the opening 306. Figures 10C-10G and Figures 11C-11G The processing order in the middle can then be compared with the previous ones. Figures 5B-5G and Figures 6B-6G The same applies to those described and illustrated.

[0051] Figures 12A-12B This is a close-up cross-sectional side view of another packaging substrate variant according to an embodiment, which includes trenches formed in a stacked structure between an SMT metal bump array and a metal dike structure. Figure 12A It is based on the surface finishing manufacturing sequence after the use of the implementation plan (such as...). Figures 13A-13F It is manufactured using the provided (materials). Figure 12B It is based on the surface finishing manufacturing sequence before the use of the implementation plan (such as...). Figures 14A-14F The provided packaging substrate is used for manufacturing. The variations in the packaging substrate and processing sequence are consistent with those already referenced. Figures 1-8C The structures and processing sequences shown and described have similarities; therefore, for clarity and brevity, the following description focuses on specific variants rather than shared features and processes.

[0052] See Figure 12A and Figure 12B Both trench 160 and the metal embankment structure 124 are formed in a stacked structure (e.g., top dielectric layer 115) between the SMT metal bump array 122 and the metal embankment structure 124. Trench 160 may have a bottom surface 162 below the bottom surface 141 of the SMT metal bump array 122 and the metal embankment structure 124, which may be defined by a bulk metal layer 142. Trench 160 may completely surround the drop regions 123A, 123B or only surround a portion of the drop regions.

[0053] See now Figures 13A-13B and Figures 14A-14B The processing order is similar to the previous one. Figures 5A-5E and Figures 6A-6E The process begins as shown and described. A mask layer 320 (e.g., a photoresist) can then be formed over the simulated metal structure 145 in the bulk metal layer 142, such as... Figure 13C and Figure 14C As shown, etching is then performed to remove the simulated metal structure 145, as... Figure 13D andFigure 14D As shown, the Figure 13D and Figure 14D The removal of mask layer 320 is also shown. Figures 13E-13F and Figures 14E-14F The processing order in the middle can then be compared with the previous ones. Figures 5F-5G and Figures 6F-6G The same process continues as those shown and illustrated. It should be noted that during the etch-back sequence, the bottom surface 162 of the trenches 160 is also etched back, causing them to descend below the bottom surface of the bulk metal layer 142, and thus below the bottom surface 141 of the SMT metal bump array 122 and the metal dike structure 124.

[0054] It should be understood that while various structural variations and processing sequences according to the embodiments have been described and illustrated individually, many of these structures and sequences can be combined. In utilizing various aspects of the embodiments, it will be apparent to those skilled in the art that combinations or variations of the above embodiments are possible for forming SMT metal bumps and reinforcement structures within the package substrate. Although the embodiments have been described in language specific to structural features and / or methodological behavior, it should be understood that the appended claims are not necessarily limited to the specific features or behaviors described. Rather, the specific features and behaviors disclosed should be understood as embodiments used for illustrative purposes.

Claims

1. A semiconductor package, comprising: Packaging substrate, including: Multiple metal wiring layers; Multiple dielectric layers, the multiple dielectric layers including a top dielectric layer forming the topmost surface; A patterned metal contact layer, wherein the patterned metal contact layer comprises: A surface-mount SMT metal bump array located in the chip mounting area, the SMT metal bump array being partially embedded in the top dielectric layer and protruding from the topmost surface of the top dielectric layer; and A metal embankment structure laterally surrounding the SMT metal bump array located in the chip mounting area, the metal embankment structure being partially embedded in the top dielectric layer and protruding from the topmost surface of the top dielectric layer; and Devices bonded to the SMT metal bump array; The metal embankment structure forms a first geometry adjacent to the first edge and the second edge of the device, and forms a second geometry adjacent to the corner where the first edge and the second edge of the device intersect.

2. The semiconductor package of claim 1, wherein the patterned metal contact layer comprises a bulk metal layer and a surface trimming layer located on the bulk metal layer.

3. The semiconductor package of claim 2, wherein each SMT metal bump includes a straight sidewall for a portion of the SMT metal bump embedded in the top dielectric layer and for a portion of the SMT metal bump extending above the topmost surface of the top dielectric layer laterally adjacent to the SMT metal bump.

4. The semiconductor package of claim 3, wherein for each SMT metal bump: The top surface of the bulk metal layer extends above the topmost surface of the top dielectric layer, which is laterally adjacent to the SMT metal bump.

5. The semiconductor package of claim 4, wherein for each SMT metal bump: The straight sidewalls of the SMT metal bumps are defined by the bulk metal layer; and The surface trimming layer covers the top surface of the bulk metal layer and the straight sidewall of the portion of the SMT metal bump, the portion extending above the topmost surface of the top dielectric layer laterally adjacent to the SMT metal bump.

6. The semiconductor package of claim 5, wherein the surface trimming layer comprises a nickel layer and the bulk metal layer comprises copper.

7. The semiconductor package of claim 6, wherein the surface trimming layer comprises a nickel-palladium-gold stack, and the bulk metal layer comprises copper.

8. The semiconductor package of claim 3, wherein the straight sidewall of each SMT metal bump spans the bulk metal layer and the surface trimming layer.

9. The semiconductor package of claim 8, wherein the bulk metal layer of each SMT metal bump is fully embedded in the top dielectric layer and is covered by the surface trimming layer.

10. The semiconductor package of claim 9, wherein each surface trimming layer for each SMT metal bump is partially embedded in the top dielectric layer and extends partially above the topmost surface of the top dielectric layer that is laterally adjacent to the SMT metal bump.

11. The semiconductor package of claim 10, wherein the surface trimming layer comprises a nickel layer and the bulk metal layer comprises copper.

12. The semiconductor package of claim 11, wherein the surface trimming layer comprises a nickel-palladium-gold stack, and the bulk metal layer comprises copper.

13. The semiconductor package of claim 1, wherein the first geometry of the metal embankment structure comprises a plurality of parallel metal lines extending parallel to a first edge and a second edge of a device mounted on the SMT metal bump array.

14. The semiconductor package of claim 1, further comprising a trench formed in the top dielectric layer between the SMT metal bump array and the metal embankment structure.

15. The semiconductor package of claim 1, wherein the metal dike structure protrudes above the SMT metal bump array, and the top dielectric layer protrudes into an inner portion of the metal dike structure.

16. The semiconductor package according to claim 2, wherein: Each SMT metal bump includes a straight sidewall for a portion of the SMT metal bump embedded in the top dielectric layer, and a portion of the SMT metal bump extending above the topmost surface of the top dielectric layer laterally adjacent to the SMT metal bump. and The metal embankment structure includes straight sidewalls for portions of the metal embankment structure embedded in the top dielectric layer, and portions of the metal embankment structure extending above the topmost surface of the top dielectric layer that is laterally adjacent to the metal embankment structure.

17. The semiconductor package of claim 16, wherein for the metal dike structure and each SMT metal bump: The top surface of the bulk metal layer extends above the topmost surface of the top dielectric layer, which is laterally adjacent to the corresponding metal dike structure and the corresponding SMT metal bump.

18. The semiconductor package of claim 16, wherein the straight sidewalls for the dike structure and each SMT metal bump span the bulk metal layer and the surface trimming layer.

19. A method of forming a packaging substrate, the method comprising: A patterned metal substrate layer is formed on a carrier substrate, the patterned metal substrate layer including a bulk metal layer located on a barrier layer; A stacked structure is formed on the patterned metal substrate layer; Remove the carrier substrate; Remove the barrier layer; The thickness of the stacked structure is reduced such that the top surface of the bulk metal layer protrudes from the stacked structure to form a surface-mounted SMT metal bump array that is partially embedded in the stacked structure and protrudes from the stacked structure in the chip mounting area, and a metal dike structure that is laterally adjacent to the SMT metal bump array that is partially embedded in the stacked structure and protrudes from the stacked structure. Each SMT metal bump includes a straight sidewall for the portion of the SMT metal bump embedded in the stacked structure and for the portion of the SMT metal bump extending above the topmost surface of the stacked structure laterally adjacent to the SMT metal bump. and The metal embankment structure includes straight sidewalls for the portion of the metal embankment structure embedded in the stacked structure and for the portion of the metal embankment structure extending above the topmost surface of the stacked structure laterally adjacent to the metal embankment structure. as well as A surface finishing layer is formed on the exposed bulk metal layer.

20. The method of claim 19, wherein reducing the thickness of the stacked structure comprises plasma etching or wet chemical etching.

21. A method for forming a packaging substrate, the method comprising: A patterned metal substrate layer is formed on a carrier substrate, the patterned metal substrate layer including a barrier layer and a bulk metal layer located on the barrier layer; A stacked structure is formed on the patterned metal substrate layer; Remove the carrier substrate; Remove the barrier layer; and A surface finishing layer is formed on the exposed bulk metal layer within the opening previously occupied by the barrier layer in the stacked structure; as well as The thickness of the stacked structure is reduced such that the top surface of the surface trimming layer protrudes from the stacked structure, and the top surface of the bulk metal layer is embedded in the stacked structure.

22. The method of claim 21, wherein reducing the thickness of the stacked structure comprises plasma etching or wet chemical etching.

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