Radio frequency identification decoding circuit, method and radio frequency identification device

Abstract

The present invention discloses a radio frequency identification decoding circuit, method and radio frequency identification device. A radio frequency identification decoding circuit includes: a synchronization module, a clock generation module and a decoding control module; the synchronization module is used to synchronize the data signal demodulated by the radio frequency identification circuit to the clock domain of the radio frequency identification circuit, and send the synchronized data signal to the clock generation module and the decoding control module; the clock generation module is used to divide the frequency based on the clock signal of the radio frequency identification circuit to obtain the divided clock signal, wherein the synchronized data signal is used as an asynchronous setting signal of the divider, and there is a preset time interval between the divided clock signal and the synchronized data signal; the decoding control module is used to decode the synchronized data signal according to the divided clock signal. The radio frequency identification decoding circuit, method and radio frequency identification device disclosed in the embodiments of the present invention can achieve correct decoding within a larger Pause width range.

Description

Technical Field

[0001] The embodiments of the present invention relate to radio frequency identification technology, and more particularly to a radio frequency identification decoding circuit, method and radio frequency identification device. Background Art

[0002] Radio Frequency Identification (RFID) is a type of automatic identification technology that uses wireless radio frequency to perform non-contact two-way data communication and read and write recording media to achieve the purpose of identifying targets and exchanging data. International Organization for Standardization (ISO) 15693 is an RFID standard that defines the air interface and data communication specifications for smart tags and readers working at 13.56Mhz. The maximum reading distance of tags that meet the ISO15693 standard is 2 meters.

[0003] The ISO 15693 standard stipulates that the communication from the vicinity coupling device (VCD) to the vicinity card (VICC) uses pulse position modulation (PPM) encoding, that is, the pause position is used to represent the data information. When the VICC receives, the analog circuit first recovers the baseband signal and 13.56Mhz clock from the 13.56Mhz carrier, and then the digital circuit decodes the baseband signal to obtain the data information.

[0004] The Pause width interval sent by VCD is [6us, 9.44us]. In actual engineering applications, the operating distance and the processing of the analog front-end demodulation circuit will cause the Pause width in the baseband signal received by the VICC decoding circuit to exceed this interval to a certain extent, thus affecting the decoding of VICC. Summary of the invention

[0005] The present invention provides a radio frequency identification decoding circuit, method and radio frequency identification device, which can realize correct decoding within a wider Pause width without using error prior information.

[0006] In a first aspect, an embodiment of the present invention provides a radio frequency identification decoding circuit, including: a synchronization module, a clock generation module and a decoding control module;

[0007] The synchronization module is used to synchronize the data signal demodulated by the RFID circuit to the clock domain of the RFID circuit, and send the synchronized data signal to the clock generation module and the decoding control module;

[0008] The clock generation module is used to divide the frequency of the clock signal of the radio frequency identification circuit to obtain a divided clock signal, wherein the synchronized data signal is used as an asynchronous set signal of the divider, and there is a preset time interval between the divided clock signal and the synchronized data signal;

[0009] The decoding control module is used to decode the synchronized data signal according to the divided clock signal.

[0010] In a possible implementation manner of the first aspect, the synchronization module is specifically configured to obtain a synchronized data signal based on a falling edge synchronization of a clock signal of the radio frequency identification circuit.

[0011] In a possible implementation of the first aspect, the clock generation module is specifically used to divide the rising edge of the clock signal of the radio frequency identification circuit to obtain a divided clock signal, wherein during the period when the synchronized data signal is at a low level, the divided clock signal is set to a low level, and the first divided clock signal rising edge is generated by delaying a preset time interval after each rising edge of the synchronized data signal.

[0012] In a possible implementation manner of the first aspect, the clock generating module is specifically configured to perform 128 frequency division based on a rising edge of a clock signal of the radio frequency identification circuit to obtain a 128-divided clock signal.

[0013] In a possible implementation of the first aspect, the decoding control module is specifically used to start the operation of the counter after detecting the falling edge of the synchronized data signal, and at the second rising edge of the synchronized data signal, the value of the sampling counter determines the encoding mode of the synchronized data signal; the value of the sampling counter is sampled and decoded at each subsequent rising edge of the synchronized data signal until the sampling value of the counter at the rising edge of the synchronized data signal is a preset sampling end value.

[0014] In a second aspect, an embodiment of the present invention provides a radio frequency identification device, including: a radio frequency identification circuit and a radio frequency identification decoding circuit;

[0015] The radio frequency identification circuit is used to receive radio frequency signals and demodulate the radio frequency signals;

[0016] The radio frequency identification circuit includes the radio frequency identification circuit as described in any implementation manner of the first aspect.

[0017] In a third aspect, an embodiment of the present invention provides a radio frequency identification circuit decoding method, comprising:

[0018] Synchronizing the data signal demodulated by the RFID circuit to the clock domain of the RFID circuit;

[0019] Performing frequency division based on the clock signal of the radio frequency identification circuit to obtain a divided clock signal, wherein the synchronized data signal is used as an asynchronous set signal of the divider, and there is a preset time interval between the divided clock signal and the synchronized data signal;

[0020] The synchronized data signal is decoded according to the divided clock signal.

[0021] In a possible implementation of the third aspect, synchronizing a data signal demodulated by the radio frequency identification circuit to a clock domain of the radio frequency identification circuit includes:

[0022] The synchronized data signal is obtained based on the falling edge synchronization of the clock signal of the radio frequency identification circuit.

[0023] In a possible implementation of the third aspect, dividing the frequency of a clock signal based on the radio frequency identification circuit to obtain a divided clock signal includes:

[0024] Based on the rising edge division of the clock signal of the radio frequency identification circuit, a divided clock signal is obtained, wherein during the period when the synchronized data signal is at a low level, the divided clock signal is set to a low level, and the first divided clock signal rising edge is generated by delaying a preset time interval after each synchronized data signal rising edge.

[0025] In a possible implementation of the third aspect, frequency division based on a rising edge of a clock signal of a radio frequency identification circuit to obtain a divided clock signal includes:

[0026] The rising edge of the clock signal of the radio frequency identification circuit is divided by 128 to obtain a clock signal after the frequency division by 128.

[0027] In a possible implementation manner of the third aspect, decoding the synchronized data signal according to the divided clock signal includes:

[0028] After detecting the falling edge of the synchronized data signal, the counter starts working;

[0029] At the second rising edge of the synchronized data signal, the value of the sampling counter determines the encoding mode of the synchronized data signal;

[0030] The value of the counter is sampled and decoded at each subsequent rising edge of the synchronized data signal until the sampling value of the counter at the rising edge of the synchronized data signal is a preset sampling 0 end value.

[0031] The radio frequency identification decoding circuit, method and radio frequency identification device provided by the embodiment of the present invention include a synchronization module, a clock generation module and a decoding control module, wherein the synchronization module is used to synchronize the data signal demodulated by the radio frequency identification circuit to the clock domain of the radio frequency identification circuit, the clock generation module is used to divide the frequency based on the clock signal of the radio frequency identification circuit to obtain the divided clock signal, and the decoding control module decodes the synchronized data signal according to the divided clock signal. Since the clock signal is divided, the decoding control module works in a slower clock domain, which is beneficial to the power consumption and area optimization of the circuit, and can achieve correct decoding within a larger Pause width range without using error prior information. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the structure of a radio frequency identification decoding circuit provided by an embodiment of the present invention;

[0033] Figure 2 A schematic diagram of signal synchronization and frequency division waveforms of a radio frequency identification decoding circuit provided by an embodiment of the present invention;

[0034] Figure 3 and Figure 4 A schematic diagram of a signal decoding waveform of a radio frequency identification decoding circuit provided by an embodiment of the present invention;

[0035] Figure 5 The present invention provides a flowchart of a radio frequency identification circuit decoding method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0037] Figure 1 A schematic diagram of the structure of a radio frequency identification decoding circuit provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the RFID decoding circuit provided in this embodiment includes: a synchronization module 11 , a clock generation module 12 and a decoding control module 13 .

[0038] The communication from VCD to VICC specified in the ISO 15693 protocol uses PPM encoding, that is, the Pause position is used to represent data information. When VICC receives data sent by VCD, the analog circuit first recovers the baseband signal and clock information from the carrier, and then decodes the baseband signal to obtain the data information. Among them, the analog circuit is used to receive the radio frequency signal sent by VCD and demodulate it to obtain a data signal containing data information. The decoding circuit decodes the data signal demodulated by the analog circuit, decodes the data information contained in the data signal, and obtains the actual data sent by VCD. However, due to factors such as the actual communication distance, the processing error of the analog circuit, and the influence of the external electromagnetic environment, the Pause width of the data signal received by the decoding circuit may exceed the width that the VICC decoding circuit can handle, which will cause VICC to fail to decode correctly.

[0039] In order to solve the above problems, this embodiment provides a radio frequency identification decoding circuit, including: a synchronization module 11, a clock generation module 12 and a decoding control module 13. The radio frequency identification decoding circuit is a circuit part used for decoding in the VICC, and is connected to the radio frequency identification circuit (i.e., analog circuit) 14 in the VICC for receiving the radio frequency signal sent by the VCD, and decodes the data signal demodulated by the radio frequency identification circuit 14. The connection relationship between the synchronization module 11, the clock generation module 12, the decoding control module 13 and the radio frequency identification circuit 14 is as shown in FIG. Figure 1 shown.

[0040] The synchronization module 11 is used to synchronize the data signal demodulated by the RFID circuit 14 to the clock domain of the RFID circuit 14, and send the synchronized data signal to the clock generation module 12 and the decoding control module 13. The clock generation module 12 is used to divide the frequency based on the clock signal of the RFID circuit 14 to obtain a divided clock signal, wherein the synchronized data signal is used as an asynchronous set signal of the divider, and there is a preset time interval between the divided clock signal and the synchronized data signal; the decoding control module 13 decodes the synchronized data signal according to the divided clock signal.

[0041] After demodulating the received RF signal, the RFID circuit 14 will output a data signal (Pause), and the RFID circuit 14 can also output a clock signal (Ck). The data signal output by the RFID circuit 14 will be output to the synchronization module 11, and the clock signal output by the RFID circuit 14 will be output to the synchronization module 11 and the clock generation module 12.

[0042] The synchronization module 11 synchronizes the received demodulated data signal to the clock signal of the RFID circuit 14 to obtain a synchronized data signal (Pause_sync). The synchronization module 11 synchronizes the data signal to reduce the error of the RFID circuit 14 in demodulating the RF signal. The synchronized data signal is synchronized with the clock signal, which is convenient for subsequent processing. The synchronization module 11 sends the synchronized data signal to the clock generation module 12 and the decoding control module 13.

[0043] Since the clock signal of the RFID circuit 14 of the VICC that complies with the ISO 15693 protocol is 13.56MHz, which is a relatively high frequency, the decoding circuit needs to be able to work on a clock based on 13.56MHz in order to perform decoding. If a decoding device with stronger decoding capability is to be used, the power consumption and required space occupied by the decoding circuit will be increased. Therefore, in this embodiment, a clock generation module 12 is added, and the function of the clock generation module 12 is to divide the clock signal of the RFID circuit 14 to obtain a divided clock signal. Dividing the clock signal means using 1 / n of the clock signal as the divided clock signal, thereby reducing the frequency of the clock signal. This enables the decoding control module 13 to work on the divided clock signal, which is beneficial to the power consumption optimization and area optimization of the decoding control module 13.

[0044] When the clock generation module 12 divides the frequency based on the clock signal of the radio frequency identification circuit, the synchronized data signal is used as the asynchronous setting signal of the divider, and a fixed divider setting value is set to control the preset time interval between the divided clock signal and the synchronized data signal. Specifically, the phase of the divided clock signal after each Pause of the synchronized data signal can be controlled, that is, the time of occurrence of the first effective edge of the divided clock signal after each Pause, and the time is recorded as t1, and the rising edge time of the synchronized data signal is recorded as t2, then the preset time interval Δ is t1-t2.

[0045] The decoding control module 13 can decode the data according to the synchronized data signal input by the synchronization module 11 and the divided clock signal input by the clock generation module 12. Since there is a preset time interval between the synchronized data signal and the divided clock signal, the decoding control module 13 has a greater tolerance for the Pause width in the synchronized data signal. Therefore, when the Pause width in the data signal demodulated by the RFID circuit 14 is inconsistent or has obvious jitter due to various reasons, the synchronized data signal can be correctly decoded. At the same time, the RFID decoding circuit provided in this embodiment only uses the synchronization module and the clock generation module to process the data signal and the clock signal demodulated by the RFID circuit 14, without relying on error prior information, so the structure of the RFID circuit 14 is simple and easy to implement and apply.

[0046] It should be noted that the synchronization module 11, the clock generation module 12 and the decoding control module 13 are all implemented by circuits composed of various logic devices or integrated circuits that can realize the required functions. Those skilled in the art can design circuits or integrated circuits that realize the required functions of each module based on the technical solution provided in this embodiment, or can realize the above-mentioned functions of each module through programmable logic devices.

[0047] In summary, the RFID decoding circuit provided in this embodiment, on the one hand, because the clock signal is divided, the decoding control module 13 can work on the slower clock signal after the division, which is beneficial to the power consumption optimization and area optimization of the decoding control module 13. On the other hand, because there is a preset time interval between the synchronized data signal and the divided clock signal, the decoding control module 13 has a larger tolerance for the Pause width in the synchronized data signal, and does not need to rely on error prior information. Therefore, the structure of the RFID circuit 14 is simple and easy to implement and apply. Finally, when the Pause width in the data signal demodulated by the RFID circuit 14 is inconsistent or has obvious jitter due to various reasons, the synchronized data signal can also be correctly decoded.

[0048] The radio frequency identification decoding circuit provided in this embodiment includes a synchronization module, a clock generation module and a decoding control module, wherein the synchronization module is used to synchronize the data signal demodulated by the radio frequency identification circuit to the clock domain of the radio frequency identification circuit, the clock generation module is used to divide the frequency based on the clock signal of the radio frequency identification circuit to obtain the divided clock signal, and the decoding control module decodes the synchronized data signal according to the divided clock signal. Since the clock signal is divided, the decoding control module works in a slower clock domain, which is beneficial to the power consumption and area optimization of the circuit, and can achieve correct decoding within a larger Pause width range without using error prior information.

[0049] The following takes the clock generation module dividing the clock signal by 128 as an example to further illustrate the RFID decoding circuit provided by the embodiment of the present invention, wherein the 128-frequency division means that 1 / 128 of the clock signal is used as the divided clock signal.

[0050] Figure 2 A schematic diagram of signal synchronization and frequency division waveforms of a radio frequency identification decoding circuit provided by an embodiment of the present invention, such as Figure 2 As shown, Ck is the clock signal of the radio frequency identification circuit 14, Pause_sync is the synchronized data signal, and Ck128 is the clock signal after 128 division.

[0051] The synchronization module 11 obtains a synchronized data signal based on the falling edge synchronization of the clock signal of the RFID circuit 14 .

[0052] The clock generation module 12 divides the rising edge of the clock signal of the RFID circuit 14 to obtain Pause_sync. Pause_sync is used as an asynchronous setting signal of the frequency division circuit. During the period when Pause_sync is at a low level, CK128 is set to a low level, and the first Ck128 rising edge is delayed by Δ after each Pause_sync rising edge. The purpose of staggering Pause_sync and Ck128 is to avoid the problem of recovery / removal caused by asynchronous setting from the design point of view. Δ = t_ck128_pos-t_pause_pos, t_ck128_pos is the time when the first CK128 rising edge (i.e., the first Ck128 after the end of Pause) appears after the Pause_sync rising edge, and t_pause_pos is the rising edge time of Pause_sync.

[0053] Furthermore, the decoding control module 13 is specifically used to start the operation of the counter after detecting the falling edge of the synchronized data signal, and at the second rising edge of the synchronized data signal, the value of the sampling counter determines the encoding mode of the synchronized data signal; the value of the sampling counter is sampled and decoded at each subsequent rising edge of the synchronized data signal until the sampling value of the counter at the rising edge of the synchronized data signal is a preset sampling end value.

[0054] Still taking the clock generation module dividing the clock signal by 128 as an example, the core of the decoding control module 13 is a 9-bit counter working in the Ck128 clock domain. The counter is reset to 1 when it is powered on, and the counter starts working after detecting the falling edge of Pause_sync. The 15693 protocol stipulates that there are two encoding modes, namely 4 / 1 encoding mode and 256 / 1 encoding mode. In the 4 / 1 encoding mode, the count value is reset to 1 after reaching 7; in the 256 / 1 encoding mode, the count value is reset to 1 after reaching 511. The sampled count value at the rising edge of Pause_sync is recorded as decode_cnt_sample. In the 4 / 1 encoding mode, decode_cnt_sample[2:1] is taken as the decoding value of the current period, and in the 256 / 1 mode, decode_cnt_sample[8:1] is taken as the decoding value of the current period.

[0055] Figure 3 and Figure 4 A schematic diagram of a signal decoding waveform of a radio frequency identification decoding circuit provided by an embodiment of the present invention, wherein Figure 3 This is a schematic diagram of the decoding waveform of the standard Pause. Figure 4 Figure 1 is a schematic diagram of a Pause decoding waveform with a non-standard width. Psuse includes a Start of Frame (SOF), 2 bits of data, and an End of Frame (EOF). Figure 3 and Figure 4 In the figure, Pause_sync is the synchronized data signal, Ck128 is the clock signal after 128 division, decode_en is the enable signal of the decoding control module 13, decode_cnt is the counter signal of the decoding control circuit, sof_end is the SOF reception completion indication signal, and eof_flag is the signal indicating the arrival of EOF. Figure 3 and Figure 4 The 4 / 1 decoding method is used as an example for explanation.

[0056] The power-on reset value of the decode control module 13 counter decode_cnt is set to 1. After the first Pause falling edge arrives, the decode control module 13 enables decode_en, and the counter starts working. After counting to 7, decode_cnt is reset to 1, and the sof_end signal is set at the same time, indicating that SOF reception is completed. At the second Pause_sync rising edge in the SOF stage, decode_cnt is sampled and the encoding mode is determined. Figure 3 and Figure 4If the sampling count value is 5, the sof_mode signal is set high, indicating that the encoding mode is 4 / 1; if the sampling count value is 7, the sof_mode signal is pulled low, indicating that the encoding mode is 256 / 1. The sof_mode signal is not shown in the figure.

[0057] After SOF reception is completed, the data decoding phase begins. decode_cnt cycles between 1 and 7, sampling the count value at each Pause_sync rising edge. decode_cnt[2:1] is the decoded value for the current period. Figure 3 and Figure 4 As shown in the figure, the count value at the rising edge of Pause_sync in the data phase is 3, and the corresponding 2-bit data is 01. At each rising edge of Pause_sync in the data receiving phase, EOF is judged. If the sampled count value is 2, eof_flag is set to indicate that EOF has arrived, and then decode_en and sof_end are pulled low to indicate that a frame of instructions has been received.

[0058] The width of the short Pause is x, x<9.44us, and the width of the long Pause is y, y>9.44us. For any two adjacent non-standard Pauses, it can be considered that the distance between the falling edges is consistent with the standard Pause, so only the position of the rising edge of the previous Pause will affect the count value between the two adjacent Pauses, that is, the determination of the position of the next Pause. For a short Pause, as long as 9.44-x<Δ, there will not be one more Ck128 rising edge between two adjacent Pauses than in the standard case, the count value will be consistent with the standard case, and the position determination of the next Pause will not be wrong; for a long Pause, as long as y-9.44us<9.44us-Δ, there will not be one less Ck128 rising edge between two adjacent Pauses than in the standard case, the count value will be consistent with the standard case, and the position determination of the next Pause will not be wrong.

[0059] Therefore, the error tolerance of the Pause width of the RFID decoding circuit provided by the embodiment of the present invention is (9.44us-Δ, 18.88us-Δ), and as long as the Pause width is within this range, even if there are Pauses with inconsistent widths in the same frame instruction, the count value is still consistent with the standard situation, and decoding will not go wrong.

[0060] The embodiment of the present invention further provides a radio frequency identification device, including: a radio frequency identification circuit and a radio frequency identification decoding circuit. The radio frequency identification device provided by the embodiment of the present invention is as follows Figure 1As shown, the RFID circuit 14 and the RFID decoding circuit are included. The RFID decoding circuit is composed of a synchronization module 11, a clock generation module 12 and a decoding control module 13. The RFID circuit 11 is used to receive a RF signal and demodulate the RF signal to obtain a data signal. The processing performed by the RFID decoding circuit has been described in detail in the above embodiments and will not be repeated here.

[0061] Figure 5 A flowchart of a radio frequency identification circuit decoding method provided by an embodiment of the present invention, such as Figure 5 As shown, the method provided in this embodiment includes:

[0062] Step S5010: synchronizing the data signal demodulated by the RFID circuit to the clock domain of the RFID circuit.

[0063] Step S5020, frequency division is performed based on the clock signal of the radio frequency identification circuit to obtain a divided clock signal, wherein the synchronized data signal is used as an asynchronous set signal of the divider, and there is a preset time interval between the divided clock signal and the synchronized data signal.

[0064] Step S5030: Decode the synchronized data signal according to the divided clock signal.

[0065] The RFID circuit decoding method provided in this embodiment is used to implement Figure 1 The working principle and technical effect of the RFID decoding circuit shown in the figure have been Figure 1 The detailed description is given in the illustrated embodiment and will not be repeated here.

[0066] Further, in Figure 5 Based on the illustrated embodiment, step S5010 includes: obtaining a synchronized data signal based on the falling edge synchronization of the clock signal of the radio frequency identification circuit.

[0067] Further, in Figure 5 Based on the embodiment shown, step S5020 includes: dividing the rising edge of the clock signal of the radio frequency identification circuit to obtain a divided clock signal, wherein during the period when the synchronized data signal is at a low level, the divided clock signal is set to a low level, and the first divided clock signal rising edge is generated after a preset time interval is delayed after each synchronized data signal rising edge.

[0068] Further, in Figure 5 Based on the illustrated embodiment, step S5020 includes: performing 128 frequency division based on the rising edge of the clock signal of the radio frequency identification circuit to obtain a clock signal after 128 frequency division.

[0069] Further, in Figure 5Based on the illustrated embodiment, step S5030 includes: starting the operation of the counter after detecting the falling edge of the synchronized data signal; at the second rising edge of the synchronized data signal, the value of the sampling counter determines the encoding mode of the synchronized data signal; sampling the value of the counter at each subsequent rising edge of the synchronized data signal and decoding it until the sampling value of the counter at the rising edge of the synchronized data signal is a preset sampling end value.

[0070] In addition, an embodiment of the present invention further provides a radio frequency identification device, the radio frequency identification device is, for example, a VICC, and the structure of the radio frequency identification device is as follows: Figure 1 As shown, the RFID device comprises a synchronization module 11, a clock generation module 12, a decoding control module 13 and a radio frequency identification circuit 14. Figure 1 According to the description in the illustrated embodiment, the decoding of the data signal can be completed in a slower clock domain, thereby being able to tolerate a wider Pause width and facilitating the optimization of power consumption and area.

[0071] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A radio frequency identification decoding circuit, characterized in that: include: Synchronization module, clock generation module and decoding control module; The synchronization module is used to synchronize the data signal demodulated by the RFID circuit to the clock domain of the RFID circuit, and send the synchronized data signal to the clock generation module and the decoding control module; The clock generating module is used to perform frequency division based on the clock signal of the radio frequency identification circuit to obtain a divided clock signal, wherein the synchronized data signal is used as an asynchronous set signal of the divider, and the divided clock signal is generated after a preset time interval after the synchronized data signal; The decoding control module is used to decode the synchronized data signal according to the divided clock signal; The clock generation module is specifically used to divide the frequency based on the rising edge of the clock signal of the radio frequency identification circuit to obtain the divided clock signal, wherein, during the period when the synchronized data signal is at a low level, the divided clock signal is set to a low level, and after each rising edge of the synchronized data signal, the first rising edge of the divided clock signal is generated by delaying the preset time interval.

2. The circuit according to claim 1, characterized in that The synchronization module is specifically used to obtain the synchronized data signal based on the falling edge synchronization of the clock signal of the radio frequency identification circuit.

3. The circuit according to claim 1, characterized in that The clock generation module is specifically used to perform 128 frequency division based on the rising edge of the clock signal of the radio frequency identification circuit to obtain a clock signal after 128 frequency division.

4. The circuit according to any one of claims 1 to 3, characterized in that: The decoding control module is specifically used to start the operation of the counter after detecting the falling edge of the synchronized data signal, sample the value of the counter at the second rising edge of the synchronized data signal to determine the encoding mode of the synchronized data signal; sample the value of the counter at each subsequent rising edge of the synchronized data signal and decode it until the sampling value of the counter at the rising edge of the synchronized data signal is a preset sampling end value.

5. A radio frequency identification device, characterized in that: include: Radio frequency identification circuit and radio frequency identification decoding circuit; The radio frequency identification circuit is used to receive radio frequency signals and demodulate the radio frequency signals; The radio frequency identification circuit comprises the radio frequency identification circuit as claimed in any one of claims 1 to 4.

6. A radio frequency identification circuit decoding method, characterized in that: include: Synchronizing the data signal demodulated by the RFID circuit to the clock domain of the RFID circuit; Performing frequency division based on the clock signal of the radio frequency identification circuit to obtain a divided clock signal, wherein the synchronized data signal is used as an asynchronous set signal of the divider, and the divided clock signal is generated after a preset time interval after the synchronized data signal; Decoding the synchronized data signal according to the divided clock signal; The frequency division of the clock signal based on the radio frequency identification circuit to obtain the divided clock signal includes: Based on the frequency division of the rising edge of the clock signal of the radio frequency identification circuit, the divided clock signal is obtained, wherein during the period when the synchronized data signal is at a low level, the divided clock signal is set to a low level, and after each rising edge of the synchronized data signal, the first rising edge of the divided clock signal is generated by delaying the preset time interval.

7. The method according to claim 6, characterized in that The step of synchronizing the data signal demodulated by the radio frequency identification circuit to the clock domain of the radio frequency identification circuit includes: The synchronized data signal is obtained based on the falling edge synchronization of the clock signal of the radio frequency identification circuit.

8. The method according to claim 6, characterized in that The method of dividing the frequency of the clock signal based on the rising edge of the radio frequency identification circuit to obtain the divided clock signal includes: The rising edge of the clock signal of the radio frequency identification circuit is divided by 128 to obtain a clock signal after the frequency division by 128.

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