Display device

Abstract

A display device is provided, which can include a substrate, at least one pixel divided along a first direction on the substrate and including first, second, and third emission areas each of which is provided with a plurality of light emitting elements, a light blocking pattern corresponding to an area between the first to third emission areas, and a color filter layer including a first color filter pattern provided in the first emission area, a second color filter pattern provided in the second emission area, and a third color filter pattern provided in the third emission area. Here, the pixel can include first, second, and third storage capacitors overlaid on the substrate and one of the first, second, and third color filter patterns.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0083754, filed on July 7, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more embodiments of this disclosure relate to a display device. Background Technology

[0003] The growing interest in displaying information and the increasing demand for portable information media have increased the demand (or expectation) for display devices and promoted their commercialization. Summary of the Invention

[0004] One or more embodiments of this disclosure relate to a display device capable of improving light output efficiency.

[0005] One or more embodiments of this disclosure may provide a display device. The display device may include: a substrate; at least one pixel divided on the substrate along a first direction, the at least one pixel including a first emitting region, a second emitting region, and a third emitting region, each of the first, second, and third emitting regions including a plurality of light-emitting elements; a light-blocking pattern corresponding to the region between the first, second, and third emitting regions; and a color filter layer including a first color filter pattern in the first emitting region, a second color filter pattern in the second emitting region, and a third color filter pattern in the third emitting region. The pixel may include a first storage capacitor, a second storage capacitor, and a third storage capacitor on the substrate, the first, second, and third storage capacitors being superimposed on one of the first, second, and third color filter patterns.

[0006] In one or more embodiments of this disclosure, the first color filter pattern may be a red color filter, the second color filter pattern may be a green color filter, and the third color filter pattern may be a blue color filter.

[0007] In one or more embodiments of this disclosure, the display device may further include: a buffer layer on a substrate; and a first insulating layer, a second insulating layer, and a third insulating layer, sequentially disposed on the buffer layer. Here, each of the first storage capacitor, the second storage capacitor, and the third storage capacitor may include a lower electrode and an upper electrode, the lower electrode being disposed on the first insulating layer, and the upper electrode being superimposed on the lower electrode on the second insulating layer.

[0008] In one or more embodiments of this disclosure, a pixel may include: a first sub-pixel including a first storage capacitor and at least one transistor electrically connected to the first storage capacitor; a second sub-pixel including a second storage capacitor and at least one transistor electrically connected to the second storage capacitor; and a third sub-pixel including a third storage capacitor and at least one transistor electrically connected to the third storage capacitor.

[0009] In one or more embodiments of this disclosure, a pixel region including pixels may be divided along a second direction different from the first direction into a first sub-pixel region including a first sub-pixel, a second sub-pixel region including a second sub-pixel, and a third sub-pixel region including a third sub-pixel.

[0010] In one or more embodiments of this disclosure, a first storage capacitor may correspond to a first sub-pixel region, a second storage capacitor may correspond to a second sub-pixel region, and a third storage capacitor may correspond to a third sub-pixel region.

[0011] In one or more embodiments of this disclosure, the pixel may further include: a first data line, a second data line, a third data line, and a first-1 power line extending in a second direction and disposed on a substrate corresponding to the second color filter pattern; and a second-1 power line and an initialization power line extending in a second direction and disposed on a substrate corresponding to the third color filter pattern.

[0012] In one or more embodiments of this disclosure, the first data line, the second data line, the third data line, the first-1 power line, the second-1 power line, and the initialization power line may be disposed on the buffer layer.

[0013] In one or more embodiments of this disclosure, the pixel may further include a bottom metal layer stacked with each of the first storage capacitor, the second storage capacitor, and the third storage capacitor. Here, the bottom metal layer may be on the same layer as the layer in which the first data line, the second data line, the third data line, the first-1 power line, the second-1 power line, and the initialization power line are disposed.

[0014] In one or more embodiments of this disclosure, the pixel may further include: a first-2 power line and a second-2 power line, extending in a first direction and spaced apart from each other on a second insulating layer. Here, the first-2 power line may be electrically connected to the first-1 power line, and the second-2 power line may be electrically connected to the second-1 power line.

[0015] In one or more embodiments of this disclosure, the pixel may further include a first electrode, a second electrode, a third electrode, and a fourth electrode, on a third insulating layer, and positioned to correspond to each of the first, second, and third emission regions. Here, the first, second, third, and fourth electrodes may be spaced apart from each other in a first direction.

[0016] In one or more embodiments of this disclosure, in each of the first, second, and third transmitting regions, the first electrode may be electrically connected to the 2-2 power line. In the first transmitting region, the third electrode may be electrically connected to the second storage capacitor. In the second transmitting region, the third electrode may be electrically connected to the third storage capacitor. In the third transmitting region, the third electrode may be electrically connected to the first storage capacitor.

[0017] In one or more embodiments of this disclosure, the plurality of light-emitting elements may include: a plurality of first light-emitting elements, located between a first electrode and a second electrode, and electrically connected to the first electrode and the second electrode; and a plurality of second light-emitting elements, located between a third electrode and a fourth electrode, and electrically connected to the third electrode and the fourth electrode.

[0018] In one or more embodiments of this disclosure, the pixel may further include: a first contact electrode on a first electrode such that the first electrode is electrically connected to a first end of each of the plurality of first light-emitting elements; an intermediate electrode on corresponding second and fourth electrodes such that a second end of each of the plurality of first light-emitting elements is electrically connected to a first end of each of the plurality of second light-emitting elements; and a second contact electrode on a third electrode such that the third electrode is electrically connected to a second end of each of the plurality of second light-emitting elements.

[0019] In one or more embodiments of this disclosure, the first contact electrode, the intermediate electrode, and the second contact electrode may be spaced apart from each other.

[0020] In one or more embodiments of this disclosure, the plurality of second light-emitting elements may be connected in parallel between the third and fourth electrodes to form a first series group, and the plurality of first light-emitting elements may be connected in parallel between the first and second electrodes to form a second series group. Here, the third electrode may be an anode electrode, and the first electrode may be a cathode electrode.

[0021] In one or more embodiments of this disclosure, the pixel may further include a dam, the dam comprising: a first opening corresponding to each of the first, second, and third emission regions; and a second and third opening spaced apart from the first opening. Here, a light-blocking pattern may be on the dam.

[0022] In one or more embodiments of this disclosure, the first opening of the dam corresponding to the first launch area, the first opening of the dam corresponding to the second launch area, and the first opening of the dam corresponding to the third launch area may have the same size.

[0023] In one or more embodiments of this disclosure, the light-blocking pattern may include a first opening, a second opening, and a third opening, wherein the first opening corresponds to a first color filter pattern, the second opening corresponds to a second color filter pattern, and the third opening corresponds to a third color filter pattern. Here, the size of the first opening may be different from the size of the second opening and the size of the third opening.

[0024] In one or more embodiments of this disclosure, the size of the first opening may be larger than the size of each of the second and third openings. Furthermore, the size of the first color filter pattern may be larger than the size of the second and third color filter patterns.

[0025] In one or more embodiments of this disclosure, the display device may further include a color conversion layer between the pixels and the color filter layer.

[0026] In one or more embodiments of this disclosure, the color conversion layer may include: a first color conversion layer corresponding to a first color filter pattern to convert light emitted from the plurality of light-emitting elements into light of a first color; a second color conversion layer corresponding to a second color filter pattern to convert light emitted from the plurality of light-emitting elements into light of a second color; and a third color conversion layer corresponding to a third color filter pattern to convert light emitted from the plurality of light-emitting elements into light of a third color, or to transmit the emitted light without changing its color. Attached Figure Description

[0027] The accompanying drawings, together with the specification, illustrate embodiments of the subject matter of this disclosure and, together with the description, serve to explain the principles of embodiments of the subject matter of this disclosure.

[0028] Figure 1 This is a perspective view schematically showing a light-emitting element according to one or more embodiments of the present disclosure.

[0029] Figure 2 yes Figure 1 A cross-sectional view of the light-emitting element.

[0030] Figure 3 A display device according to one or more embodiments of the present disclosure is shown, specifically, Figure 3 It is one of them Figure 1 and Figure 2 The diagram shows a schematic plan view of a display device in which the light-emitting element is used as a light source.

[0031] Figure 4It is shown that, according to one or more embodiments, it includes Figure 3 The circuit diagram shows the electrical connections between the components in the pixel shown.

[0032] Figure 5 It is shown schematically. Figure 3 A planar view of one of the pixels shown.

[0033] Figure 6 It is an illustrative representation of including Figure 5 A plan view of an example pixel circuit layer in a display device.

[0034] Figure 7 It is an illustrative representation of including Figure 5 A plan view of an example of a display element layer in a display device.

[0035] Figure 8 It is an illustrative representation of including Figure 5 A plan view of an example of a color filter layer and light-blocking pattern in a display device.

[0036] Figure 9 This is only shown schematically. Figure 7 The plan view of the first area A1 in the diagram.

[0037] Figure 10 It is along Figure 9 The sectional view taken by line V-V' in the middle.

[0038] Figure 11 and Figure 12 It is along Figure 9 The sectional view taken by line VI-VI' in the middle.

[0039] Figure 13 and Figure 14 It is along Figure 5 A schematic cross-sectional view taken by line I-I' in the diagram.

[0040] Figure 15 It is along Figure 5 A schematic cross-sectional view taken from line II-II' in the diagram.

[0041] Figure 16 It is along Figure 5 A schematic cross-sectional view taken from line III-III' in the diagram.

[0042] Figure 17 It is along Figure 5 A schematic cross-sectional view taken from line IV-IV' in the diagram. Detailed Implementation

[0043] Because this disclosure allows for various variations and numerous embodiments, specific embodiments will be illustrated in the accompanying drawings and described in more detail in the written description. However, this is not intended to limit this disclosure to specific models of practice, and it will be understood that all changes, equivalents, and alternatives are included in this disclosure without departing from the spirit and scope of the disclosure.

[0044] Throughout this disclosure, the same reference numerals denote the same parts throughout the various figures and embodiments. For clarity, the dimensions of elements in the figures may be exaggerated. It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed below may be referred to as a second element without departing from the spirit and scope of this disclosure. Similarly, a second element may also be referred to as a first element. In this disclosure, unless the context clearly indicates otherwise, the singular forms are intended to include the plural forms as well.

[0045] It will also be understood that when the terms "comprising," "including," "having," etc., are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, components, and / or combinations thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. Furthermore, when a first component, such as a layer, film, region, or plate, is on a second component, the first component may not only be directly on the second component (without any intermediate components between them), but a third component may be inserted between them. Additionally, when it is stated that a first component, such as a layer, film, region, or plate, is formed on a second component, the surface of the second component on which the first component is formed is not limited to the upper surface of the second component, but may include other surfaces of the second component, such as side surfaces or lower surfaces. When a first component, such as a layer, film, region, or plate, is under a second component, the first component may not only be directly under the second component (without any intermediate components between them), but a third component may be inserted between them.

[0046] In this specification, when it is stated that a first component is operatively or communicatively combined with / operably or communicatively combined to a second component, or that a first component is connected to a second component, the first component should be understood as being directly combined to the second component, or being combined to the second component via a third component. Conversely, when it is stated that a first component is directly combined with / combined to / directly connected to a second component, or is directly connected to a second component, it can be understood that there is no intermediate component between them.

[0047] The term "and / or" includes one or more combinations that can be defined by the relevant elements. When expressions such as "at least one of...", "one of...", and "selected from..." follow a list of elements, they modify the entire list of elements without modifying individual elements within the list. Furthermore, when describing embodiments of this disclosure, the use of "may" indicates "one or more embodiments of this disclosure".

[0048] As used herein, the term “use” and its variations can be considered synonymous with the term “utilize” and its variations, respectively.

[0049] In addition, the terms “basically,” “about,” and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for the inherent biases of the measured or calculated values ​​that would be recognized by a person skilled in the art.

[0050] Furthermore, any numerical range described herein is intended to include all subranges with the same numerical precision contained within the described range. For example, the range "1.0 to 10.0" is intended to include all subranges between the described minimum value of 1.0 and the described maximum value of 10.0 (and includes both the described minimum value of 1.0 and the described maximum value of 10.0), that is, all subranges having a minimum value greater than or equal to 1.0 and a maximum value less than or equal to 10.0, such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, while any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly describe any subranges contained within the range expressly described herein.

[0051] In the following, exemplary embodiments of the present disclosure and other matters necessary to enable those skilled in the art to readily understand the contents of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0052] Figure 1 This is a perspective view schematically illustrating a light-emitting element according to one or more embodiments of the present disclosure. Figure 2 yes Figure 1 A cross-sectional view of the light-emitting element.

[0053] In one or more embodiments of this disclosure, the type (e.g., variety) and / or shape of the light-emitting element is not limited to... Figure 1 and Figure 2 The embodiment shown.

[0054] Reference Figure 1 and Figure 2The light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed therebetween. For example, the light-emitting element (LD) may be implemented as a light-emitting stack in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked.

[0055] The light-emitting element (LD) can be arranged in a shape that extends in one direction. If the direction in which the LD extends is longitudinal, the LD may include a first end (or lower end) and a second end (or upper end) along the extension direction. Either the first semiconductor layer 11 or the second semiconductor layer 13 may be on the first end (or lower end) of the LD, and the other semiconductor layer 11 or the second semiconductor layer 13 may be on the second end (or upper end) of the LD. For example, the first semiconductor layer 11 may be on the first end (or lower end) of the LD, and the second semiconductor layer 13 may be on the second end (or upper end) of the LD.

[0056] The light-emitting element (LD) can be arranged in any of a variety of suitable shapes. For example, the LD can have a rod-like or bar-like shape extending in the longitudinal direction (e.g., with an aspect ratio greater than 1). In one or more embodiments of this disclosure, the length L of the LD in the longitudinal direction can be larger than its diameter D (or the width of its cross-section). Such a LD can include an inorganic light-emitting diode (LED) manufactured with an ultra-small size having a diameter D and / or length L corresponding to, for example, micrometer-scale to nanometer-scale dimensions.

[0057] The size of the light-emitting element (LD) can be appropriately changed to meet the requirements (or design requirements) of lighting devices or self-emitting display devices that use the light-emitting element LD.

[0058] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include any semiconductor material such as InAlGaN, GaN, AlGaN, InGaN, AlN, and / or InN, and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as Si, Ge, and / or Sn. However, the materials forming the first semiconductor layer 11 are not limited thereto, and various other suitable materials may be used to form the first semiconductor layer 11. In one or more embodiments of this disclosure, the first semiconductor layer 11 may include gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). Along the length L of the light-emitting element LD, the first semiconductor layer 11 may include an upper surface in contact (e.g., physical contact) with the active layer 12 and a lower surface exposed to the outside. The lower surface of the first semiconductor layer 11 may be a first end (or lower end) of the light-emitting element LD.

[0059] The active layer 12 can be on the first semiconductor layer 11 and can be formed as a single quantum well structure or a multi-quantum well structure. For example, when the active layer 12 is formed as a multi-quantum well structure, the active layer 12 can be formed by periodically and repeatedly stacking a barrier layer, a strain enhancement layer, and a well layer into a single unit. Because the strain enhancement layer has a smaller lattice constant than the barrier layer, it can enhance the strain applied to the well layer (e.g., compressive strain). However, the structure of the active layer 12 is not limited to the embodiments described above.

[0060] The active layer 12 can emit light with wavelengths in the range of 400 nm to 900 nm and can use a dual heterostructure. In one or more embodiments of this disclosure, a capping layer doped with conductive dopant can optionally be formed on and / or under the active layer 12 along the length L of the light-emitting element LD. For example, the capping layer can be formed as an AlGaN layer and / or an InAlGaN layer. According to one or more embodiments, materials such as AlGaN and / or InAlGaN can be used to form the active layer 12, and various other suitable materials can be used to form the active layer 12. The active layer 12 may include a first surface in contact (e.g., physical contact) with the first semiconductor layer 11 and a second surface in contact (e.g., physical contact) with the second semiconductor layer 13.

[0061] When an electric field of a predetermined (or set) voltage or higher is applied to the opposite ends of the light-emitting element LD, electron-hole pairs combine in the active layer 12, thereby causing the light-emitting element LD to emit light. By using this principle to control the emission of the light-emitting element LD, the light-emitting element LD can be used as a light source (or light source) for various suitable light-emitting devices such as pixels of a display device.

[0062] The second semiconductor layer 13 may be located on the second surface of the active layer 12 and may include a semiconductor layer of a different type (or kind) than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as Mg. However, the materials forming the second semiconductor layer 13 are not limited thereto, and various other suitable materials may be used to form the second semiconductor layer 13. In one or more embodiments of this disclosure, the second semiconductor layer 13 may include gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant). Along the length L of the light-emitting element LD, the second semiconductor layer 13 may include a lower surface in contact (e.g., physical contact) with the second surface of the active layer 12 and an upper surface exposed to the outside. Here, the upper surface of the second semiconductor layer 13 may be the second end (or upper end) of the light-emitting element LD.

[0063] In one or more embodiments of this disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses along the length L of the light-emitting element LD. For example, along the length L of the light-emitting element LD, the first semiconductor layer 11 may have a relatively larger thickness than the second semiconductor layer 13. Therefore, the active layer 12 of the light-emitting element LD may be positioned closer to the upper surface of the second semiconductor layer 13 than the lower surface of the first semiconductor layer 11.

[0064] Although each of the first semiconductor layer 11 and the second semiconductor layer 13 is shown as comprising a single layer, this disclosure is not limited thereto. In one or more embodiments of this disclosure, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further comprise one or more layers (e.g., capping layers and / or tensile strain barrier reduction (TSBR) layers) depending on the material of the active layer 12. The TSBR layer may be a strain relaxation layer that acts as a buffer for reducing the difference in lattice constants between semiconductor layers with different lattice structures. The TSBR layer may be formed of a p-type semiconductor layer such as p-GaInP, p-AlInP, and / or p-AlGaInP, but this disclosure is not limited thereto.

[0065] According to one or more embodiments, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 described above, the light-emitting element LD may also include an additional electrode (hereinafter referred to as the "first additional electrode") on the second semiconductor layer 13. Furthermore, according to one or more embodiments, the light-emitting element LD may also include another additional electrode (hereinafter referred to as the "second additional electrode") on a first end of the first semiconductor layer 11.

[0066] In one or more embodiments, each of the first and second additional electrodes may be an ohmic contact electrode, but this disclosure is not limited thereto. According to one or more embodiments, the first and second additional electrodes may be Schottky contact electrodes. The first and second additional electrodes may include conductive materials (or substances). For example, the first and second additional electrodes may include opaque metals, such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and their oxides or alloys, or combinations thereof, but this disclosure is not limited thereto. According to one or more embodiments, the first and second additional electrodes may include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and / or indium tin zinc oxide (ITZO).

[0067] The materials included in the first and second additional electrodes may be the same or different from each other. The first and second additional electrodes may be substantially transparent or translucent. Therefore, light generated in the light-emitting element LD passes through each of the first and second additional electrodes, thereby being emitted to the outside of the light-emitting element LD. According to one or more embodiments, when light generated in the light-emitting element LD is emitted to the outside of the light-emitting element LD through a region other than the opposite ends of the light-emitting element LD without passing through the first and second additional electrodes, the first and second additional electrodes may comprise opaque metals.

[0068] In one or more embodiments of this disclosure, the light-emitting element LD may further include an insulating layer 14. However, according to one or more embodiments, the insulating layer 14 may be omitted, or the insulating layer 14 may be configured to cover some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0069] The insulating layer 14 prevents or reduces short circuits that might otherwise occur when the active layer 12 comes into contact (e.g., physical contact) with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. Furthermore, the insulating layer 14 minimizes or reduces the occurrence of defects on the surface of the light-emitting element LD, thereby improving the lifetime and light output efficiency of the light-emitting element LD. Additionally, when multiple light-emitting elements LDs are close to each other, the insulating layer 14 prevents or reduces unwanted short circuits that might otherwise occur between the light-emitting elements LDs. If the active layer 12 includes an external conductive material capable of preventing or reducing short circuits, the insulating layer 14 is optional (e.g., the insulating layer 14 may be omitted).

[0070] The insulating layer 14 can be configured to completely surround the outer peripheral surface (e.g., the outer circumferential surface) of the light-emitting stack including the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0071] In the above embodiments, the insulating layer 14 has been described as having a shape that completely surrounds the outer peripheral surface (e.g., outer circumferential surface) of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, but this disclosure is not limited thereto. According to one or more embodiments, when the light-emitting element LD includes a first additional electrode, the insulating layer 14 may completely surround the outer peripheral surface (e.g., outer circumferential surface) of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the first additional electrode. According to one or more embodiments, the insulating layer 14 may not surround the outer peripheral surface (e.g., outer circumferential surface) of the first additional electrode, or may only surround a portion of the outer peripheral surface (e.g., outer circumferential surface) of the first additional electrode, without surrounding the remaining portion. Furthermore, according to one or more embodiments, when the first additional electrode is on a second end (or upper end) of the light-emitting element LD and when the second additional electrode is on a first end (or lower end) of the light-emitting element LD, the insulating layer 14 may allow at least a portion of each of the first and second additional electrodes to be exposed.

[0072] The insulating layer 14 may include a transparent insulating material. For example, the insulating layer 14 may include materials selected from silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x The insulating layer 14 is one or more insulating materials from the group consisting of titanium dioxide (TiO2), etc. However, this disclosure is not limited thereto, and various suitable materials having insulating properties can be used as the material for the insulating layer 14. The insulating layer 14 can be provided in the form of a single-layer film or in the form of a multilayer film comprising at least two films.

[0073] According to one or more embodiments, the light-emitting element (LD) can be implemented as a light-emitting pattern with a core-shell structure. In this case, the first semiconductor layer 11 described above may be located at the core of the light-emitting element LD (e.g., at its center), the active layer 12 may be disposed and / or formed in a shape surrounding the outer peripheral surface (e.g., the outer circumferential surface) of the first semiconductor layer 11, and the second semiconductor layer 13 may be disposed and / or formed in a shape surrounding the active layer 12. In one or more embodiments, the light-emitting element LD may further include an additional electrode surrounding at least one side of the second semiconductor layer 13. According to one or more embodiments, the light-emitting element LD may further include an insulating layer 14, which comprises a transparent insulating material and is disposed on the outer peripheral surface (e.g., the outer circumferential surface) of the light-emitting pattern with the core-shell structure. The light-emitting element LD implemented as a light-emitting pattern with a core-shell structure can be fabricated using a growth method.

[0074] The aforementioned light-emitting elements (LDs) can be used as light sources for various suitable display devices. LDs can be manufactured using surface treatment processes. For example, when multiple LDs are mixed with a liquid solution (or solvent) and supplied to each pixel region (e.g., the emitting region of each pixel or the emitting region of each sub-pixel), a surface treatment can be performed on each of the LDs to ensure that the LDs are sprayed (or distributed) substantially uniformly, rather than unevenly aggregated in the solution.

[0075] Light-emitting units (or light-emitting devices) including the aforementioned light-emitting elements (LDs) can be used in various suitable types of electronic devices that require a light source, such as display devices. For example, when multiple light-emitting elements (LDs) are located in the pixel area of ​​each pixel on a display panel, the light-emitting elements (LDs) can be used as a light source for the pixels. However, the application areas of light-emitting elements (LDs) are not limited to the examples described above. For example, light-emitting elements (LDs) can also be used in other types (or kinds) of electronic devices that require a light source, such as lighting devices.

[0076] Figure 3 A display device according to one or more embodiments of the present disclosure is shown, specifically, Figure 3 It is one of them Figure 1 and Figure 2 The diagram shows a schematic plan view of a display device in which the light-emitting element is used as a light source.

[0077] exist Figure 3 For convenience, the structure of the display device is briefly shown in the display area DA where the image is displayed.

[0078] Reference Figures 1 to 3A display device according to one or more embodiments of the present disclosure may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB and each including at least one light-emitting element LD, a driver disposed on the substrate SUB and configured to drive the pixels PXL, and a line assembly configured to combine the pixels PXL to the driver.

[0079] This disclosure can be applied to electronic devices such as smartphones, televisions, tablet PCs, mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, PDAs, portable multimedia players (PMPs), MP3 players, medical devices, cameras, and / or wearable devices, where the display surface is applied to at least one of their surfaces.

[0080] Based on the method of driving the light-emitting element (LD), the display device can be classified into passive matrix type (or type) display devices and active matrix type (or type) display devices. For example, when the display device is implemented as an active matrix type (or type), each of the pixels PXL may include a driving transistor configured to control the amount of current supplied to the light-emitting element (LD), a switching transistor configured to transmit data signals to the driving transistor, etc.

[0081] The display device can be configured in any of a variety of suitable shapes. For example, the display device can be configured as a rectangular plate shape with two pairs of parallel sides, but this disclosure is not limited thereto. When the display device is configured as a rectangular plate shape, any pair of sides can be configured to be longer than the other pair of sides. For convenience, a case is shown in which the display device has a rectangular shape having a pair of long sides and a pair of short sides. Furthermore, the direction along which the long side extends is indicated as a second direction DR2, the direction along which the short side extends is indicated as a first direction DR1, and the direction perpendicular to the directions along which the long side extends and the short side extends is indicated as a third direction DR3. In a display device configured as a rectangular plate shape, the corners where a single long side and a single short side contact each other (e.g., physically contact) (or meet each other) can have a rounded (or chamfered) shape.

[0082] The base SUB can include the display area DA and the non-display area NDA.

[0083] The display area DA can be an area in which pixels PXL, configured to display an image, are disposed. The non-display area NDA can be an area in which a driver for driving pixels PXL is disposed, and a line assembly configured to connect pixels PXL to the driver is disposed. For convenience, in Figure 3 Only a single pixel PXL is shown, but multiple pixels PXL can be set in the display area DA of the base SUB.

[0084] The non-display area NDA can be located on at least one side of the display area DA. The non-display area NDA can surround the periphery (or edge) of the display area DA. In the non-display area NDA, a line assembly connected to the pixel PXL and a driver connected to the line assembly and configured to drive the pixel PXL can be located.

[0085] A line assembly can electrically connect a driver to the pixel PXL. The line assembly can be a signal line connected to each of the pixels PXL and configured to provide signals to the pixel PXL, and can be a fan-out line, for example, connected to scan lines, data lines, and / or transmit control lines. In one or more embodiments, the line assembly can be a signal line connected to each of the pixels PXL to compensate for changes in the electrical characteristics of the pixel PXL in real time, and can be a fan-out line, for example, connected to control lines and / or sensing lines.

[0086] A substrate SUB can transmit light by including a transparent insulating material. The substrate SUB can be a rigid substrate or a flexible substrate.

[0087] A region on the base SUB can be set as a display region DA, with pixels PXL disposed therein, and the remaining region on the base SUB can be set as a non-display region NDA. For example, the base SUB may include a display region DA and a non-display region NDA surrounding (or adjacent to) the display region DA, the display region DA including the pixel region in which each pixel PXL is disposed.

[0088] Each of the pixels PXL can be disposed inside the display area DA on the substrate SUB. In one or more embodiments of this disclosure, the pixels PXL can be arranged in the display area DA to have a stripe arrangement structure or Arrangement structure or pattern ( (These are registered trademarks owned by Samsung Display Co., Ltd., but this disclosure is not limited thereto.)

[0089] Each pixel PXL may include at least one light-emitting element (LD) driven in response to a scan signal and a corresponding data signal. The LD may have a small size ranging from nanometers to micrometers and may be connected in parallel with adjacent light-emitting elements, but this disclosure is not limited thereto. The LD may constitute the light source for each pixel PXL.

[0090] Each pixel PXL may include at least one light source (e.g., driven in response to a predetermined (or set) signal (e.g., a scan signal and a data signal) and / or a predetermined (or set) power (e.g., a first drive power and a second drive power). Figure 1The light-emitting element LD shown is not limited to this. However, in one or more embodiments of this disclosure, the light-emitting element LD that can be used as the light source for each pixel PXL is not limited to this.

[0091] The driver controls the driving of each pixel PXL by providing a predetermined (or set) signal and predetermined (or set) power to each pixel PXL through a line component. The driver may include a scan driver, a transmit driver, a data driver, and a timing controller.

[0092] Figure 4 It is shown that, according to one or more embodiments, it includes Figure 3 The circuit diagram shows the electrical connections between the components in the pixel shown.

[0093] For example, Figure 4 Electrical connections between components included in a pixel PXL, applicable to an active-mode (or similar) display device according to one or more embodiments, are illustrated. However, the components included in the pixel PXL, applicable to one or more embodiments of this disclosure, are not limited thereto.

[0094] exist Figure 4 In China, it will include not only Figure 3 Each of the pixels shown includes the component, and also includes the portion of the area in which the component is set, referred to as pixel PXL.

[0095] Reference Figures 1 to 4 Each pixel (hereinafter referred to as a "pixel") PXL may include a light-emitting unit (EMU) configured to generate light with a brightness corresponding to the data signal. Additionally, the pixel PXL may optionally include a pixel circuit (PXC) for driving the light-emitting unit (EMU).

[0096] The pixel circuit PXC can be connected to the scan line Si and data line Dj of the corresponding pixel PXL. For example, when pixel PXL is located in the i-th row (i is a natural number) and j-th column (j is a natural number) of display area DA, the pixel circuit PXC of pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of display area DA. Furthermore, the pixel circuit PXC can be connected to the i-th control line CLI and the j-th sensing line SENj of display area DA.

[0097] The aforementioned pixel circuit PXC may include a first transistor T1 to a third transistor T3 and a storage capacitor Cst.

[0098] The first terminal of the second transistor (switching transistor) T2 can be connected to the j-th data line Dj, and its second terminal can be connected to the first node N1. Here, the first and second terminals of the second transistor T2 are different from each other; for example, when the first terminal is the drain electrode, the second terminal can be the source electrode. Furthermore, the gate electrode of the second transistor T2 can be connected to the i-th scan line Si.

[0099] When a scan signal capable of turning on the second transistor T2 is supplied from the i-th scan line Si, the second transistor T2 turns on, thereby electrically connecting the j-th data line Dj to the first node N1. Here, the data signal corresponding to the frame is supplied to the j-th data line Dj, thereby transmitting the data signal to the first node N1. The storage capacitor Cst is charged with the data signal transmitted to the first node N1.

[0100] The first terminal of the first transistor (driving transistor) T1 can be connected to the first driving power supply VDD, and its second terminal can be electrically connected to the first electrode EL1 of each of the light-emitting elements LD. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of driving current supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0101] A third transistor T3 can be connected between the first transistor T1 and the j-th sensing line SENj. For example, the first terminal of the third transistor T3 can be connected to the second terminal of the first transistor T1 connected to the first electrode EL1, and the second terminal of the third transistor T3 can be connected to the j-th sensing line SENj. The gate electrode of the third transistor T3 can be connected to the i-th control line CLI. The third transistor T3 is turned on in response to a control signal that supplies a gate on-state voltage to the i-th control line CLI during a predetermined sensing period, thereby electrically connecting the j-th sensing line SENj to the first transistor T1.

[0102] The sensing period can be the period in which characteristic information (e.g., the threshold voltage of the first transistor T1, etc.) of each pixel PXL in the display area DA is extracted.

[0103] The first electrode of the storage capacitor Cst can be connected to the first drive power supply VDD, and its second electrode can be connected to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to the data signal supplied to the first node N1, and can maintain this voltage until the data signal of the next frame is supplied.

[0104] The light-emitting unit (EMU) may include multiple light-emitting elements (LDs) connected in parallel between each other via a first power line PL1 and a second power line PL2. The voltage of the first driving power supply VDD is applied through the first power line PL1, and the voltage of the second driving power supply VSS is applied through the second power line PL2. For example, the EMU may include a first electrode (or "first alignment electrode") EL1 connected to the first driving power supply VDD via the pixel circuit PXC and the first power line PL1, a second electrode (or "second alignment electrode") EL2 connected to the second driving power supply VSS via the second power line PL2, and multiple light-emitting elements (LDs) connected in parallel between the first electrode EL1 and the second electrode EL2 in the same direction.

[0105] Each of the light-emitting elements (LDs) included in the light-emitting unit (EMU) may include a first terminal connected to a first driving power supply VDD via a first electrode EL1 and a second terminal connected to a second driving power supply VSS via a second electrode EL2. The first driving power supply VDD and the second driving power supply VSS may have different potentials than each other. For example, the first driving power supply VDD may be set to a high potential power supply, and the second driving power supply VSS may be set to a low potential power supply. Here, during the emission period of pixel PXL, the potential difference between the first driving power supply VDD and the second driving power supply VSS may be set to be equal to or higher than the threshold voltage of the light-emitting element LD.

[0106] As described above, the light-emitting elements (LDs) connected in parallel with each other in the same direction (e.g., the forward direction) between the first electrode EL1 and the second electrode EL2 can construct each effective (or forward-biased) light source, with voltages of different potentials supplied to the first electrode EL1 and the second electrode EL2 respectively. These effective (or forward-biased) light sources are collected to construct the light-emitting unit (EMU) of the pixel PXL.

[0107] The light-emitting element (LD) of the light-emitting unit (EMU) can emit light with a brightness corresponding to the driving current supplied through the corresponding pixel circuit (PXC). For example, during each frame period, the pixel circuit (PXC) can supply the EMU with a driving current corresponding to the grayscale value of the data in the corresponding frame. The driving current supplied to the EMU can be divided so that it flows in each light-emitting element (LD). Therefore, each light-emitting element (LD) emits light with a brightness corresponding to the current flowing therein, thereby enabling the EMU to emit light with a brightness corresponding to the driving current.

[0108] According to one or more embodiments, in addition to the light-emitting element LD that constitutes a corresponding effective (or forward-biased) light source, the light-emitting unit (EMU) may also include at least one ineffective light source (e.g., a reverse-emitting element LDr or a reverse-biased light-emitting element LDr). This reverse-emitting element LDr is connected in parallel with the light-emitting element LD that constitutes the effective (e.g., forward-biased) light source between the first electrode EL1 and the second electrode EL2, but may be connected in the opposite direction relative to the light-emitting element LD between the first electrode EL1 and the second electrode EL2. Even when a predetermined (or set) driving voltage (e.g., a forward driving voltage) is applied between the first electrode EL1 and the second electrode EL2, the reverse-emitting element LDr remains in an disabled state, and current may not flow substantially in the reverse-emitting element LDr.

[0109] Each light-emitting unit (EMU) can be configured to include at least one series group, wherein the at least one series group comprises multiple light-emitting elements (LDs) connected in parallel with each other. For example, such as Figure 4 As shown, the light-emitting unit (EMU) can be formed with a hybrid series / parallel structure.

[0110] The light-emitting unit (EMU) may include a first series group SET1 and a second series group SET2 connected sequentially between a first driving power supply VDD and a second driving power supply VSS. The first series group SET1 may include two electrodes EL1 and CTE1 configured as a pair of electrodes corresponding to the series group, and a plurality of light-emitting elements LD connected in parallel with each other in the same direction between the two electrodes EL1 and CTE1. The second series group SET2 may include two electrodes CTE2 and EL2 configured as a pair of electrodes corresponding to the series group, and a plurality of light-emitting elements LD connected in parallel with each other in the same direction between the two electrodes CTE2 and EL2.

[0111] The first series group SET1 may include a first electrode EL1 and a first intermediate electrode CTE1, and may include at least one first light-emitting element LD1 connected between the first electrode EL1 and the first intermediate electrode CTE1. Furthermore, the first series group SET1 may include a reverse light-emitting element LDr coupled between the first electrode EL1 and the first intermediate electrode CTE1 in the opposite direction to the first light-emitting element LD1.

[0112] The second series group SET2 may include a second intermediate electrode CTE2 and a second electrode EL2, and may include at least one second light-emitting element LD2 connected between the second intermediate electrode CTE2 and the second electrode EL2. Furthermore, the second series group SET2 may include a reverse light-emitting element LDr coupled between the second intermediate electrode CTE2 and the second electrode EL2 in the opposite direction to the second light-emitting element LD2.

[0113] The first intermediate electrode CTE1 of the first series group SET1 and the second intermediate electrode CTE2 of the second series group SET2 are configured as a single body, thereby connecting them to each other. For example, the first intermediate electrode CTE1 and the second intermediate electrode CTE2 can form an intermediate electrode CTE that electrically connects adjacent first series groups SET1 and second series groups SET2 to each other. When the first intermediate electrode CTE1 and the second intermediate electrode CTE2 are configured as a single body, the first intermediate electrode CTE1 and the second intermediate electrode CTE2 can be different parts of the intermediate electrode CTE.

[0114] In the above embodiments, the first electrode EL1 of the first series group SET1 can be the anode electrode of the light-emitting unit EMU of each pixel PXL, and the second electrode EL2 of the second series group SET2 can be the cathode electrode of the light-emitting unit EMU.

[0115] Figure 4 An embodiment in which all of the first transistor T1 to the third transistor T3 are N-type transistors is shown, but this disclosure is not limited thereto. For example, at least one of the first transistor T1 to the third transistor T3 described above can be changed to a P-type transistor. Furthermore, Figure 4 One or more embodiments are shown in which the light-emitting unit (EMU) is connected between the pixel circuit PXC and the second driving power supply VSS, but the light-emitting unit (EMU) may optionally be connected between the first driving power supply VDD and the pixel circuit PXC.

[0116] The structure of the pixel circuit PXC can be modified appropriately in various ways. For example, the pixel circuit PXC may also include at least one transistor element (such as a transistor element for initializing the first node N1 and / or a transistor element for controlling the emission time of the light-emitting element LD) and other circuit elements (such as a boost capacitor for increasing the voltage of the first node N1).

[0117] The structures applicable to the pixel PXL of this disclosure are not limited to Figure 4 In the embodiment shown, the pixel PXL can have any of a variety of suitable structures. For example, each pixel PXL can be constructed as a passive (or similar) light-emitting display device. In this case, the pixel circuit PXC is omitted, and the opposite ends of the light-emitting element LD included in the light-emitting unit EMU can be directly connected to the i-th scan line Si, the j-th data line Dj, the first power line PL1 through which the voltage of the first driving power supply VDD is applied, the second power line PL2 through which the voltage of the second driving power supply VSS is applied, and / or a predetermined (or specific) control line.

[0118] Figure 5 It is shown schematically. Figure 3 A planar view of one of the pixels shown.

[0119] In one or more embodiments of this disclosure, for ease of description, the transverse direction (or horizontal direction) in a plane is represented as the first direction DR1, the longitudinal direction (or vertical direction) in a plane is represented as the second direction DR2, and the thickness direction of the substrate SUB in a cross-section is represented as the third direction DR3. (Refer to...) Figures 1 to 5 Each pixel PXL may include a first sub-pixel SPXL1 to a third sub-pixel SPXL3. The pixel region PXA containing each pixel PXL may include a first sub-pixel region SPXA1 containing the first sub-pixel SPXL1, a second sub-pixel region SPXA2 containing the second sub-pixel SPXL2, and a third sub-pixel region SPXA3 containing the third sub-pixel SPXL3.

[0120] The first sub-pixel region SPXA1, the second sub-pixel region SPXA2, and the third sub-pixel region SPXA3 can be set sequentially along the second direction DR2 in the pixel region PXA.

[0121] The pixel region PXA can be divided into a first region A1, a second region A2, and a third region A3 along a direction different from the second direction DR2 (e.g., along a first direction DR1 that intersects the second direction DR2).

[0122] The first region A1 may include a first emission region EMA1 in which light is emitted, and an outer region (e.g., a non-emission region NEMA) adjacent to (or surrounding the periphery of) the first emission region EMA1.

[0123] The second region A2 may include a second emission region EMA2 in which light is emitted, and an outer region (e.g., a non-emission region NEMA) adjacent to (or surrounding the periphery of) the second emission region EMA2.

[0124] The third region A3 may include a third emission region EMA3 in which light is emitted, and an outer region (e.g., a non-emission region NEMA) adjacent to (or surrounding the periphery of) the third emission region EMA3.

[0125] In each of the first emission regions EMA1 to the third emission regions EMA3, a light-emitting element LD and a connection electrode electrically connected to the light-emitting element LD (e.g., a first contact electrode CNE1 and a second contact electrode CNE2, and an intermediate electrode CTE including a first intermediate electrode CTE1 and a second intermediate electrode CTE2) may be provided.

[0126] In one or more embodiments of this disclosure, the first emitting region EMA1 may be the emitting region of the second sub-pixel SPXL2, the second emitting region EMA2 may be the emitting region of the third sub-pixel SPXL3, and the third emitting region EMA3 may be the emitting region of the first sub-pixel SPXL1. In this case, the light-emitting element LD in the first emitting region EMA1 can be electrically connected to some components of the second sub-pixel SPXL2 through its corresponding first contact hole CNT1 and second contact hole CNT2. The light-emitting element LD in the second emitting region EMA2 can be electrically connected to some components of the third sub-pixel SPXL3 through its corresponding first contact hole CNT1 and second contact hole CNT2. The light-emitting element LD in the third emitting region EMA3 can be electrically connected to some components of the first sub-pixel SPXL1 through its corresponding first contact hole CNT1 and second contact hole CNT2.

[0127] In one or more embodiments of this disclosure, when each of the first sub-pixel SPXL1 to the third sub-pixel SPXL3 includes as follows Figure 4 When the light-emitting elements (LDs) are divided into two series groups as shown, each of the first emitting regions EMA1 to the third emitting regions EMA3 may include the light-emitting element LD from each of the two series groups and an electrode connected to the light-emitting element LD. For example, the emitting region of each of the first sub-pixels SPXL1 to the third sub-pixels SPXL3 may include multiple light-emitting elements LD from the corresponding first and second series groups and multiple electrodes connected to the light-emitting elements LD. In this case, at least one light-emitting element LD in the first series group and at least one light-emitting element LD in the second series group can be connected in series with each other.

[0128] The following will refer to Figures 6 to 12 The structure of each pixel PXL, including the first sub-pixel SPXL1 to the third sub-pixel SPXL3, is described in more detail.

[0129] In addition to the first emission regions EMA1 to the third emission regions EMA3 mentioned above, the remaining area of ​​the pixel region PXA of each pixel PXL can be a non-emission region NEMA. BNK can be located within the non-emission region NEMA.

[0130] A dam BNK is a structure used to define (or divide) the pixel region PXA or emission region of a corresponding pixel PXL and the pixels PXL adjacent to the corresponding pixel PXL, and can be, for example, a pixel defining layer. In one or more embodiments of this disclosure, the dam BNK can be a structure used to define a first emission region EMA1, a second emission region EMA2, and a third emission region EMA3 of the corresponding pixel PXL. The dam BNK can be located in the region between the first emission region EMA1 and the third emission region EMA3, and is located outside the first emission region EMA1 to the third emission region EMA3.

[0131] A dam BNK can be a dam structure used to define each emission region, in which the light-emitting element LD is supplied to each emission region during the process of supplying light-emitting elements LD to each pixel PXL. For example, first emission regions EMA1 to third emission regions EMA3 are separated by a dam BNK, thereby allowing a mixture (e.g., ink) including a desired amount and / or type (or variety) of light-emitting elements to be supplied to each of the first emission regions EMA1 to the third emission regions EMA3.

[0132] Such a dam BNK may include at least one light-blocking material and / or reflective material to prevent or reduce light leakage defects between each sub-pixel and its adjacent sub-pixels. According to one or more embodiments, the dam BNK may include a transparent material (or substance). Transparent materials may include, for example, polyamide resins and / or polyimide resins, but this disclosure is not limited thereto. According to one or more embodiments, to further improve the efficiency of light emitted from each pixel PXL, a reflective material layer may be individually disposed and / or formed on the dam BNK.

[0133] The embankment BNK may include multiple openings in each of the first regions A1 to the third regions A3, exposing components located beneath the embankment BNK. The first emission regions EMA1 to the third emission regions EMA3 may be defined by the openings of the embankment BNK. For example, the first emission region EMA1 may be defined by the opening with the largest area among the multiple openings of the embankment BNK in the first region A1. The second emission region EMA2 may be defined by the opening with the largest area among the multiple openings of the embankment BNK in the second region A2. The third emission region EMA3 may be defined by the opening with the largest area among the multiple openings of the embankment BNK in the third region A3.

[0134] As described above, the BNK defines the non-emission region NEMA between the first emission region EMA1 and the third emission region EMA3, thereby allowing the area to which the light-emitting element LD will be supplied (or inserted) to be located in each of the first region A1 to the third region A3. This means the light-emitting element LD can be supplied only to the supply region, thereby improving material efficiency. Furthermore, it prevents or reduces defects that may occur when the light-emitting element LD is supplied to areas other than the supply region, and increases the number of light-emitting element LDs that can be used as effective (e.g., forward biased) light sources in each emission region. For example, in the step of supplying the light-emitting element LD to each pixel PXL, it prevents or reduces the supply of the light-emitting element LD to undesirable areas, and allows for the effective (or appropriate) supply of the light-emitting element LD to each of the first emission region EMA1 to the third emission region EMA3. Therefore, unnecessary waste of the light-emitting element LD is prevented, and the manufacturing cost of the display device can be reduced.

[0135] Light blocking pattern LBP and color filter CF can be located above each pixel PXL.

[0136] The light blocking pattern LBP can be set in the pixel area PXA of each pixel PXL to cover the peripheral area of ​​the first emission area EMA1 to the third emission area EMA3, the peripheral area including the non-emission area NEMA between the first emission area EMA1 to the third emission area EMA3 of pixel PXL.

[0137] The light blocking pattern LBP can be set to correspond to the embankment BNK in the outer region of the first emission region EMA1 to the third emission region EMA3, while surrounding the light-emitting element LD.

[0138] The light-blocking pattern LBP may include multiple openings, each having an open portion, above each of the first emitting regions EMA1 to the third emitting regions EMA3. For example, the light-blocking pattern LBP may be a black matrix pattern in which the openings correspond to the first emitting regions EMA1 to the third emitting regions EMA3 respectively, and in which the remaining area other than the openings is formed of a light-blocking material or the like.

[0139] The aforementioned light-blocking pattern LBP can be disposed on the embankment BNK of each pixel PXL, and can include light-blocking material for preventing (or reducing) light leakage defects that cause light to leak between each of the first emission regions EMA1 to the third emission regions EMA3 and their adjacent emission regions. Furthermore, the light-blocking pattern LBP can prevent (or reduce) the mixing of colors of light emitted from adjacent individual pixels PXL.

[0140] According to one or more embodiments, the light-blocking pattern LBP includes at least one light-blocking material and / or a reflective material, whereby light emitted from the light-emitting element LD in each of the first emitting region EMA1 to the third emitting region EMA3 can travel in the image display direction of the display device. Therefore, the light output efficiency of the light-emitting element LD can be improved.

[0141] Above the first emission regions EMA1 to the third emission regions EMA3, color filters of a predetermined (or set) color corresponding to the color of light intended to be emitted from the corresponding emission regions can be provided. According to one or more embodiments of this disclosure, the color filter pattern of the predetermined (or set) color can be provided above the first emission regions EMA1 to the third emission regions EMA3 corresponding to the respective openings of the light-blocking pattern LBP. For example, above each of the first emission regions EMA1 to the third emission regions EMA3 of each pixel PXL, a corresponding color filter pattern can be provided.

[0142] In one or more embodiments of this disclosure, the color filter may include a first color filter pattern CF1, a second color filter pattern CF2, and a third color filter pattern CF3.

[0143] Each of the first color filter pattern CF1, the second color filter pattern CF2, and the third color filter pattern CF3 can be separated from its adjacent color filter pattern, with a light-blocking pattern LBP between them. For example, the first color filter pattern CF1 can be separated from the second color filter pattern CF2 with the light-blocking pattern LBP between the first color filter pattern CF1 and the second color filter pattern CF2, and the second color filter pattern CF2 can be separated from the third color filter pattern CF3 with the light-blocking pattern LBP between the second color filter pattern CF2 and the third color filter pattern CF3.

[0144] The light-blocking pattern LBP and the color filter CF will be described in more detail below, together with the structure of the first sub-pixel SPXL1 to the third sub-pixel SPXL3.

[0145] Figure 6 It is an illustrative representation of including Figure 5 A plan view of an example pixel circuit layer in a display device. Figure 7 It is an illustrative representation of including Figure 5 A plan view of an example of a display element layer in a display device. Figure 8 It is an illustrative representation of including Figure 5 A plan view of an example of a color filter layer and light-blocking pattern in a display device. Figure 9 This is only shown schematically. Figure 7 A plan of the first area. Figure 10 It is along Figure 9 A cross-sectional view taken by line V-V'. Figure 11 and Figure 12 It is along Figure 9 A sectional view taken from line VI-VI'.

[0146] Figures 7 to 12 The illustration shows one or more embodiments in which the first emission region EMA1 to the third emission region EMA3 of each pixel PXL includes light-emitting elements LDs arranged in two series groups. However, this disclosure is not limited thereto, and the number of series groups in each of the first emission region EMA1 to the third emission region EMA3 may vary according to one or more embodiments.

[0147] Figures 10 to 12 The single pixel PXL is shown by simplifying the single pixel PXL by showing each electrode as a single-layer electrode and each insulating layer as an insulating layer formed of a single layer, but this disclosure is not limited thereto.

[0148] In one or more embodiments of this disclosure, the “connection” between two components can be used to include both electrical and physical connections.

[0149] Furthermore, in one or more embodiments of the invention, when a component is described as “formed and / or disposed on the same layer”, this may refer to the component being formed in the same process (e.g., during the same step of a manufacturing process), while when a component is described as “formed and / or disposed on different layers”, this may refer to the component being formed in different processes (e.g., during different steps of a manufacturing process).

[0150] Reference Figures 1 to 12 Each pixel PXL can include a first sub-pixel SPXL1, a second sub-pixel SPXL2, and a third sub-pixel SPXL3.

[0151] In each pixel region PXA of pixel PXL, the region where the first sub-pixel SPXL1 is set can be the first sub-pixel region SPXA1, the region where the second sub-pixel SPXL2 is set can be the second sub-pixel region SPXA2, and the region where the third sub-pixel SPXL3 is set can be the third sub-pixel region SPXA3.

[0152] In one or more embodiments, the pixel region PXA where each pixel PXL is disposed may include a first region A1, a second region A2, and a third region A3 separated along a first direction DR1.

[0153] In one or more embodiments of this disclosure, the first sub-pixel SPXL1 may be a blue pixel, the second sub-pixel SPXL2 may be a red pixel, and the third sub-pixel SPXL3 may be a green pixel. The emission region of the first sub-pixel SPXL1 may be the third emission region EMA3 of the third region A3, the emission region of the second sub-pixel SPXL2 may be the first emission region EMA1 of the first region A1, and the emission region of the third sub-pixel SPXL3 may be the second emission region EMA2 of the second region A2.

[0154] Each pixel PXL may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL.

[0155] A substrate SUB can transmit light by including a transparent insulating material. The substrate SUB can be a rigid substrate or a flexible substrate.

[0156] The rigid substrate can be, for example, a glass substrate, a quartz substrate, a glass-ceramic substrate, or a crystalline glass substrate.

[0157] The flexible substrate can be one of a membrane substrate comprising polymeric organic materials and a plastic substrate. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0158] In the manufacturing process of display devices, it is desirable for the material applied to the substrate SUB to be resistant (or heat-resistant) to high processing temperatures.

[0159] Multiple insulating layers and multiple conductive layers may be disposed on the substrate SUB. For example, the insulating layers may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, a passivation layer PSV, and first insulating layers INS1 to third insulating layers INS3 sequentially disposed on the substrate SUB. Conductive layers may be disposed and / or formed between the aforementioned insulating layers. For example, conductive layers may include a first conductive layer disposed on the substrate SUB, a second conductive layer disposed on the gate insulating layer GI, a third conductive layer disposed on the interlayer insulating layer ILD, a fourth conductive layer disposed on the passivation layer PSV, and a fifth conductive layer disposed on the second insulating layer INS2. However, the insulating layers and conductive layers disposed on the substrate SUB are not limited to the above embodiments. According to one or more embodiments, in addition to the insulating layers and conductive layers, other insulating layers and / or other conductive layers may be disposed on the substrate SUB.

[0160] A line assembly electrically connected to each pixel PXL may be located on the substrate SUB. The line assembly may include multiple signal lines configured to transmit a predetermined (or set) signal (or a predetermined or set voltage) to each pixel PXL. The signal lines may include scan lines Si, data lines D1 to D3, control lines CLI, a first power line PL1, a second power line PL2, and an initialization power line IPL.

[0161] The scan line Si can extend along the first direction DR1. A scan signal can be applied to the scan line Si. The scan line Si can serve as a reference. Figure 4 The i-th scan line Si is described. The scan line Si can be a third conductive layer disposed on the interlayer insulating layer ILD. The third conductive layer can be a monolayer formed of a single material or a mixture of materials selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), silver (Ag) and their alloys, or it can be a double-layer or multi-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) and / or silver (Ag) as a material with low resistance to reduce wiring resistance.

[0162] The interlayer insulating layer (ILD) can be an inorganic insulating layer comprising inorganic materials. For example, the interlayer insulating layer (ILD) may include materials selected from silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO x The material is at least one of the inorganic materials described above. However, the material of the interlayer insulating layer (ILD) is not limited to the embodiments described above. According to one or more embodiments, the interlayer insulating layer (ILD) may be formed from an organic insulating layer including organic materials. The interlayer insulating layer (ILD) may be configured as a single layer, but may optionally be configured as a multilayer structure having two or more layers.

[0163] Data lines D1 to D3 are spaced apart from each other along a first direction DR1, and may include a first data line D1, a second data line D2, and a third data line D3 extending in a direction different from the first direction DR1 (e.g., in a second direction DR2 intersecting the first direction DR1). A corresponding data signal can be applied to each of the first data lines D1 to the third data lines D3. Each of the first data lines D1 to the third data lines D3 can be a reference. Figure 4The j-th data line Dj is described. A first data line D1 can be electrically connected to the second transistor T2 of the first sub-pixel SPXL1, a second data line D2 can be electrically connected to the second transistor T2 of the second sub-pixel SPXL2, and a third data line D3 can be electrically connected to the second transistor T2 of the third sub-pixel SPXL3. The first data lines D1 to D3 can be a first conductive layer disposed on the substrate SUB. The first conductive layer can include the same material as the third conductive layer, or can include one or more materials selected from those exemplified as materials for forming the third conductive layer.

[0164] The control line CLI can extend along the first direction DR1 while being spaced apart from the scan line Si. A control signal can be applied to the control line CLI. The control line CLI can serve as a reference. Figure 4 The i-th control line CLi is described. The control line CLi can be disposed and / or formed on the same layer as the scan line Si. For example, the control line CLi can be a third conductive layer disposed on the interlayer insulating layer ILD.

[0165] The voltage of the first drive power supply VDD can be applied to the first power line PL1. The first power line PL1 can be a reference. Figure 4 The first power line PL1 is described. The first power line PL1 may include power line 1a PL1a and power line 1b PL1b.

[0166] The first power line PL1a may extend along the second direction DR2. The first power line PL1a may be a first conductive layer disposed and / or formed on the substrate SUB. The first power line PL1a may be disposed on the same layer as the first data lines D1 to the third data lines D3, and may be spaced apart from the first data lines D1 to the third data lines D3 in a plan view.

[0167] The first power line PL1b may extend along the first direction DR1. The first power line PL1b may be a third conductive layer disposed on and / or formed on the interlayer insulating layer ILD. The first power line PL1b may be disposed on the same layer as the control line CLI, and may be spaced apart from the control line CLI in a plan view.

[0168] The first electric power line PL1a and the first electric power line PL1b can be electrically connected to each other through their corresponding contact holes CH. For example, the first electric power line PL1a and the first electric power line PL1b can be electrically connected to each other through contact holes CH that sequentially pass through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. The first electric power line PL1, including the first electric power line PL1a and the first electric power line PL1b that are electrically connected to each other, can have a mesh structure.

[0169] The voltage of the second drive power supply VSS can be applied to the second power line PL2. The second power line PL2 can be a reference. Figure 4 The second power line PL2 is described. The second power line PL2 may include the second power line PL2a and the second power line PL2b.

[0170] The second power line PL2a may extend along the second direction DR2. The second power line PL2a may be a first conductive layer disposed and / or formed on the substrate SUB. The second power line PL2a may be disposed on the same layer as the first data lines D1 to the third data lines D3 and the first power line PL1a, and may be spaced apart from the first data lines D1 to the third data lines D3 and the first power line PL1a in a plan view.

[0171] The second electric field line PL2b may extend along the first direction DR1. The second electric field line PL2b may be a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. The second electric field line PL2b may be disposed on the same layer as the scan line Si, and may be spaced apart from the scan line Si in a planar view.

[0172] The second power line PL2a and the second power line PL2b can be electrically connected to each other through their corresponding contact holes CH. For example, the second power line PL2a and the second power line PL2b can be electrically connected to each other through contact holes CH that sequentially pass through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. The second power line PL2, including the electrically connected second power lines PL2a and PL2b, can have a mesh structure.

[0173] The initial power line IPL can extend along the second direction DR2 and can be located between the second power line PL2a and the first power line PL1a. The initial power line IPL can be a reference... Figure 4 The j-th sensing line SENj is described. The initialization power line IPL can be electrically connected via the seventh connection line CNL7 to some components (e.g., the third transistor T3) in each of the first sub-pixel regions SPXA1 to the third sub-pixel regions SPXA3. The voltage of the initialization power supply can be applied to the initialization power line IPL. The initialization power line IPL can be a first conductive layer disposed on the substrate SUB. The initialization power line IPL can be disposed and / or formed on the same layer as the first data lines D1 to the third data lines D3, and the first a power line PL1a and the second a power line PL2a.

[0174] The seventh connection line CNL7 may extend along the second direction DR2 and may be superimposed on the initialization power line IPL in a plan view. The seventh connection line CNL7 may be electrically connected to the initialization power line IPL via its corresponding contact hole CH. For example, the seventh connection line CNL7 may be electrically connected to the initialization power line IPL via at least two contact holes CH sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. In one or more embodiments, the seventh connection line CNL7 may be electrically connected to the third transistor T3 in each of the first sub-pixels SPXL1 to SPXL3 via corresponding contact holes CH sequentially passing through the gate insulating layer GI and the interlayer insulating layer ILD. For example, the seventh connection line CNL7 can be electrically connected to the third transistor T3 of the first sub-pixel SPXL1 by sequentially passing through the contact hole CH of the gate insulating layer GI and the interlayer insulating layer ILD, and can be electrically connected to the third transistor T3 of the second sub-pixel SPXL2 by sequentially passing through the contact hole CH of the gate insulating layer GI and the interlayer insulating layer ILD, and can be electrically connected to the third transistor T3 of the third sub-pixel SPXL3 by sequentially passing through the contact hole CH of the gate insulating layer GI and the interlayer insulating layer ILD.

[0175] The first electric field line PL1, the second electric field line PL2, and the initialization electric field line IPL can be common components set together for the first sub-pixel region SPXA1 to the third sub-pixel region SPXA3.

[0176] Each of the first sub-pixels SPXL1 to the third sub-pixels SPXL3 may include a pixel circuit layer PCL containing pixel circuits PXC.

[0177] The first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may have similar or identical structures. In the following text, for convenience, the first sub-pixel SPXL1 among the first sub-pixels SPXL1 to the third sub-pixels SPXL3 will be used as the representative, and the second sub-pixel SPXL2 and the third sub-pixel SPXL3 will be briefly described.

[0178] The first sub-pixel SPXL1 may include a pixel circuit layer PCL, which is disposed on the substrate SUB and includes pixel circuits PXC.

[0179] The pixel circuit layer PCL may include a buffer layer BFL, pixel circuits PXC, and a passivation layer PSV.

[0180] The buffer layer (BFL) can be disposed on the first conductive layer and can prevent impurities from diffusing into the pixel circuit (PXC). The buffer layer (BFL) can be an inorganic insulating layer comprising inorganic materials. The buffer layer (BFL) can include materials selected from silicon nitride (SiN). x), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO x The buffer layer BFL can be a single layer, but it can also be a multilayer structure with two or more layers. When the buffer layer BFL is a multilayer structure, the individual layers can be formed of the same material or different materials. Depending on the material and / or process conditions of the substrate SUB, the buffer layer BFL may be omitted.

[0181] The pixel circuit PXC may include a first transistor T1 to a third transistor T3 disposed on the buffer layer BFL and a first storage capacitor Cst1.

[0182] The first transistor T1 can be a reference. Figure 4 The first transistor T1 and the second transistor T2 described can be referenced. Figure 4 The second transistor T2 and the third transistor T3 described can be referenced. Figure 4 The third transistor T3 is described.

[0183] The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source region SE1, and a first drain region DE1.

[0184] The first gate electrode GE1 can be connected to the second source region SE2 of the second transistor T2 via the second connection line CNL2. The first gate electrode GE1 can be disposed on and / or formed on the gate insulating layer GI. The first gate electrode GE1 can be a second conductive layer disposed on and / or formed on the gate insulating layer GI. The second conductive layer can be a monolayer formed of a single material or a mixture of materials selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), silver (Ag) and their alloys, or it can be a double-layer or multi-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) and / or silver (Ag) as materials with low resistance to reduce wiring resistance.

[0185] The gate insulating layer GI may include the same material as the interlayer insulating layer ILD, or may include one or more materials selected from those exemplified as materials for forming the interlayer insulating layer ILD. The gate insulating layer GI may be a single layer, but may be configured as a multilayer structure having two or more layers.

[0186] The second connection line CNL2 may be a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. The first end of the second connection line CNL2 may be electrically connected to the first gate electrode GE1 through a contact hole CH passing through the interlayer insulating layer ILD. The second end of the second connection line CNL2 may be electrically connected to the second source region SE2 of the second transistor T2 through contact holes CH sequentially passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0187] The first active pattern ACT1, the first source region SE1, and the first drain region DE1 can be semiconductor patterns formed from polycrystalline silicon, amorphous silicon, and / or oxide semiconductors. The first active pattern ACT1, the first source region SE1, and the first drain region DE1 can each be independently formed as a doped or undoped semiconductor layer. For example, the first source region SE1 and the first drain region DE1 can be formed as doped semiconductor layers, and the first active pattern ACT1 can be formed as an undoped semiconductor layer. n-type impurities can be used as impurities.

[0188] The first active pattern ACT1, the first source region SE1, and the first drain region DE1 can be set and / or formed on the buffer layer BFL.

[0189] The first active pattern ACT1 can be a region superimposed on the first gate electrode GE1, and can be the channel region of the first transistor T1. When the first active pattern ACT1 is formed in an elongated shape, the channel region of the first transistor T1 can also be formed in an elongated shape. In this case, the driving range of the gate voltage (or gate signal) applied to the first transistor T1 can be expanded. Therefore, the grayscale of the light emitted from the light-emitting element LD can be precisely (or appropriately) controlled.

[0190] The first source region SE1 may be connected to (or contact (e.g., physically contact)) a first end of the first active pattern ACT1. In one or more embodiments, the first source region SE1 may be electrically connected to the first bottom metal layer BML1 via a contact hole CH through the buffer layer BFL.

[0191] The first bottom metal layer BML1 may be a first conductive layer disposed on and / or formed on the substrate SUB. The first bottom metal layer BML1 may be disposed on and / or formed on the same layer as the first data lines D1 to D3, the first power line PL1a and the second power line PL2a, and the initialization power line IPL. The first bottom metal layer BML1 may be electrically connected to the first source region SE1 of the first transistor T1 through the corresponding contact hole CH.

[0192] The first drain area DE1 may be connected to (or contact (e.g., physically contact)) the second end of the first active pattern ACT1. In one or more embodiments, the first drain area DE1 may be electrically connected to the first power line PL1a via the eighth connection line CNL8.

[0193] The first end of the eighth connection line CNL8 can be connected to the first drain region DE1 through contact holes CH that sequentially pass through the gate insulating layer GI and the interlayer insulating layer ILD. In one or more embodiments, the second end of the eighth connection line CNL8 can be electrically connected to the first power line PL1a through contact holes CH that sequentially pass through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. The eighth connection line CNL8 can electrically connect the first drain region DE1 to the first power line PL1a.

[0194] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source region SE2, and a second drain region DE2.

[0195] The second gate electrode GE2 may extend along the second direction DR2 and may be a common component commonly disposed (or placed) for the first sub-pixels SPXL1 to the third sub-pixels SPXL3. The second gate electrode GE2 may be a second conductive layer disposed and / or formed on the gate insulating layer GI. The second gate electrode GE2 may be electrically connected to the scan line Si through a contact hole CH passing through the interlayer insulating layer ILD. Therefore, the scan signal applied to the scan line Si may be transmitted to the second gate electrode GE2.

[0196] In the above embodiments, the second gate electrode GE2 (a component configured to be separate from the scan line Si) is described as being electrically connected to the scan line Si through a corresponding contact hole CH, but this disclosure is not limited thereto. According to one or more embodiments, the second gate electrode GE2 may be integral with the scan line Si. In this case, the second gate electrode GE2 may be configured as part of the scan line Si, or may be configured in a shape protruding from the scan line Si.

[0197] The second active pattern ACT2, the second source region SE2, and the second drain region DE2 can be semiconductor patterns formed from polycrystalline silicon, amorphous silicon, and / or oxide semiconductors. The second active pattern ACT2, the second source region SE2, and the second drain region DE2 can be formed as semiconductor layers with or without impurities. For example, the second source region SE2 and the second drain region DE2 can be formed as semiconductor layers with impurities, and the second active pattern ACT2 can be formed as an undoped semiconductor layer. n-type impurities can be used as the impurities.

[0198] The second active pattern ACT2, the second source region SE2, and the second drain region DE2 can be set and / or formed on the buffer layer BFL.

[0199] The second active pattern ACT2 can be a region superimposed on the second gate electrode GE2, and can be the channel region of the second transistor T2.

[0200] The second source region SE2 may be connected to (or contact (e.g., physically contact)) the first end of the second active pattern ACT2. In one or more embodiments, the second source region SE2 may be connected to the first gate electrode GE1 of the first transistor T1 via the second connection line CNL2.

[0201] The second drain area DE2 can be connected to (or contact (e.g., physically contact)) the second end of the second active pattern ACT2. In one or more embodiments, the second drain area DE2 can be connected to the first data line D1 via the first connection line CNL1.

[0202] The first connection line CNL1 may be a third conductive layer disposed on and / or formed on the interlayer insulating layer ILD. A first end of the first connection line CNL1 may be electrically connected to the first data line D1 through contact holes CH sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. A second end of the first connection line CNL1 may be connected to the second drain region DE2 through contact holes CH sequentially passing through the gate insulating layer GI and the interlayer insulating layer ILD. The second drain region DE2 and the first data line D1 may be electrically connected to each other through the first connection line CNL1.

[0203] The third transistor T3 may include a third gate electrode GE3, a third active pattern ACT3, a third source region SE3, and a third drain region DE3.

[0204] The third gate electrode GE3 may extend along the second direction DR2 and may be a common component commonly disposed (or placed) for the first sub-pixels SPXL1 to the third sub-pixels SPXL3. The third gate electrode GE3 may be a second conductive layer disposed and / or formed on the gate insulating layer GI. The third gate electrode GE3 may be electrically connected to the control line CLI through a contact hole CH passing through the interlayer insulating layer ILD. Therefore, the control signal applied to the control line CLI may be transmitted to the third gate electrode GE3.

[0205] In the above embodiments, the third gate electrode GE3 (a component configured to be separate from the control line CLI) is described as being electrically connected to the control line CLI through a corresponding contact hole CH, but this disclosure is not limited thereto. According to one or more embodiments, the third gate electrode GE3 may be integrated with the control line CLI. In this case, the third gate electrode GE3 may be configured as part of the control line CLI, or may be configured in a shape that protrudes from the control line CLI.

[0206] The third active pattern ACT3, the third source region SE3, and the third drain region DE3 can be semiconductor patterns formed from polycrystalline silicon, amorphous silicon, and / or oxide semiconductors. The third active pattern ACT3, the third source region SE3, and the third drain region DE3 can each be independently formed as a doped or undoped semiconductor layer. For example, the third source region SE3 and the third drain region DE3 can be formed as doped semiconductor layers, while the third active pattern ACT3 can be formed as an undoped semiconductor layer. n-type impurities can be used as impurities.

[0207] The third active pattern ACT3, the third source region SE3, and the third drain region DE3 can be set and / or formed on the buffer layer BFL.

[0208] The third active pattern ACT3 can be a region superimposed on the third gate electrode GE3, and can be the channel region of the third transistor T3.

[0209] The third source region SE3 may be connected to (or contact (e.g., physically contact)) the first end of the third active pattern ACT3. In one or more embodiments, the third source region SE3 may be electrically connected to the first bottom metal layer BML1 via a contact hole CH through the buffer layer BFL.

[0210] The third drain region DE3 can be connected to (or contact (e.g., physically contact)) the second end of the third active pattern ACT3. In one or more embodiments, the third drain region DE3 can be electrically connected to the initialization power line IPL via the seventh connection line CNL7.

[0211] The first storage capacitor Cst1 may include a first lower electrode LE1 and a first upper electrode UE1. Here, the first storage capacitor Cst1 may be a reference. Figure 4 The storage capacitor Cst is described.

[0212] The first lower electrode LE1 can be integrated with the first gate electrode GE1. When the first lower electrode LE1 is integrated with the first gate electrode GE1, the first lower electrode LE1 can be a part of the first gate electrode GE1.

[0213] The first upper electrode UE1 may be stacked with the first lower electrode LE1 in a planar view and may have a larger area (or size) than the first lower electrode LE1. In a planar view, the first upper electrode UE1 may be stacked with each of the first source region SE1 and the third source region SE3. The first upper electrode UE1 may be a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. The first upper electrode UE1 may be disposed and / or formed on the same layer as the scan line Si, the control line CLI, and the first b electric field line PL1b and the second b electric field line PL2b. In one or more embodiments of this disclosure, the first upper electrode UE1 may include a first bridging pattern BRP1 extending along a first direction DR1 to a pixel region PXA of an adjacent pixel PXL. The first bridging pattern BRP1 may be integral with the first upper electrode UE1. In this case, the first bridging pattern BRP1 may be part of the first upper electrode UE1.

[0214] The first upper electrode UE1 can be electrically connected to the first bottom metal layer BML1 through contact holes CH that sequentially pass through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. The first upper electrode UE1, the first source region SE1 of the first transistor T1, and the third source region SE3 of the third transistor T3 can be connected to each other through the first bottom metal layer BML1.

[0215] In the second sub-pixel region SPXA2, where the second sub-pixel SPXL2 is located, the first transistor T1 to the third transistor T3, the second storage capacitor Cst2, and the second bottom metal layer BML2 can be disposed.

[0216] The first transistor T1 of the second sub-pixel SPXL2 may include a first gate electrode GE1, a first active pattern ACT1, a first source region SE1, and a first drain region DE1.

[0217] The first drain region DE1 of the first transistor T1 can be electrically connected to the first power line PL1a via the ninth connection line CNL9.

[0218] The ninth connection line CNL9 may be a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. The ninth connection line CNL9 may be electrically connected to the first power line PL1a via contact holes CH that sequentially pass through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. In one or more embodiments, the ninth connection line CNL9 may be electrically connected to the first drain region DE1 via contact holes CH that sequentially pass through the gate insulating layer GI and the interlayer insulating layer ILD.

[0219] The second transistor T2 of the second sub-pixel SPXL2 may include a second gate electrode GE2, a second active pattern ACT2, a second source region SE2, and a second drain region DE2.

[0220] The second source region SE2 of the second transistor T2 can be electrically connected to the first gate electrode GE1 of the first transistor T1 of the second sub-pixel SPXL2 via the fourth connection line CNL4.

[0221] The fourth connection line CNL4 may be a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. The first end of the fourth connection line CNL4 may be electrically connected to the first gate electrode GE1 through a contact hole CH passing through the interlayer insulating layer ILD. The second end of the fourth connection line CNL4 may be electrically connected to the second source region SE2 through contact holes CH sequentially passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0222] The second drain region DE2 of the second transistor T2 of the second sub-pixel SPXL2 can be electrically connected to the second data line D2 via a third connection line CNL3. Here, the third connection line CNL3 can be a third conductive layer disposed on and / or formed on the interlayer insulating layer ILD. The first end of the third connection line CNL3 can be electrically connected to the second data line D2 via a contact hole CH that sequentially passes through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. The second end of the third connection line CNL3 can be electrically connected to the second drain region DE2 via a contact hole CH that sequentially passes through the gate insulating layer GI and the interlayer insulating layer ILD.

[0223] The second storage capacitor Cst2 may have a structure substantially the same as that of the first storage capacitor Cst1 of the first sub-pixel SPXL1. For example, the second storage capacitor Cst2 may include a second lower electrode LE2 and a second upper electrode UE2. The second lower electrode LE2 may be a second conductive layer disposed on the gate insulating layer GI. The second lower electrode LE2 may be integrated with the first gate electrode GE1 of the first transistor T1 of the second sub-pixel SPXL2. The second upper electrode UE2 may be a third conductive layer disposed on the interlayer insulating layer ILD, and may be stacked with the second lower electrode LE2 in a planar view.

[0224] The second bottom metal layer BML2 may be disposed and / or formed on the same layer as the first bottom metal layer BML1. For example, the second bottom metal layer BML2 may be a first conductive layer disposed on the substrate SUB. The second bottom metal layer BML2 may be electrically connected to the first source region SE1, the third source region SE3, and the second upper electrode UE2. Specifically, the second bottom metal layer BML2 may be electrically connected to each of the first source region SE1 and the third source region SE3 through a contact hole CH passing through the buffer layer BFL. In one or more embodiments, the second bottom metal layer BML2 may be electrically connected to the second upper electrode UE2 through contact holes CH sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. The first source region SE1, the third source region SE3, and the second upper electrode UE2 may be electrically connected to each other through the second bottom metal layer BML2.

[0225] In the third sub-pixel region SPXA3, where the third sub-pixel SPXL3 is located, the first transistor T1 to the third transistor T3, the third storage capacitor Cst3, and the third bottom metal layer BML3 can be disposed.

[0226] The first transistor T1 of the third sub-pixel SPXL3 may include a first gate electrode GE1, a first active pattern ACT1, a first source region SE1, and a first drain region DE1.

[0227] The first drain region DE1 of the first transistor T1 can be electrically connected to the first power line PL1a via the ninth connection line CNL9. The ninth connection line CNL9 can be electrically connected to the first power line PL1a via contact holes CH that sequentially pass through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. In one or more embodiments, the ninth connection line CNL9 can be electrically connected to the first drain region DE1 via contact holes CH that sequentially pass through the gate insulating layer GI and the interlayer insulating layer ILD.

[0228] The second transistor T2 of the third sub-pixel SPXL3 may include a second gate electrode GE2, a second active pattern ACT2, a second source region SE2, and a second drain region DE2.

[0229] The second source region SE2 of the second transistor T2 of the third sub-pixel SPXL3 can be electrically connected to the first gate electrode GE1 of the first transistor T1 of the third sub-pixel SPXL3 via the sixth connection line CNL6.

[0230] The sixth connection line CNL6 may be a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. The first end of the sixth connection line CNL6 may be electrically connected to the first gate electrode GE1 through a contact hole CH passing through the interlayer insulating layer ILD. The second end of the sixth connection line CNL6 may be electrically connected to the second source region SE2 through contact holes CH sequentially passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0231] The second drain region DE2 of the second transistor T2 of the third sub-pixel SPXL3 can be electrically connected to the third data line D3 via the fifth connection line CNL5. Here, the fifth connection line CNL5 can be a third conductive layer disposed and / or formed on the interlayer insulating layer ILD. The first end of the fifth connection line CNL5 can be electrically connected to the third data line D3 via a contact hole CH that sequentially passes through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. The second end of the fifth connection line CNL5 can be electrically connected to the second drain region DE2 via a contact hole CH that sequentially passes through the gate insulating layer GI and the interlayer insulating layer ILD.

[0232] The third storage capacitor Cst3 may include a third lower electrode LE3 and a third upper electrode UE3.

[0233] The third lower electrode LE3 can be a second conductive layer disposed on the gate insulating layer GI. The third lower electrode LE3 can be configured to be integrated with the first gate electrode GE1 of the first transistor T1 of the third sub-pixel SPXL3.

[0234] The third upper electrode UE3 may be a third conductive layer disposed on the interlayer insulating layer ILD, and may be stacked with the third lower electrode LE3 in a plan view. In one or more embodiments of this disclosure, the third upper electrode UE3 may include a second bridging pattern BRP2 extending along the first direction DR1 to a pixel region PXA of the adjacent pixel PXL. The second bridging pattern BRP2 may be integral with the third upper electrode UE3. In this case, the second bridging pattern BRP2 may be part of the third upper electrode UE3.

[0235] The third bottom metal layer BML3 may be disposed and / or formed on the same layer as the first bottom metal layer BML1 and the second bottom metal layer BML2. For example, the third bottom metal layer BML3 may be a first conductive layer disposed on the substrate SUB. The third bottom metal layer BML3 may be electrically connected to the first source region SE1, the third source region SE3, and the third upper electrode UE3. For example, the third bottom metal layer BML3 may be electrically connected to each of the first source region SE1 and the third source region SE3 through a contact hole CH passing through the buffer layer BFL. In one or more embodiments, the third bottom metal layer BML3 may be electrically connected to the third upper electrode UE3 through contact holes CH sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. The first source region SE1, the third source region SE3, and the third upper electrode UE3 may be electrically connected to each other through the third bottom metal layer BML3.

[0236] The passivation layer PSV can be disposed and / or formed on the scan line Si, control line CLI, first b electric field line PL1b and second b electric field line PL2b as described above, first connection line CNL1 to ninth connection line CNL9 and first upper electrode UE1 to third upper electrode UE3.

[0237] The passivation layer PSV can be provided in the form of an organic insulating layer, an inorganic insulating layer, or an organic insulating layer on an inorganic insulating layer. The inorganic insulating layer can include, for example, silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO x The organic insulating layer may include at least one of the inorganic materials selected from, for example, polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin and benzocyclobutene resin.

[0238] The passivation layer PSV may include a first contact hole CNT1 and a second contact hole CNT2. The second contact hole CNT2 may expose each of a portion of a first upper electrode UE1 (e.g., a portion of a first bridging pattern BRP1), a portion of a second upper electrode UE2, and a portion of a third upper electrode UE3 (e.g., a portion of a second bridging pattern BRP2). The first contact hole CNT1 may expose each of a first portion, a second portion, and a third portion of a second-b power line PL2b. In one or more embodiments of this disclosure, the number of first contact holes CNT1 disposed in the pixel region PXA of each pixel PXL may be three, and the number of second contact holes CNT2 disposed in the pixel region PXA may be three.

[0239] like Figure 7 as well as Figures 9 to 12 As shown, each of the first sub-pixels SPXL1 to SPXL3 may include a display element layer DPL containing a light-emitting element (LD). The display element layer DPL of the first sub-pixel SPXL1 may be located in the third region A3 of the pixel region PXA of each pixel PXL, the display element layer DPL of the second sub-pixel SPXL2 may be located in the first region A1 of the corresponding pixel region PXA, and the display element layer DPL of the third sub-pixel SPXL3 may be located in the second region A2 of the corresponding pixel region PXA. In one or more embodiments, the display element layer DPL of each of the first sub-pixels SPXL1 to SPXL3 may correspond to the emission region of each of the first sub-pixels SPXL1 to SPXL3. For example, the display element layer DPL of the first sub-pixel SPXL1 may correspond to the third emission region EMA3, the display element layer DPL of the second sub-pixel SPXL2 may correspond to the first emission region EMA1, and the display element layer DPL of the third sub-pixel SPXL3 may correspond to the second emission region EMA2.

[0240] The display element layer DPL of each of the first sub-pixels SPXL1 to the third sub-pixels SPXL3 can be set and / or formed on the passivation layer PSV.

[0241] The display element layer (DPL) may include a dam (BNK), first electrodes EL1 to fourth electrodes EL4, a light-emitting element (LD), first contact electrode CNE1 and second contact electrode CNE2, intermediate electrode CTE, and first insulating layer INS1 to third insulating layer INS3.

[0242] Because the embankment BNK corresponds to the reference Figure 5 The components described are the same as those in the BNK, so they will only be briefly described below.

[0243] The embankment BNK may include first openings OP1 to third openings OP3 that expose components located beneath the embankment BNK in each of the first regions A1 to the third regions A3.

[0244] The first emission region EMA1 to the third emission region EMA3 of each pixel PXL can be defined by the second aperture OP2 of the embankment BNK. For example, the first emission region EMA1 can be defined by the second aperture OP2 in the first region A1 of the embankment BNK, the second emission region EMA2 can be defined by the second aperture OP2 in the second region A2 of the embankment BNK, and the third emission region EMA3 can be defined by the second aperture OP2 in the third region A3 of the embankment BNK.

[0245] In each of the first regions A1 to the third regions A3, each of the first opening OP1 and the third opening OP3 of the embankment BNK can be positioned spaced apart from the second opening OP2 in each of the first regions A1 to the third regions A3, and can be positioned closer to one side of the corresponding region (e.g., the lower or upper side). For example, in each of the first regions A1 to the third regions A3, the first opening OP1 of the embankment BNK can be positioned closer to the upper side in the plan view, and the third opening OP3 of the embankment BNK can be positioned closer to the lower side in the plan view.

[0246] The size and shape of the second opening OP2 in the first region A1 of the dam BNK, the size and shape of the second opening OP2 in the second region A2 of the dam BNK, and the size and shape of the second opening OP2 in the third region A3 of the dam BNK can be the same as each other. For example, the size and shape of the second opening OP2 in each of the first regions A1 to the third regions A3 of the dam BNK can be the same as the size and shape of the second opening OP2 in the region adjacent to it along the first direction DR1 of the dam BNK. However, this disclosure is not limited thereto. According to one or more embodiments, the size of the second opening OP2 corresponding to each of the first emission regions EMA1 to the third emission regions EMA3 of the dam BNK can be set with consideration of the efficiency (e.g., color reproduction rate, etc.) of the light ultimately emitted from the first emission region EMA1 to the third emission region EMA3.

[0247] The dam BNK may be disposed and / or formed on the first insulating layer INS1, but this disclosure is not limited thereto. According to one or more embodiments, the dam BNK may optionally be disposed and / or formed on the passivation layer PSV.

[0248] The first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 can be sequentially arranged along the first direction DR1 on the passivation layer PSV of each of the first regions A1 to the third regions A3. The first electrode EL1 to the fourth electrode EL4 can be a fourth conductive layer disposed on and / or formed on the passivation layer PSV.

[0249] The first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may extend along the second direction DR2. The two ends of each of the first electrode EL1 to the fourth electrode EL4 may be located in the first opening OP1 and the third opening OP3 of the embankment BNK, respectively. In the process of manufacturing the display device, after the light-emitting element LD is supplied and arranged in each of the first emitting regions EMA1 to the third emitting regions EMA3, the first electrode EL1 to the fourth electrode EL4 may be separated from the other electrodes in each of the first opening OP1 and the third opening OP3 (e.g., the first electrode to the fourth electrode provided for the pixel PXL adjacent to it on the second direction DR2). To facilitate the separation process of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4, each of the first opening OP1 and the third opening OP3 of the embankment BNK may be provided.

[0250] Each of the first electrode EL1 to the fourth electrode EL4 can be spaced apart from its adjacent electrode along a first direction DR1 in each of the first region A1 to the third region A3. For example, the first electrode EL1 can be spaced apart from the second electrode EL2, the second electrode EL2 can be spaced apart from the third electrode EL3, and the third electrode EL3 can be spaced apart from the fourth electrode EL4. The distances between the first electrode EL1 and the second electrode EL2, the distances between the second electrode EL2 and the third electrode EL3, and the distances between the third electrode EL3 and the fourth electrode EL4 can be the same, but this disclosure is not limited thereto. According to one or more embodiments, the distances between the first electrode EL1 and the second electrode EL2, the distances between the second electrode EL2 and the third electrode EL3, and the distances between the third electrode EL3 and the fourth electrode EL4 can be different from each other.

[0251] The first electrodes EL1 to the fourth electrodes EL4 can be formed of a material with a constant reflectivity, so that light emitted from each of the light-emitting elements LD travels in the image display direction (e.g., the forward direction) of the display device. For example, the first electrodes EL1 to the fourth electrodes EL4 can be formed of a conductive material (or substance) with a constant reflectivity. The conductive material (or substance) can include an opaque metal that is advantageous (or suitable) for reflecting light emitted from the light-emitting element LD in the image display direction of the display device. The opaque metal can include metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and / or alloys thereof. According to one or more embodiments, the first electrodes EL1 to the fourth electrodes EL4 can include a transparent conductive material (or substance). Transparent conductive materials (or substances) may include conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and / or indium tin zinc oxide (ITZO)) and / or conductive polymers (such as poly(3,4-ethylenedioxythiophene) (PEDOT)). When the first electrode EL1 to the fourth electrode EL4 comprises a transparent conductive material (or substance), a separate conductive layer formed of an opaque metal may be added to reflect light emitted from the light-emitting element LD in the image display direction of the display device. However, the materials of the first electrode EL1 to the fourth electrode EL4 are not limited to those mentioned above.

[0252] In one or more embodiments, each of the first electrode EL1 to the fourth electrode EL4 may be configured and / or formed as a single layer, but this disclosure is not limited thereto. According to one or more embodiments, each of the first electrode EL1 to the fourth electrode EL4 may be configured and / or formed as a multilayer structure in which at least two materials selected from metals, alloys, conductive oxides, and conductive polymers are stacked. Each of the first electrode EL1 to the fourth electrode EL4 may be formed as a multilayer structure having two or more layers to minimize (or reduce) distortion that may be caused by signal delay when a signal (or voltage) is transmitted to opposite ends of each of the light-emitting elements LD. For example, each of the first electrode EL1 to the fourth electrode EL4 may be formed as a multilayer structure in which indium tin oxide (ITO), silver (Ag), and / or indium tin oxide (ITO) are sequentially stacked.

[0253] In each of the first regions A1 to the third regions A3, the first electrode EL1 can be electrically connected to some components of the corresponding pixel circuit layer PCL through the first contact hole CNT1 of the passivation layer PSV. For example, the first electrode EL1 of the first region A1 can be electrically connected to the second b power line PL2b corresponding to the first region A1 through one of the three first contact holes CNT1 of the passivation layer PSV. The first electrode EL1 of the second region A2 can be electrically connected to the second b power line PL2b corresponding to the second region A2 through another of the three first contact holes CNT1. The first electrode EL1 of the third region A3 can be electrically connected to the second b power line PL2b corresponding to the third region A3 through the remaining one of the three first contact holes CNT1.

[0254] In each of the first regions A1 to the third regions A3, the third electrode EL3 can be electrically connected to some components of the corresponding pixel circuit layer PCL through the second contact holes CNT2 of the passivation layer PSV. For example, the third electrode EL3 of the first region A1 can be electrically connected to the second upper electrode UE2 corresponding to the first region A1 through one of the three second contact holes CNT2 of the passivation layer PSV. The third electrode EL3 of the second region A2 can be electrically connected to the second bridging pattern BRP2 corresponding to the second region A2 through another of the three second contact holes CNT2. The third electrode EL3 of the third region A3 can be electrically connected to the first bridging pattern BRP1 corresponding to the third region A3 through the remaining one of the three second contact holes CNT2. As described above, since the first bridging pattern BRP1 is part of the first upper electrode UE1, the third electrode EL3 of the third region A3 can be electrically connected to the first upper electrode UE1. Furthermore, since the second bridging pattern BRP2 is part of the third upper electrode UE3, the third electrode EL3 of the second region A2 can be electrically connected to the third upper electrode UE3.

[0255] In each of the first regions A1 to the third regions A3, the first electrode EL1 can be a reference electrode. Figure 4 The second electrode EL2 described is essentially the same component, and the third electrode EL3 may be the same as the referenced component. Figure 4 The first electrode EL1 described is essentially the same component.

[0256] According to one or more embodiments, the support member may be located in each of the first regions A1 to the third regions A3 between the first electrode EL1 to the fourth electrode EL4 and the passivation layer PSV. For example, as Figure 12 As shown, the embankment pattern BNKP can be located between each of the first electrode EL1 to the fourth electrode EL4 and the passivation layer PSV.

[0257] The dam pattern BNKP can be located in the emission region of each pixel PXL. For example, the dam pattern BNKP can be located in each of the first emission regions EMA1 to the third emission regions EMA3. The dam pattern BNKP can be a support member for supporting the first electrodes EL1 to the fourth electrodes EL4 to change the surface profile (or shape) of each of the first electrodes EL1 to the fourth electrodes EL4 in the corresponding region, so that the light emitted from the light-emitting element LD is guided to travel in the image display direction of the display device.

[0258] The dam pattern BNKP can be disposed between the passivation layer PSV and the first electrode EL1 to the fourth electrode EL4 in the corresponding emission region. For example, the dam pattern BNKP can be disposed between the passivation layer PSV and the first electrode EL1 to the fourth electrode EL4 in each of the first emission regions EMA1 to the third emission region EMA3.

[0259] The embankment pattern BNKP can be an inorganic insulating layer comprising inorganic materials or an organic insulating layer comprising organic materials. According to one or more embodiments, the embankment pattern BNKP may comprise a single organic insulating layer and / or a single inorganic insulating layer, but this disclosure is not limited thereto. According to one or more embodiments, the embankment pattern BNKP may be configured as a multilayer structure in which at least one organic insulating layer and at least one inorganic insulating layer are stacked. However, the materials of the embankment pattern BNKP are not limited to the above embodiments, and according to one or more embodiments, the embankment pattern BNKP may comprise a conductive material (or substance).

[0260] The embankment pattern BNKP may have a trapezoidal cross-section, the width of which decreases from one surface (e.g., the upper surface) of the passivation layer PSV along the third direction DR3 toward the upper part of the cross-section, but this disclosure is not limited thereto. According to one or more embodiments, the embankment pattern BNKP may include curved surfaces such as a semi-elliptical cross-section and / or a semi-circular (or hemispherical) cross-section, the width of which decreases from one surface of the passivation layer PSV along the third direction DR3 toward the upper part of the cross-section. In the cross-sectional view, the shape of the embankment pattern BNKP is not limited to the embodiments described above and can be appropriately modified within a range that can improve the efficiency of light emitted from each of the light-emitting elements LD.

[0261] Each of the first electrodes EL1 to the fourth electrodes EL4 can be disposed and / or formed on the embankment pattern BNKP. Therefore, each of the first electrodes EL1 to the fourth electrodes EL4 has a surface profile corresponding to the shape of the embankment pattern BNKP beneath it, and light emitted from the light-emitting element LD is reflected by each of the first electrodes EL1 to the fourth electrodes EL4, thereby further traveling in the image display direction of the display device. Each of the first electrodes EL1 to the fourth electrodes EL4 and the embankment pattern BNKP guides the light emitted from the light-emitting element LD in a desired direction, thus acting as a reflective member for improving the light efficiency of the display device. When each pixel PXL does not include the embankment pattern BNKP, the first electrodes EL1 to the fourth electrodes EL4 can be disposed and / or formed on one surface (e.g., the upper surface) of the passivation layer PSV.

[0262] Each of the first electrodes EL1 to the fourth electrodes EL4 can be used as an alignment electrode (or alignment line) for aligning the light-emitting element LD by receiving a predetermined (or set) alignment signal (or alignment voltage) before the light-emitting element LD is aligned in the pixel region PXA of each pixel PXL. For example, before the light-emitting element LD is aligned in the first emission region EMA1 to the third emission region EMA3 defined (or separated) by the embankment BNK, each of the first electrodes EL1 to the fourth electrodes EL4 can be used as an alignment electrode for aligning the light-emitting element LD by receiving a predetermined (or set) alignment signal.

[0263] In each of the first regions A1 to the third regions A3, the first electrode EL1 can be used as the first alignment electrode (or the first alignment line) by receiving a first alignment signal (or a first alignment voltage), the second electrode EL2 can be used as the second alignment electrode (or the second alignment line) by receiving a second alignment signal (or a second alignment voltage), the third electrode EL3 can be used as the third alignment electrode (or the third alignment line) by receiving a third alignment signal (or a third alignment voltage), and the fourth electrode EL4 can be used as the fourth alignment electrode (or the fourth alignment line) by receiving a fourth alignment signal (or a fourth alignment voltage). Here, the first alignment signal and the fourth alignment signal can be the same alignment signal, and the second alignment signal and the third alignment signal can be the same alignment signal. The first alignment signal and the fourth alignment signal, as well as the second alignment signal and the third alignment signal, can be signals with a voltage difference and / or a phase difference, and the light-emitting element LD can be aligned between two adjacent electrodes by the voltage difference and / or the phase difference. Among the first alignment signal and the fourth alignment signal, as well as the second alignment signal and the third alignment signal, at least the first alignment signal and the fourth alignment signal can be alternating current (AC) signals (or voltages), but this disclosure is not limited thereto, and at least the second alignment signal and the third alignment signal can be AC ​​signals (or voltages).

[0264] After the light-emitting element LD is aligned in each of the first emission regions EMA1 to the third emission regions EMA3, a portion of each of the first electrodes EL1 to the fourth electrodes EL4 located between adjacent sub-pixels in the second direction DR2 is removed to drive each of the first sub-pixels SPXL1 to the third sub-pixels SPXL3 independently of the sub-pixels adjacent to them in the second direction DR2. Thus, the two ends of each of the first electrodes EL1 to the fourth electrodes EL4 can be located in the first opening hole OP1 and the third opening hole OP3 of the embankment BNK, respectively.

[0265] After the light-emitting element LD is aligned in each of the first emission regions EMA1 to the third emission regions EMA3, each of the first electrode EL1 to the fourth electrode EL4 can be used as a driving electrode for driving the light-emitting element LD.

[0266] In each of the first emission regions EMA1 to the third emission regions EMA3 of each pixel PXL, the third electrode EL3 and the fourth electrode EL4 can form a first series group SET1 together with a plurality of light-emitting elements LD connected in parallel between them, and the first electrode EL1 and the second electrode EL2 can form a second series group SET2 together with a plurality of light-emitting elements LD connected in parallel between them.

[0267] In one or more embodiments of this disclosure, the first tandem group SET1 and the second tandem group SET2 can form the light-emitting unit (EMU) of each of the first emission regions EMA1 to the third emission regions EMA3 of each pixel PXL.

[0268] The third electrode EL3 included in the first series group SET1 can be the anode electrode of the light-emitting unit EMU of each of the first sub-pixels SPXL1 to the third sub-pixels SPXL3, and the first electrode EL1 included in the second series group SET2 can be the cathode electrode of the light-emitting unit EMU.

[0269] Each of the light-emitting elements (LDs) can be an ultra-miniature light-emitting diode with a nanometer-scale to micrometer-scale size and using a material with an inorganic crystal structure. Each of the light-emitting elements (LDs) can be an ultra-miniature light-emitting diode manufactured using an etching method or a growth method.

[0270] In each of the first emission regions EMA1 to the third emission regions EMA3, at least two to dozens of light-emitting elements (LDs) may be aligned and / or arranged, but the number of light-emitting elements (LDs) is not limited thereto. According to one or more embodiments, the number of light-emitting elements (LDs) aligned and / or arranged in each of the first emission regions EMA1 to the third emission regions EMA3 may be appropriately varied.

[0271] Each of the light-emitting elements (LDs) can emit any of colored light and / or white light. Each of the LDs can be aligned on a first insulating layer INS1 between two adjacent electrodes among the first electrodes EL1 to the fourth electrodes EL4, such that the LDs are parallel to a first direction DR1 in a plan view or cross-sectional view along their extending direction (or the direction of length L). The LDs are configured to be dispersed in a solution, thereby supplying the dispersed LDs in the solution to each of the first emitting regions EMA1 to the third emitting regions EMA3 in a jet-like manner.

[0272] The light-emitting element LD can be supplied to each of the first emitting regions EMA1 to the third emitting regions EMA3 of each pixel PXL using any of the inkjet printing method, slot coating method, or various other suitable methods. For example, the light-emitting element LD can be mixed with a volatile solvent and then supplied to the pixel region PXA by inkjet printing or slot coating method. Here, when an alignment signal corresponding to each of the first electrodes EL1 to the fourth electrodes EL4 is applied for each of the first emitting regions EMA1 to the third emitting regions EMA3, an electric field can be formed between two adjacent electrodes among the first electrodes EL1 to the fourth electrodes EL4. Therefore, the light-emitting element LD can be aligned between two adjacent electrodes among the first electrodes EL1 to the fourth electrodes EL4. As described above, because the same alignment signal (or alignment voltage) is applied to each of the second electrodes EL2 and the third electrodes EL3, no light-emitting element LD can be aligned between the second electrodes EL2 and the third electrodes EL3. However, this disclosure is not limited thereto. According to one or more embodiments, when an alignment signal is applied to each of the second electrode EL2 and the third electrode EL3, the wiring resistance of the two electrodes and / or the effect of the electric field induced between adjacent electrodes may cause a potential difference between the alignment signals applied to the second electrode EL2 and the third electrode EL3. In this case, the light-emitting element LD may be aligned between the second electrode EL2 and the third electrode EL3.

[0273] After the light-emitting element LD is aligned, the solvent is removed by evaporation or by using another suitable solvent removal method, thereby the light-emitting element LD can be finally aligned and / or set in each of the first emission regions EMA1 to the third emission regions EMA3.

[0274] exist Figure 5 , Figure 7 and Figure 9 The illustration shows an example of a light-emitting element LD with its length L direction parallel to a first direction DR1, aligned between two adjacent electrodes among the first electrodes EL1 to the fourth electrodes EL4. However, this disclosure is not limited thereto. According to one or more embodiments, some of the light-emitting elements LD may be aligned between two adjacent electrodes such that the direction of their length L is parallel to a second direction DR2 and / or a direction inclined relative to the second direction DR2. According to one or more embodiments, at least one reverse light-emitting element (LD) may also be provided between two adjacent electrodes connected in opposite directions. Figure 4 (LDr in the middle).

[0275] In one or more embodiments of this disclosure, the light-emitting element LD may include a plurality of first light-emitting elements LD1 and a plurality of second light-emitting elements LD2.

[0276] The first light-emitting element LD1 can be located between the first electrode EL1 and the second electrode EL2. The second light-emitting element LD2 can be located between the third electrode EL3 and the fourth electrode EL4.

[0277] The first light-emitting element LD1 can be aligned in the same direction between the first electrode EL1 and the second electrode EL2. The first electrode EL1 and the second electrode EL2 can form a second series group SET2 together with the first light-emitting element LD1 connected in parallel with each other in the same direction between them.

[0278] The second light-emitting element LD2 can be aligned in the same direction between the third electrode EL3 and the fourth electrode EL4. The third electrode EL3 and the fourth electrode EL4 can form a first series group SET1 together with the second light-emitting element LD2 connected to each other in the same direction between them.

[0279] The first light-emitting element LD1 and the second light-emitting element LD2 mentioned above can be disposed and / or formed on the first insulating layer INS1.

[0280] The first insulating layer INS1 may comprise an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. In one or more embodiments of this disclosure, the first insulating layer INS1 may be formed of an inorganic insulating layer that is advantageous (or suitable) for protecting the light-emitting element LD from the pixel circuit layer PCL of each pixel PXL. For example, the first insulating layer INS1 may comprise a layer selected from silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y) and aluminum oxide (AlO x The first insulating layer INS1 may be formed of at least one of the inorganic materials, but this disclosure is not limited thereto. According to one or more embodiments, the first insulating layer INS1 may be formed of an organic insulating layer that is advantageous (or suitable) for planarizing the support surface of the light-emitting element LD.

[0281] The first insulating layer INS1 may include a first via VIH1 exposing a portion of the first electrode EL1 and a second via VIH2 exposing a portion of the third electrode EL3. The first insulating layer INS1 may cover the remaining portions of the first electrode EL1 except for the portion corresponding to the first via and the portion of the third electrode EL3 corresponding to the second via.

[0282] A second insulating layer INS2 may be disposed and / or formed on the light-emitting element LD. The second insulating layer INS2 partially covers the peripheral surface (e.g., the outer circumferential surface or surface) of each of the light-emitting elements LD by being disposed and / or formed on the light-emitting element LD, thereby exposing the opposite ends of each of the light-emitting elements LD to the outside.

[0283] The second insulating layer INS2 can be formed of a single layer or multiple layers, and can include an inorganic insulating layer containing at least one inorganic material or an organic insulating layer containing at least one organic material. The second insulating layer INS2 can more firmly fix each of the light-emitting elements LD. The second insulating layer INS2 can include an inorganic insulating layer that is beneficial (or suitable) for protecting the active layer 12 of each of the light-emitting elements LD from the effects of external oxygen and / or moisture, etc. However, this disclosure is not limited thereto. In one or more embodiments, depending on the design conditions of the display device in which the above-described light-emitting elements LD are used as a light source, the second insulating layer INS2 can be formed of an organic insulating layer including organic materials.

[0284] After the alignment of the light-emitting elements (LDs) in each of the first emission regions EMA1 to the third emission regions EMA3 of each pixel PXL is completed, a second insulating layer INS2 is formed on the light-emitting elements LD, thereby preventing or reducing deviations between the light-emitting elements LD and their aligned positions. If a gap (or space) exists between the first insulating layer INS1 and the light-emitting element LD before the formation of the second insulating layer INS2, the gap can be filled with the second insulating layer INS2 during the process of forming the second insulating layer INS2. Therefore, the second insulating layer INS2 can be formed of an organic insulating layer that is advantageous (or suitable) for filling the gap between the first insulating layer INS1 and the light-emitting element LD.

[0285] The first contact electrode CNE1, the second contact electrode CNE2, and the intermediate electrode CTE may be disposed on and / or formed on the first electrode EL1 to the fourth electrode EL4 of each of the first regions A1 to the third regions A3. The first contact electrode CNE1, the second contact electrode CNE2, and the intermediate electrode CTE may be a fifth conductive layer disposed on the second insulating layer INS2.

[0286] In the first region A1 to the third region A3, the first contact electrode CNE1, the second contact electrode CNE2, and the intermediate electrode CTE can be components for more stably electrobonding the first electrode EL1 to the fourth electrode EL4 to the light-emitting element LD.

[0287] The first contact electrode CNE1 may be disposed and / or formed on the first electrode EL1. The first contact electrode CNE1 can be directly connected to the first electrode EL1 through a first via VIH1. According to one or more embodiments, when a conductive capping layer is on the first electrode EL1, the first contact electrode CNE1 is on the capping layer, thereby being connected to the first electrode EL1 through the capping layer. The capping layer can enhance the adhesion between the first electrode EL1 and the passivation layer PSV located beneath the first electrode EL1, while protecting the first electrode EL1 from potential defects generated during the manufacturing process of the display device. The capping layer may include a transparent conductive material (or substance) such as indium zinc oxide (IZO).

[0288] In one or more embodiments, a first contact electrode CNE1 is disposed on and / or formed on the second end of each of the first light-emitting elements LD1 in each of the first emission regions EMA1 to the third emission regions EMA3 of each pixel PXL, thereby connecting to the second end of each of the first light-emitting elements LD1. Therefore, the second end of each of the first light-emitting elements LD1 and the first electrode EL1 can be electrically connected to each other via the first contact electrode CNE1.

[0289] The second contact electrode CNE2 may be disposed on and / or formed on the third electrode EL3. The second contact electrode CNE2 can be connected to the third electrode EL3 through the second via VIH2 in direct contact (e.g., physical contact). According to one or more embodiments, when the capping layer is on the third electrode EL3, the second contact electrode CNE2 is on the capping layer, thereby connecting to the third electrode EL3 through the capping layer.

[0290] In one or more embodiments, the second contact electrode CNE2 is disposed on and / or formed on the first end of each of the second light-emitting elements LD2 in each of the first emitting regions EMA1 to the third emitting regions EMA3, thereby connecting to the first end of each of the second light-emitting elements LD2. Therefore, the first end of each of the second light-emitting elements LD2 and the third electrode EL3 can be electrically connected to each other through the second contact electrode CNE2.

[0291] The first contact electrode CNE1 and the second contact electrode CNE2 can be formed of various suitable transparent conductive materials to ensure that light emitted from each of the light-emitting elements LD and reflected from the first electrode EL1 and the third electrode EL3 travels in the image display direction of the display device without (or substantially without) loss. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may include at least one of various suitable transparent conductive materials (or substances) (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and / or indium tin zinc oxide (ITZO), etc.) and can be formed to be substantially transparent or translucent to meet (e.g., exhibit) a predetermined (or set) transmittance. However, the materials of the first contact electrode CNE1 and the second contact electrode CNE2 are not limited to the embodiments described above. According to one or more embodiments, the first contact electrode CNE1 and the second contact electrode CNE2 may optionally be formed of various suitable opaque conductive materials (or substances). The first contact electrode CNE1 and the second contact electrode CNE2 may be formed of a single layer or multiple layers.

[0292] In the plan view, each of the first contact electrode CNE1 and the second contact electrode CNE2 may have a rod-like shape extending in the second direction DR2, but this disclosure is not limited thereto. According to one or more embodiments, the shapes of the first contact electrode CNE1 and the second contact electrode CNE2 may be appropriately modified, provided that they are stably electrically connected to each of the light-emitting elements LD. Furthermore, considering the connection relationship between the first contact electrode CNE1 and the second contact electrode CNE2 and the electrodes below them, the shapes of each of the first contact electrode CNE1 and the second contact electrode CNE2 may be appropriately modified.

[0293] The intermediate electrode CTE may include a first intermediate electrode CTE1 and a second intermediate electrode CTE2 extending in the second direction DR2.

[0294] The first intermediate electrode CTE1 can be disposed on the second electrode EL2, and can be stacked with the second electrode EL2 in a plan view. The first intermediate electrode CTE1 can be electrically insulated from the second electrode EL2 through a first insulating layer INS1 located on the second electrode EL2. The first intermediate electrode CTE1 can be electrically connected and / or physically connected to the first light-emitting element LD1 in each of the first emitting regions EMA1 to the third emitting regions EMA3 through a first end located in each of the first light-emitting elements LD1.

[0295] The second intermediate electrode CTE2 can be disposed on the fourth electrode EL4 and can be stacked with the fourth electrode EL4 in a plan view. The second intermediate electrode CTE2 can be electrically insulated from the fourth electrode EL4 through a first insulating layer INS1 located on the fourth electrode EL4. The second intermediate electrode CTE2 can be electrically connected and / or physically connected to the second light-emitting element LD2 in each of the first emission regions EMA1 to the third emission regions EMA3 through a second end located on each of the second light-emitting elements LD2.

[0296] The first intermediate electrode CTE1 and the second intermediate electrode CTE2 can be connected to each other by being configured as a single entity. The first intermediate electrode CTE1 and the second intermediate electrode CTE2 can be different parts of the intermediate electrode CTE. The first intermediate electrode CTE1 can be related to a reference... Figure 4 The second intermediate electrode CTE2 described is essentially the same component as the referenced one. Figure 4 The first intermediate electrode CTE1 described is essentially the same component. The intermediate electrode CTE can be used as a bridging electrode (or connecting electrode) for electrically bonding the second terminal of each of the second light-emitting elements LD2 in the first series group SET1 to the first terminal of each of the first light-emitting elements LD1 in the second series group SET2. For example, the intermediate electrode CTE can be a bridging electrode (or connecting electrode) for bonding the first series group SET1 to the second series group SET2.

[0297] In the plan view, the intermediate electrode CTE, including the first intermediate electrode CTE1 and the second intermediate electrode CTE2, can be arranged in a shape that surrounds at least a portion of the second contact electrode CNE2 while being spaced apart from the second contact electrode CNE2, but this disclosure is not limited thereto. According to one or more embodiments, the intermediate electrode CTE can be changed to any of a variety of suitable shapes, as long as it stably connects adjacent first series group SET1 and second series group SET2 to each other.

[0298] The first contact electrode CNE1, the second contact electrode CNE2, and the intermediate electrode CTE can be spaced apart from each other in a plan view or sectional view.

[0299] The intermediate electrode CTE can be formed of various suitable transparent conductive materials so that light emitted from each of the light-emitting elements LD and reflected from the first electrode EL1 to the fourth electrode EL4 travels without loss in the image display direction of the display device.

[0300] The intermediate electrode CTE can be formed using the same process as the first contact electrode CNE1 and the second contact electrode CNE2, but disposed on the same layer. For example, the intermediate electrode CTE, as well as the first contact electrode CNE1 and the second contact electrode CNE2, can be disposed on and / or formed on the second insulating layer INS2. However, this disclosure is not limited thereto. According to one or more embodiments, the intermediate electrode CTE can be disposed on a layer different from the layer on which the first contact electrode CNE1 and the second contact electrode CNE2 are disposed, and can be formed using a process different from the process in which the first contact electrode CNE1 and the second contact electrode CNE2 are formed.

[0301] A third insulating layer INS3 may be disposed and / or formed on the first contact electrode CNE1, the second contact electrode CNE2, and the intermediate electrode CTE. The third insulating layer INS3 may be an inorganic insulating layer comprising inorganic materials or an organic insulating layer comprising organic materials. For example, the third insulating layer INS3 may have a structure in which at least one inorganic insulating layer and at least one organic insulating layer are alternately stacked. The third insulating layer INS3 completely covers the display element layer DPL, thereby preventing or reducing the ingress of external water and / or moisture into the display element layer DPL, including the light-emitting element LD.

[0302] When the driving current flows from the first power line PL1 through the first transistor T1 of each of the first sub-pixels SPXL1 to the third sub-pixel SPXL3 to the second power line PL2, the driving current can flow into the light-emitting unit EMU of the corresponding sub-pixel through the second contact hole CNT2 of the corresponding sub-pixel.

[0303] For example, a driving current is supplied to the third electrode EL3 of the third region A3 through the second contact hole CNT2 of the first sub-pixel SPXL1, and the driving current flows to the intermediate electrode CTE via the second light-emitting element LD2 through the second contact electrode CNE2, which is in direct contact (e.g., physical contact) (or connected) with the third electrode EL3. Therefore, the second light-emitting element LD2 can emit light with a brightness corresponding to the current allocated to each of the second light-emitting elements LD2 in the first series group SET1 of the first sub-pixel SPXL1. The driving current flowing in the intermediate electrode CTE flows to the first contact electrode CNE1 via the intermediate electrode CTE and the first light-emitting element LD1. Therefore, the first light-emitting element LD1 can emit light with a brightness corresponding to the current allocated to each of the first light-emitting elements LD1 in the second series group SET2 of the first sub-pixel SPXL1.

[0304] In one or more embodiments, a driving current is supplied to the third electrode EL3 of the first region A1 through the second contact hole CNT2 of the second sub-pixel SPXL2, and the driving current flows to the intermediate electrode CTE via the second light-emitting element LD2 through the second contact electrode CNE2 connected to the third electrode EL3. Therefore, the second light-emitting element LD2 can emit light with a brightness corresponding to the current allocated to each of the second light-emitting elements LD2 in the first series group SET1 of the second sub-pixel SPXL2. The driving current flowing in the intermediate electrode CTE flows to the first contact electrode CNE1 via the intermediate electrode CTE and the first light-emitting element LD1. Therefore, the first light-emitting element LD1 can emit light with a brightness corresponding to the current allocated to each of the first light-emitting elements LD1 in the second series group SET2 of the second sub-pixel SPXL2.

[0305] In one or more embodiments, a driving current is supplied to the third electrode EL3 of the second region A2 through the second contact hole CNT2 of the third sub-pixel SPXL3, and the driving current flows to the intermediate electrode CTE via the second light-emitting element LD2 through the second contact electrode CNE2 connected to the third electrode EL3. Therefore, the second light-emitting element LD2 can emit light with a brightness corresponding to the current allocated to each of the second light-emitting elements LD2 in the first series group SET1 of the third sub-pixel SPXL3. The driving current flowing in the intermediate electrode CTE flows to the first contact electrode CNE1 via the intermediate electrode CTE and the first light-emitting element LD1. Therefore, the first light-emitting element LD1 can emit light with a brightness corresponding to the current allocated to each of the first light-emitting elements LD1 in the second series group SET2 of the third sub-pixel SPXL3.

[0306] According to the method described above, the driving current of each of the first sub-pixels SPXL1 to the third sub-pixels SPXL3 can flow sequentially through the second light-emitting element LD2 of the first series group SET1 and the first light-emitting element LD1 of the second series group SET2. Therefore, each pixel PXL can emit light with a brightness corresponding to the data signal supplied during each frame period.

[0307] Above each pixel PXL, a light-blocking pattern LBP and a color filter CF can be positioned.

[0308] The light-blocking pattern LBP can be configured to correspond to the embankment BNK, while surrounding the light-emitting element LD within the non-emitting region NEMA, which is the outer periphery of the first emitting region EMA1 to the third emitting region EMA3. The light-blocking pattern LBP can be a black matrix pattern. The light-blocking pattern LBP can be a reference. Figure 5 The light-blocking pattern LBP is described.

[0309] In one or more embodiments of this disclosure, such as Figure 8 As shown, the light blocking pattern LBP may include a first opening OPN1 corresponding to the first emission region EMA1, a second opening OPN2 corresponding to the second emission region EMA2, and a third opening OPN3 corresponding to the third emission region EMA3.

[0310] The widths W1 of the first opening OPN1, W2 of the second opening OPN2, and W3 of the third opening OPN3 in the first direction DR1 may be the same, but this disclosure is not limited thereto. According to one or more embodiments, the widths W1 of the first opening OPN1, W2 of the second opening OPN2, and W3 of the third opening OPN3 in the first direction DR1 may be different from each other. According to one or more embodiments, among the widths W1 of the first opening OPN1, W2 of the second opening OPN2, and W3 of the third opening OPN3 in the first direction DR1, at least one opening may have a width in the first direction DR1 that is different from, or vice versa, the widths of the two remaining openings in the first direction DR1.

[0311] The length h1 of the first opening OPN1 in the second direction DR2 (hereinafter referred to as the "first length"), the length h2 of the second opening OPN2 in the second direction DR2 (hereinafter referred to as the "second length"), and the length h3 of the third opening OPN3 in the second direction DR2 (hereinafter referred to as the "third length") can be different from each other (see example). Figure 8For example, the first length h1 of the first opening OPN1 can be longer than the second length h2 of the second opening OPN2 and the third length h3 of the third opening OPN3. The second length h2 of the second opening OPN2 can be shorter than the first length h1 of the first opening OPN1 and longer than the third length h3 of the third opening OPN3. The third length h3 of the third opening OPN3 can be shorter than the length of each of the first opening OPN1 and the second opening OPN2. That is, the first length h1 of the first opening OPN1 can be the longest, while the third length h3 of the third opening OPN3 can be the shortest.

[0312] As described above, because the first opening OPN1 to the third opening OPN3 are formed such that their lengths in the second direction DR2 are different from each other, the first opening OPN1 to the third opening OPN3 can have different dimensions. For example, the first opening OPN1 can have the largest dimension, while the third opening OPN3 can have the smallest dimension. However, this disclosure is not limited thereto, and according to one or more embodiments, the dimensions of each of the first opening OPN1 to the third opening OPN3 can be adjusted according to the component located below each of the first opening OPN1 to the third opening OPN3.

[0313] The color filter CF may include a first color filter pattern CF1, a second color filter pattern CF2, and a third color filter pattern CF3.

[0314] The first color filter pattern CF1 may correspond to the first opening OPN1 of the light blocking pattern LBP and may be located above the display element layer DPL exposed by the first opening OPN1 in the first emission region EMA1.

[0315] The second color filter pattern CF2 may correspond to the second opening OPN2 of the light blocking pattern LBP, and may be located above the display element layer DPL exposed by the second opening OPN2 in the second emission region EMA2.

[0316] The third color filter pattern CF3 can correspond to the third opening OPN3 of the light blocking pattern LBP, and can be located above the display element layer DPL exposed by the third opening OPN3 in the third emission region EMA3.

[0317] In one or more embodiments of this disclosure, the first color filter pattern CF1 may be a red color filter to selectively transmit light of a predetermined (or set) color (e.g., red light), the second color filter pattern CF2 may be a green color filter to selectively transmit light of a predetermined (or set) color (e.g., green light), and the third color filter pattern CF3 may be a blue color filter to selectively transmit light of a predetermined (or set) color (e.g., blue light).

[0318] According to one or more embodiments, a color filter CF can be disposed on a color conversion layer comprising color conversion particles for changing the color of light emitted from the light-emitting element LD to a predetermined (or set) color. Reference will be made below. Figures 13 to 17 A more detailed description of the color conversion layer.

[0319] As described above, when the second sub-pixel SPXL2 is a red pixel, the first sub-pixel SPXL1 is a blue pixel, and the third sub-pixel SPXL3 is a green pixel, the first color filter pattern CF1, which is a red color filter, can be positioned to correspond to the first opening OPN1, the second color filter pattern CF2, which is a green color filter, can be positioned to correspond to the second opening OPN2, and the third color filter pattern CF3, which is a blue color filter, can be positioned to correspond to the third opening OPN3.

[0320] In the relevant display device, when the light-emitting element (LD) emits blue light, and this blue light passes through a red color filter, the blue light mixes in the red domain because the red color filter absorbs blue light in the short wavelength region, resulting in color mixing. Due to this color mixing, the area of ​​pure red light that ultimately passes through the red color filter may become narrower. Therefore, the red color filter is designed to have a relatively larger size than the green and blue color filters, so that the amount (or intensity) of light from the red color filter can become equal to the amount (or intensity) of light from each of the green and blue color filters. In this case, the first color filter pattern CF1, which is the red color filter, can be positioned to correspond to the first opening OPN1 of the light-blocking pattern LBP, which has a relatively large size.

[0321] As described above, the first color filter pattern CF1 can be disposed in the first region A1 of each pixel PXL so as to correspond to the first opening OPN1 of the light-blocking pattern LBP, which has a relatively large size. The third color filter pattern CF3 can be disposed in the third region A3 of each pixel PXL so as to correspond to the third opening OPN3 of the light-blocking pattern LBP, which has a relatively small size. The second color filter pattern CF2 can be disposed in the second region A2 of each pixel PXL so as to correspond to the second opening OPN2 of the light-blocking pattern LBP.

[0322] In one or more embodiments, the storage capacitors of the first sub-pixels SPXL1 to the third sub-pixels SPXL3 may be centrally located (e.g., collectively) in the first region A1 of each pixel PXL. For example, the first storage capacitor Cst1 of the first sub-pixel SPXL1, the second storage capacitor Cst2 of the second sub-pixel SPXL2, and the third storage capacitor Cst3 of the third sub-pixel SPXL3 may be located in the first region A1. As described above, the first storage capacitor Cst1 may be electrically connected to the third electrode EL3 located in the third region A3 of each pixel PXL, the second storage capacitor Cst2 may be electrically connected to the third electrode EL3 located in the first region A1 of the corresponding pixel PXL, and the third storage capacitor Cst3 may be electrically connected to the third electrode EL3 located in the second region A2 of the corresponding pixel PXL.

[0323] In this configuration, when the light-emitting element LD is aligned in each of the first regions A1 to the third regions A3 of each pixel PXL, a predetermined (or set) alignment signal (or alignment voltage) can be applied to the first storage capacitors Cst1 to the third storage capacitors Cst3 in the first region A1. When the predetermined (or set) alignment signal is applied to the first storage capacitors Cst1 to the third storage capacitors Cst3, an electric field can be formed between the first storage capacitors Cst1 to the third storage capacitors Cst3 in the first region A1 and the first electrodes EL1 to the fourth electrodes EL4. Here, when the light-emitting element LD is supplied to (or placed in) each of the first regions A1 to the third regions A3 using an inkjet printing method or the like, at least some of the light-emitting elements LD may be aligned in areas where they are not targeted (e.g., undesirable areas) due to deviation from the target area (e.g., the area where they are concentratedly aligned). For example, at least some of the light-emitting elements (LDs) may be located in the upper part of the first emission region EMA1 adjacent to the embankment BNK (e.g., in the upper part of the first storage capacitor Cst1) and / or in the lower part of it (e.g., in the lower part of the third storage capacitor Cst3).

[0324] A relatively large first opening OPN1 of the light-blocking pattern LBP can be located above the aforementioned first region A1, and a first color filter pattern CF1, serving as a red color filter, can correspond to the first opening OPN1. Here, the first color filter pattern CF1 can have a size sufficient to cover the first storage capacitors Cst1 to Cst3 located in the first region A1. Because the relatively large first color filter pattern CF1 is located above the first region A1, at least some light-emitting elements LDs aligned in undesirable areas of the first region A1 can be covered by the first color filter pattern CF1. Therefore, at least some light-emitting elements LDs are electrically connected to the first electrode EL1 to the fourth electrode EL4, thereby serving as an effective (e.g., forward-biased) light source. Therefore, even though at least some of the light-emitting elements (LDs) are aligned in undesirable areas due to deviation from the target area because the first storage capacitors Cst1 to the third storage capacitors Cst3 are concentrated in the first region A1, the corresponding light-emitting elements (LDs) can also be used as effective (e.g., forward-biased) light sources because the relatively large first color filter pattern CF1 corresponds to the relatively large first opening OPN1 of the light-blocking pattern LBP above the first region A1. Thus, the loss of the light-emitting elements (LDs) is minimized or reduced, and some LDs that are off-aligned are used as effective (e.g., forward-biased) light sources. Therefore, the number of effective (e.g., forward-biased) light sources provided for each unit region in the first region A1 is increased, thereby improving light output efficiency.

[0325] If the third color filter pattern CF3, which is the blue color filter with the smallest size, is above the first region A1, some light-emitting elements (LDs) that are off-aligned in the first region A1 will be covered by the light-blocking pattern LBP. In this case, the corresponding light-emitting elements (LDs) become ineffective (e.g., reverse-biased) light sources, and the number of effective (e.g., forward-biased) light sources provided for each unit area of ​​the first region A1 is reduced. Therefore, this results in the loss of light-emitting elements (LDs).

[0326] Therefore, in this disclosure, a first color filter pattern CF1 with a relatively large red color filter is placed above the first region A1 to increase the number of effective (e.g., forward biased) light sources in the first region A1, thereby minimizing or reducing the loss of the light-emitting element LD.

[0327] Figure 13 and Figure 14 It is along Figure 5 A schematic cross-sectional view taken from line I-I'. Figure 15 It is along Figure 5 A schematic cross-sectional view taken from line II-II'. Figure 16 It is along Figure 5A schematic cross-sectional view taken from line III-III'. Figure 17 It is along Figure 5 A schematic cross-sectional view taken from line IV-IV'.

[0328] For reference only. Figures 13 to 17 An embodiment of a display device including color conversion particles is shown. For example, the display device according to this disclosure may optionally include color conversion particles above each pixel PXL.

[0329] exist Figures 13 to 17 The focus is on the settings including Figure 5 The pixel region PXA of the individual pixel PXL of the first sub-pixel SPXL1 to the third sub-pixel SPXL3 shown in the figure briefly illustrates a cross-section of the display device.

[0330] about Figures 13 to 17 The display device described herein will focus on points that differ from those in the above embodiments to avoid repetition. Parts not specifically described in one or more embodiments of this disclosure follow the above embodiments. Furthermore, the same reference numerals denote the same components, and similar reference numerals denote similar components.

[0331] Reference Figures 1 to 17 A display device according to one or more embodiments of the present disclosure may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB, and an upper substrate U_SUB located above each of the pixels PXL.

[0332] Each of the pixels PXL includes a first sub-pixel SPXL1 to a third sub-pixel SPXL3, and can be divided into a first sub-pixel region SPXA1 to a third sub-pixel region SPXA3 based on the area where the pixel circuit PXC corresponding to the sub-pixel is located. In one or more embodiments, the pixel PXL can be divided into a first region A1 to a third region A3 based on the area where the light-emitting element LD is located.

[0333] The upper substrate U_SUB can be on each pixel PXL to cover the display area DA in which the pixels PXL are disposed. The upper substrate U_SUB can form an encapsulation substrate (or thin film encapsulation layer) and / or a window member. An intermediate layer CTL can be disposed between the upper substrate U_SUB and each of the pixels PXL. The intermediate layer CTL can be a transparent adhesive layer (or bonding layer) (e.g., an optically transparent adhesive layer) for enhancing the adhesion between each of the pixels PXL and the upper substrate U_SUB, but this disclosure is not limited thereto. According to one or more embodiments, the intermediate layer CTL can be an air layer. Furthermore, according to one or more embodiments, the intermediate layer CTL can be formed of a predetermined (or set) filler having a relatively low refractive index so that light emitted from the light-emitting element LD can travel upward relative to the pixel PXL in the upward direction (e.g., the image display direction of the display device) without loss.

[0334] The upper substrate U_SUB may include a substrate layer BSL and an optical conversion patterning layer LCP.

[0335] The substrate layer (BSL) can be a rigid or flexible substrate, and its material or properties are not limited to specific materials or properties. The BSL can be composed of a reference... Figures 6 to 12 The substrate described is formed of the same material as the reference substrate, or is made of the same material as the reference substrate. Figures 6 to 12 The substrate SUB is made of different materials.

[0336] The light conversion pattern layer (LCP) can be located on one surface of the base layer (BSL) so as to face each of the pixels (PXL). The light conversion pattern layer (LCP) may include a color conversion layer and a color filter pattern corresponding to a predetermined (or set) color.

[0337] The light conversion pattern layer LCP may include a first light conversion pattern layer LCP1 facing a first region A1 facing each of the pixels PXL, a second light conversion pattern layer LCP2 facing a second region A2 facing the pixels PXL, and a third light conversion pattern layer LCP3 facing a third region A3 facing the pixels PXL.

[0338] According to one or more embodiments, at least some of the first light conversion pattern layers LCP1 to the third light conversion pattern layer LCP3 may include a color conversion layer and / or a color filter pattern corresponding to a predetermined (or set) color. For example, the first light conversion pattern layer LCP1 may include a first color conversion layer CCL1 and a first color filter pattern CF1, wherein the first color conversion layer CCL1 includes first color conversion particles QD1 corresponding to a first color, and the first color filter pattern CF1 selectively transmits light of the first color. The second light conversion pattern layer LCP2 may include a second color conversion layer CCL2 and a second color filter pattern CF2, wherein the second color conversion layer CCL2 includes second color conversion particles QD2 corresponding to a second color, and the second color filter pattern CF2 selectively transmits light of the second color. The third light conversion pattern layer LCP3 may include a third color conversion layer CCL3 and a third color filter pattern CF3, wherein the third color conversion layer CCL3 includes third color conversion particles QD3 corresponding to a third color, and the third color filter pattern CF3 selectively transmits light of the third color. According to one or more embodiments, the third light conversion patterning layer LCP3 may include a light scattering layer LSL instead of the third color conversion layer CCL3, the light scattering layer LSL including light scattering particles SCT. For example, when the light-emitting element LD emits blue light, the third light conversion patterning layer LCP3 may include a light scattering layer LSL containing light scattering particles SCT.

[0339] The light-emitting elements (LDs) aligned in the emission region of each of the first sub-pixels SPXL1 to the third sub-pixels SPXL3 can emit light of the same color. In one or more embodiments, a color conversion layer may be located above at least some of the first sub-pixels SPXL1 to the third sub-pixels SPXL3. Therefore, the above-described display device can display full-color images.

[0340] The first color conversion layer CCL1 can be located on one surface of the substrate layer BSL, facing the display element layer DPL including the light-emitting element LD of the first region A1, and can include first color conversion particles QD1 configured to convert light emitted from the light-emitting element LD into light of a first color. Here, because the light-emitting element LD of the first region A1 emits light through the pixel circuit PXC electrically connected to the second sub-pixel SPXL2, when the second sub-pixel SPXL2 is a red pixel, the first color conversion particles QD1 of the first color conversion layer CCL1 facing the first region A1 can be red quantum dots.

[0341] The first color filter pattern CF1 can be on the first color conversion layer CCL1. The first color filter pattern CF1 can be a reference. Figures 5 to 12 The first color filter pattern CF1 is described. For example, the first color filter pattern CF1 could be a red color filter.

[0342] The second color conversion layer CCL2 can be located on one surface of the substrate layer BSL, facing the display element layer DPL including the light-emitting element LD of the second region A2, and can include second color conversion particles QD2 configured to convert the light emitted from the light-emitting element LD into light of a second color. Here, because the light-emitting element LD of the second region A2 emits light through the pixel circuit PXC electrically connected to the third sub-pixel SPXL3, when the third sub-pixel SPXL3 is a green pixel, the second color conversion particles QD2 of the second color conversion layer CCL2 facing the second region A2 can be green quantum dots.

[0343] The second color filter pattern CF2 can be on the second color conversion layer CCL2. The second color filter pattern CF2 can be a reference. Figures 5 to 12 The second color filter pattern CF2 is described. For example, the second color filter pattern CF2 could be a green color filter.

[0344] The third color conversion layer CCL3 can be located on one surface of the substrate layer BSL, facing the display element layer DPL including the light-emitting element LD of the third region A3, and can include third color conversion particles QD3 configured to convert light emitted from the light-emitting element LD into light of a third color. Here, since the light-emitting element LD of the third region A3 emits light through the pixel circuit PXC electrically connected to the first sub-pixel SPXL1, when the first sub-pixel SPXL1 is a blue pixel, the third color conversion particles QD3 of the third color conversion layer CCL3 facing the third region A3 can be blue quantum dots. According to one or more embodiments, when the light-emitting element LD of the third region A3 emits blue light, a light scattering layer LSL including light scattering particles SCT can be located on one surface of the substrate layer BSL, facing the display element layer DPL including the light-emitting element LD.

[0345] The third color filter pattern CF3 can be on the third color conversion layer CCL3 or the light scattering layer LSL. The third color filter pattern CF3 can be a reference. Figures 5 to 12 The third color filter pattern CF3 is described. For example, the third color filter pattern CF3 could be a blue color filter.

[0346] A light-blocking pattern LBP can be positioned between each of the first color filter patterns CF1 to the third color filter pattern CF3 and its adjacent color filter pattern. The light-blocking pattern LBP can be positioned above each pixel PXL to cover the area excluding the corresponding pixel PXL's first emission region EMA1 to third emission region EMA3. The light-blocking pattern LBP can be a reference... Figures 5 to 12 The light-blocking pattern LBP is described.

[0347] A light-blocking pattern LBP can be disposed on one surface of the substrate layer BSL to face the embankment BNK located in the non-emissive region NEMA of each pixel PXL, and can be superimposed on the edges of each of the first color filter patterns CF1 to the third color filter patterns CF3. The light-blocking pattern LBP can include at least one black matrix material (e.g., at least one suitable light-blocking material) and / or a color filter material having a specific (or defined) color. In one or more embodiments, the light-blocking pattern LBP can be formed of the same material as the embankment BNK, but is not limited thereto. For example, the light-blocking pattern LBP and the embankment BNK can include the same material or different materials. According to one or more embodiments, a sub-light-blocking pattern S_LBP can be disposed on the light-blocking pattern LBP. The sub-light-blocking pattern S_LBP can include the same material as the light-blocking pattern LBP. The sub-light-blocking pattern S_LBP can be disposed on one surface of the light-blocking pattern LBP to be located between adjacent color conversion layers CCL.

[0348] The light-blocking pattern LBP can be open in the region corresponding to the emission region of each of the first regions A1 to the third regions A3. For example, the light-blocking pattern LBP may include a first opening OPN1 open in the region corresponding to the first emission region EMA1 of the first region A1, a second opening OPN2 open in the region corresponding to the second emission region EMA2 of the second region A2, and a third opening OPN3 open in the region corresponding to the third emission region EMA3 of the third region A3. The first opening OPN1 may be formed to have a relatively larger size than the second opening OPN2 and the third opening OPN3.

[0349] The first color filter pattern CF1 can correspond to the first opening OPN1, the second color filter pattern CF2 can correspond to the second opening OPN2, and the third color filter pattern CF3 can correspond to the third opening OPN3. Because the first color filter pattern CF1 is positioned to correspond to the first opening OPN1, which has a relatively large size, the first color filter pattern CF1 can have a relatively larger size than the second color filter pattern CF2 and the third color filter pattern CF3.

[0350] The first emission region EMA1, in which light is emitted in the first region A1, can be ultimately set (e.g., specified) based on the first color filter pattern CF1 and the light blocking pattern LBP located near the first color filter pattern CF1. Here, the first emission region EMA1 can be the emission region of the second sub-pixel SPXL2.

[0351] The second emission region EMA2, in which light is emitted in the second region A2, can be finally set (e.g., specified) based on the second color filter pattern CF2 and the light blocking pattern LBP located near the second color filter pattern CF2. Here, the second emission region EMA2 can be the emission region of the third sub-pixel SPXL3.

[0352] The third emission region EMA3, in which light is emitted in the third region A3, can be finally set (e.g., specified) based on the third color filter pattern CF3 and the light blocking pattern LBP located near the third color filter pattern CF3. Here, the third emission region EMA3 can be the emission region of the first sub-pixel SPXL1.

[0353] As described above, because the first color filter pattern CF1 is formed to have a relatively larger size than the second color filter pattern CF2 and the third color filter pattern CF3, the area (or size) of the first emission region EMA1 can be larger than the area (or size) of each of the second emission regions EMA2 and the third emission region EMA3. Even when at least some of the light-emitting elements LD are misaligned in an undesirable area due to some components (e.g., storage capacitors) of the pixel circuit PXC of each of the first sub-pixels SPXL1 to the third sub-pixels SPXL3 in the first region A1, the first color filter pattern CF1 covers the corresponding light-emitting element LD, so that the corresponding light-emitting element LD can still be used as an effective (e.g., forward biased) light source. Therefore, in the above embodiment, the number of effective (e.g., forward biased) light sources is increased, while the loss of the light-emitting elements LD in the first region A1 is minimized or reduced, thereby improving the light output efficiency.

[0354] Although in the above embodiments the upper substrate U_SUB, comprising the substrate layer BSL, the light-blocking pattern LBP, and the light-converting pattern layer LCP, is described as being disposed above each pixel PXL, this disclosure is not limited thereto. According to one or more embodiments, such as Figure 14As shown, the light conversion pattern layer LCP, including the first light conversion pattern layer LCP1, and the light blocking pattern LBP can be formed on a substrate SUB on which each pixel PXL is disposed. For example, in order to cover the light-emitting element LD located in each of the first regions A1 to the third regions A3 of each pixel PXL, the light blocking pattern LBP and the light conversion pattern layer LCP can be alternately formed on the substrate SUB on which the pixel PXL is disposed. Here, the intermediate layer CTL can be between the first color conversion layer CCL1 and the first color filter pattern CF1. The intermediate layer CTL can be at least one insulating layer. In this case, the second dam BNK2 can be disposed in the non-emitting region NEMA of the pixel PXL. The second dam BNK2 is disposed on the first dam BNK1 located on the first insulating layer INS1 of the display element layer DPL of the pixel PXL, thereby forming a dam structure together with the first dam BNK1. In the cross-sectional view, the second dam BNK2 can be superimposed on the first dam BNK1. Here, the first dam BNK1 can be a reference Figures 5 to 12 The described embankment BNK. Furthermore, in this case, an encapsulation layer ENC can be set on the light-blocking pattern LBP and the light-converting pattern layer LCP.

[0355] A display device according to one or more embodiments of the present disclosure may include a first to a third emission region separated along a first direction, a first to a third capacitor corresponding to one of the first to third emission regions, and a color filter pattern disposed in the respective first to third emission regions. By providing a red color filter of a relatively large size in the emission region in which the first to third capacitors are centrally disposed, the number of light-emitting elements covered by the light-blocking pattern is minimized (or reduced), thereby increasing the number of light-emitting elements that can be used as an effective (e.g., forward-biased) light source and improving the light output efficiency of the display device.

[0356] The effects of one or more embodiments of this disclosure are not limited to the above embodiments, and various effects are included in this disclosure.

[0357] Although exemplary embodiments of this disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure as disclosed in the appended claims and their equivalents.

[0358] Therefore, the technical scope of this disclosure should be defined by the technical spirit of the claims and their equivalents, rather than by the detailed description.

Claims

1. A display device, the display device comprising: Base; At least one pixel is divided on the substrate along a first direction, the at least one pixel including a first emission region, a second emission region and a third emission region, each of the first emission region, the second emission region and the third emission region including a plurality of light-emitting elements; The light-blocking pattern corresponds to the area between the first emission region, the second emission region, and the third emission region; as well as The color filter layer includes a first color filter pattern in the first emission region, a second color filter pattern in the second emission region, and a third color filter pattern in the third emission region, wherein the size of the first color filter pattern is larger than the size of the second color filter pattern and the size of the third color filter pattern. The at least one pixel includes a first storage capacitor, a second storage capacitor, and a third storage capacitor on the substrate, wherein the first storage capacitor, the second storage capacitor, and the third storage capacitor are superimposed on the first color filter pattern.

2. The display device according to claim 1, wherein: The first color filter pattern is a red color filter. The second color filter pattern is a green color filter, and The third color filter pattern is a blue color filter.

3. The display device according to claim 2, further comprising: A buffer layer is placed on the substrate. as well as The first insulating layer, the second insulating layer, and the third insulating layer are sequentially arranged on the buffer layer. Each of the first storage capacitor, the second storage capacitor, and the third storage capacitor includes a lower electrode and an upper electrode, the lower electrode being on the first insulating layer, and the upper electrode being on the second insulating layer and stacked with the lower electrode.

4. The display device according to claim 3, wherein, The at least one pixel includes: The first sub-pixel includes the first storage capacitor and at least one transistor electrically connected to the first storage capacitor; The second sub-pixel includes the second storage capacitor and at least one transistor electrically connected to the second storage capacitor; and The third sub-pixel includes the third storage capacitor and at least one transistor electrically connected to the third storage capacitor.

5. The display device according to claim 4, wherein, The pixel region including the at least one pixel is divided along a second direction different from the first direction into a first sub-pixel region including the first sub-pixel, a second sub-pixel region including the second sub-pixel, and a third sub-pixel region including the third sub-pixel.

6. The display device according to claim 5, wherein: The first storage capacitor corresponds to the first sub-pixel region. The second storage capacitor corresponds to the second sub-pixel region, and The third storage capacitor corresponds to the third sub-pixel region.

7. The display device according to claim 6, wherein: The at least one pixel also includes: A first data line, a second data line, a third data line, and a first-1 power line extend on the substrate in the second direction and correspond to the second color filter pattern; and The second-first electric field line and the initial electric field line extend on the substrate in the second direction and correspond to the third color filter pattern, and The first data line, the second data line, the third data line, the first-1 power line, the second-1 power line, and the initialization power line are on the buffer layer.

8. The display device according to claim 7, wherein: The at least one pixel further includes: a bottom metal layer, stacked with each of the first storage capacitor, the second storage capacitor, and the third storage capacitor, and The bottom metal layer is on the same layer as the first data line, the second data line, the third data line, the first-1 power line, the second-1 power line, and the initialization power line.

9. The display device according to claim 8, wherein: The at least one pixel further includes: a first-second electric field line and a second-second electric field line, extending in the first direction and spaced apart from each other on the second insulating layer, and The first-2 power line is electrically connected to the first-1 power line, and the second-2 power line is electrically connected to the second-1 power line.

10. The display device according to claim 9, wherein: The at least one pixel further includes: a first electrode, a second electrode, a third electrode, and a fourth electrode, on the third insulating layer, and corresponding to each of the first emitting region, the second emitting region, and the third emitting region. The first electrode, the second electrode, the third electrode, and the fourth electrode are spaced apart from each other in the first direction.

11. The display device according to claim 10, wherein: In each of the first, second, and third transmission regions, the first electrode is electrically connected to the second-2nd power line. In the first emission region, the third electrode is electrically connected to the second storage capacitor. In the second emission region, the third electrode is electrically connected to the third storage capacitor, and In the third emission region, the third electrode is electrically connected to the first storage capacitor.

12. The display device according to claim 11, wherein, The plurality of light-emitting elements include: A plurality of first light-emitting elements are located between the first electrode and the second electrode, and are electrically connected to the first electrode and the second electrode; and A plurality of second light-emitting elements are located between the third electrode and the fourth electrode, and are electrically connected to the third electrode and the fourth electrode.

13. The display device according to claim 12, wherein, The at least one pixel also includes: A first contact electrode is provided on the first electrode such that the first electrode is electrically connected to a first end of each of the plurality of first light-emitting elements; Intermediate electrodes, on corresponding second and fourth electrodes, are provided to electrically connect the second end of each of the plurality of first light-emitting elements to the first end of each of the plurality of second light-emitting elements; and A second contact electrode is placed on the third electrode to electrically connect the third electrode to a second end of each of the plurality of second light-emitting elements.

14. The display device according to claim 13, wherein: The first contact electrode, the intermediate electrode, and the second contact electrode are spaced apart from each other.

15. The display device according to claim 13, wherein: The plurality of second light-emitting elements are connected in parallel between the third electrode and the fourth electrode to form a first series group. The plurality of first light-emitting elements are connected in parallel between the first electrode and the second electrode to form a second series group, and The third electrode is an anode electrode, and the first electrode is a cathode electrode.

16. The display device according to claim 13, wherein: The at least one pixel also includes a dike, the dike comprising: A first opening corresponds to each of the first, second, and third emission regions; and The second and third openings are spaced apart from the first opening, and The light-blocking pattern is on the embankment.

17. The display device according to claim 16, wherein: The first opening of the dike corresponding to the first launch area, the first opening of the dike corresponding to the second launch area, and the first opening of the dike corresponding to the third launch area have the same size.

18. The display device according to claim 17, wherein: The light-blocking pattern includes a first opening, a second opening, and a third opening. The first opening corresponds to the first color filter pattern, the second opening corresponds to the second color filter pattern, and the third opening corresponds to the third color filter pattern. The size of the first opening is different from the size of the second opening and the size of the third opening.

19. The display device according to claim 18, wherein: The size of the first opening is larger than the size of each of the second and third openings.

20. The display device according to claim 19, further comprising: A color conversion layer is placed between the at least one pixel and the color filter layer. The color conversion layer includes: A first color conversion layer, corresponding to the first color filter pattern, converts the light emitted from the plurality of light-emitting elements into light of a first color; A second color conversion layer, corresponding to the second color filter pattern, converts light emitted from the plurality of light-emitting elements into light of a second color; and A third color conversion layer, corresponding to the third color filter pattern, converts light emitted from the plurality of light-emitting elements into light of a third color, or transmits the emitted light without changing its color.

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