Storage device, flash memory controller and access method thereof

Abstract

The present invention relates to a storage device, a flash memory controller and an access method thereof. The present invention discloses a control method for a flash memory controller, which comprises the following steps: establishing a write time record table, wherein the write time record table records the block number of the block with data written in the flash memory module and the corresponding first time and second time; referring to the write time record table to determine whether there is at least one first block in the flash memory module with a first time earlier than a first threshold value, and if so, recording at least one first block in an expired block table; referring to the write time record table to determine whether there is at least one second block in the flash memory module with a second time earlier than a second threshold value, and if so, recording at least one second block in the expired block table; and performing expired block recovery operations according to the expired block table.

Description

Technical Field

[0001] The invention relates to a flash memory controller and a related control method. Background Art

[0002] With the development of three-dimensional flash memory technology, the number of stacked layers in flash memory chips is increasing. In addition, the current flash memory modules contain many blocks using triple-level cell (TLC) or quad-level cell (QLC). Therefore, the quality of data stored in the flash memory is getting worse and worse. Even a few weeks after the data is written, the quality will drop rapidly, causing difficulties in subsequent decoding or even being unable to read. In order to solve this problem, the flash memory controller can use idle time to read part of the content of each block in the flash memory module to determine the quality of each block. However, the above method will consume a lot of time, and if the flash memory controller is often in a busy state, it will not be able to take into account both access efficiency and block quality. Summary of the invention

[0003] Therefore, one of the objectives of the present invention is to provide a flash memory controller and a related control method, which can effectively pre-process blocks with quality problems in a flash memory module to solve the problems described in the prior art.

[0004] In one embodiment of the present invention, a control method applied to a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of blocks, and each block includes a plurality of data pages, and the control method includes: when data is written to a first data page of any block of the flash memory module, a first time is recorded in the first data page; when data is written to at least one intermediate data page of any block of the flash memory module, a second time is recorded in the at least one intermediate data page; when data is written to a last data page of any block of the flash memory module, the first time and the second time are recorded in the last data page; a write time record table is established, wherein the write time record table records the block number of the block in the flash memory module to which data is written and the corresponding first time, or records the flash The method comprises the steps of: determining the block numbers of the blocks in the memory module to which data is written and the corresponding first time and second time; referring to the write time record table to determine whether the first time of a block in the flash memory module is earlier than a first threshold value, and if the first time of at least one first block in the flash memory module is earlier than the first threshold value, recording the at least one first block in an expired block table; referring to the write time record table to determine whether the second time of a block in the flash memory module is earlier than a second threshold value, and if the second time of at least one second block in the flash memory module is earlier than the second threshold value, recording the at least one second block in the expired block table; and performing an expired block recovery operation according to the at least one first block and the at least one second block recorded in the expired block table, so as to sequentially move the valid data in the at least one first block and the at least one second block to at least one blank block.

[0005] In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes a read-only memory, a microprocessor, and a buffer memory. When the microprocessor writes data to a first data page of any block of the flash memory module, a first time is recorded in the first data page; when the microprocessor writes data to at least one intermediate data page of any block of the flash memory module, a second time is recorded in the at least one intermediate data page; when the microprocessor writes data to a last data page of any block of the flash memory module, the first time and the second time are recorded in the last data page; the microprocessor also establishes a write time record table, wherein the write time record table records the block number of the block with data written in the flash memory module and the corresponding first time, or records the block number of the block with data written in the flash memory module and the corresponding first time and the second time. In addition, the microprocessor refers to the write time record table to determine whether there is a block in the flash memory module whose first time is earlier than a first threshold value, and if the first time of at least one first block in the flash memory module is earlier than the first threshold value, the at least one first block is recorded in an expired block table; the microprocessor refers to the write time record table to determine whether there is a block in the flash memory module whose second time is earlier than a second threshold value, and if the second time of at least one second block in the flash memory module is earlier than the second threshold value, the at least one second block is recorded in the expired block table; and an expired block recovery operation is performed according to the at least one first block and the at least one second block recorded in the expired block table, so as to sequentially move valid data in the at least one first block and the at least one second block to at least one blank block.

[0006] In another embodiment of the present invention, a storage device is disclosed, which includes a flash memory module and a flash memory controller. When the flash memory controller writes data to a first data page of any block of the flash memory module, a first time is recorded in the first data page; when the flash memory controller writes data to at least one intermediate data page of any block of the flash memory module, a second time is recorded in the at least one intermediate data page; when the flash memory controller writes data to a last data page of any block of the flash memory module, the first time and the second time are recorded in the last data page; the flash memory controller also establishes a write time record table, wherein the write time record table records the block number of the block with data written in the flash memory module and the corresponding first time, or records the block number of the block with data written in the flash memory module and the corresponding first time and the second time; in addition, the flash memory controller The memory controller refers to the write time record table to determine whether there is a block in the flash memory module whose first time is earlier than a first threshold value, and if the first time of at least one first block in the flash memory module is earlier than the first threshold value, the at least one first block is recorded in an expired block table; the flash memory controller refers to the write time record table to determine whether there is a block in the flash memory module whose second time is earlier than a second threshold value, and if the second time of at least one second block in the flash memory module is earlier than the second threshold value, the at least one second block is recorded in the expired block table; and an expired block recovery operation is performed according to the at least one first block and the at least one second block recorded in the expired block table, so as to sequentially move valid data in the at least one first block and the at least one second block to at least one blank block. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a schematic diagram of a storage device according to an embodiment of the present invention.

[0008] Figure 2 FIG. 4 is a schematic diagram of a block in a flash memory module according to an embodiment of the present invention.

[0009] Figure 3 FIG. 1 is a flow chart of establishing a write time record table according to an embodiment of the present invention.

[0010] Figure 4 Schematic diagram of writing time information in a block.

[0011] Figure 5 FIG. 4 is a schematic diagram of a writing time record table according to an embodiment of the present invention.

[0012] Figure 6The flowchart shown is a flow chart of establishing a write time record table in a DRAM after a storage device is powered on according to an embodiment of the present invention.

[0013] Figure 7 The figure is a flow chart of an expired block recovery operation according to an embodiment of the present invention.

[0014] Figure 8 Schematic diagram of the compressed write time record table shown.

[0015] Explanation of symbols

[0016] 100: Storage device

[0017] 110: Flash memory controller

[0018] 112: Microprocessor

[0019] 112C: Program code

[0020] 112M: Read-only memory

[0021] 114: Control Logic

[0022] 116: Buffer memory

[0023] 118: Interface interface logic

[0024] 120: Flash memory module

[0025] 130: Main device

[0026] 132: Encoder

[0027] 134:Decoder

[0028] 140: Dynamic Random Access Memory

[0029] 300~308: Steps

[0030] 500: Write time record table

[0031] 600~608: Steps

[0032] 700~714: Steps

[0033] 800: Compress and write to the time record table

[0034] B1,B2,B200,B201,B202: Block

[0035] BL1, BL2, BL3: bit lines

[0036] P1~P256: data page

[0037] T1_1, T1_M, T2_1, T2_M: Time information

[0038] WL0~WL2,WL4~WL6: word line DETAILED DESCRIPTION

[0039] Figure 1 1 is a schematic diagram of a storage device 100 according to an embodiment of the present invention. The electronic device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The ROM 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access to the flash memory module 120. The control logic 114 includes an encoder 132 and a decoder 134, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or error correction code (ECC)), and the decoder 134 is used to decode the data read from the flash memory module 120.

[0040] In a typical case, the flash memory module 120 includes a plurality of flash memory chips, each of which includes a plurality of blocks, and the flash memory controller 110 performs an erase operation on the flash memory module 120 in units of blocks. In addition, a block can record a specific number of data pages, wherein the flash memory controller 110 performs a write operation on the flash memory module 120 in units of data pages. In the present embodiment, the flash memory module 120 is a 3D NAND-type flash module.

[0041] In practice, the flash memory controller 110 executing the program code 112C through the microprocessor 112 can use its own internal components to perform a variety of control operations, such as: using the control logic 114 to control the access operation of the flash memory module 120 (especially the access operation to at least one block or at least one data page), using the buffer memory 116 to perform the required buffer processing, and using the interface logic 118 to communicate with a host device 130. The buffer memory 116 is implemented as a random access memory (Random Access Memory, RAM). For example, the buffer memory 116 can be a static random access memory (Static RAM, SRAM), but the present invention is not limited to this. In addition, the flash memory controller 110 is coupled to a dynamic random access memory (Dynamic Random Access Memory, DRAM).

[0042] In one embodiment, the storage device 100 may be a portable storage device (e.g., a memory card that complies with SD / MMC, CF, MS, or XD standards), and the host device 130 is an electronic device that can be connected to the storage device 100, such as a mobile phone, a notebook computer, a desktop computer, etc. In another embodiment, the storage device 100 may be a solid state drive or an embedded storage device that complies with Universal Flash Storage (UFS) or Embedded MultiMedia Card (EMMC) specifications, and may be disposed in a mobile phone, a notebook computer, or a desktop computer, and in this case, the host device 130 may be a processor of the mobile phone, the notebook computer, or the desktop computer.

[0043] Figure 2 FIG. 2 is a schematic diagram of a block 200 in a flash memory module 120 according to an embodiment of the present invention, wherein the flash memory module 120 is a three-dimensional NAND flash memory. Figure 2 As shown, block 200 includes a plurality of memory cells (such as the floating gate transistor 202 shown in the figure or other charge trap elements), which form a three-dimensional NAND flash memory architecture through a plurality of bit lines (only BL1 to BL3 are shown in the figure) and a plurality of word lines (such as WL0 to WL2, WL4 to WL6 shown in the figure). Figure 2In the example of the top plane, all floating gate transistors on word line WL0 constitute at least one data page, all floating gate transistors on word line WL1 constitute another at least one data page, and all floating gate transistors on word line WL2 constitute another at least one data page... and so on. In addition, depending on the different writing methods of the flash memory, the definition between word line WL0 and data page (logical data page) will also be different. Specifically, when writing using single-level cell (SLC) method, all floating gate transistors on word line WL0 correspond to only one logical data page; when writing using multi-level cell (MLC) method, all floating gate transistors on word line WL0 correspond to two logical data pages; when writing using triple-level cell (TLC) method, all floating gate transistors on word line WL0 correspond to three logical data pages; and when writing using quad-level cell (QLC) method, all floating gate transistors on word line WL0 correspond to four logical data pages. Since a person skilled in the art should be able to understand the structure of a three-dimensional NAND flash memory and the relationship between a word line and a data page, the relevant details are not described in detail here.

[0044] Figure 3 The flowchart of establishing a write time record table according to an embodiment of the present invention is shown. In step 300, the process starts, the flash memory controller 110 is powered on and completes the initialization operation. In step 302, the flash memory controller 110 selects a block from multiple blank blocks of the flash memory module 120, and prepares to write the data from the main device 130 into the block. In step 304, the flash memory controller 110 writes the data starting from the first data page of the block, and writes the time information at that time into the spare area when the data is written to the first data page and the intermediate data page. Specifically, refer to Figure 4The schematic diagram of the flash memory module 120 shown in the figure assumes that block B1 includes multiple data pages P1~P256, and the flash memory controller 110 writes the data from the main device 130 in sequence starting from the first data page P1 of block B1, wherein when the flash memory controller 110 is ready to write data to the data page P1, the flash memory controller 110 will simultaneously capture the current time information T1_1, for example, the corresponding time information can be generated by a built-in timer or the absolute time from the main device 130 (for example, 2:00 p.m. on May 11, 2020), and the data from the main device and the related time information T1_1 are written into the data page P1 together, wherein the time information T1_1 can be written into the spare area located at the back end of the data page P1. Then, the flash memory controller 110 sequentially writes the data into the data pages P2, P3, ... until the flash memory controller 110 is ready to write the data into the intermediate data page P128, the flash memory controller 110 will simultaneously capture the current time information T1_M and write the data from the master device and the related time information T1_M into the data page P128, wherein the time information T1_M can be written into the spare area located at the back end of the data page P128. It should be noted that the data pages P2 to P127 between the first data page P1 and the intermediate data page P128 do not need to write any time information to reduce the burden of the flash memory controller 110. It should be noted that the spare area of ​​the data page mentioned above can also be called a management area, that is, it is used to store some management data, such as logical addresses, etc.

[0045] It should be noted that in Figure 4 In the embodiment of the present invention, data page P128 is used as the intermediate data page, but this is only an example and not a limitation of the present invention. In other embodiments, data page P127 can also be used as the intermediate data page, or data pages P127 and P128 can be used as the intermediate data page at the same time. In addition, in another embodiment, the number of intermediate data pages can be multiple data pages. For example, the four data pages P126, P127, P128, and P129 are all used as the multiple intermediate data pages described in this embodiment, that is, the spare areas of data pages P126, P127, P128, and P129 all store corresponding time information.

[0046] Next, the flash memory controller 110 sequentially writes the data to data pages P129, P130, ... until the flash memory controller 110 is ready to write the data to the last data page (i.e., data page P256), in which case the flash memory controller 110 writes the time information T1_1 of the previous data page P1 and the time information T1_M of the data page P128 together with the data from the master device 130 to the data page P256, wherein the time information T1_M can be written to a spare area located at the rear end of the data page P256.

[0047] In step 306, during the data writing process of block B1, the flash memory controller 110 will synchronously create the following in the DRAM 140: Figure 5 The write time record table 500 shown, that is, the write time record table 500 records the block number B1 and the corresponding time information T1_1, T1_M. It should be noted that the write time record table 500 records the time information T1_1 of the first data page P1 and the time information T1_M of the intermediate data page (for example, data page P128). If, as described in the previous paragraph, each block has multiple intermediate data pages, for example, the four data pages P126, P127, P128, and P129 are simultaneously used as intermediate data pages, then the write time record table 500 can generate a single time information of the intermediate data page based on the multiple time information recorded by the data pages P126, P127, P128, and P129, for example, averaging or taking the middle value of the multiple time information recorded by the data pages P126, P127, P128, and P129 to obtain a single time information corresponding to the intermediate data page.

[0048] It should be noted that for some storage devices that do not have the DRAM 140 , the above-mentioned write time record table 500 may also be stored in the buffer memory 116 .

[0049] In step 308, the microprocessor 112 determines whether all data pages of the current block B1 are fully written. If not, the process returns to step 304 to continue writing data to the remaining data pages of block B1. If so, the process returns to step 302 to select the next blank block, such as Figure 4As shown in block B2, then, similar to the data writing process of the flash memory controller 110 to block B1, when the flash memory controller 110 is ready to write data to the data page P1 of block B2, the flash memory controller 110 will simultaneously capture the current time information T2_1, and write the data from the master device and the related time information T2_1 into the data page P1 of block B2; when the flash memory controller 110 is ready to write data to the data page P128 of block B2, the flash memory controller 110 will simultaneously capture the current time information T2_M, and write the data from the master device and the related time information T2_M into the data page P128 of block B2; and when the flash memory controller 110 is ready to write data to the data page P256, the flash memory controller 110 will write the time information T2_1 of the previous data page P1 and the time information T2_M of the data page P128 together with the data from the master device 130 into the data page P256. In addition, the microprocessor 112 updates the write time record table 500 to record the block number B2 and the corresponding time information T2_1 and T2_M.

[0050] Whenever a blank block in the flash memory module 120 starts to write data, the microprocessor 112 will update the write time record table 500, that is, the write time record table 500 records the time information of the first data page P1 of each block in the flash memory module 120 and the time information of the intermediate data pages (such as data page P128).

[0051] In addition, the write time record table 500 will reside in the DRAM 140 to facilitate subsequent expired block judgment and garbage collection operations. When the storage device 100 needs to be powered off, the microprocessor 112 will first write the write time record table 500 to the flash memory module 120, and wait for the storage device 100 to be powered on before re-reading the write time record table 500 in the flash memory module 120 and loading it into the DRAM 140 for subsequent use.

[0052] However, the storage device 100 may be suddenly powered off due to various reasons, which may cause the write time record table 500 stored in the DRAM 140 to be lost. Therefore, after the storage device 100 is powered on again, it is necessary to re-establish the write time record table 500 in the DRAM 140. Figure 6The flowchart of establishing the write time record table 500 in the DRAM 140 after the storage device 100 is powered on according to one embodiment of the present invention is shown. At step 600, the process starts, and the storage device 100 is powered on and starts the initialization operation. At step 602, the microprocessor 112 determines whether the power failure of the storage device 100 before powering on is an abnormal power failure (sudden power failure). If not, the process enters step 604 to read the write time record table 500 from the flash memory module 120 and temporarily store it in the DRAM 140; if so, the process enters step 606. For example, when the storage device 100 is normally shut down / powered off, the flash memory controller 110 stores the multiple temporary tables and data stored in the buffer memory 116 in the flash memory module 120, and includes a flag for indicating whether the storage device 100 is normally shut down. Therefore, after powering on, the flash memory controller 110 can determine whether the storage device 100 has previously encountered an abnormal power outage by reading the flag stored in the flash memory module 120. For example, when the flag is not correctly set, it is determined that an abnormal power outage has previously occurred. In step 606, the microprocessor 112 sequentially reads the last data page of each block with data written in the flash memory module 120 (for example, Figure 4 256) to obtain the time information of the first data page of each block and the time information of the intermediate data pages. Figure 4 , the microprocessor 112 can directly read the last data page P256 of the block B1 to obtain the time information T1_1 of the first data page P1 and the time information T1_M of the intermediate data page P128, and can also directly read the last data page P256 of the block B2 to obtain the time information T2_1 of the first data page P1 and the time information T2_M of the intermediate data page P128. In addition, in some special situations, such as the data of the last data page P256 of the block is damaged, or the last data page P256 of the block has not yet been written, then the microprocessor 112 can directly read the time information of the first data page and the intermediate data page of the above block.

[0053] Since the initialization time of the storage device 100 is limited to a certain extent, such as 1 to 2 seconds, and the flash memory controller 110 needs to rebuild many other reference tables / mapping tables during the initialization operation, the present embodiment can obtain the time information of the first data page and the time information of the intermediate data pages by only reading the last data page of the block, thereby making the reconstructed write time record table 500 very fast to avoid timeout of the initialization operation.

[0054] After obtaining the time information of the first data page and the time information of the intermediate data pages of each block with data written, the write time record table 500 can be re-established in the DRAM 140, and the flow enters 608 to end the operation.

[0055] Figure 7 The flowchart of the expired block recovery operation according to one embodiment of the present invention. In step 700, the process starts, and the storage device 100 has completed the initialization operation. In step 702, the microprocessor 112 determines whether the time information of the first data page P1 of any block in the flash memory module 120 is earlier than a first threshold value according to the write time record table 500. If yes, the process enters step 704; if not, the process enters step 708. The first threshold value can be a time determined according to the current time. For example, assuming that the current time is 8:00 p.m. on May 21, 2020, the first threshold value can be 12 days ago, that is, the first threshold value can be 8:00 p.m. on May 9, 2020.

[0056] In step 704, the microprocessor 112 adds the blocks whose time information of the first data page P1 is earlier than a first threshold value to an expired block table (for example, the block numbers of these blocks are recorded in the expired block table), and marks these blocks as pending blocks. In this embodiment, the expired block table is used to record the priority of expired block recovery operations, and has a fixed size (that is, the number of blocks that can be recorded has an upper limit value). Therefore, if the number of blocks determined in step 702 is too large, the blocks whose time information of the first data page P1 is earlier are preferentially selected to be added to the expired block table.

[0057] In step 706 , the microprocessor 112 determines whether the blocks recorded in the expired block table have reached the upper limit. If so, the process proceeds to step 712 ; if not, the process proceeds to step 708 .

[0058] In step 708, the microprocessor 112 determines whether there is any intermediate data page (eg, Figure 4 If the time information of the data page P128 of the data is earlier than a second threshold value, the process proceeds to step 710; if not, the process proceeds to step 712. The second threshold value can be a time determined according to the current time, and the second threshold value is later than the first threshold value. For example, assuming that the current time is 8:00 p.m. on May 21, 2020, the second threshold value can be 11 days ago, that is, the first threshold value can be 8:00 p.m. on May 10, 2020.

[0059] In step 710, the microprocessor 112 adds the blocks whose time information of the intermediate data page is earlier than a second threshold value to an expired block table, and marks these blocks as pending blocks. In addition, if the number of blocks determined in step 708 is too large, the blocks whose time information of the intermediate data page is earlier are preferentially selected to be added to the expired block table.

[0060] Regarding the above steps 708 and 710, since the blocks whose time information of the first data page P1 is earlier than the first threshold value have been added to the expired block table in step 704, steps 708 and 710 can actually be regarded as adding the blocks whose time information of the intermediate data pages is between the second threshold value and the first threshold value to the expired block table.

[0061] It should be noted that not all blocks recorded in the above expired block table are determined according to the methods in steps 702 and 708 , that is, some of the blocks recorded in the expired block table may be determined based on block quality or other mechanisms.

[0062] In step 712, the microprocessor 112 performs expired block recovery operations in sequence according to the blocks recorded in the above-mentioned expired block table. Specifically, the microprocessor 112 can move the valid data in the block recorded in the expired block table to a blank data page, and after the valid data of the block is completely moved, mark the block as invalid or erase it. It should be noted that the expired block recovery operation described in step 712 can be performed in the background, that is, when the flash memory controller 110 is in an idle state (for example, it does not need to process the access instruction from the main device 130), the microprocessor 112 can start to execute the expired block recovery operation until the flash memory controller 110 receives the access instruction from the main device 130 and needs to start being busy.

[0063] Due to the continuous increase in the unit density of the memory capacity of the three-dimensional NAND flash memory, the memory performance continues to deteriorate. After the data is written to the new three-dimensional NAND flash memory, the charge stored in the gate of the memory cell will continue to be lost. After a period of time, the charge stored in the gate of some memory cells can no longer reflect the charge amount of the data originally intended to be stored, resulting in frequent errors during reading. These errors usually require the flash memory controller to start the correction mechanism of changing the read voltage and hard decoding and soft decoding in order to read the correct data from these expired blocks. These correction mechanisms are usually very time-consuming and power-consuming, and may not be able to correct the errors at all, resulting in the memory controller not being able to read the correct data. Therefore, it is necessary to record the write time of the block to avoid the above problems. It should be noted that the expired block recovery operation described in the above embodiment is different from the garbage collection operation, and the expired block table of this embodiment is also different from the garbage collection sequence required for the garbage collection operation. Specifically, during the operation of the storage device 100, the flash memory controller 110 will continuously determine the number of valid data pages of each block in the current flash memory module 120 to determine which blocks need to be garbage collected. For example, when the number of valid data pages of a block is lower than a critical value, the block will be placed in the garbage collection sequence to perform garbage collection operations later. However, the expired block table described in this embodiment records blocks that have been written for too long, that is, some of these blocks may not meet the standard of garbage collection operations, for example, the number of valid data pages of these blocks is much higher than the critical value. In addition, since the data of the blocks recorded in the expired block table will deteriorate rapidly, the priority of the expired block table is higher than the garbage collection sequence, that is, if any block number is recorded in the expired block table, then in the case where the garbage collection operation is allowed to be interrupted, the flash memory controller 110 will stop the garbage collection operation first and start the expired block recovery operation. In other words, the flash memory controller 110 will immediately perform an expired block recycling operation on the blocks recorded in the expired block table.

[0064] In step 714, since the block is written and erased during the expired block recovery operation in step 712, the microprocessor 112 updates the write time record table 500 according to the write and erase of the block. For example, if the block B1 is marked as invalid or erased, the microprocessor 112 can delete the time information about the block B1 in the write time record table 500.

[0065] The reason why the blocks to be added to the expired block table are determined according to the second threshold value in the above steps 708 and 710 is that the time information of the intermediate data page can better reflect the overall write time of the block, and by setting the second threshold value to be later than the first threshold value and adding the blocks whose time information of the intermediate data page is between the second threshold value and the first threshold value to the expired block table, a sufficient number of blocks can be added to the expired block table at one time for subsequent expired block recovery operations without the need to repeat the operation frequently. Figure 7 The process or other mechanism is used to select the blocks that need to be reclaimed for expired blocks. In addition, in a three-dimensional flash memory, the data stored in the block will deteriorate rapidly as time goes by, but if the block is read or written (writing data to the remaining data pages), the overall data quality of the block can be slightly improved. Therefore, the use of the second threshold value and the first threshold value as a judgment mechanism can allow blocks with poorer quality to be added to the expired block table first. In addition, since the time when the data of the block is written may vary greatly, that is, the time information of the first data page of the block and the time information of the intermediate data page may be very different, therefore, by using the time information of the intermediate data page that can better reflect the overall write time of the block, the judgment of block expiration can be made more accurate.

[0066] Refer to above Figures 3 to 7 As described in the embodiment, by establishing a write time record table 500 to record the time information of the first data page and the intermediate data page of each block, and using the first threshold value and the second threshold value to select the blocks that need to perform the expired block recovery operation, overall, the blocks that need to perform the expired block recovery operation can be selected more quickly and efficiently.

[0067] The expired block recovery operation needs to cooperate with the logical data page and physical data page link table to find all valid data pages of the block, and move the valid data page from the expired block to the new block. The data in the valid data page is rewritten to the new block due to the move, and the validity period of these data is reset, and the expired block is erased for standby. After moving the valid data, the microprocessor 112 needs to update the logical data page and physical data page link table and establish a data number table of valid data pages of the new block. For the sake of caution, the invalid data in the expired block can also be moved to another new block, and the logical data page and physical data page link table of invalid data can be established accordingly to avoid the host from accidentally deleting the data and still being able to save the data. Please note that in some expired blocks, all the data pages may be valid data pages, then all the data must be moved to the new data and the validity period of all the data must be reset.

[0068] In addition, in some applications, the flash memory module 120 may have thousands of blocks and be frequently written. Therefore, the write time record table 500 may need to record many block numbers and related time information, which seriously consumes the storage space of the DRAM 140. In addition, if the storage device 100 does not have the DRAM 140 and the write time record table 500 needs to be stored in the buffer memory 116, then at this time, since the buffer memory 116 is usually implemented using a more expensive SRAM and the capacity is not too large, it will cause more trouble in the memory configuration of the buffer memory 116. As described above, in the following embodiments, a compression method for the write time record table 500 is also proposed, which can write most of the content of the write time record table 500 into the blocks of the flash memory module 120 to reduce the size of the write time record table 500 stored in the DRAM 140 or the buffer memory 116.

[0069] For example, refer to Figure 8 FIG. 8 is a schematic diagram of a compressed write time record table 800, wherein the compressed write time record table 800 can be obtained by simplifying and compressing the write time record table 500. Figure 8 In the compressed write time record table 800, multiple time ranges and corresponding at least one data page address are included, wherein the multiple time ranges can be any suitable time ranges, and in this embodiment, the time range is based on one day. Figure 8 In the embodiment of the present invention, the microprocessor 112 sequentially or periodically writes the block number and the corresponding time information in the write time record table 500 into the block of the flash memory module 120 to Figure 8 The time range is today's situation. When the flash memory controller 110 writes data to multiple blocks of the flash memory module 120 and synchronously establishes the write time record table 500, the microprocessor 112 will write the block number and corresponding time information recorded in the write time record table 500 into the data page P25 of block B200, and the compressed write time record table 800 will record the data page address "PPA98765" of the data page P25 of block B200; in addition, since the data page P25 of block B200 has recorded the content of the write time record table 500, the microprocessor 112 can delete the relevant data in the write time record table 500 to release the memory space. Similarly, Figure 8 The time range shown is that the data page address "PPA33333" recorded in "Yesterday" corresponds to the data page P46 of block B201, and the data page P46 of block B201 records the block written yesterday and the corresponding time information; similarly, Figure 8The data page address "PPA33445" recorded in the time range "the day before yesterday" corresponds to the data page P37 of block B202, and the data page P37 of block B202 records the block written the day before yesterday and the corresponding time information. Figure 5 The contents of the write time record table 500 shown can be stored in the flash memory module 120, and the compressed write time record table 800 only needs to record some data page addresses in the flash memory module 120, thereby effectively reducing the burden of the write time record table 500 on the memory space.

[0070] In addition, since the blocks in the flash memory module 120 may be erased and become blank blocks, when the microprocessor 112 learns that a block has been erased, it will update the contents of the flash memory module 120 and the compressed write time record table 800. For example, assuming that the block B1 written yesterday is erased today, the microprocessor 112 reads the contents of the data page P46 of the block B201, deletes the block B1 and the related time information, and rewrites it to another data page, such as the data page P47 of the block B201; in addition, the data page address of the data page P46 of the block B201 in the compressed write time record table 800 is replaced with the data page address of the data page P47 of the block B201.

[0071] In addition, in order to facilitate the management of blocks and data pages, each time range in the compressed write time record table 800 corresponds to a dedicated block, for example, the block numbers and time information of all blocks where data was written the day before yesterday are written into block B202, the block numbers and time information of all blocks where data was written yesterday are written into block B201, the block numbers and time information of all blocks where data was written today are written into block B200, and so on. In addition, the above dedicated blocks will not be used to store other data.

[0072] To briefly summarize the present invention, in the control method of a flash memory controller of the present invention, a write time record table is established to record the time information of the first data page and the middle data page of each block, and the first threshold value and the second threshold value are used to select the blocks that need to be reclaimed for expired blocks, so as to efficiently complete the reclaiming of expired blocks. In addition, by compressing the write time record table, the burden of the write time record table on the memory space can be reduced.

[0073] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A control method for a flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module is a 3D NAND-type flash module, the flash memory module includes a plurality of flash memory chips, each of the flash memory chips includes a plurality of blocks, each of the blocks includes a plurality of data pages; each block includes a plurality of floating gate transistors controlled by a plurality of word lines and bit lines located in a plurality of different planes, and the floating gate transistors on each word line constitute at least one data page of the plurality of data pages; and the control method includes: When data is written into a first data page of any block of the flash memory module, a first time is recorded in the first data page; When data is written into at least one intermediate data page of any block of the flash memory module, a second time is recorded in the at least one intermediate data page; When data is written into a last data page of any block of the flash memory module, the first time and the second time are recorded in the last data page; Establishing a write time record table, wherein the write time record table records the block number of the block in the flash memory module where data is written and the corresponding first time, or records the block number of the block in the flash memory module where data is written and the corresponding first time and second time; Refer to the write time record table to determine whether there is a block in the flash memory module whose first time is earlier than a first threshold value, and if there is at least one first block in the flash memory module whose first time is earlier than the first threshold value, record the at least one first block in an expired block table; Refer to the write time record table to determine whether there is a block in the flash memory module whose second time is earlier than a second threshold value, and if there is at least one second block in the flash memory module whose second time is earlier than the second threshold value, record the at least one second block in the expired block table; as well as An expired block recovery operation is performed according to the at least one first block and the at least one second block recorded in the expired block table, so as to sequentially move valid data in the at least one first block and the at least one second block to at least one blank block.

2. The control method according to claim 1, characterized in that: The time represented by the second threshold value is later than the time represented by the first threshold value.

3. The control method according to claim 1 or 2, characterized in that: The first threshold value is determined according to the current time when the control method is executed.

4. The control method according to claim 1, characterized in that: The at least one intermediate data page includes a plurality of intermediate data pages, and the second time recorded in the write time record table is determined according to a plurality of write times of the plurality of intermediate data pages.

5. The control method according to claim 1, characterized in that: Referring to the write time record table to determine whether there is a block in the flash memory module whose second time is earlier than the second threshold value, if there is at least one second block in the flash memory module whose second time is earlier than the second threshold value, the step of recording the at least one second block in the expired block table includes: Determine whether the number of blocks recorded in the expired block table has reached an upper limit; If the number of blocks recorded in the expired block table has reached the upper limit, not recording the at least one second block in the expired block table; as well as If the number of blocks recorded in the expired block table does not reach the upper limit, sequentially record the at least one second block in the expired block table until the number of blocks recorded in the expired block table reaches the upper limit; as well as The step of performing an expired block recovery operation according to the at least one first block and the at least one second block recorded in the expired block table includes: In a background operation of the flash memory controller, an expired block recovery operation is immediately performed according to the at least one first block and the at least one second block recorded in the expired block table.

6. The control method according to claim 1, characterized in that: Also included: When the flash memory controller is ready to shut down, writing the write time record table into a specific block of the flash memory module; When the flash memory controller is powered on, determining whether the flash memory controller encounters an abnormal power failure before powering on; If it is determined that the flash memory controller does not encounter an abnormal power failure before powering on, the write time record table is read from the specific block and temporarily stored in a buffer memory or a dynamic random access memory; as well as If it is determined that the flash memory controller encounters an abnormal power outage before power-on, the last data page of each block with data written in the flash memory module is read in sequence to re-establish the write time record table, and the write time record table is temporarily stored in the buffer memory or the dynamic random access memory.

7. The control method according to claim 6, characterized in that: If it is determined that the flash memory controller encounters an abnormal power failure before powering on, the steps of sequentially reading the last data page of each block in the flash memory module to which data is written to re-establish the write time record table include: If the last data page of any block in each block in the flash memory module does not include the first time and the second time, the first data page and the middle data page of the block are read to obtain the corresponding first time and the second time.

8. The control method according to claim 6, characterized in that: The operation of re-establishing the write time record table is completed within the time of an initialization operation after the flash memory controller is powered on.

9. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module is a 3D NAND-type flash module, the flash memory module includes a plurality of flash memory chips, each of the flash memory chips includes a plurality of blocks, each of the blocks includes a plurality of data pages; each block includes a plurality of floating gate transistors controlled by a plurality of word lines and bit lines located in a plurality of different planes, and the floating gate transistors on each word line constitute at least one data page of the plurality of data pages; and the flash memory controller includes: A read-only memory for storing a program code; a microprocessor, used to execute the program code to control access to the flash memory module; as well as a buffer memory; When the microprocessor writes data to a first data page of any block of the flash memory module, a first time is recorded in the first data page; when the microprocessor writes data to at least one intermediate data page of any block of the flash memory module, a second time is recorded in the at least one intermediate data page; when the microprocessor writes data to a last data page of any block of the flash memory module, the first time and the second time are recorded in the last data page; the microprocessor further establishes a write time record table, wherein the write time record table records the block number of the block in the flash memory module where data is written and the corresponding first time, or records the block number of the block in the flash memory module where data is written and the corresponding first time and the second time; The microprocessor refers to the write time record table to determine whether there is a block in the flash memory module whose first time is earlier than a first threshold value, and if there is at least one first block in the flash memory module whose first time is earlier than the first threshold value, the microprocessor records the at least one first block in an expired block table; the microprocessor refers to the write time record table to determine whether there is a block in the flash memory module whose second time is earlier than a second threshold value, and if there is at least one second block in the flash memory module whose second time is earlier than the second threshold value, the microprocessor records the at least one second block in the expired block table; And an expired block recovery operation is performed according to the at least one first block and the at least one second block recorded in the expired block table, so as to sequentially move valid data in the at least one first block and the at least one second block to at least one blank block.

10. The flash memory controller according to claim 9, wherein: The time represented by the second threshold value is later than the time represented by the first threshold value.

11. The flash memory controller according to claim 9 or 10, characterized in that: The first threshold value is determined according to the current time when the flash memory controller is executed.

12. The flash memory controller according to claim 9, wherein: The at least one intermediate data page includes a plurality of intermediate data pages, and the second time recorded in the write time record table is determined according to a plurality of write times of the plurality of intermediate data pages.

13. The flash memory controller according to claim 9, wherein: The microprocessor determines whether the number of blocks recorded in the expired block table has reached an upper limit; if the number of blocks recorded in the expired block table has reached the upper limit, the at least one second block is not recorded in the expired block table; and if the number of blocks recorded in the expired block table does not reach the upper limit, the microprocessor sequentially records the at least one second block in the expired block table until the number of blocks recorded in the expired block table reaches the upper limit; And in a background operation of the flash memory controller, the microprocessor immediately performs an expired block recovery operation according to the at least one first block and the at least one second block recorded in the expired block table.

14. The flash memory controller according to claim 9, wherein: When the flash memory controller is ready to shut down, the microprocessor writes the write time record table into a specific block of the flash memory module; when the flash memory controller is powered on, the microprocessor determines whether the flash memory controller encounters an abnormal power failure before powering on; If it is determined that the flash memory controller does not encounter an abnormal power failure before powering on, the microprocessor reads the write time record table from the specific block and temporarily stores the write time record table in a buffer memory or a dynamic random access memory; And if it is determined that the flash memory controller encounters an abnormal power outage before power-on, the microprocessor sequentially reads the last data page of each block in the flash memory module where data is written to re-establish the write time record table, and temporarily stores the write time record table in the buffer memory or the dynamic random access memory.

15. The flash memory controller according to claim 14, wherein: If the last data page of any block in each block in the flash memory module does not include the first time and the second time, the microprocessor reads the first data page and the middle data page of the block to obtain the corresponding first time and the second time.

16. The flash memory controller according to claim 14, wherein: The operation of re-establishing the write time record table is completed within the time of an initialization operation after the flash memory controller is powered on.

17. A storage device comprising: A flash memory module, wherein the flash memory module is a 3D flash memory (3D NAND-type flash) module, the flash memory module includes a plurality of flash memory chips, each of which includes a plurality of blocks, each of which includes a plurality of data pages; each block includes a plurality of floating gate transistors controlled by a plurality of word lines and bit lines located in a plurality of different planes, and the floating gate transistors on each word line constitute at least one data page among the plurality of data pages; as well as a flash memory controller for accessing the flash memory module; When the flash memory controller writes data to a first data page of any block of the flash memory module, a first time is recorded in the first data page; when the flash memory controller writes data to at least one intermediate data page of any block of the flash memory module, a second time is recorded in the at least one intermediate data page; when the flash memory controller writes data to a last data page of any block of the flash memory module, the first time and the second time are recorded in the last data page; the flash memory controller further establishes a write time record table, wherein the write time record table records the block number of the block in the flash memory module with data written and the corresponding first time, or records the block number of the block in the flash memory module with data written and the corresponding first time and the second time; The flash memory controller refers to the write time record table to determine whether there is a block in the flash memory module whose first time is earlier than a first threshold value, and if there is at least one first block in the flash memory module whose first time is earlier than the first threshold value, the at least one first block is recorded in an expired block table; the flash memory controller refers to the write time record table to determine whether there is a block in the flash memory module whose second time is earlier than a second threshold value, and if there is at least one second block in the flash memory module whose second time is earlier than the second threshold value, the at least one second block is recorded in the expired block table; And an expired block recovery operation is performed according to the at least one first block and the at least one second block recorded in the expired block table, so as to sequentially move valid data in the at least one first block and the at least one second block to at least one blank block.

18. The storage device according to claim 17, wherein: The time represented by the second threshold value is later than the time represented by the first threshold value.

19. The storage device according to claim 17 or 18, characterized in that: The first threshold value is determined according to the current time when the storage device is executed.

20. The storage device according to claim 17, wherein: The at least one intermediate data page includes a plurality of intermediate data pages, and the second time recorded in the write time record table is determined according to a plurality of write times of the plurality of intermediate data pages.

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