Configurable NAND firmware search parameters

Abstract

This application relates to configurable NAND firmware search parameters. In some examples, memory devices are disclosed that include electrically programmable elements that specify values for one or more firmware search parameters used by a bootloader to locate and read firmware objects. The values for the firmware search parameters can be dynamically selected at the time of manufacture by modifying the configuration of the electrically programmable elements by applying or not applying a specified voltage to the electrically programmable elements. In some examples, the electrically programmable elements can include fuses, anti-fuses, and / or e-fuses.

Description

[0001] Related information of divisional application

[0002] This case is a divisional application. The parent case of this divisional application is the invention patent application with the application date of December 31, 2019, the application number of 201911411938.1, and the invention name of “Configurable NAND firmware search parameter”. TECHNICAL FIELD

[0003] The present application relates to memory devices, and particularly to configurable NAND firmware search parameters. BACKGROUND

[0004] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory needs power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or a synchronous dynamic random access memory (SDRAM), among others.

[0005] Non-volatile memory retains stored data when unpowered, and includes flash memory, read only memory (ROM), electrically-erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistive variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or 3D XPoint memory, among others. TM Memory, among others.

[0006] Flash memory is used for non-volatile storage in a wide range of electronic applications. Flash memory devices typically include one or more arrays of single transistor, floating gate, or charge trap memory cells that allow high memory density, high reliability, and low power consumption.

[0007] Two common types of flash memory array architecture include NAND and NOR architectures, named in logical form of the basic memory cell configuration of each. Memory cells of a memory array are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drains of each memory cell in a string of the array are coupled together in a source-to-drain series between a source line and a bit line.

[0008] Both "NOR" and "NAND" architecture semiconductor memory arrays are accessed through a decoder that activates a particular memory cell by selecting a word line coupled to its gate. In an "NOR" architecture semiconductor memory array, once activated, the selected memory cell places its data value on a bit line, resulting in different current flow depending on the particular cell's programmed state. In a "NAND" architecture semiconductor memory array, a high bias is applied to a drain side select gate (SGD) line. A word line coupled to the gates of unselected memory cells of each group is driven with a pass voltage (e.g., Vpass) to operate the unselected memory cells of each group as pass transistors (e.g., to pass current in a manner not limited by their stored data values). Current then flows from a source line to a bit line through each series-coupled group, limited only by the selected memory cell of each group, placing the selected memory cell's current encoded data value on the bit line.

[0009] Each flash memory cell in an "NOR" or "NAND" architecture semiconductor memory array can be individually or collectively programmed to one or more programmed states. For example, a single level cell (SLC) can represent one of two programmed states (e.g., 1 or 0), representing one bit of data. However, a flash memory cell can also represent one of more than two programmed states, allowing for higher density memory to be manufactured without increasing the number of memory cells, as each cell can represent more than one binary digit (e.g., more than one bit). Such a cell can be referred to as a multi-state memory cell, a multi-bit cell, or a multi-level cell (MLC). In certain examples, MLC can refer to a memory cell that can store two bits of data per cell (e.g., one of four programmed states), a triple level cell (TLC) can refer to a memory cell that can store three bits of data per cell (e.g., one of eight programmed states), and a quad level cell (QLC) can store four bits of data per cell. MLC is used in a broader context herein to refer to any memory cell that can store more than one bit of data per cell (i.e., that can represent more than two programmed states).

[0010] Conventional memory arrays are two-dimensional (2D) structures arranged on the surface of a semiconductor substrate. To increase the storage capacity of a given area and reduce cost, the size of individual memory cells has been reduced. However, there are technical limits to reducing the size of individual memory cells, and thus the memory density of 2D memory arrays. In response, three-dimensional (3D) memory structures, such as 3D "NAND" architecture semiconductor memory devices, are being developed to further increase memory density and reduce memory cost.

[0011] Such 3D "NOR" devices typically include multiple strings of memory cells coupled in series (e.g., drain to source) between one or more source side select gates (SGS) proximate the source and one or more drain side select gates (SGD) proximate the bit line. In examples, the SGS or SGD can include one or more field effect transistors (FETs) or metal oxide semiconductor (MOS) structure devices, among others. In some examples, the string will extend vertically and through multiple vertically spaced tiers containing respective word lines. A semiconductor structure (e.g., a polysilicon structure) can extend adjacent the string of memory cells to form a channel for the memory cells of the string. In examples of vertical strings, the polysilicon structure can be in the form of a vertically extending pillar. In some examples, the string can be "folded" and thus arranged relative to a U-shaped pillar. In other examples, multiple vertical structures can be stacked on one another to form a stacked array of memory cell strings.

[0012] Memory arrays or devices can be combined together to form a storage volume of a memory system, such as a solid state drive (SSD), a Universal Flash Storage (UFS TM ) device, a MultiMediaCard (MMC) solid state storage device, an embedded MMC device (eMMC TM ), among others. Further, SSDs can also be used as the primary storage device for a computer, which has advantages over traditional hard disk drives with moving parts in terms of, for example, performance, size, weight, ruggedness, operating temperature range, and power consumption. For example, SSDs can reduce seek time, latency, or other delays associated with disk drives (e.g., electromechanical, etc.). SSDs use non-volatile memory cells (e.g., flash memory cells) to eliminate the internal battery power requirement, thus allowing the drive to be more versatile and compact.

[0013] SSDs can include multiple memory devices, including multiple dies or logical units (e.g., logical unit numbers or LUNs), and can include one or more processors or other controllers that perform logical functions required to operate the memory devices or interface with external systems. Such SSDs can include one or more flash memory dies including multiple memory arrays and peripheral circuitry thereon. The flash memory arrays can include multiple blocks of memory cells organized into multiple physical pages. In many examples, the SSD will also include DRAM or SRAM (or other forms of memory dies or other memory structures). The SSD can receive commands related to storage operations from a host, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory devices and the host, or erase operations to erase data from the memory devices. SUMMARY

[0014] One aspect of the disclosure provides a memory device, wherein the memory device comprises: a first set of one or more electrically programmable elements indicative of values of one or more first firmware search parameters; a second set of one or more electrically programmable elements indicative of values of one or more second firmware search parameters; and a processor configured to perform operations comprising: determining one or more possible locations of a firmware image in memory cells of the memory device according to the values of the one or more first firmware search parameters indicated by the first set of one or more electrically programmable elements; searching the one or more possible locations for a valid firmware image by reading the memory cells at the one or more possible locations according to the values of the one or more second firmware search parameters indicated by the second set of one or more electrically programmable elements; and causing execution of the firmware image in response to reading a valid firmware image.

[0015] Another aspect of the disclosure provides a machine-readable medium, wherein the machine-readable medium comprises instructions that, when executed by a processor of a memory device, cause the processor to perform operations comprising: determining one or more possible locations of a firmware image in memory cells of the memory device according to values of one or more first firmware search parameters indicated by a first set of one or more electrically programmable elements; searching the one or more possible locations for a valid firmware image by reading the memory cells at the one or more possible locations according to values of one or more second firmware search parameters indicated by a second set of one or more electrically programmable elements; and causing execution of the firmware image in response to reading a valid firmware image. BRIEF DESCRIPTION OF DRAWINGS

[0016] In the drawings, which are not necessarily drawn to scale, like numerals can describe similar components in different views. Like numerals having different letter suffixes can represent different instances of similar components. The drawings illustrate generally, by way of example, various embodiments discussed in the present document.

[0017] Figure 1 An example of an environment including a memory device is illustrated.

[0018] Figures 2 to 3 A schematic diagram illustrating an example of a 3D "NAND" architecture semiconductor memory array.

[0019] Figure 4 An example block diagram of a memory module is illustrated.

[0020] Figure 5 A block diagram of an example memory device is illustrated in accordance with some examples of the disclosure.

[0021] Figure 6A flowchart of a method for searching for a firmware object performed by a processor of a memory device is illustrated in accordance with some examples of the present disclosure.

[0022] Figure 7 A flowchart of a method for loading a firmware object is illustrated in accordance with some examples of the present disclosure.

[0023] Figure 8 A flowchart of a method for searching for a firmware object performed by a processor of a memory device is illustrated in accordance with some examples of the present disclosure.

[0024] Figure 9 A block diagram of an example of a machine upon which one or more embodiments can be implemented. DETAILED DESCRIPTION

[0025] As will be more fully explained below, a memory device can include a controller that comprises a processor and a working memory. The processor can be communicatively coupled to the working memory. The working memory can include read-only memory (ROM) and random access memory (RAM). Upon power-up of the memory device, the processor is configured to execute instructions at a defined address in the ROM. During manufacturing, a piece of software code, referred to herein as a bootloader, is flashed into the ROM at this address. The bootloader is configured to initialize the controller, including loading software, referred to as firmware, into the working memory (e.g., in random access memory (RAM)), and cause the processor to execute the firmware. The firmware is a collection of operational instructions that cause the controller to perform operations associated with the memory device (e.g., reading from and writing to NAND devices).

[0026] If the firmware object is in the same location on each NAND device, the task of finding the firmware is very simple. For reliability and functionality reasons (e.g., retention, read disturb, update failure, etc.), managed memory devices have multiple copies of the firmware, so the search algorithm can need to search for it in different locations. Furthermore, modern NAND devices utilize the same controller on many different NAND memory devices with different geometries and configurations and thus possibly different firmware locations. Still further, manufacturing defects can cause the location to vary from die to die of the same product. All of these variations cause the bootloader to utilize more complex strategies to find the firmware object. This can increase the size and complexity of the bootloader; can result in reduced chances of actually finding the firmware object; and / or increase the search time for the firmware object, thus increasing the boot time. Other strategies to address this situation can include a custom bootloader for each memory device. This can increase the controller cost, to implement a portion of the ROM as non-volatile memory, and increase manufacturing difficulty due to the need to flash the bootloader to the ROM during manufacturing.

[0027] In some examples, memory devices are disclosed that include electrically programmable elements that specify values for one or more firmware search parameters used by a bootloader to locate and read firmware objects. The values for the firmware search parameters can be dynamically selected at the time of manufacture by modifying the configuration of the electrically programmable elements by applying or not applying a specified voltage to the electrically programmable elements. In some examples, electrically programmable elements can include fuses, anti-fuses, and / or e-fuses.

[0028] For example, an electrically programmable element can include a fuse that can be blown or not blown during manufacturing by applying a determined voltage to an input of the fuse. By blowing or not blowing the fuse, the electrically programmable element can be reconfigured such that an input voltage to the fuse can be inhibited (if the fuse is blown) or passed through (if the fuse is not blown). One or more fuses can correspond to a single firmware search parameter. As an example, if two fuses correspond to a first search parameter, and one fuse is blown and the second fuse is not blown, the electrically programmable element provides a signal of 1-0 to a processor. The processor can then convert this signal to a value for the first firmware search parameter.

[0029] By providing the ability to quickly and easily customize search parameters during manufacturing, a bootloader can determine information that allows it to quickly and accurately find firmware regardless of the type of device. This avoids the problems of previous solutions that utilize custom bootloaders by providing a standardized bootloader that can be loaded on a ROM at the time of manufacturing controller and does not need to be loaded during manufacturing of a memory device. The standardized bootloader is customized by providing different values for the firmware search parameters selected for the electrically programmable elements. This makes manufacturing simple because there is no need to load a custom bootloader - instead, the selected electrically programmable elements can be quickly charged with an electrical charge, which is faster and more cost effective.

[0030] Electronic devices, such as mobile electronic devices (e.g., smartphones, tablet computers, etc.), electronic devices for automotive applications (e.g., automotive sensors, control units, driver-assistance systems, passenger safety or comfort systems, etc.), and appliances or devices connected to the Internet (e.g., Internet of Things (IoT) devices, etc.) have different memory requirements, which depend, among other things, on the electronic device type, the usage environment, the performance expectations, etc.

[0031] An electronic device can be decomposed into several major components: a processor (e.g., a central processing unit (CPU) or other main processor); a memory (e.g., one or more volatile or non-volatile random access memory (RAM) memory devices such as dynamic RAM (DRAM), mobile or low power double data rate synchronous DRAM (DDR SDRAM), etc.); and a storage device (e.g., a non-volatile memory (NVM) device such as flash memory, read-only memory (ROM), an SSD, an MMC, or other memory card structure or component, etc.). In certain examples, an electronic device can include a user interface (e.g., a display, a touchscreen, a keyboard, one or more buttons, etc.), a graphics processing unit (GPU), power management circuitry, a baseband processor or one or more transceiver circuits, etc.

[0032] Figure 1 An example of an environment 100 is illustrated that includes a host device 105 and a memory device 110 configured to communicate via a communication interface. The host device 105 or the memory device 110 can be included in various products 150, such as an Internet of Things (IoT) device (e.g., a refrigerator or other appliance, a sensor, a motor or actuator, a mobile communication device, an automobile, a drone, etc.) to support processing, communication, or control of the product 150.

[0033] The memory device 110 includes a memory controller 115 and a memory array 120 including, for example, a plurality of individual memory dies (e.g., three-dimensional (3D) “NAND” die stacks, one or more “NAND” dies, etc.). In 3D architecture semiconductor memory technology, vertical structures are stacked, increasing the number of layers, physical pages, and thus the density of the memory device (e.g., storage device). In examples, the memory device 110 can be a discrete memory or storage device component of the host device 105. In other examples, the memory device 110 can be part of an integrated circuit (e.g., a system on a chip (SOC), etc.) stacked or otherwise included with one or more other components of the host device 105.

[0034] One or more communication interfaces can be used to transfer data between the memory device 110 and one or more other components of the host device 105 (e.g., a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a universal flash storage (UFS) interface, an eMMC interface, etc.). TM The host device 105 can include a host system, an electronic device, a processor, a memory card reader, or one or more other electronic devices external to the memory device 110. In some examples, the host device 105 can be a device having a reference Figure 8a machine that is part of or all of the components discussed with respect to the machine 800.

[0035] The memory controller 115 can be located on one or more separate integrated circuits from the memory array 120, or can be located on the same integrated circuit. In some examples, the functionality of the memory controller 115 can be divided across multiple integrated circuits. For example, some functionality can be on a separate integrated circuit, and some functionality can be part of the controller on each memory die of the memory array 120. The memory controller 115 can receive instructions from the host device 105 and can communicate with the memory array, for example, to transfer data into (e.g., write or erase) or from (e.g., read) one or more of the memory cells, planes, sub-blocks, blocks, or pages of the memory array. Further, the memory controller 115 can also include circuitry or firmware, including one or more components or integrated circuits. For example, the memory controller 115 can include one or more memory control units, circuits, or components configured to control access across the memory array 120 and provide a translation layer between the host device 105 and the memory device 110. The memory controller 115 can include one or more input / output (I / O) circuits, lines, or interfaces to transfer data to or from the memory array 120. The memory controller 115 can include a memory manager 125 and an array controller 135.

[0036] Further, the memory manager 125 can also include circuitry or firmware, such as a number of components or integrated circuits associated with various memory management functions. For purposes of this description, example memory operations and management functions will be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory can have similar memory operations or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or recycling), error detection or correction, block deactivation, or one or more other memory management functions. The memory manager 125 can parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with operations of the memory array, etc.), or generate device commands (e.g., to complete various memory management functions) for the array controller 135 or one or more other components of the memory device 110.

[0037] The memory manager 125 can include a set of management tables 130 configured to maintain various information associated with one or more components of the memory device 110 (e.g., various information associated with a memory rank or one or more memory cells coupled to the memory controller 115). For example, the management tables 130 can include information regarding the block age, block erase count, error history, or one or more error counts (e.g., write operation error count, read bit error count, read operation error count, erase error count, etc.) for one or more blocks of memory cells coupled to the memory controller 115. In certain instances, a bit error can be referred to as an uncorrectable bit error if the number of detected errors for one or more of the error counts is above a threshold. The management tables 130 can maintain counts of correctable or uncorrectable bit errors, among other counts.

[0038] Additionally, the array controller 135 can also include circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory operations can be based on host commands received, for example, from the host device 105 or generated internally by the memory manager 125 (e.g., associated with wear leveling, error detection or correction, etc.).

[0039] The array controller 135 can include an error correction code (ECC) component 140, which can additionally include an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory controller 115 can be configured to proactively detect error occurrences (e.g., bit errors, operation errors, etc.) associated with the operation or storage of various data and recover therefrom while maintaining the integrity of data transferred between the host device 105 and the memory device 110, or maintaining the integrity of stored data (e.g., using redundant RAID storage, etc.), and can remove (e.g., deactivate) faulty storage resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.

[0040] In some instances, a memory array can include multiple NAND dies, and one or more functions of the memory controller 115 for a particular die can be implemented on-die on a die controller on the particular die. Other organizations and descriptions of control functions can also be utilized, such as a controller for each die, plane, superblock, block, page, etc.

[0041] The memory array 120 can include a number of memory cells arranged in, for example, a number of devices, semiconductor dies, planes, sub-blocks, blocks, or pages. As one example, a 48 GB TLC NAND memory device can include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32 GB MLC memory device (storing two bits of data per cell (i.e., 4 programmable states)) can include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but with half the required write time and twice the program / erase (P / E) cycles of the corresponding TLC memory device. Other examples can include other numbers or arrangements. In some examples, a memory device or a portion thereof can be selectively operated in an SLC mode or a desired MLC mode (e.g., TLC, QLC, etc.).

[0042] In operation, data is typically written to or read from the NAND memory device 110 in units of pages and erased in units of blocks. However, one or more memory operations (e.g., read, write, erase, etc.) can be performed on larger or smaller groups of memory cells as desired. The data transfer size of the NAND memory device 110 is typically referred to as a page, while the data transfer size of the host is typically referred to as a sector.

[0043] Although a page of data can include a number of bytes of user data (e.g., a data payload including a number of data sectors) and its corresponding metadata, the size of a page typically only refers to the number of bytes used to store user data. As an example, a page of data having a page size of 4 KB can include 4 KB of user data (e.g., 8 sectors in a sector size of 512 B) and several bytes (e.g., 32 B, 54 B, 224 B, etc.) of metadata corresponding to the user data, such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0044] Different types of memory cells or memory arrays 120 can provide different page sizes, or may require different amounts of metadata associated with them. For example, different memory device types may have different bit error rates, which may result in different amounts of metadata required to ensure data page integrity (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data than a memory device with a lower bit error rate). As an example, a multilevel cell (MLC) NAND flash memory device can have a higher bit error rate than its corresponding single-level cell (SLC) NAND flash memory device. Thus, an MLC device may require more bytes of metadata for error data than its corresponding SLC device.

[0045] Figure 2 This illustration shows an example of a 3D NAND architecture semiconductor memory array 200, which includes multiple memory cell strings (e.g., first A0 memory string 205A0 to third A0 memory string 207A0, first A...). n Memory String 205A n To the third A n Memory String 207A n From the first B0 memory string 205B0 to the third B0 memory string 207B0, the first B n Memory String 205B n To the third B n Memory String 207B n (etc.), by block (e.g., block A 201A, block B 201B, etc.) and sub-block (e.g., sub-block A0201A0, sub-block A... n 201A n Sub-block B0 201B0, Sub-block B n 201B n (etc.) organization. Memory array 200 represents a portion of a large number of similar structures typically found in blocks, devices, or other units of memory devices.

[0046] Each memory cell string contains multiple layers of charge storage transistors (e.g., floating gate transistors, charge trapping structures, etc.), which are stacked from source to drain in the Z direction on the source line (SRC) 235 or the source-side selected gate (SGS) (e.g., first A0 SGS 231A0 to third A0 SGS 233A0, first A... n SGS 231A n To the third A n SGS 233A n First B0SGS 231B0 to Third B0SGS 233B0, First B n SGS 231B n To the third Bn SGS 233B n and drain-side select gates (SGDs) (e.g., first A0 SGDs 226A0 through third A0 SGDs 228A0, first B0 SGDs 226B0 through third B0 SGDs 228B0, first SGDs 226B1 through third SGDs 228B1, etc.). Each memory cell string in the 3D memory array can be arranged along an X-direction as a data line (e.g., bit lines (BLs) BL0 220 through BL2 222) and along a Y-direction as a physical page. n SGD 226A n through third A n SGD 228A n , first B0 SGDs 226B0 through third B0 SGDs 228B0, first SGDs 226B n through third B n SGD 228B n and drain-side select gates (SGDs) (e.g., first A0 SGDs 226A0 through third A0 SGDs 228A0, first B0 SGDs 226B0 through third B0 SGDs 228B0, first SGDs 226B1 through third SGDs 228B1, etc.). Each memory cell string in the 3D memory array can be arranged along an X-direction as a data line (e.g., bit lines (BLs) BL0 220 through BL2 222) and along a Y-direction as a physical page.

[0047] In a physical page, each layer represents a row of memory cells and each memory cell string represents a column. A sub-block can include one or more physical pages. A block can include multiple sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). Although illustrated herein as having two blocks, each block having two sub-blocks, each sub-block having a single physical page, each physical page having three memory cell strings, and each string having 8 memory cell layers, in other examples, the memory array 200 can include more or fewer blocks, sub-blocks, physical pages, memory cell strings, memory cells, or layers. For example, each memory cell string can include more or fewer layers (e.g., 16, 32, 64, 128, etc.), and one or more additional layers of semiconductor material above or below the charge storage transistor (e.g., select gate, data line, etc.), as desired. As an example, a 48 GB TLC NAND memory device can include 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more than 4 planes per device.

[0048] Each memory cell in the memory array 200 includes a control gate (CG) that is coupled to (e.g., electrically or otherwise operatively connected to) an access line (e.g., word line (WL) WL00 210A to WL70 217A, WL01210B to WL71 217B, etc.), which collectively couple the control gates (CGs) across a particular tier or portion of tiers as needed. Particular tiers in a 3D memory array, and particular memory cells in the respective strings, can be accessed or controlled using respective access lines. Various select lines can be used to access the select gate groups. For example, the A0 SGD lines SGDA0 225A0 can be used to access the first A0 SGD 226A0 to the third A0 SGD 228A0, the A n SGD lines SGDB n 225A n 226A n 228A n 226B n 228B n 231A n 233A n 231B n 233B n 231A n 233A n 231B n 233B n 231A n 233A n 231B n 233B n 231A n 233A n 231B n 233B .

[0049] In examples, the memory array 200 can include multiple levels of semiconductor material (e.g., polysilicon, etc.) configured to couple a control gate (CG) of each memory cell or a select gate of a respective layer of the array (or a portion of the CG or select gate). A particular string of memory cells in the array can be accessed, selected, or controlled using a combination of bit lines (BLs) and select gates, and a particular memory cell of one or more layers in a particular string can be accessed, selected, or controlled using one or more access lines (e.g., word lines).

[0050] Figure 3 An example diagram illustrating a portion of a “NOR” architecture semiconductor memory array 300 including a plurality of memory cells 302 in a two-dimensional array of strings (e.g., first string 305 to third string 307) and layers (e.g., illustrated as respective word lines (WL) WL0310 to WL7 317, source side select gate (SGD) lines 325, source side select gate (SGS) lines 330, etc.). For example, the memory array 300 can illustrate a portion of a physical page of memory cells of a 3D “NOR” architecture semiconductor memory device as illustrated in FIG. 1C, for example. Figure 2 An example diagram illustrating a portion of a physical page of memory cells of a 3D “NOR” architecture semiconductor memory device as illustrated in FIG. 1C, for example.

[0051] Each string of memory cells is coupled to a source line (SRC) 335 using a respective source side select gate (SGS) (e.g., first SGS 331 to third SGS 333) and to a respective data line (e.g., first (BL) BL0320 to third bit line BL2322) using a respective drain side select gate (SGD) (e.g., first SGD 326 to third SGD 328). Although illustrated in examples of FIGS. 1C and 1D with 8 layers (e.g., using word lines (WL) WL0310 to WL7 317) and three data lines (BL0326-BL2328), other examples can include strings of memory cells with more or fewer layers or data lines as desired. Figure 3 An example diagram illustrating a portion of a physical page of memory cells of a 3D “NOR” architecture semiconductor memory device as illustrated in FIG. 1C, for example.

[0052] In a “NOR” architecture semiconductor memory array (e.g., example memory array 300), a state of a selected memory cell 302 can be accessed by sensing a current or voltage change associated with a particular data line that includes the selected memory cell. The memory array 300 can be accessed, selected, or controlled using one or more drivers (e.g., by a control circuit, one or more processors, digital logic, etc.). In examples, the one or more drivers can activate a particular memory cell or group of memory cells by driving a particular potential to one or more data lines (e.g., bit lines BL0-BL2), access lines (e.g., word lines WL0-WL7), or select gates, depending on a type of operation desired to be performed on the particular memory cell or group of memory cells.

[0053] To program or write data to a memory cell, a program voltage (Vpgm) (e.g., one or more program pulses, etc.) can be applied to a selected word line (e.g., WL4), and thus, to the control gates of each memory cell coupled to the selected word line (e.g., first control gate (CG) 341 to third control gate (CG) 343 of the memory cells coupled to WL4). The program pulse can start, for example, at 15V or near 15V, and in certain instances, can increase in magnitude during each program pulse application. When a program voltage is applied to a selected word line, a potential, e.g., a ground potential (e.g., Vss), can be applied to the data lines (e.g., bit lines) and substrate (and thus, the channel between the source and drain) of the memory cells targeted for programming, causing a transfer of charge from the channel to the floating gate of the targeted memory cell (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.).

[0054] Conversely, a pass voltage (Vpass) can be applied to one or more word lines having memory cells that are not targeted for programming, or a inhibit voltage (e.g., Vcc) can be applied to the data lines (e.g., bit lines) having memory cells that are not targeted for programming, to, for example, inhibit a transfer of charge from the channel to the floating gate of such non-targeted memory cells. The pass voltage can be variable, for example, depending on the proximity of the applied pass voltage to the word line targeted for programming. The inhibit voltage can include a supply voltage (Vcc), e.g., a voltage from an external power source or supply (e.g., a battery, an AC-to-DC converter, etc.) relative to a ground potential (e.g., Vss).

[0055] As an example, if a program voltage (e.g., 15V or higher) is applied to a particular word line (e.g., WL4), a pass voltage of 10V can be applied to one or more other word lines, e.g., WL3, WL5, etc., to inhibit programming of non-targeted memory cells, or to preserve the values stored on such non-targeted memory cells. As the distance between the applied program voltage and the non-targeted memory cells increases, the pass voltage needed to inhibit programming of the non-targeted memory cells can decrease. For example, with a program voltage of 15V applied to WL4, a pass voltage of 10V can be applied to WL3 and WL5, a pass voltage of 8V can be applied to WL2 and WL6, a pass voltage of 7V can be applied to WL1 and WL7, etc. In other instances, the pass voltage or number of word lines, etc., can be higher or lower, or more or less.

[0056] A sense amplifier 360 coupled to one or more of the data lines (e.g., first, second, or third bit lines (BL0-BL2) 320-322) can detect the state of each memory cell in the respective data line by sensing the voltage or current on the particular data line.

[0057] Between the application of one or more program pulses (e.g., Vpgm), a verify operation can be performed to determine whether a selected memory cell has reached its intended programmed state. If the selected memory cell has reached its intended programmed state, it can be inhibited from further programming. If the selected memory cell has not reached its intended programmed state, further program pulses can be applied. If the selected memory cell has not reached its intended programmed state after a particular number of program pulses (e.g., a maximum number), the selected memory cell or a string, block, or page associated with such selected memory cell can be marked as defective.

[0058] To erase a memory cell or group of memory cells (e.g., erasing is typically performed in units of blocks or sub-blocks), an erase voltage (Vers) (e.g., typically Vpgm) can be applied to the substrate (and thus the channel between the source and drain) of the memory cell targeted for erasure (e.g., using one or more bit lines, select gates, etc.), while the word line of the targeted memory cell is held at a potential, e.g., a ground potential (e.g., Vss), resulting in charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the floating gate to the channel of the targeted memory cell.

[0059] Figure 4 An example block diagram of a memory device 400 is illustrated, including a memory array 402 having a plurality of memory cells 404, and one or more circuits or components to provide communication with or perform one or more memory operations on the memory array 402. The memory device 400 can include a row decoder 412, a column decoder 414, a sense amplifier 420, a page buffer 422, a selector 424, an input / output (I / O) circuit 426, and a memory control unit 430.

[0060] The memory cells 404 of the memory array 402 can be arranged in blocks, such as a first block 402A and a second block 402B. Each block can include sub-blocks. For example, the first block 402A can include a first sub-block 402A0 and a second sub-block 402A n , and the second block 402B can include a first sub-block 402B0 and a second sub-block 402B nEach sub-block can include a number of physical pages, each page including a number of memory cells 404. Although illustrated herein as having two blocks, each block having two sub-blocks, and each sub-block having a number of memory cells 404, in other examples, the memory array 402 can include more or fewer blocks, sub-blocks, memory cells. In other examples, the memory cells 404 can be arranged into a number of rows, columns, pages, sub-blocks, blocks, etc., and accessed using, for example, access lines 406, first data lines 410, or one or more select gates, source lines, etc.

[0061] The memory control unit 430 can control memory operations of the memory device 400 according to one or more signals or instructions received on control lines 432, such as including one or more clock signals or control signals indicating a desired operation (e.g., write, read, erase, etc.), or address signals (A0 to AX) received on one or more address lines 416. One or more devices external to the memory device 400 can control the values of the control signals on the control lines 432 or the address signals on the address lines 416. Examples of devices external to the memory device 400 can include, but are not limited to, a host, a memory controller, a processor, or Figure 4 one or more circuits or components not illustrated in FIG. 4.

[0062] The memory device 400 can use the access lines 406 and the first data lines 410 to transfer data to or from one or more of the memory cells 404 (e.g., write or erase, or read). The row decoder 412 and the column decoder 414 can receive and decode address signals (A0 to AX) from the address lines 416, can determine which of the memory cells 404 are to be accessed, and can provide signals to one or more of the access lines 406 (e.g., one or more of a plurality of word lines (WL0 to WLm)) or the first data lines 410 (e.g., one or more of a plurality of bit lines (BL0 to BLn)).

[0063] The memory device 400 can include sensing circuitry, such as the sense amplifiers 420, configured to determine a value of data (e.g., read), or to determine a value of data to be written to the memory cells 404 using the first data lines 410. For example, in a selected string of memory cells 404, one or more of the sense amplifiers 420 can read a logic level in a selected memory cell 404 in response to a flow of a read current through the selected string in the memory array 402 to the data line 410.

[0064] One or more devices external to the memory device 400 can communicate with the memory device 400 using the I / O lines (DQ0 through DQN) 408, the address lines 416 (A0 through AX), or the control lines 432. The input / output (I / O) circuitry 426 can transfer values of data into or out of the memory device 400 using the I / O lines 408 in accordance with, for example, the control lines 432 and the address lines 416, for example, into or out of the page buffer 422 or the memory array 402. The page buffer 422 can store data received from the one or more devices external to the memory device 400 prior to the data being programmed into the relevant portion of the memory array 402, or can store data read from the memory array 402 prior to the data being transferred to the one or more devices external to the memory device 400.

[0065] The column decoder 414 can receive address signals (A0 through AX) and decode them into one or more column select signals (CSEL1 through CSELn). The selector 424 (e.g., a selection circuit) can receive the column select signals (CSEL1 through CSELn) and select data in the page buffer 422 representing values of data to be read from or programmed into the memory cells 404. The selected data can be transferred between the page buffer 422 and the input / output (I / O) circuitry 426 using the second data lines 418. In some examples, a flash translation layer (not shown) can map addresses provided by a host to physical memory addresses used by the row decoder 412 and the column decoder 414 to read data in the memory array 402.

[0066] The memory control unit 430 can receive positive and negative supply signals, such as a supply voltage (Vcc) 434 and a negative supply voltage (Vss) 436 (e.g., a ground potential), from an external power source or supply (e.g., an internal or external battery, an AC-to-DC converter, etc.). In certain examples, the memory control unit 430 can include a regulator 428 to internally provide the positive or negative supply signals.

[0067] As previously described, a controller can be initialized by a software object known as a bootloader. Part of this initialization can include loading and executing one or more firmware objects. In some examples, one firmware object can load a second firmware object, and so on. These firmware objects can be quickly located by the bootloader or other firmware objects with the aid of values for firmware search parameters that are programmed into the device by configuring one or more electrically programmable elements (e.g., during manufacturing). During operation of the memory device, the one or more electrically programmable elements can receive an input signal and generate an output signal that is input to a microprocessor of the controller. The output signal for a given input can depend on the configuration of the electrically programmable element. The signal is then read by the bootloader executing on the microprocessor and converted to a value for the firmware search parameter.

[0068] During manufacturing, the configuration of the electrically programmable element can be changed by applying an electrical signal above a voltage or current threshold to the electrically programmable element. For example, if the electrically programmable element includes an electrical fuse, then the electrically programmable element can be reconfigured by blowing one or more electrical fuses. Blowing the electrical fuse changes the output signal fed to the microprocessor of the controller in response to the input signal of the electrically programmable element.

[0069] As noted, the output signal of the electrically programmable element can select each of one or more values for one or more firmware search parameters, and the output can be changed by reconfiguring the electrically programmable element. For example, if all of the electrically programmable elements default to carrying the signal (e.g., all register as "high") when a signal is applied to the electrically programmable elements, then by applying an electrical signal above a threshold voltage or current to one of the electrically programmable elements, a fuse can blow and the signal can no longer pass through the microprocessor and the signal goes low. By using multiple electrically programmable elements and by applying electrical power above a threshold current or voltage to select one of the electrically programmable elements, a manufacturer can specify one or more values for one or more firmware search parameters. For example, if two electrically programmable elements are used, then in an initial state each electrically programmable element can output a high signal. By applying electrical power above a threshold voltage or current, one or both can be changed to a second state that outputs a low signal (e.g., a fuse blows and stops conducting the input signal to the output). Thus, if the two electrically programmable elements are mapped to a particular firmware search parameter, this can provide up to 4 selectable possible values.

[0070] Figure 5A block diagram of an example memory device 510 is illustrated in accordance with some examples of the present disclosure. The memory device 510 can be one example of the memory device 110. The memory controller 515 can be an example of the memory controller 115. Similarly, the memory cell array 545 can be a "NAND" memory cell managed by the memory controller 515. The memory cell array 545 can be organized as a 2D "NAND" array, a 3D "NAND" array (e.g., 3D "NAND"), etc. For example, the memory cell array 545 can be organized as shown for the memory array 402 of Figure 2 , 3 and / or for the memory array 402 of Figure 4 . The memory cell array 545 can include system storage for storing the firmware object 550. The memory cell array 545 can also store user data. Thus, the memory cell array 545 can be a general purpose memory cell for user storage, or can be a dedicated cell for storing the firmware object 550.

[0071] The memory device 510 can include one or more electrically programmable elements 535. The electrically programmable elements 535 can provide one or more electrical signals 595 to the processor 555 that specify one or more values for one or more respective firmware search parameters. The electrically programmable elements 535 can be part of the memory controller 515, or can be external to the memory controller 515. For example, the input signals to the electrically programmable elements can be modified by the configuration of the electrically programmable elements 535. The electrically programmable elements 535 can be reconfigured (e.g., during manufacturing) using one or more electrical pulses applied to one or more of the electrically programmable elements. For example, the electrically programmable elements 535 can include one or more fuses, anti-fuses, and / or e-fuses that change the output of the electrically programmable elements 535, and thus the value of the signal 595, based on whether a voltage or current above a specified threshold is applied to a particular fuse, anti-fuse, and / or e-fuse.

[0072] Signal 595 is applied as input to processor 555 and specifies one or more values for one or more firmware search parameters. Upon initial power-up or reset of memory device 510, processor 555 can be configured to access instructions at a hard-coded address in read-only memory (ROM) 575 of operating memory 570 of memory controller 515. A bootloader object 580 including executable instructions can be placed at this address. Bootloader object 580 includes one or more instructions that, when executed by processor 555, cause the processor to perform operations as described herein. Bootloader object 580 reads signal 595 from electrically programmable element 535. The signal can be a direct input to processor 555 or a signal that is accessible by processor 555 using a bus or other interconnect, which can involve other components. Signal 595 can specify one or more values for one or more firmware search parameters that bootloader object 580 uses to search for a valid firmware image (e.g., firmware object 550) in memory cell array 545. In some examples, electrically programmable element 535 can be on the same semiconductor package as memory controller 515 and can be reconfigured using one or more input lines to the memory controller.

[0073] Operating memory 570 can include random access memory (RAM) and read-only memory (ROM). Operating memory 570 can store instructions, data structures, operating storage, and other storage used by processor 555 in executing bootloader object 580 and firmware object 550.

[0074] Because memory controller 515 can be used in a variety of different memory devices, the location of firmware object 550 in memory cell array 545 can be different in different memory devices. Additionally, as previously described, some memory cells in memory cell array 545 can be defective, which can result in firmware object 550 being placed at a different location.

[0075] The firmware search parameters can include an offset from a first search location hard-coded into the bootloader. In some examples, the offset parameter can specify an offset of 0, 2, 4, or 8 pages from a default location in memory cell array 545. This can be used in cases where some memory cells in memory cell array 545 have manufacturing defects that make them unusable for storing firmware objects, so it is necessary to place firmware objects at an offset from the default location. In the case of NAND memory chips that are unusable due to a location defect required to store firmware (while still having enough memory cells to meet the desired capacity), the above scenario can improve yield and reduce waste.

[0076] The firmware search parameters can include a step size selection. If a valid firmware object is not found in the first location, the bootloader increments the physical address by the step size and looks in this new location. In some instances, the step size can be selected between 2048 and 4096 (pages).

[0077] The firmware search parameters can include a number of locations to be tried. The number of locations to be tried can be selected by two electrically programmable elements 535, allowing for 2, 4, 8, or 16 locations to be selected (e.g., 00 maps to 2 locations, 01 maps to 4 locations, 10 maps to 8 locations, and 11 maps to 16 locations). Thus, the bootloader first looks in the starting location, and then if a valid firmware image is not found in the starting location, an offset equal to the step size is added and looked at there. This continues for a number of times specified by the value of the number of locations to be tried firmware search parameter. In an instance, if the parameter is set to a value that selects 16 times, the bootloader looks in 16 different locations, each of which is a certain "offset" distance from the previous location.

[0078] The firmware search parameters can also include a read retry option, which specifies options regarding how to retry reading firmware at a particular location. For example, when the controller reads a location in NOR to find a firmware object, the read can fail. The failure can be caused by an uncorrectable error correction code (UECC), a checksum mismatch, etc. For example, a first option can select the number of times to retry reading firmware at a particular location. A second firmware search option can specify a first read retry voltage to be tried, and a third firmware search option can specify a voltage step. Thus, the first read retry uses the first read retry voltage, and the second read retry adds the voltage step to the first read retry voltage, etc., until the firmware is successfully read or the number of read retries has been tried. Once the bootloader has tried the specified number of read retries without obtaining valid firmware, the memory device will either move to the next location or give up, depending on whether the maximum number of locations to be tried has been exceeded.

[0079] If the bootloader object 580 finds a firmware object 550, the bootloader can cause the processor to load the firmware object 550 or a portion of the firmware object 550 into random access memory (RAM) 590. The bootloader object 580 can complete execution and cause the processor to begin executing the firmware object 550. The firmware object 550 includes instructions that, when executed by the processor 555, cause the processor 555 to perform certain operations. For example, the firmware can be responsible for implementing software for host interface, host command processing, memory management, etc.

[0080] Figure 6A flowchart of a method 600 performed by a processor of a memory device for searching for a firmware object 550 is illustrated in accordance with some examples of the present disclosure. Once power is applied to the memory device, at operation 602, the processor executes instructions at a default address in working memory. The instructions can be part of a bootloader, and thus the bootloader begins execution.

[0081] At operation 604, the bootloader can then determine the value of the firmware search parameter. For example, by reading an input signal from an electrically programmable element 535. As described, the electrically programmable element 535 can be a fuse, an antifuse, an e-fuse, etc. One or more of the fuses, antifuses, and / or e-fuses can be blown (automatically or manually) during manufacturing to provide a firmware configuration parameter to the bootloader. In some examples, the bootloader can convert the signal from the electrically programmable element into a value for various parameters according to a translation programmed into the bootloader (e.g., the signal can be 11 can indicate to search 16 different memory locations).

[0082] At operation 606, the bootloader can determine a first location to look for in memory based on the value of the firmware search parameter. For example, the bootloader can have a default memory location (e.g., memory address) programmed into ROM (e.g., in instructions). The memory address can point to one or more memory units of the memory device. The value of the firmware search parameter can specify an offset, which can be 2 bits, that specifies an offset of 0, 2, 4, or 8 pages from the default location. The firmware object can be moved to different locations, and the offset bits can be set (e.g., fuses can be blown) to indicate the offset location. Thus, in one example, the first location can be the default location offset by any offset location specified in the firmware search parameter.

[0083] At operation 608, the first location can be read. If the memory is successfully read at operation 610— e.g., there are no uncorrectable error correction code (ECC) errors, then at operation 612, the firmware image is checked. For example, one or more of the following are compared or otherwise verified against expected values, etc.: hash value, parity value, digital certificate, firmware version, etc. If the firmware is invalid (e.g., it fails this check), then the flow proceeds to operation 624. If the firmware is valid, then at operation 614, the firmware is loaded into RAM and executed. The firmware can be executed immediately, or after the bootloader further processes and / or clears.

[0084] If the read is not successful at operation 610 (e.g., uncorrectable ECC error), a read retry loop (including operations 616, 618, 620, 622, and 623) begins. At operation 616, the bootloader determines a first read retry level (e.g., voltage level) to be attempted. For example, a default voltage level. In other examples, the firmware search parameters can have a value for a read retry parameter, such as an option for selecting a first read retry level. At operation 618, the first read retry is attempted.

[0085] If the read is successful at operation 620, the bootloader determines at operation 612 whether the read was of valid firmware, and if the firmware is valid, the firmware is executed at operation 614. If the firmware is not valid, flow proceeds to operation 624.

[0086] If the read is not successful at operation 620 (e.g., uncorrectable ECC), the bootloader determines at operation 622 whether the number of read retries attempted exceeds a maximum number of read retries for the read retry loop. The maximum number of read retries for the read retry loop can be a configurable value in the firmware search parameters set by the electrically programmable element. If the number of read retries attempted is greater than the maximum value, flow proceeds to operation 624.

[0087] If the number of attempts is less than the maximum number of read retries for the read retry loop, the read retry level can be incremented by a read retry step size at operation 623. In some examples, the read retry step size can be a value specified in the firmware search parameters set by the electrically programmable element. Flow proceeds to operation 618, where the memory address is read using the incremented read retry level (e.g., voltage level) determined at operation 623.

[0088] If valid firmware is not found at operation 612 (but the memory was properly read), or the maximum number of read retries have been attempted without success, a check is made at operation 624 to determine whether the number of addresses attempted is greater than a maximum number of addresses. The maximum number of addresses to be attempted can be specified as a value in the firmware search parameters set by the electrically programmable element. If the number of locations attempted exceeds the threshold, the operation will terminate and the bootloader will not find a firmware image. If the number of locations attempted is less than the maximum number of locations, a next address is determined at operation 626. For example, the current address is offset by a firmware search step size parameter. The firmware search step size can be specified as a value in the firmware search parameters set by the electrically programmable element. Flow then continues to operation 608.

[0089] Figure 7 A flowchart of a method 700 of loading a firmware object according to some examples of the present disclosure. Figure 7 ToFigure 6 A simplified version of the flowchart of FIG. 6. At operation 710, the processor of the controller can determine one or more locations of the firmware image in the NAND memory. This can be done according to one or more values of one or more first firmware search parameters, indicated by a first set of electrically programmable elements. For example, the controller can read one or more signals from one or more of the first set of electrically programmable elements to determine a starting location. The starting location can be based on a default location (e.g., a location programmed into the bootloader) and an offset determined based on one or more signals from one or more of the first set of electrically programmable elements. If the firmware object is not at the first location, other locations can be determined. The other locations can be determined based on the current location and values of other parameters of the first firmware search parameters (e.g., a step size), which can be determined based on other elements of the first set of electrically programmable elements. In some examples, each of the values of the one or more firmware search parameters can be specified by one or more electrically programmable elements, and each electrically programmable element can specify the value of one, a portion of one, multiple, or a portion of multiple of the firmware search parameters. In some examples, the other firmware search parameters can include one or more electrically programmable elements that specify a bitmask to skip some of a range of locations obtained by the start, stop, and step options.

[0090] At operation 715, the locations—e.g., the first location, then the second location, and so on—may be searched until a valid firmware image is found or until the bootloader has attempted the maximum number of locations specified by the value of one of the firmware search parameters. As part of the search, the controller can read the NAND memory and, if necessary, perform one or more read retry procedures. The read retry procedures can be done according to one or more values of one or more second firmware search parameters, indicated by a second set of electrically programmable elements. In some examples, the first and second firmware search parameters and the first and second sets of electrically programmable elements can be different. At operation 720, if a valid firmware image is found, the bootloader can cause execution of the valid firmware image. In some examples, this can be done by the bootloader loading the firmware into RAM and causing the current instruction pointer of the processor of the controller to jump to the location of the firmware in the RAM.

[0091] Figure 8 A flowchart of a method 800 performed by a processor of a memory device for searching for a firmware object 550 according to some examples of the disclosure. Figure 8 The flowchart of FIG. 8 attempts all locations before increasing the read retry level in the read retry procedure. This is different from the flowchart of FIG. 6, where a read retry procedure has been completed for a particular location before moving to the next location.

[0092] Once power is applied to the memory device, at operation 802, the processor executes an instruction at a default address in the working memory. This instruction can be part of a bootloader, and thus the bootloader begins execution. At operation 804, the bootloader can then determine the value of the firmware search parameter. For example, by reading an input signal from the electrically programmable element 535. As described, the electrically programmable element 535 can be a fuse, anti-fuse, e-fuse, etc. One or more of the fuses, anti-fuses, and / or e-fuses can be blown (automatically or manually) during manufacturing to provide the firmware configuration parameter to the bootloader. In some examples, the bootloader can convert the signal from the electrically programmable element into a value for the various parameters according to a translation programmed into the bootloader (e.g., the signal can be 11 can indicate to search 16 different memory locations).

[0093] At operation 806, the bootloader can determine a first location to look for in the memory based on the value of the firmware search parameter. For example, the bootloader can have a default memory location (e.g., memory address) programmed into the ROM (e.g., in the instructions). The memory address can point to one or more memory cells of the memory device. The value of the firmware search parameter can specify an offset, which can be 2 bits, that specifies an offset of 0, 2, 4, or 8 pages from the default location. The firmware object can be moved to different locations, and the offset bits can be set (e.g., fuses can be blown) to indicate the offset location. Thus, in one example, the first location can be the default location offset by any offset location specified in the firmware search parameter.

[0094] At operation 808, the first location can be read. If the memory is successfully read at operation 810 - e.g., there are no uncorrectable error correction code (ECC) errors, then at operation 812, the firmware image is checked. For example, one or more of the following are compared or otherwise verified against expected values, etc.: hash value, parity value, digital certificate, firmware version, etc. If the firmware is valid, then at operation 814, the firmware is loaded into RAM and executed. The firmware can be executed immediately, or after the bootloader further processes and / or clears.

[0095] If the firmware is invalid at operation 810 (e.g., it fails this check), or the read is unsuccessful, then flow continues to operation 816. At operation 816, the bootloader determines whether all locations have been checked. If all locations have not been checked, then at operation 818, the bootloader determines the next address to be checked based on the firmware search parameters. For example, an offset value specified by the firmware search parameters is added to the current location. Flow then continues to operation 808, where the new memory location is read, checked at operations 810 and 812 to determine whether a valid firmware image was found, and if a valid firmware image was found, the firmware is executed at operation 814.

[0096] The new locations are read and checked until valid firmware objects are executed at operation 814, or until the number of locations to be tried has been exhausted at operation 816. When the number of locations to be tried has been exhausted, at operation 820, the location system can determine whether the number of times the system has tried each location exceeds the maximum number of read retry cycles. If the answer is yes, then processing terminates. If the number of times the system has tried each location does not exceed the maximum number of read retry cycles at operation 820, then at operation 822, the system can increment the read retry level indicated by the value of the read retry step in the firmware search parameters. The system then again tries all locations with the increased read retry level. Each time all locations are tried, the read retry level is incremented until a valid image is found or until the number of read retry cycles is exhausted at operation 820.

[0097] Figure 9A block diagram of an example machine 900 is illustrated upon which any one or more of the techniques (e.g., methodologies) discussed herein can perform. In alternative embodiments, the machine 900 can operate as a standalone device or can be connected (e.g., networked) to other machines. In a networked deployment, the machine 900 can operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine 900 can act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine 900 can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, an IoT device, an automotive system, a mainframe, a server, a client, or any machine capable of executing instructions (sequential or otherwise) that define actions to be taken by that machine. Machine 1000 can exist in a memory device (e.g., processor, memory, mass storage device, etc.). Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, e.g., cloud computing, software as a service (SaaS), other computer cluster configurations.

[0098] As described herein, examples can include, or can operate by, logic, a component, device, package, or mechanism. Circuitry is a collection (e.g., set) of circuits implemented in tangible entities that include hardware (e.g., simple circuits, gates, logic, etc.). Circuitry membership can be flexible over time and underlying hardware variability. Circuitries include members that may, alone or in combination, perform specific tasks when operating in a collection of circuitry and individual members can be new when different members are selected or already exist in the circuitry collection. In an example, humans can be considered circuitry members to the extent that they integrate with the circuitry collection. Circuitry can be synchronized in various ways including by at least partially sharing at least one of a physical base, a physical interface, a memory, a bus, a signal, a virtual machine, a power supply, or a controller, among other possibilities. Where multiple of such physical or virtual entities are present (for example, in a shared system, a distributed system, a multi-processor system, or in a multi-tenant system), a bus, physical or virtual, can interconnect the physical or virtual entities. A bus can include any parallel, serial, networked, or other communication mechanism, or a combination thereof. In an example, multiple physical entities can be located in the same physical housing or in different physical housings. A physical base can be a physical entity that supports a physical interface. A physical interface can be a physical connection on a physical base or it can be a virtual connection that does not include a corresponding physical connection on a physical base. Circuitry can interact or share data or other operations with each other or with external entities.

[0099] The machine (e.g., computer system) 900 (e.g., host device 105, memory device 110, etc.) can include a hardware processor 902 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, e.g., memory controller 115, etc.), a main memory 904 and a static memory 906, some or all of which can communicate with one another via an interlink (e.g., bus) 908. The machine 900 can further include a display unit 910, an alphanumeric input device 912 (e.g., a keyboard), and a user interface (UI) navigation device 914 (e.g., a mouse). In an example, the display unit 910, input device 912 and UI navigation device 914 can be a touch screen display. The machine 900 can additionally include a storage device (e.g., drive unit) 921, a signal generation device 918 (e.g., a speaker), a network interface device 920, and one or more sensors 916, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine 900 can include an output controller 928, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

[0100] The machine-readable medium 922 can include a storage device 921 on which is stored one or more sets of data structures or instructions 924 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 924 can also reside, completely or at least partially, within the main memory 904, within static memory 906, or

[0101] While the machine-readable medium 922 is illustrated as a single medium, the term "machine-readable medium" can include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store the one or more instructions 924.

[0102] The term "machine-readable media" can include any medium capable of storing, encoding, or transporting instructions for execution by machine 900 and causing machine 900 to perform any one or more of the techniques of the present invention, or any medium capable of storing, encoding, or transporting data structures used by or associated with such instructions. Non-limiting examples of machine-readable media can include solid-state memory as well as optical and magnetic media. In examples, massed machine-readable media includes machine-readable media having a plurality of particles having invariant (e.g., rest) masses. Therefore, massed machine-readable media is not a transient propagation signal. Specific examples of massed machine-readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0103] Instructions 924 (e.g., software, programs, operating system (OS), etc.) or other data stored on storage device 921 can be accessed via memory 904 for use by processor 902. Memory 904 (e.g., DRAM) is generally faster but volatile, and therefore a different type of storage from storage device 921 (e.g., SSD), suitable for long-term storage, including when in a "shutdown" state. Instructions 924 or data being used by user or machine 900 are typically loaded into memory 904 for use by processor 902. When memory 904 is full, virtual space from storage device 921 can be allocated to supplement memory 904; however, since storage device 921 is generally slower than memory 904, and write speeds are typically at least twice as slow as read speeds, using virtual memory can significantly degrade the user experience (compared to memory 904, e.g., DRAM) due to storage device latency. Furthermore, using storage device 921 for virtual memory can significantly reduce the available lifespan of storage device 921.

[0104] Compared to virtual memory, virtual memory compression (e.g., The kernel feature “ZRAM” uses a portion of memory as a compacted block storage device to avoid paging to memory device 921. Paging occurs within the compacted block until it is necessary to write such data to memory device 921. Virtual memory compaction increases the available size of memory 904 while reducing wear and tear on memory device 921.

[0105] Storage devices optimized for mobile electronic devices or mobile storage devices traditionally include MMC solid-state storage devices (e.g., microSD cards). TM(e.g., cards, etc.) MMC devices contain numerous parallel interfaces (e.g., 8-bit parallel interfaces) with the host device and are typically removable and decoupled from the host device. In contrast, eMMC... TM The device is attached to the circuit board and is considered a component of the host device, where the read speed is comparable to that based on Serial ATA. TM Comparable to SSDs using Serial ATA (Advanced Technology) accessories or SATA. However, the demands on mobile device performance continue to increase, such as for fully enabling virtual or augmented reality devices and taking advantage of ever-growing network speeds. In response to this demand, storage devices have transitioned from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices (including the controller and firmware) communicate with host devices using a Low Voltage Differential Signaling (LVDS) serial interface with dedicated read / write paths, thereby further improving read / write speeds.

[0106] The transmission medium may be further used to transmit or receive instructions 924 on network 926 via network interface device 920 utilizing any of a variety of transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., referred to as…). The Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard series is known as The network interface device 920 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to the network 926. In an example, the network interface device 920 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered as any intangible medium capable of storing, encoding, or carrying instructions executed by the machine 900, and includes digital or analog communication signals or other intangible media to facilitate communication of such software.

[0107] The above detailed description includes references to the accompanying drawings, which form a part of this detailed description. The drawings show, by way of illustration, specific embodiments in which the application can be practiced. These embodiments are also referred to as "examples." Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0108] In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, independent of any other instances or "at least one." In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" can mean "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0109] In various examples, components, controllers, processors, units, engines, or tables described herein can include, among other things, physical circuitry or firmware stored on a physical device, as described herein. As used herein, "processor" means any type of computational circuit, such as, but not limited to, a microprocessor, microcontroller, graphics processor, digital signal processor (DSP), or any other type of processor or processing circuit, including a group of processors or multi-core devices.

[0110] The term "horizontal" as used in this document is defined as a plane or surface parallel to the normal plane or surface of a substrate, e.g., the plane of an underlying wafer or die, regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions such as "on," "over," and "under" are defined with respect to the normal plane or surface at the top or exposed surface of the substrate, regardless of the orientation of the substrate; and while "on" is intended to imply direct contact of one structure relative to another structure on which it is located (in the absence of explicit indication to the contrary); the terms "over" and "under" are expressly intended to identify the relative placement of structures (or layers, features, etc.), which explicitly includes (but is not limited to) identifying direct contact between structures, unless such direct contact is explicitly identified. Similarly, the terms "over" and "under" are also not limited to horizontal orientations, as a structure can be "over" a referenced structure if it is the outermost portion of the structure at issue at some point in time, even if the structure extends vertically relative to the referenced structure, rather than in a horizontal orientation.

[0111] The terms "wafer" and "substrate" are used herein generally to refer to any structure on which integrated circuitry is formed, and also to refer to such structures during various phases of integrated circuit fabrication. Accordingly, the following detailed description is not to be considered limiting in nature, and the scope of the various embodiments is defined only by the appended claims, along with equivalents of this claims as authorized by law.

[0112] Various embodiments in accordance with the present disclosure and described herein include memory that utilizes vertical structures of memory cells (e.g., NAND strings of memory cells). As used herein, directional adjectives will take with respect to a surface of a substrate on which the memory cells are formed (i.e., a vertical structure will be considered to extend away from the substrate surface, a bottom end of the vertical structure will be considered to be the end closest to the substrate surface and a top end of the vertical structure will be considered to be the end furthest from the substrate surface).

[0113] As used herein, directional adjectives such as horizontal, vertical, normal, parallel, perpendicular, etc. can refer to relative orientations and are not intended to require strict adherence to particular geometric properties, unless otherwise noted. For example, as used herein, a vertical structure need not be strictly perpendicular to a surface of a substrate, but can be generally perpendicular to a surface of a substrate and can form an acute angle (e.g., between 60 degrees and 120 degrees, etc.) with a surface of a substrate.

[0114] In some embodiments described herein, different doping configurations can be applied to the source side select gate (SGS), control gate (CG), and drain side select gate (SGD), each of which in this example can be formed of or at least include polysilicon, thus enabling these layers (e.g., polysilicon, etc.) to have different etch rates when exposed to an etching solution. For example, in a process of forming a monolithic pillar in a 3D semiconductor device, the SGS and CG can form a recess, while the SGD can remain less recessed or even un-recessed. Thus, these doping configurations can enable selective etching into different layers (e.g., SGS, CG, and SGD) in a 3D semiconductor device by using an etching solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0115] As used herein, operating a memory cell includes reading from, writing to, or erasing the memory cell. An operation that places a memory cell in an intended state is referred to herein as "programming," and can include both writing to or erasing from the memory cell (e.g., a memory cell can be programmed to an erased state).

[0116] According to one or more embodiments of the present disclosure, a memory controller (e.g., processor, controller, firmware, etc.) located internal or external to a memory device can determine (e.g., select, set, adjust, calculate, change, clear, communicate, adapt, derive, define, utilize, modify, apply, etc.) a number of wear cycles or a wear state (e.g., record wear cycles, count occurrences of operations of the memory device, track operations of the memory device initiated, evaluate memory device characteristics corresponding to the wear state, etc.).

[0117] According to one or more embodiments of the present disclosure, a memory access device can be configured to provide wear cycle information to the memory device with each memory operation. Memory device control circuitry (e.g., control logic) can be programmed to compensate for memory device performance changes corresponding to the wear cycle information. The memory device can receive the wear cycle information and determine one or more operational parameters (e.g., values, characteristics) in response to the wear cycle information.

[0118] It will be understood that when an element is referred to as being "on" another element, "connected to" another element or "coupled to" another element, it can be directly on, directly connected to or directly coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements or layers present. By the term "coupled" or "directly coupled" as used herein, it is meant to include the possibility that two elements can be coupled or directly coupled to each other.

[0119] Method examples described herein can be machine or computer- implemented at least in part. Some examples can include a computer- readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level languages code, or the like. Such code can include computer readable instructions for performing various methods. The code can form portions of computer program products. Further, the code can be tangibly embodied in one or more volatile or non-volatile tangible computer-readable media during execution or at other times. Examples of these tangible computer- readable media can include, but are not limited to, volatile or non-volatile memory devices, such as a hard disk, a removable magnetic disk, a removable optical disk (such as a compact disk or a digital video disk), a magnetic cassette, memory cards or sticks, a random access memory (RAM), a read-only memory (ROM), a solid state drive (SSD), a universal flash storage (UFS), an embedded MMC (eMMC) device, and the like.

[0120] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments will be readily ascertainable by persons of ordinary skill in the art upon reviewing the above description. This Abstract is included to provide a brief overview of the disclosure. It is not intended to be used to interpret or limit the scope or meaning of the claims. Furthermore, in the above Detailed Description, various features can be grouped together or described in a single embodiment for the purpose of streamlining the disclosure. This should not be interpreted as intending that an disclosed feature is a prerequisite to any claim unless expressly recited in that claim. Rather, inventive subject matter can be claimed in less than all features of a particular disclosed embodiment. The scope of the claims should therefore be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the claims, means-plus-function, step-plus-function, and / or other means-or-step for performing a function limitations are expressly incorporated under 35 U.S.C. § 112(f) to the extent possible, and other limitation will be treated as being implied under 35 U.S.C. § 112(f) to the extent possible.

[0121] Other Notes and Examples

[0122] Example 1 is a memory device comprising: a first set of one or more electrically programmable elements indicative of values of one or more first firmware search parameters; a second set of one or more electrically programmable elements indicative of values of one or more second firmware search parameters; and a processor configured to perform operations comprising: determining one or more possible locations of a firmware image in memory cells of the memory device according to the values of the one or more first firmware search parameters indicated by the first set of one or more electrically programmable elements; searching the one or more possible locations for a valid firmware image by reading the memory cells at the one or more possible locations according to the values of the one or more second firmware search parameters indicated by the second set of one or more electrically programmable elements; and causing execution of the firmware image in response to reading a valid firmware image.

[0123] In Example 2, the subject matter of Examples 1 includes, wherein the first and second set of one or more electrically programmable elements comprises one of: a fuse, an anti-fuse, an electrical fuse.

[0124] In Example 3, the subject matter of Examples 1-2 includes, wherein one of the first firmware search parameters is a firmware search step size, wherein the firmware search step size specifies an offset between possible locations of the firmware image.

[0125] In Example 4, the subject matter of Examples 1-3 includes, wherein one of the first firmware search parameters is a number of possible locations to be tried.

[0126] In Example 5, the subject matter of Examples 1-4 includes, wherein one of the first firmware search parameters is an offset from a default possible location.

[0127] In Example 6, the subject matter of Examples 1-5 includes, wherein one of the second firmware search parameters is a number of read retry loops, the number of read retry loops specifying a number of times to attempt searching each of the one or more possible locations.

[0128] In Example 7, the subject matter of Examples 1-6 includes, wherein one of the second firmware search parameters is a first read retry to be tried.

[0129] In Example 8, the subject matter of Examples 1-7 includes, wherein one of the second firmware search parameters is a read retry step size.

[0130] In Example 9, the subject matter of Examples 1-8 includes, wherein the operation of determining one or more possible locations of a firmware image in memory cells comprises determining a first possible location using a default location and a value of a first parameter of the first firmware search parameters specifying an initial offset.

[0131] In Example 10, the subject matter of Example 9 includes, wherein determining the one or more possible locations of the firmware image in the memory unit comprises determining a second possible location based on the first possible location and a value of a second parameter of the first firmware search parameter that specifies a firmware search step size.

[0132] In Example 11, the subject matter of Examples 1-10 includes, wherein the first and second set of one or more electrically programmable elements and the processor are part of a controller.

[0133] In Example 12, the subject matter of Examples 1-11 includes, wherein the processor is part of the controller, and the first and second set of one or more electrically programmable elements are separate from the controller.

[0134] In Example 13, the subject matter of Examples 1-12 includes, wherein the memory unit is a NAND memory unit.

[0135] Example 14 is a machine-readable medium comprising instructions that, when executed by a processor of a memory device, cause the processor to perform operations comprising: determining one or more possible locations of a firmware image in a memory unit of the memory device according to values of one or more first firmware search parameters indicated by a first set of one or more electrically programmable elements; searching the one or more possible locations for a valid firmware image by reading the memory unit at the one or more possible locations according to values of one or more second firmware search parameters indicated by a second set of one or more electrically programmable elements; and causing execution of the firmware image in response to reading a valid firmware image.

[0136] In Example 15, the subject matter of Example 14 includes, wherein the first and second set of one or more electrically programmable elements comprises one of: a fuse, an anti-fuse, an electrical fuse.

[0137] In Example 16, the subject matter of Examples 14-15 includes, wherein one of the first firmware search parameters is a firmware search step size, wherein the firmware search step size specifies an offset between possible locations of the firmware image.

[0138] In Example 17, the subject matter of Examples 14-16 includes, wherein one of the first firmware search parameters is a number of possible locations to be tried.

[0139] In Example 18, the subject matter of Examples 14-17 includes, wherein one of the first firmware search parameters is an offset from a default possible location.

[0140] In Example 19, the subject matter of Examples 14-18 includes, wherein one of the second firmware search parameters is a number of read retry loops, the number of read retry loops specifying a number of times to attempt searching each of the one or more possible locations.

[0141] In Example 20, the subject matter of Examples 14-19 includes, wherein one of the second firmware search parameters is a first read retry to be attempted.

[0142] In Example 21, the subject matter of Examples 14-20 includes, wherein one of the second firmware search parameters is a read retry step size.

[0143] In Example 22, the subject matter of Examples 14-21 includes, wherein the operation of determining one or more possible locations of a firmware image in a memory cell includes determining a first possible location using a default location and a value of a first parameter of the first firmware search parameters specifying an initial offset.

[0144] In Example 23, the subject matter of Example 22 includes, wherein the operation of determining one or more possible locations of a firmware image in a memory cell includes determining a second possible location based on the first possible location and a value of a second parameter of the first firmware search parameters specifying a firmware search step size.

[0145] In Example 24, the subject matter of Examples 14-23 includes, wherein the first and second set of one or more electrically programmable elements and the processor are part of a controller.

[0146] In Example 25, the subject matter of Examples 14-24 includes, wherein the processor is part of the controller, and the first and second set of one or more electrically programmable elements are separate from the controller.

[0147] In Example 26, the subject matter of Examples 14-25 includes, wherein the memory cell is a NAND memory cell.

[0148] Example 27 is a method performed by a NAND controller, the method comprising: determining one or more possible locations of a firmware image in a memory cell of the memory device according to values of one or more first firmware search parameters indicated by a first set of one or more electrically programmable elements; searching the one or more possible locations for a valid firmware image by reading the memory cell at the one or more possible locations according to values of one or more second firmware search parameters indicated by a second set of one or more electrically programmable elements; and causing execution of the firmware image in response to reading a valid firmware image.

[0149] In Example 28, the subject matter of Example 27 includes, wherein the first and second set of one or more electrically programmable elements includes one of: a fuse, an anti-fuse, an electrical fuse.

[0150] In Example 29, the subject matter of Examples 27-28 includes, wherein one of the first firmware search parameters is a firmware search step size, wherein the firmware search step size specifies an offset between possible locations of the firmware image.

[0151] In Example 30, the subject matter of Examples 27-29 includes, wherein one of the first firmware search parameters is a number of possible locations to be attempted.

[0152] In Example 31, the subject matter of Examples 27-30 includes, wherein one of the first firmware search parameters is an offset from a default possible location.

[0153] In Example 32, the subject matter of Examples 27-31 includes, wherein one of the second firmware search parameters is a number of read retry loops, the number of read retry loops specifying a number of times to attempt searching each of the one or more possible locations.

[0154] In Example 33, the subject matter of Examples 27-32 includes, wherein one of the second firmware search parameters is a first read retry to be attempted.

[0155] In Example 34, the subject matter of Examples 27-33 includes, wherein one of the second firmware search parameters is a read retry step size.

[0156] In Example 35, the subject matter of Examples 27-34 includes, wherein determining one or more possible locations of a firmware image in a memory unit includes determining a first possible location using a default location and a value of a first parameter of the first firmware search parameters specifying an initial offset.

[0157] In Example 36, the subject matter of Example 35 includes, wherein determining one or more possible locations of a firmware image in a memory unit includes determining a second possible location based on the first possible location and a value of a second parameter of the first firmware search parameters specifying a firmware search step size.

[0158] In Example 37, the subject matter of Examples 27-36 includes, wherein the first and second set of one or more electrically programmable elements and the processor are part of a controller.

[0159] In Example 38, the subject matter of Examples 27-37 includes, wherein the processor is part of the controller and the first and second set of one or more electrically programmable elements are separate from the controller.

[0160] In Example 39, the subject matter of Examples 27-38 includes, wherein the memory cell is a NAND memory cell.

[0161] Example 40 is a memory device comprising: means for determining one or more possible locations of a firmware image in memory cells of the memory device according to values of one or more first firmware search parameters indicated by a first set of one or more electrically programmable elements; means for searching the one or more possible locations for a valid firmware image by reading the memory cells at the one or more possible locations according to values of one or more second firmware search parameters indicated by a second set of one or more electrically programmable elements; and means for causing execution of the firmware image in response to reading a valid firmware image.

[0162] In Example 41, the subject matter of Example 40 includes, wherein the first and second sets of one or more electrically programmable elements comprise one of: a fuse, an anti-fuse, an electrical fuse.

[0163] In Example 42, the subject matter of Examples 40-41 includes, wherein one of the first firmware search parameters is a firmware search step size, wherein the firmware search step size specifies an offset between possible locations of the firmware image.

[0164] In Example 43, the subject matter of Examples 40-42 includes, wherein one of the first firmware search parameters is a number of possible locations to be tried.

[0165] In Example 44, the subject matter of Examples 40-43 includes, wherein one of the first firmware search parameters is an offset from a default possible location.

[0166] In Example 45, the subject matter of Examples 40-44 includes: wherein one of the second firmware search parameters is a number of read retry loops, the number of read retry loops specifying a number of times to attempt searching each of the one or more possible locations.

[0167] In Example 46, the subject matter of Examples 40-45 includes, wherein one of the second firmware search parameters is a first read retry to be tried.

[0168] In Example 47, the subject matter of Examples 40-46 includes, wherein one of the second firmware search parameters is a read retry step size.

[0169] In Example 48, the subject matter of Examples 40-47 includes, wherein the means for determining one or more possible locations of a firmware image in memory cells comprises means for determining a first possible location using a default location and values of first parameters of the first firmware search parameters specifying an initial offset.

[0170] In Example 49, the subject matter of Example 48 includes, wherein the means for determining one or more possible locations of the firmware image in the memory unit comprises means for determining a second possible location based on the first possible location and a value of a second parameter of the first firmware search parameter that specifies a firmware search step size.

[0171] In Example 50, the subject matter of Examples 48-49 includes, wherein the first and second set of one or more electrically programmable elements and the processor are part of a controller.

[0172] In Example 51, the subject matter of Examples 48-50 includes, wherein the processor is part of the controller and the first and second set of one or more electrically programmable elements are separate from the controller.

[0173] In Example 52, the subject matter of Examples 48-51 includes, wherein the memory unit is a NAND memory unit.

[0174] Example 53 is at least one machine readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-52.

[0175] Example 54 is an apparatus comprising means to implement any of Examples 1-52.

[0176] Example 55 is a system to implement any of Examples 1-52. Example 56 is a method to implement any of Examples 1-52.

Claims

1. A memory device comprising: a first set of one or more electrically programmable elements indicative of values of one or more firmware search parameters, the first set of one or more electrically programmable elements comprising a fuse, an anti-fuse, or an e-fuse; and a processor configured to perform operations comprising: reading a signal from the first set of one or more electrically programmable elements; interpreting the signal from the first set of one or more electrically programmable elements to determine values of a first firmware search parameter and a second firmware search parameter, the first firmware search parameter comprising a step size and the second firmware search parameter comprising a number of locations to be tried; when the number of locations tried has not exceeded the number of locations to be tried and when a valid firmware image is not found, performing operations comprising: determining a likely location of a firmware image in a memory cell of the memory device based on a starting location, the number of locations tried, and the step size; and reading the memory device at the likely location to determine whether a valid firmware exists at the likely location.

2. The memory device of claim 1, wherein the starting location is a fixed location.

3. The memory device of claim 1, wherein the operations further comprise: interpreting the signal from the first set of one or more electrically programmable elements to determine a value of a third firmware search parameter, the third firmware search parameter identifying the starting location.

4. The memory device of claim 1, wherein the operations further comprise: interpreting the signal from the first set of one or more electrically programmable elements to determine a value of a third firmware search parameter, the third firmware search parameter being a read retry voltage; and wherein reading the memory device at the likely location to determine whether a valid firmware exists at the location comprises: reading the memory device at the likely location; determining that a read error occurred; and re-reading the likely location with a read voltage determined based on the read retry voltage.

5. The memory device of claim 4, wherein the operations further comprise: interpreting the signal from the first set of one or more electrically programmable elements to determine a value of a fourth firmware search parameter, the fourth firmware search parameter being a number of read retries; and wherein re-reading the likely location with the read voltage determined based on the read retry voltage comprises repeatedly re-reading the likely location up to the number of read retries.

6. The memory device of claim 5, wherein the operations further comprise: interpreting the signal from the first set of one or more electrically programmable elements to determine a value of a fifth firmware search parameter, the fifth firmware search parameter being a read retry step voltage; and wherein re-reading the likely location with the read voltage determined based on the read retry voltage comprises repeatedly re-reading the likely location up to the number of read retries, each successive re-reading using the read voltage also determined based on the read retry step voltage. ​ ​ 7. The memory device of claim 1, wherein the processor is a memory controller.

8. A method performed by a memory controller of a memory device, the method comprising: reading a signal from a first set of one or more electrically programmable elements, the one or more electrically programmable elements indicating values of one or more firmware search parameters, the first set of one or more electrically programmable elements comprising fuses, anti-fuses, or e-fuses; interpreting the signal from the first set of one or more electrically programmable elements to determine values of a first firmware search parameter and a second firmware search parameter; the first firmware search parameter comprising a step size, and the second firmware search parameter comprising a number of locations to be attempted; when the number of locations attempted has not exceeded the number of locations to be attempted, and when no valid firmware image is found, performing operations comprising: determining a likely location of a firmware image in a memory cell of the memory device based on a starting location, the number of locations attempted, and the step size; and reading the memory device at the likely location to determine whether a valid firmware exists at the location.

9. The method of claim 8, wherein the starting location is a fixed location.

10. The method of claim 8, further comprising: interpreting the signal from the first set of one or more electrically programmable elements to determine a value of a third firmware search parameter, the third firmware search parameter identifying the starting location.

11. The method of claim 8, further comprising: interpreting the signal from the first set of one or more electrically programmable elements to determine a value of a third firmware search parameter, the third firmware search parameter being a read retry voltage; and wherein reading the memory device at the likely location to determine whether a valid firmware exists at the location comprises: reading the memory device at the likely location; determining that a read error occurred; and re-reading the likely location with a read voltage determined based on the read retry voltage.

12. The method of claim 11, further comprising: interpreting the signal from the first set of one or more electrically programmable elements to determine a value of a fourth firmware search parameter, the fourth firmware search parameter being a number of read retries; and wherein re-reading the likely location with the read voltage determined based on the read retry voltage comprises repeatedly re-reading the likely location up to the number of read retries.

13. The method of claim 12, further comprising: interpreting the signal from the first set of one or more electrically programmable elements to determine a value of a fifth firmware search parameter, the fifth firmware search parameter being a read retry step voltage; and wherein re-reading the likely location with the read voltage determined based on the read retry voltage comprises repeatedly re-reading the likely location up to the number of read retries, each successive re-reading using the read voltage also determined based on the read retry step voltage.

14. A machine-readable medium storing instructions that, when executed by a processor on a memory device, cause the processor of the memory device to perform operations comprising: reading a signal from a first set of one or more electrically programmable elements, the one or more electrically programmable elements indicating values of one or more firmware search parameters, the first set of one or more electrically programmable elements comprising fuses, anti-fuses, or e-fuses; interpreting the signal from the first set of one or more electrically programmable elements to determine values of a first firmware search parameter and a second firmware search parameter; the first firmware search parameter comprising a step size, and the second firmware search parameter comprising a number of locations to be attempted; when the number of locations attempted has not exceeded the number of locations to be attempted, and when no valid firmware image is found, performing the following: determining a likely location of a firmware image in a memory cell of the memory device based on a starting location, the number of locations attempted, and the step size; and reading the memory device at the likely location to determine whether a valid firmware exists at the location.

15. The machine-readable medium of claim 14, wherein the starting location is a fixed location.

16. The machine-readable medium of claim 14, wherein the operations further comprise: interpreting the signal from the first set of one or more electrically programmable elements to determine a value of a third firmware search parameter, the third firmware search parameter identifying the starting location.

17. The machine-readable medium of claim 14, wherein the operations further comprise: interpreting the signal from the first set of one or more electrically programmable elements to determine a value of a third firmware search parameter, the third firmware search parameter being a read retry voltage; and wherein reading the memory device at the likely location to determine whether a valid firmware exists at the location comprises: reading the memory device at the likely location; determining that a read error occurred; and re-reading the likely location with a read voltage determined based on the read retry voltage.

18. The machine-readable medium of claim 17, wherein the operations further comprise: interpreting the signal from the first set of one or more electrically programmable elements to determine a value of a fourth firmware search parameter, the fourth firmware search parameter being a number of read retries; and wherein re-reading the likely location with the read voltage determined based on the read retry voltage comprises repeatedly re-reading the likely location up to the number of read retries.

19. The machine-readable medium of claim 18, wherein the operations further comprise: interpreting the signal from the first set of one or more electrically programmable elements to determine a value of a fifth firmware search parameter, the fifth firmware search parameter being a read retry step voltage; and wherein re-reading the likely location with the read voltage determined based on the read retry voltage comprises repeatedly re-reading the likely location up to the read retry step voltage. ​ ​ wherein the operation of re-reading the possible locations with the read voltage determined based on the read retry voltage comprises repeatedly re-reading the possible locations up to a number of the read retries, each successive re-read using the read voltage, the read voltage also determined based on the read retry step voltage.

20. The machine-readable medium of claim 14, wherein the processor is a memory controller.

Images