Anti-fuse circuit and anti-fuse cell burn-in state real-time verification method

Abstract

The embodiment of the present disclosure provides a kind of anti-fuse circuit, it includes: anti-fuse unit;Burn write circuit, for the anti-fuse unit is burned according to burn write signal;Verification unit includes first input, second input and first output, the burn write signal of the anti-fuse unit is as the input signal of the first input, the data signal stored in the anti-fuse unit is as the input signal of the second input, the verification unit can verify the burn write state of the anti-fuse according to the input signal of the first input and second input, and the first output is used to output verification signal.The anti-fuse circuit provided in the embodiment of the present disclosure does not need to read out the data signal of anti-fuse unit to testing machine again to verify the burn write state of anti-fuse unit, save time, and verification accuracy is high.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to an antifuse circuit and a method for real-time verification of the antifuse unit's programming status. Background Technology

[0002] In the semiconductor industry, fuses are widely used in integrated circuits due to their versatility. For example, multiple circuit modules with the same function are designed as backups in an integrated circuit. When one circuit module fails, the fuse burns out the circuit module and other functional circuits in the integrated circuit, and another circuit module with the same function replaces the failed one.

[0003] With the continuous development of semiconductor technology, anti-fuse technology has attracted the attention of many inventors and manufacturers. Anti-fuse elements store information by changing from an insulating state to a conductive state. Writing information to the anti-fuse element is performed by applying high voltage, causing dielectric breakdown. Before programming, the anti-fuse memory cell exhibits capacitive characteristics, with no conductive channel formed; after programming breakdown occurs, a conductive channel is formed across the cell, allowing current to pass through. The magnitude of the conducting current is related to the programming effect.

[0004] However, existing antifuse circuits cannot achieve real-time verification of antifuse units, thus failing to meet the requirements. Summary of the Invention

[0005] The technical problem to be solved by the embodiments of this disclosure is to provide an antifuse circuit and a method for real-time verification of the antifuse unit's programming status, which can verify the programming status of the antifuse unit in real time.

[0006] To address the aforementioned problems, this disclosure provides an antifuse circuit comprising: an antifuse unit; a programming circuit for programming the antifuse unit according to a programming signal; and a verification unit comprising a first input terminal, a second input terminal, and a first output terminal, wherein the programming signal of the antifuse unit serves as the input signal of the first input terminal, the data signal stored in the antifuse unit serves as the input signal of the second input terminal, the verification unit is capable of verifying the programming status of the antifuse based on the input signals of the first and second input terminals, and the first output terminal is used to output a verification signal.

[0007] In one embodiment, the verification unit includes a logic gate circuit, which is used to perform an XOR or XOR logic operation on the programming signal and the data signal and output the operation result as the verification signal.

[0008] In one embodiment, the logic gate circuit includes: a first transistor, wherein a first terminal of the first transistor is electrically connected to a second input terminal, a second terminal of the first transistor is electrically connected to a first node, and a gate of the first transistor is electrically connected to the first input terminal; a second transistor, wherein a first terminal of the second transistor is electrically connected to the first input terminal, a second terminal of the second transistor is electrically connected to the first node, a gate of the second transistor is electrically connected to the second input terminal, and the first node is electrically connected to the first output terminal; and a charging unit, wherein the charging unit is used to provide a weak 1 logic state value to the first output terminal.

[0009] In one embodiment, the first transistor and the second transistor are transistors of the same type.

[0010] In one embodiment, both the first transistor and the second transistor are NMOS transistors or PNOS transistors.

[0011] In one embodiment, the charging unit includes a third transistor, which is a PMOS transistor. The gate of the third transistor is grounded, the first terminal of the third transistor is connected to the power supply voltage, and the second terminal of the third transistor is connected to the first output terminal.

[0012] In one embodiment, the logic gate circuit further includes a switching unit connected between the first node and the first output terminal, the switching unit being used to turn on or off in response to a verification enable signal.

[0013] In one embodiment, the switching unit includes a fourth transistor, the first terminal of which is electrically connected to the first node, the second terminal of which is electrically connected to the first output terminal, and the gate of which receives the verification enable signal.

[0014] In one embodiment, the fourth transistor is an NMOS transistor.

[0015] In one embodiment, a reading unit is also included, which is used to read the data signal of the antifuse unit.

[0016] In one embodiment, a read switch unit is further included, which is used to control the electrical connection between the antifuse unit and the read unit according to a read enable signal.

[0017] In one embodiment, the antifuse unit includes a first end and a second end. The first end of the antifuse unit is grounded, and the second end of the antifuse unit is connected to a second node through the read switch unit, the input end of the read unit, and the second input end of the verification unit.

[0018] In one embodiment, the reading unit includes: a pre-charging unit for pre-charging the second node according to a pre-charging control signal; and a latch, the input of which is electrically connected to the second node, and the output of which serves as the output of the reading unit.

[0019] In one embodiment, the pre-charge unit includes a fifth transistor, the first terminal of which is electrically connected to a power supply voltage, the second terminal of which is electrically connected to the second node, and the gate of which receives the pre-charge control signal.

[0020] This disclosure also provides a method for real-time verification of the antifuse unit's programming status, using the aforementioned antifuse circuit. The method includes: inputting a programming signal; programming the antifuse unit according to the programming signal; reading the data signal stored in the antifuse unit; and verifying whether the antifuse unit has been programmed correctly based on the data signal and the programming signal.

[0021] In one embodiment, verifying whether the antifuse unit is programmed correctly based on the data signal and the programming signal includes: if the programming signal of the antifuse unit is consistent with the data signal of the antifuse unit, then the antifuse unit is programmed correctly; if the programming signal of the antifuse unit is inconsistent with the data signal of the antifuse unit, then the antifuse unit is programmed incorrectly.

[0022] When the antifuse unit completes the breakdown and enters the verification mode, the verification unit can use the programming signal input from the first input terminal and the data signal of the antifuse unit input from the second input terminal to verify the programming status of the antifuse unit in real time. This eliminates the need to read the data signal of the antifuse unit to the test instrument to verify the programming status of the antifuse unit, saving time and achieving high verification accuracy. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the antifuse circuit provided in the first embodiment of this disclosure;

[0024] Figure 2 This is a signal timing diagram of the antifuse circuit provided in the first embodiment of this disclosure;

[0025] Figure 3 This is another signal timing diagram of the antifuse circuit provided in the first embodiment of this disclosure;

[0026] Figure 4 This is a schematic diagram of the steps of the real-time verification method for the antifuse unit programming status provided in the second embodiment of this disclosure;

[0027] Figure 5It is a truth table for signals. Detailed Implementation

[0028] The following detailed description, in conjunction with the accompanying drawings, provides a specific implementation method for the antifuse circuit and the real-time verification method for the antifuse unit's programming status provided by the present invention.

[0029] Figure 1 This is a schematic diagram of the antifuse circuit provided in the first embodiment of this disclosure. Please refer to [link / reference]. Figure 1 The antifuse circuit includes an antifuse unit 10, a programming circuit 20, and a verification unit 40. The programming circuit 20 programs the antifuse unit 10 according to a programming signal. The verification unit 40 includes a first input terminal 40A, a second input terminal 40B, and a first output terminal 40C. The programming signal of the antifuse unit 10 serves as the input signal to the first input terminal 40A, and the data signal stored in the antifuse unit 10 serves as the input signal to the second input terminal 40B. The verification unit 40 can verify the programming status of the antifuse unit 10 based on the input signals from the first input terminal 40A and the second input terminal 40B. The first output terminal 40C outputs a verification signal, VerifyOut. In this embodiment, the antifuse circuit also includes a read-out unit 30, which reads the data signal stored in the antifuse unit 10.

[0030] In this embodiment, the antifuse unit 10 includes a first terminal 10A and a second terminal 10B. The first terminal 10A is grounded (GND), and the second terminal 10B can be electrically connected to the input terminal IN of the read unit 30, the second input terminal 40B of the verification unit 40, and the programming circuit 20, and is connected to the second node Q2. A high voltage is applied between the first terminal 10A and the second terminal 10B of the antifuse unit 10. This high voltage can break down the dielectric of the antifuse unit 10, causing it to change from an insulating state to a conductive state, thus storing information. After performing a programming operation on the antifuse unit 10, if the antifuse unit 10 is in a conducting state, it indicates that the antifuse unit 10 has broken down; if the antifuse unit 10 is in an insulating state, it indicates that the antifuse unit 10 has not broken down. In this embodiment, a programming signal Data value of "0" indicates that the antifuse unit 10 has broken down, and a programming signal Data value of "1" indicates that the antifuse unit 10 has not broken down.

[0031] In this embodiment, the programming circuit 20 is connected to the antifuse unit 10 and is used to program the antifuse unit 10 according to the programming control signal BlowEn, that is, the programming control signal BlowEn serves as the enable signal for the programming circuit 20. When programming the antifuse unit 10 is required, the programming control signal BlowEn enables the programming circuit 20, and the programming operation is performed on the antifuse unit 10.

[0032] As an example, this embodiment also provides a structure for a programming circuit 20. The programming circuit 20 includes a programming control unit 21 and a signal conversion unit 22.

[0033] The programming control unit 21 uses the programming control signal BlowEn as an enable signal to transmit the programming signal Data to the signal conversion unit 22. For example, in this embodiment, the programming control unit includes a third NMOS transistor MN3. The control terminal of the third NMOS transistor MN3 is connected to the programming control signal BlowEn, one end of the third NMOS transistor MN3 is connected to the programming signal Data, and the other end is connected to the signal conversion unit 22. When programming is required, the programming control signal BlowEn is set to a high level to turn on the third NMOS transistor MN3, and the programming signal Data is transmitted to the signal conversion unit 22.

[0034] The signal conversion unit 22 is connected at one end to the programming voltage VPP and at the other end to the antifuse unit 10, and uses the programming signal Data as the control signal to program the antifuse unit 10. For example, in this embodiment, the signal conversion unit 22 includes a first PMOS transistor MP1 and a second PNOS transistor MP2. One end of the first PMOS transistor MP1 is connected to the programming voltage VPP and the other end is connected to the antifuse unit 10. The control terminal of the first PMOS transistor MP1 receives the programming signal Data. One end of the second PNOS transistor MP2 is connected to the programming voltage VPP and the other end is connected to the control terminal of the first PMOS transistor MP1. The control terminal of the second PNOS transistor MP2 receives a bias signal, wherein the voltage Vbias of the bias signal is less than the programming voltage VPP.

[0035] When programming the antifuse unit 10 is required, the programming signal Data is set to low, the programming control signal BlowEn is set to high, the third NMOS transistor MN3 is turned on, and the programming signal Data controls the first PMOS transistor MP1 to turn on. The voltage difference across the antifuse unit 10 is the voltage difference between the programming voltage VPP and the ground terminal GND, thereby enabling programming of the antifuse unit 10. If the programming signal Data is set to high, the first PMOS transistor MP1 is not turned on, and the programming circuit 20 does not program the antifuse unit 10.

[0036] In this embodiment, the programming circuit 20 further includes an amplification unit 23, and the programming signal Data output by the programming control unit 21 is transmitted to the signal conversion unit 22 after passing through the amplification unit 23.

[0037] In the above example, the first terminal 10A of the antifuse unit 10 is grounded to GND, and the second terminal 10B is connected to the second node Q2 via the input terminal IN of the read unit 30, the second input terminal 40B of the verification unit 40, and the programming circuit 20. It is understood that in other examples, the first terminal of the antifuse unit 10 is connected to the programming voltage, and the second terminal is connected to the second node Q2 via the input terminal of the read unit, the second input terminal of the verification unit, and the programming circuit. The programming circuit is connected to the ground terminal GND.

[0038] Please continue reading. Figure 1 The input terminal IN of the reading unit 30 is connected to the second terminal 10B of the antifuse unit 10, and the output terminal OUT of the reading unit 30 outputs the signal EFOUT. When the input terminal IN of the reading unit 30 is connected to the second terminal 10B of the antifuse unit 10, the input signal EFDAT of the reading unit 30 is affected by the data signal of the antifuse unit 10. Specifically, in this embodiment, if the antifuse unit 10 breaks down, the antifuse unit 10 is connected, the second terminal 10B of the antifuse unit 10 is grounded, and the data signal of the antifuse unit 10 is low, then the input signal EFDAT of the reading unit 30 is pulled low and set to a low level; if the antifuse unit 10 does not break down, the antifuse unit 10 is not connected, the second terminal 10B of the antifuse unit 10 is not grounded, and the data signal of the antifuse unit 10 is high, then the input signal EFDAT of the reading unit 30 maintains its original level, for example, maintains a high level.

[0039] As an example, this embodiment provides a circuit structure for a read unit 30. The read unit 30 includes a pre-charge unit 31 and a latch 32.

[0040] The pre-charging unit 31 is used to pre-charge the second node Q2 according to the pre-charging control signal pre, that is, to charge the input terminal IN of the reading unit 30.

[0041] In some embodiments, the pre-charge unit 31 includes a fifth transistor, the first terminal of which is electrically connected to the power supply voltage VDD, the second terminal of which is electrically connected to the second node Q2, and the gate of which receives the pre-charge control signal pre. Specifically, in this embodiment, the fifth transistor is a POMS transistor, for example, such as... Figure 1 As shown, the fifth transistor is a third PMOS transistor MP3. The first terminal of the third PMOS transistor MP3 is connected to the power supply voltage VDD, and the second terminal of the third PMOS transistor MP3 is connected to the second node Q2. The gate of the third PMOS transistor MP3 receives the precharge control signal pre. When the precharge control signal pre is set to a low level, the third PMOS transistor MP3 is turned on, the second node Q2 is connected to the power supply voltage VDD, the precharge unit 31 charges the second node Q2, pulls up the voltage of the second node Q2 (i.e., the input terminal IN of the read unit 30), and sets the input signal EFDAT to a high level.

[0042] The input terminal of the latch 32 is electrically connected to the second node Q2 (i.e., the input terminal IN of the read unit 30), and the output terminal is electrically connected to the output terminal OUT of the read unit 30. The latch 32 can automatically hold the input signal EFDAT of the input terminal IN of the read unit 30. In this embodiment, the latch includes a first inverter P1 and a second inverter P2, which are connected end to end. The input terminal of the first inverter P1 is electrically connected to the second node Q2, and the output terminal of the first inverter P1 is electrically connected to the output terminal OUT of the read unit 30. The input terminal of the second inverter P2 is electrically connected to the output terminal of the first inverter P1, and the output terminal of the second inverter P2 is electrically connected to the input terminal of the first inverter P1, thus realizing the function of the latch.

[0043] The verification unit 40 can verify the programming status of the antifuse unit 10 based on the input signals from the first input terminal 40A and the second input terminal 40B. The first output terminal 40C is used to output the verification signal VerifyOut. The programming signal Data of the antifuse unit 10 serves as the input signal of the first input terminal 40A, and the data signal stored in the antifuse unit 10 serves as the input signal of the second input terminal 40B. In this embodiment, when the antifuse unit 10 is read by the reading unit 30, the signal of the second node Q2 (i.e., the input signal EFDAT of the input terminal IN of the reading unit 30) is equivalent to the data signal of the antifuse unit 10. That is, when entering the verification mode, the input signal of the second input terminal 40B of the verification unit is the signal of the second node Q2 (i.e., the input signal EFDAT of the input terminal IN of the reading unit 30).

[0044] In this embodiment, the verification unit 40 includes a logic gate circuit 41, which is used to perform an XOR logic operation or an XOR logic operation on the programming signal Data and the data signal of the antifuse unit 10, and output the operation result as the verification signal VerifyOut.

[0045] For example, the logic gate circuit 41 includes a first transistor, a second transistor, and a charging unit. The first terminal of the first transistor is electrically connected to the second input terminal, the second terminal of the first transistor is electrically connected to the first node, and the gate of the first transistor is electrically connected to the first input terminal. The first terminal of the second transistor is electrically connected to the first input terminal, the second terminal of the second transistor is electrically connected to the first node, and the gate of the second transistor is electrically connected to the second input terminal. The charging unit 42 is used to provide a weak 1 logic state value to the first output terminal.

[0046] The first transistor and the second transistor are transistors of the same type. In this embodiment, both the first transistor and the second transistor are NMOS transistors, which implement the XOR logic operation and output the operation result as the verification signal VerifyOut.

[0047] Specifically, in this embodiment, the first transistor is a first NMOS transistor MN1. The first terminal of the first NMOS transistor MN1 is electrically connected to the second input terminal 40B, the second terminal of the first NMOS transistor MN1 is electrically connected to the first node Q1, and the gate of the first NMOS transistor MN1 is electrically connected to the first input terminal 40A. The second transistor is a second NMOS transistor MN2. The first terminal of the second NMOS transistor MN2 is electrically connected to the first input terminal 40A, the second terminal of the second NMOS transistor MN2 is electrically connected to the first node Q1, and the gate of the second NMOS transistor MN2 is electrically connected to the second input terminal 40B. The first node Q is electrically connected to the first output terminal 40C.

[0048] In other embodiments, both the first transistor and the second transistor are PMOS transistors, which perform an XOR logic operation and output the result as the verification signal.

[0049] The charging unit 42 includes a third transistor, which is a PMOS transistor. The gate of the third transistor is grounded, the first terminal of the third transistor is connected to the power supply voltage VDD, and the second terminal of the third transistor is connected to the first output terminal 40C. Specifically, in this embodiment, the third transistor is a fourth PMOS transistor MP4. The first terminal of the fourth PMOS transistor MP4 is electrically connected to the power supply voltage VDD, the second terminal of the fourth PMOS transistor MP4 is electrically connected to the first output terminal 40C, and the gate of the fourth PMOS transistor MP4 is grounded. Its voltage is VSS, so the fourth PMOS transistor MP4 is in a normally open state, so that the default output of the first output terminal 40C is maintained at the power supply voltage VDD. When either the programming signal Data of the antifuse unit or the data signal stored in the antifuse unit 10 is low, the output of the logic gate circuit 41 is low, the first output terminal 40C is pulled down, and the output signal changes from high to low.

[0050] In this embodiment, the verification unit 40 further includes a switch unit 43 connected between the first node Q1 and the first output terminal 40C. The switch unit 43 is used to turn on or off in response to the verification enable signal VerifyEn to control the opening of the verification unit 40.

[0051] In some embodiments, the switching unit 43 includes a fourth transistor. The first terminal of the fourth transistor is electrically connected to the first node Q1, and the second terminal of the fourth transistor is electrically connected to the first output terminal 40C. The gate of the fourth transistor receives the verification enable signal VerifyEn. Specifically, in this embodiment, the fourth transistor is a fourth NMOS transistor MN4. When entering verification mode, the verification enable signal VerifyEn is set to a high level, the fourth NMOS transistor MN4 is turned on, and the logic gate circuit 41 is electrically connected to the first output terminal 40C to output the verification signal. When not entering verification mode, the verification enable signal VerifyEn is set to a low level, the fourth NMOS transistor MN4 is turned off, and the logic gate circuit 41 is not connected to the first output terminal 40C.

[0052] In this embodiment, the antifuse circuit further includes a read switch unit S1, which controls the electrical connection between the antifuse unit 10 and the input terminal IN of the read unit 30 according to the read enable signal discharge. The second terminal 10B of the antifuse unit 10 is connected to the second node Q2 through the read switch unit S1, the input terminal IN of the read unit 20, and the second input terminal 40B of the verification unit 40.

[0053] In this embodiment, the read switch unit S1 is an NMOS transistor, for example, the read switch unit S1 is the fifth NMOS transistor MN5. When the read enable signal discharge is set to a high level, the fifth NMOS transistor MN5 is turned on, and the second terminal 10B of the antifuse unit 10 is connected to the second node Q2 through the fifth NMOS transistor MN5, the input terminal IN of the read unit 20, and the second input terminal 40B of the verification unit 40. It can be understood that when the programming circuit 20 programs the antifuse unit 10, the read enable signal discharge is set to a low level, the read switch unit S1 is turned off, and the antifuse unit 10 is not connected to the input terminal IN of the read unit 30 and the verification unit 40.

[0054] In this embodiment, the read switch unit S1 can also function as a control switch for the read unit 30, controlling the electrical connection between the read unit 30 and the antifuse unit 10 based on the read enable signal discharge. When the read enable signal discharge is high, the fifth NMOS transistor MN5 is turned on, the input terminal IN of the read unit 30 is electrically connected to the antifuse unit 10, and the read unit 30 can read the data signal of the antifuse unit 10. It is understood that when the programming circuit 20 programs the antifuse unit 10, the read enable signal discharge is low, the read switch unit S1 is disconnected, and the input terminal IN of the read unit 30 is not connected to the antifuse unit 10.

[0055] It should be noted that, in this embodiment, when the antifuse unit 10 is read / written and amplified, the read enable signal discharge is set to a low level, the read switch unit S1 is disconnected, and the pre-charge unit 31 charges the input terminal IN (i.e., the second node Q2) of the read unit 30, making the input terminal IN of the read unit 30 set to a high level; when the read enable signal discharge is set to a high level, the read switch unit S1 is turned on, and the input terminal IN of the read unit 30 is connected to the second terminal 10B of the antifuse unit 10. If the antifuse unit 10 breaks down, the input terminal IN of the read unit 30 becomes a low level, and the output terminal OUT outputs a high level. If the antifuse unit 10 does not break down, the input terminal IN of the read unit 30 remains at a high level, and the output terminal OUT outputs a low level.

[0056] When the antifuse unit 10 completes the breakdown and enters the verification mode, the verification unit 40 can use the programming signal Data input from the first input terminal 40A and the data signal of the antifuse unit 10 input from the second input terminal 40B to verify in real time whether the antifuse unit is programmed correctly, thereby achieving the purpose of verifying the antifuse unit 10 in real time.

[0057] It is understood that in some embodiments, the verification unit 40 is not enabled when the programming circuit 20 performs the programming operation and the reading unit 30 performs the read-write amplification operation, i.e., when it is not in verification mode.

[0058] Figure 2 This is a signal timing diagram of the antifuse circuit provided in the first embodiment of this disclosure. Please refer to [link / reference]. Figure 2After the antifuse unit 10 completes the breakdown and programming, the read enable signal discharge is set to low, and the second node Q2 (i.e., the input terminal IN of the read unit 30) is not connected to the antifuse unit 10. During the pre-charging phase, the pre-charging control signal pre is set to low, the pre-charging unit 31 of the read unit 30 charges the latch 32, and the input signal EFDAT of the input terminal IN of the read unit 30 is set to high. After the pre-charging is completed, the pre-charging control signal pre is set to high, the read enable signal discharge is set to high, the second node Q2 (i.e., the input terminal IN of the read unit 30) is connected to the antifuse unit 10, and the read unit 30 reads the data signal of the antifuse unit 10 to the input terminal IN. When the reading unit 30 reads the data signal from the antifuse unit 10 to its input terminal IN, the verification enable signal VerifyEn enables the verification unit 40. For example, in this embodiment, the verification enable signal VerifyEn is set to a high level, and the switching unit 43 is turned on, entering the verification mode. In the verification mode, when the programming signal Data is low (i.e., the programming signal Data indicates that the antifuse unit 10 is broken down), if the input signal EFDAT at the input terminal of the reading unit 30 remains high (e.g., ... Figure 2 (As shown by the solid line in the middle), then the output signal VerifyOut of the first output terminal 40C of the verification unit 40 is low (as shown by the solid line in the middle). Figure 2 (As shown by the solid line in the middle), this indicates that the actual state of the antifuse unit 10 is not broken down. This actual state is inconsistent with the programming signal, indicating that the antifuse unit 10 is programming incorrectly. If the input signal EFDAT at the input terminal of the read unit 30 becomes low (e.g., Figure 2 (As shown by the dashed line in the middle), then the output signal VerifyOut of the first output terminal 40C of the verification unit 40 is at a high level (e.g., as shown by the dashed line in the middle). Figure 2 (As shown by the dashed line in the middle), this indicates that the actual state of the antifuse unit 10 is breakdown. This actual state is consistent with the programming signal, and the antifuse unit 10 is programmed correctly.

[0059] Figure 3 This is another signal timing diagram of the antifuse circuit provided in the first embodiment of this disclosure. Please refer to [link / reference]. Figure 3 In verification mode, when the programming signal Data is high (i.e., the programming signal Data indicates that the antifuse unit 10 is not broken down), if the input signal EFDAT at the input terminal of the read unit 30 remains high (e.g. Figure 3 (As shown by the dashed line in the middle), then the output signal VerifyOut of the first output terminal 40C of the verification unit 40 is at a high level (e.g., as shown by the dashed line in the middle). Figure 3(As shown by the dashed line), this indicates that the actual state of the antifuse unit 10 is not broken down. This actual state is consistent with the programming signal, and the programming state of the antifuse unit 10 is correct. If the input signal EFDAT at the input terminal of the read unit 30 becomes low (e.g., ...), it indicates that the antifuse unit 10 is not broken down. Figure 3 (As shown by the solid line in the middle), then the output signal VerifyOut of the first output terminal 40C of the verification unit 40 is low (as shown by the solid line in the middle). Figure 3 As shown by the solid line in the middle, this indicates that the true state of the antifuse unit 10 is breakdown, which is inconsistent with the programming signal, and the antifuse unit 10 is mistakenly programmed.

[0060] As can be seen, the antifuse circuit of this disclosure does not require reading the data signal of the antifuse unit 10 to the test instrument to verify the burning status of the antifuse unit 10. Instead, it can verify the burning status of the antifuse unit 10 in real time. The antifuse circuit provided in this embodiment can quickly verify the burning status of the antifuse unit 10, saving time and having a high verification accuracy.

[0061] This disclosure also provides a method for real-time verification of the antifuse unit's programming status, wherein the verification method employs the aforementioned antifuse circuit. Figure 4 This is a schematic diagram illustrating the steps of the real-time verification method for the antifuse unit programming status provided in the second embodiment of this disclosure. Please refer to [link / reference]. Figure 1 and Figure 4 The method includes:

[0062] Step S401: Input the programming signal Data, and program the antifuse unit 10 according to the programming signal Data.

[0063] Specifically, in this embodiment, the programming control signal BlowEn enables the programming unit 20 of the antifuse circuit, allowing the programming circuit to determine whether to perform a programming operation on the antifuse unit 10 based on the programming signal Data. For example, in this embodiment, the programming signal Data is input through the programming control unit 21 and serves as the control signal for the signal conversion unit 22. If the programming signal Data indicates that the antifuse unit 10 is not broken down, then the programming signal Data is at a high level; if the programming signal Data indicates that the antifuse unit 10 is broken down, then the programming signal Data is at a low level.

[0064] Step S402: Read the data signal stored in the antifuse unit 10.

[0065] In this embodiment, the reading unit 30 reads the data signal stored in the antifuse unit 10. Before the reading unit 30 reads the data signal stored in the antifuse unit 10, the method further includes a step of pre-charging the reading unit 30.

[0066] After the antifuse unit 10 completes the breakdown and programming, the read enable signal discharge is set to low, and the input terminal IN of the read unit 30 is not connected to the antifuse unit 10, entering the pre-charging stage. The pre-charging control signal pre is set to low, the pre-charging unit 31 of the read unit 30 charges the latch 32, and the input signal EFDAT of the input terminal IN of the read unit 30 is set to high. After the pre-charging is completed, the pre-charging control signal pre is set to high, the enable signal discharge is set to high, the input terminal IN of the read unit 30 is connected to the antifuse unit 10, and the read unit 30 reads the data signal stored in the antifuse unit 10 to the input terminal IN.

[0067] In this embodiment, after reading the data signal stored in the antifuse unit 10, the following step is further included: disconnecting the electrical connection between the antifuse unit 10 and the verification unit 40. For example, the read enable signal discharge is set to a low level, and the read switch unit S1 is disconnected to cut off the electrical connection between the antifuse unit 10 and the input terminal (i.e., the second node Q2) of the verification unit 40 and the read unit 30.

[0068] Step S403: Verify whether the antifuse unit 10 is programmed correctly based on the data signal and the programming signal Data.

[0069] In this step, the antifuse circuit uses verification unit 40 to verify whether the antifuse unit 10 has been correctly programmed. The programming signal Data of the antifuse unit 10 serves as the input signal of the first input terminal 40A of the verification unit 40, and the data signal stored in the antifuse unit 10 serves as the input signal of the second input terminal 40B of the verification unit 40. The verification unit 40 verifies whether the antifuse unit 10 has been correctly programmed based on the input signals of the first input terminal 40A and the second input terminal 40B. The first output terminal 40C is used to output the verification signal VerifyOut.

[0070] In this embodiment, verifying whether the antifuse unit is correctly programmed based on the data signal and the programming signal includes: if the programming signal of the antifuse unit is consistent with the data signal of the antifuse unit, then the antifuse unit is programmed correctly; if the programming signal of the antifuse unit is inconsistent with the data signal of the antifuse unit, then the antifuse unit is programmed incorrectly.

[0071] For example, in one embodiment, after the reading unit 30 reads the data signal from the antifuse unit 10 to the input terminal IN of the reading unit 10, the verification enable signal VerifyEn enables the verification unit 40. For example, in this embodiment, the verification enable signal VerifyEn is set to a high level, the switch unit 43 is turned on, and the verification mode is entered. Please refer to [link to relevant documentation]. Figure 5 This is a truth table for signals. In verification mode, when the programming signal Data is high (i.e., the programming signal Data indicates that the antifuse unit 10 is not broken down), and its truth value is "1", if the input signal EFDAT (equivalent to the data signal stored in the antifuse unit 10) at the input terminal of the reading unit 30 remains high, and its truth value is "1", then the verification signal VerifyOut output by the first output terminal 40C of the verification unit 40 is high, and its truth value is "1", indicating that the true state of the antifuse unit 10 is not broken down. This true state is consistent with... If the programming signal is consistent, the programming state of the antifuse unit 10 is not broken down, and the antifuse programming is correct; if the input signal EFDAT (equivalent to the data signal stored in the antifuse unit 10) at the input terminal of the reading unit 30 becomes low, and its true value is "0", then the verification signal VerifyOut output by the first output terminal 40C of the verification unit 40 is low, and its true value is "0", indicating that the true state of the antifuse unit 10 is broken down. This true state is inconsistent with the programming signal, and the programming state of the antifuse unit 10 is false breakdown, and the antifuse is falsely programmed.

[0072] For example, in one embodiment, in verification mode, when the programming signal Data is low (i.e., the programming signal Data represents the breakdown of the antifuse unit 10), and its true value is "0", if the input signal EFDAT (equivalent to the data signal stored in the antifuse unit 10) at the input terminal of the read unit 30 remains high, and its true value is "1", then the verification signal VerifyOut output by the first output terminal 40C of the verification unit 40 is low, and its true value is "0", indicating that the true state of the antifuse unit 10 is not broken down. This true state is inconsistent with the programming signal, and the antifuse unit is programmed incorrectly. If the input signal EFDAT (equivalent to the data signal stored in the antifuse unit 10) at the input terminal of the read unit 30 becomes low, and its true value is "0", then the verification signal VerifyOut output by the first output terminal 40C of the verification unit 40 is high, and its true value is "1", indicating that the true state of the antifuse unit 10 is broken down. This true state is consistent with the programming signal, and the antifuse unit 10 is programmed correctly.

[0073] The real-time verification method for the antifuse unit programming status provided in this embodiment can quickly verify the programming status of the antifuse unit 10 in real time based on the data signal stored in the antifuse unit 10 and the programming signal Data. It does not require reading the data signal of the antifuse unit 10 to the test instrument to verify the programming status of the antifuse unit 10, saving time and achieving high verification accuracy.

[0074] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An antifuse circuit, characterized in that, include: Anti-fuse unit; The programming circuit is used to program the antifuse unit according to the programming signal; The verification unit includes a first input terminal, a second input terminal, and a first output terminal. The programming signal of the antifuse unit is used as the input signal of the first input terminal, and the data signal stored in the antifuse unit is used as the input signal of the second input terminal. The verification unit can verify the programming status of the antifuse based on the input signals of the first input terminal and the second input terminal. The first output terminal is used to output a verification signal. The verification unit includes logic gate circuits, which are used to perform XOR or XOR logic operations on the programming signal and the data signal and output the operation result as the verification signal. The logic gate circuit includes: The first transistor has its first terminal electrically connected to the second input terminal, its second terminal electrically connected to the first node, and its gate electrically connected to the first input terminal. The second transistor has a first terminal electrically connected to the first input terminal, a second terminal electrically connected to the first node, a gate electrically connected to the second input terminal, and the first node electrically connected to the first output terminal. A charging unit is used to provide a weak 1 logic state value to the first output terminal.

2. The antifuse circuit according to claim 1, characterized in that, The first transistor and the second transistor are transistors of the same type.

3. The antifuse circuit according to claim 2, characterized in that, Both the first transistor and the second transistor are NMOS transistors or PMOS transistors.

4. The antifuse circuit according to claim 1, characterized in that, The charging unit includes a third transistor, which is a PMOS transistor. The gate of the third transistor is grounded, the first terminal of the third transistor is connected to the power supply voltage, and the second terminal of the third transistor is connected to the first output terminal.

5. The antifuse circuit according to claim 1, characterized in that, The logic gate circuit also includes a switching unit connected between the first node and the first output terminal, the switching unit being used to turn on or off in response to a verification enable signal.

6. The antifuse circuit according to claim 5, characterized in that, The switching unit includes a fourth transistor, the first terminal of which is electrically connected to the first node, the second terminal of which is electrically connected to the first output terminal, and the gate of which receives the verification enable signal.

7. The antifuse circuit according to claim 6, characterized in that, The fourth transistor is an NMOS transistor.

8. The antifuse circuit according to claim 1, characterized in that, It also includes a reading unit, which is used to read the data signal of the antifuse unit.

9. The antifuse circuit according to claim 8, characterized in that, It also includes a read switch unit, which is used to control the electrical connection between the antifuse unit and the input terminal of the read unit according to the read enable signal.

10. The antifuse circuit according to claim 9, characterized in that, The antifuse unit includes a first end and a second end. The first end of the antifuse unit is grounded, and the second end of the antifuse unit is connected to the second node through the read switch unit, the input end of the read unit, and the second input end of the verification unit.

11. The antifuse circuit according to claim 10, characterized in that, The reading unit includes: A pre-charge unit is used to pre-charge the second node according to a pre-charge control signal; A latch, the input of which is electrically connected to the second node, and the output of which serves as the output of the read unit.

12. The antifuse circuit according to claim 11, characterized in that, The pre-charge unit includes a fifth transistor, the first terminal of which is electrically connected to the power supply voltage, the second terminal of which is electrically connected to the second node, and the gate of which receives the pre-charge control signal.

13. A method for real-time verification of the programming status of an antifuse unit, employing the antifuse circuit described in any one of claims 1 to 12, characterized in that, The method includes: Input a programming signal, and program the antifuse unit according to the programming signal; Read the data signal stored in the antifuse unit; Verify whether the antifuse unit has been programmed correctly based on the data signal and the programming signal.

14. The method for real-time verification of the antifuse unit programming status according to claim 13, characterized in that, Verifying whether the antifuse unit is programmed correctly based on the data signal and the programming signal includes: if the programming signal of the antifuse unit is consistent with the data signal of the antifuse unit, then the antifuse unit is programmed correctly; if the programming signal of the antifuse unit is inconsistent with the data signal of the antifuse unit, then the antifuse unit is programmed incorrectly.

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