PMOS tube triggered bidirectional silicon controlled rectifier

Abstract

The present invention provides a PMOS tube-triggered bidirectional silicon-controlled rectifier, comprising: a substrate; a deep N-well located above the substrate; a first N-well, a first P-well, a second N-well, a second P-well, and a third N-well, arranged in sequence from left to right above the deep N-well; a first PMOS tube, comprising a P-type gate and P-type source / drain regions located on both sides of the P-type gate; two N-type doped regions, respectively located in the first P-well and the second P-well; an electrostatic pulse detection circuit having the PMOS tube, comprising a control port and two voltage ports, each of the voltage ports being electrically connected to a corresponding P-type source / drain region and a corresponding N-type doped region, and the control port being electrically connected to the P-type gate to output a control voltage to the P-type gate to control the on / off of the first PMOS tube. The present invention reduces the triggering voltage of the bidirectional silicon-controlled rectifier, thereby improving its applicability.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a PMOS tube-triggered bidirectional silicon-controlled rectifier. Background Art

[0002] In the design of anti-static protection for integrated circuits, the anti-static protection design window generally depends on the device's operating voltage and the thickness of the gate oxide layer of the internal protected circuit. However, after the anti-static protection design window is designed based on the device's operating voltage and the thickness of the gate oxide layer of the internal protected circuit, it is often found that the device's trigger voltage exceeds the anti-static protection design window. If the device is directly used in the anti-static protection design, it is easy to cause reliability problems in the device's gate oxide layer. For example, taking the 55nm process platform as an example, the operating voltage of the core device (MOSFET) is 1.2V and the thickness of the gate oxide layer is Therefore, the anti-static protection design window of the core device is usually designed to be 1.32V~5.2V. Through measurement, it is found that the trigger voltage of the core device is 6.7V, which exceeds the anti-static protection design window of the core device. If the core device is directly used for anti-static protection design, it is easy to cause reliability problems in the gate oxide layer of the core device.

[0003] Figure 1 A PMOS tube triggers a bidirectional silicon controlled rectifier. In the prior art, a PMOS tube triggers a bidirectional silicon controlled rectifier. Please refer to Figure 1 The device includes a first voltage port A, a second voltage port K, and a control port D. There is a voltage difference between the first voltage port A and the second voltage port K. The first voltage port A can be connected to a positive voltage or ground, and the second voltage port K can be connected to ground or a positive voltage. The control port D is the gate of the PMOS transistor. The device has the characteristics of small area, low trigger voltage, and high secondary breakdown current, and is suitable for anti-static protection design of low-voltage devices. However, when applied to the anti-static protection design of the IO terminal to ground, when one voltage port is grounded and an electrostatic pulse is applied to the other voltage port, the gate of the PMOS transistor is actually in a floating state. In general application scenarios, it can be considered that the gate of the PMOS transistor is at a low potential at this time. However, in some high-radiation environments, because the gate of the PMOS transistor is connected to the power supply VDD, the gate of the PMOS transistor is easily affected by radiation, causing the potential of the gate of the PMOS transistor to become unstable, thereby causing the PMOS transistor to be triggered incorrectly or triggered in time, resulting in damage to the device or loss of function. Therefore, it is necessary to design an electrostatic pulse detection circuit to accurately control the voltage applied to the control port D when the electrostatic pulse arrives to prevent the PMOS tube from being triggered incorrectly or being triggered in time, resulting in damage to the device or loss of function. Summary of the Invention

[0004] The purpose of the present invention is to provide a PMOS tube triggered bidirectional silicon-controlled rectifier, which reduces the triggering voltage of the bidirectional silicon-controlled rectifier and improves its applicability.

[0005] In order to achieve the above object, the present invention provides a PMOS tube triggered bidirectional silicon controlled rectifier, comprising:

[0006] substrate;

[0007] a deep N-well located above the substrate;

[0008] A first N-well, a first P-well, a second N-well, a second P-well and a third N-well are arranged sequentially from left to right above the deep N-well;

[0009] a first PMOS transistor, comprising a P-type gate and P-type source / drain regions located on both sides of the P-type gate, wherein the P-type gate is located above the second N-well, and the P-type source / drain regions on both sides of the P-type gate are located at the junction of the first P-well and the second N-well and at the junction of the second N-well and the second P-well, respectively;

[0010] Two N-type doped regions, respectively located in the first P-well and the second P-well, and each of the N-type doped regions is isolated from the corresponding P-type source / drain region by a trench isolation structure;

[0011] An electrostatic pulse detection circuit having a PMOS transistor has a control port and two voltage ports. Each of the voltage ports is electrically connected to the corresponding P-type source / drain region and the corresponding N-type doped region. A voltage difference exists between the two voltage ports. The control port is electrically connected to the P-type gate to output a control voltage to the P-type gate to control the on / off of the first PMOS transistor.

[0012] Optionally, the electrostatic pulse detection circuit includes a first RC circuit, a second RC circuit, a second PMOS tube and a third PMOS tube, wherein the first RC circuit includes a first resistor and a first capacitor connected in series, and the second RC circuit includes a second resistor and a second capacitor connected in series; the gate of the second PMOS tube is connected between the second resistor and the second capacitor, the gate of the third PMOS tube is connected between the first resistor and the first capacitor, the drain of the second PMOS tube and the drain of the third PMOS tube are connected to form the control port; the first resistor, the second capacitor and the source of the second PMOS tube are connected to form one voltage port; the first capacitor, the second resistor and the source of the third PMOS tube are connected to form another voltage port.

[0013] Optionally, the resistance values ​​of the first resistor and the second resistor are equal, and the capacitance values ​​of the first capacitor and the second capacitor are equal.

[0014] Optionally, the time constant of the first RC circuit and the time constant of the second RC circuit are both 1 nS to 10 nS.

[0015] Optionally, the resistance values ​​of the first resistor and the second resistor are 1KΩ to 10KΩ, and the capacitance values ​​of the first capacitor and the second capacitor are 0.2pF to 2pF.

[0016] Optionally, the trigger voltage is obtained according to the length of the P-type gate, the doping concentration of the second N-well, the time constant of the first RC circuit and the time constant of the second RC circuit.

[0017] Optionally, one of the voltage ports is grounded, and the other voltage port is connected to a positive voltage.

[0018] Optionally, the depths of the first N-well, the first P-well, the second N-well, the second P-well and the third N-well are all greater than the depths of the P-type source / drain region and the N-type doped region.

[0019] Optionally, trench isolation structures are provided on the outer sides of the two N-type doping regions.

[0020] Optionally, depths of the first N-well, the first P-well, the second N-well, the second P-well, and the third N-well are all greater than a depth of the trench isolation structure.

[0021] In the PMOS tube triggered bidirectional silicon controlled rectifier provided by the present invention, the first PMOS tube includes a P-type gate and P-type source / drain regions located on both sides of the P-type gate, the P-type gate is located above the second N-well, and the P-type source / drain regions on both sides of the P-type gate are respectively located at the junction of the first P-well and the second N-well and at the junction of the second N-well and the second P-well; two N-type doped regions are respectively located in the first P-well and the second P-well, and each N-type doped region is isolated from the corresponding P-type source / drain region by a trench isolation structure; the electrostatic pulse detection circuit with the PMOS tube has a control port and two voltage ports, each voltage port is electrically connected to the corresponding P-type source / drain region and the corresponding N-type doped region. The first PMOS transistor is electrically connected to the P-type gate, and a voltage difference exists between the two voltage ports. The control port is electrically connected to the P-type gate to output a control voltage to the P-type gate to control the on / off of the first PMOS transistor. By controlling the conduction of the first PMOS transistor, a channel current is formed in the first PMOS transistor, and the channel current acts as a trigger current of the device, thereby triggering the device to work and reducing the trigger voltage of the device. In the present invention, the P-type gate is connected to the electrostatic pulse detection circuit to control the first PMOS transistor with the electrostatic pulse signal input from the voltage port, thereby preventing the first PMOS transistor from being affected by radiation or the like, resulting in false triggering of the first PMOS transistor or untimely triggering, thereby improving the applicability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Triggering bidirectional silicon controlled rectifier for PMOS tube;

[0023] Figure 2 A PMOS tube-triggered bidirectional silicon-controlled rectifier provided in one embodiment of the present invention;

[0024] Wherein, the accompanying drawings are marked as follows:

[0025] 10-substrate; 11-deep N-well; 21-first N-well; 22-first P-well; 23-second N-well; 24-second P-well; 25-third N-well; 31-first N-type doping region; 32-second N-type doping region; 41-first P-type doping region; 42-second P-type doping region; 50-trench isolation structure; 60-P-type gate; R1-first resistor; C1-first capacitor; R2-second resistor; C2-second capacitor; P1-second PMOS transistor; P2-third PMOS transistor; A, A1-first voltage port; K, K1-second voltage port; D, D1-control port. DETAILED DESCRIPTION

[0026] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0027] Figure 2 The PMOS tube triggers the bidirectional silicon controlled rectifier provided in this embodiment. Please refer to Figure 2 This embodiment provides a PMOS transistor-triggered bidirectional silicon-controlled rectifier, including a substrate 10, a deep N-well 11, a first N-well 21, a first P-well 22, a second N-well 23, a second P-well 24, a third N-well 25, a PMOS transistor, two N-type doped regions, an electrostatic pulse detection circuit having the PMOS transistor, and a trench isolation structure 50. The deep N-well 11 is located above the N-type substrate 10. The first N-well 21, the first P-well 22, the second N-well 23, the second P-well 24, and the third N-well 25 are arranged sequentially from left to right above the deep N-well 11.

[0028] The PMOS transistor includes a P-type gate 60 and P-type source / drain regions on either side of the P-type gate 60. The P-type gate 60 is located above the second N-well 23, with a gate oxide layer (not shown) between the P-type gate 60 and the second N-well 23. The P-type source / drain regions on either side of the P-type gate 60 are located at the junction of the first P-well 22 and the second N-well 23, and at the junction of the second N-well 23 and the second P-well 24, respectively. In this embodiment, the P-type source / drain regions on either side of the P-type gate 60 are the first P-type doped region 41 and the second P-type doped region 42, respectively. If the P-type source region is the first P-type doped region 41, the P-type drain region is the second P-type doped region 42; if the P-type source region is the second P-type doped region 42, the P-type drain region is the first P-type doped region 41. The first P-type doped region 41 is located at the junction of the first P-well 22 and the second N-well 23, and the second P-type doped region 42 is located at the junction of the second N-well 23 and the second P-well 24. Since the device provided in this embodiment is a PMOS-triggered bidirectional silicon-controlled rectifier, wherein the bidirectional silicon-controlled rectifier is symmetrical in structure, the positions of the P-type source region and the P-type drain region are not distinguished.

[0029] The two N-type doping regions are respectively located in the first P-well 22 and the second P-well 24, and each N-type doping region is isolated from the corresponding P-type source / drain region by a trench isolation structure 50; in this embodiment, the two N-type doping regions are respectively a first N-type doping region 31 and a second N-type doping region 32, the first N-type doping region 31 is located in the first P-well 22 and is located outside the first P-type doping region 41, and the second N-type doping region 32 is located in the second P-well 24 and is located outside the second P-type doping region 42; and the first N-type doping region 31 and the first P-type doping region 41 and the second N-type doping region 32 are located in the second P-type doping region 42 and are isolated by the trench isolation structure 50.

[0030] In this embodiment, trench isolation structures 50 are provided outside the first N-type doping region 31 and the second N-type doping region 32. Specifically, the first N-type doping region 31 and the second N-type doping region 32 are located between the two trench isolation structures 50. The depths of the first N-well 21, the first P-well 22, the second N-well 23, the second P-well 24, and the third N-well 25 are all greater than the depths of the first N-type doping region 31, the second N-type doping region 32, the first P-type doping region 41, and the second P-type doping region 42. The trench isolation structure 50 between the first N-type doping region 31 and the first P-type doping region 41 is located in the first P-well 22, and the trench isolation structure 50 between the second N-type doping region 32 and the second P-type doping region 42 is located in the second P-well 24. The depths of the two trench isolation structures 50 are both less than the depths of the first N-well 21, the first P-well 22, the second N-well 23, the second P-well 24, and the third N-well 25. The trench isolation structure 50 outside the first N-type doping region 31 is located at the junction of the first N-well 21 and the first P-well 22, and the trench isolation structure 50 outside the second N-type doping region 32 is located at the junction of the third N-well 25 and the second P-well 24. The depths of the two trench isolation structures 50 are also smaller than the depths of the first N-well 21, the first P-well 22, the second N-well 23, the second P-well 24 and the third N-well 25.

[0031] The electrostatic pulse detection circuit with a PMOS transistor has a control port D1 and two voltage ports. Each voltage port is electrically connected to a corresponding P-type source / drain region and a corresponding N-type doped region, with a voltage difference between the two voltage ports. The control port D1 is electrically connected to the P-type gate 60 of the first PMOS transistor to output a control voltage to the P-type gate 60 to control the on / off state of the first PMOS transistor. In this embodiment, the two voltage ports are a first voltage port A1 and a second voltage port K1. The first voltage port A1 is electrically connected to the first N-type doped region 31 and the first P-type doped region 41, and the second voltage port K1 is electrically connected to the second N-type doped region 32 and the second P-type doped region 42. In this embodiment, the first voltage port A1 is grounded, and the second voltage port K1 is connected to a positive voltage. Alternatively, the first voltage port A1 is connected to a positive voltage, and the second voltage port K1 is grounded, but this is not limited to this. The connection between the first voltage port A1 and the second voltage port K1 depends on the actual situation.

[0032] The electrostatic pulse detection circuit includes a first RC circuit, a second RC circuit, a second PMOS transistor P1, and a third PMOS transistor P2. The first RC circuit includes a first resistor R1 and a first capacitor C1 connected in series, and the second RC circuit includes a second resistor R2 and a second capacitor C2 connected in series. The gate of the second PMOS transistor P1 is connected between the second resistor R2 and the second capacitor C2, and the gate of the third PMOS transistor P2 is connected between the first resistor R1 and the first capacitor C1. The drain of the second PMOS transistor P1 and the drain of the third PMOS transistor P2 are connected to form a control port D1. The source of the first resistor R1, the second capacitor C2, and the second PMOS transistor P1 are connected to form a first voltage port A1. The source of the first capacitor C1, the second resistor R2, and the third PMOS transistor P2 are connected to form a second voltage port K1.

[0033] In this embodiment, the time constant of the first RC circuit and the time constant of the second RC circuit are required to be equal. The time constant of the first RC circuit is the product of the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1, and the time constant of the second RC circuit is the product of the resistance value of the second resistor R2 and the capacitance value of the second capacitor C2. In other words, the resistance values ​​of the first resistor R1 and the second resistor R2 are required to be equal, and the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are required to be equal. In this embodiment, the time constant of the first RC circuit and the time constant of the second RC circuit can both be 1nS to 10nS, the resistance values ​​of the first resistor R1 and the second resistor R2 can be 1kΩ to 10kΩ, and the capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be 0.2pF to 2pF, but are not limited to this time constant range, resistance value range, and capacitance value range, and are determined according to actual conditions.

[0034] When the first voltage port A1 is connected to a positive voltage and the second voltage port K1 is grounded, an external electrostatic pulse signal is input from the first voltage port A1. The first RC circuit forms a capacitor charging circuit, and the potential of the node T2 of the first RC circuit is low, that is, the potential of the gate of the third PMOS transistor P2 is low, and the third PMOS transistor P2 is in the on state. At this time, the second RC circuit forms a voltage coupling circuit, and the potential of the node T1 of the second RC circuit is high, that is, the potential of the gate of the second PMOS transistor P1 is high, and the second PMOS transistor P1 is in the off state. Since the source of the third PMOS transistor P2 is grounded to the second voltage port K1, the low potential of the second voltage port K1 causes the drain of the third PMOS transistor P2 to also be low, thereby causing the P-type gate 60 of the first PMOS transistor to be low, causing the first PMOS transistor to be in the off state. After the first PMOS tube is turned on, a channel current will be formed between the first P-type doping region 41 and the second P-type doping region 42. The channel current flows from the first P-type doping region 41 to the second P-type doping region 42. The channel current will act as a trigger current to reduce the trigger voltage of the bidirectional silicon-controlled rectifier triggered by the PMOS tube. At this time, the current path formed by the PMOS tube triggering the bidirectional silicon-controlled rectifier is input from the first voltage port A1 and then passes through the first P-type doping region 41, the second N-well 23, the second P-well 24, the second N-type doping region 32 to the second voltage port K1 output, which also includes the channel current path flowing from the first P-type doping region 41 to the second P-type doping region 42 and then to the second voltage port K1 output. When the device is in a static voltage bias or normally turned on, the T1 node is at a low potential, the T2 node is at a high potential, the gate potential of the third PMOS transistor P2 is at a high potential, the third PMOS transistor P2 is in a cut-off state, the gate potential of the second PMOS transistor P1 is at a low potential, the second PMOS transistor P1 is in a conducting state, and the first voltage port A1 is at a high potential, thereby making the P-type gate 60 of the first PMOS transistor at a high potential, and making the first PMOS transistor in a cut-off state.

[0035] When the first voltage port A1 is grounded and the second voltage port K1 is connected to a positive voltage, an external electrostatic pulse signal is input from the second voltage port K1. The second RC circuit forms a capacitor charging circuit, and the potential of node T1 of the second RC circuit is low, that is, the potential of the gate of the second PMOS transistor P1 is low, and the second PMOS transistor P1 is in the on state. At this time, the first RC circuit forms a voltage coupling circuit, and the potential of node T2 of the first RC circuit is high, that is, the potential of the gate of the third PMOS transistor P2 is high, and the third PMOS transistor P2 is in the off state. Since the source of the second PMOS transistor P1 is grounded to the first voltage port A1, the low potential of the first voltage port A1 causes the drain of the second PMOS transistor P1 to also be low, thereby causing the P-type gate 60 of the first PMOS transistor to be low, turning on the first PMOS transistor. After the first PMOS tube is turned on, a channel current will be formed between the first P-type doping region 41 and the second P-type doping region 42. The channel current flows from the second P-type doping region 42 to the first P-type doping region 41. The channel current will act as a trigger current to reduce the trigger voltage of the bidirectional silicon-controlled rectifier triggered by the PMOS tube. At this time, the current path formed by the PMOS tube triggering the bidirectional silicon-controlled rectifier is input from the second voltage port K1 and then passes through the second P-type doping region 42, the second N-well 23, the first P-well 22, the first N-type doping region 31 to the first voltage port A1 output, which also includes the channel current path flowing from the second P-type doping region 42 to the first P-type doping region 41 and then to the first voltage port A1 output. When the device is in a static voltage bias or normally turned on, the T2 node is at a low potential, the T1 node is at a high potential, the gate potential of the second PMOS transistor P1 is at a high potential, the second PMOS transistor P1 is in a cut-off state, the gate potential of the third PMOS transistor P2 is at a low potential, the third PMOS transistor P2 is in a conducting state, and the second voltage port K1 is at a high potential, thereby making the P-type gate 60 of the first PMOS transistor at a high potential, and making the first PMOS transistor in a cut-off state.

[0036] In this embodiment, the control voltage output by the control port D1 to the P-type gate 60 of the first PMOS transistor can be obtained according to the length of the P-type gate 60, the doping concentration of the second N-well 23, the time constant of the first RC circuit and the time constant of the second RC circuit, wherein adjusting the time constant of the first RC circuit and the time constant of the second RC circuit can reduce this control voltage.

[0037] In this embodiment, the P-type gate 60 of the first PMOS transistor is connected to the second PMOS transistor P1 and the third PMOS transistor P2. Two RC circuits are connected in parallel between the first voltage port A1 and the second voltage port K1. The two RC circuits are used to control the operating states of the second PMOS transistor P1 and the third PMOS transistor P2, thereby controlling the on / off state of the first PMOS transistor by the input electrostatic pulse signal. The first PMOS transistor is used to trigger the bidirectional silicon-controlled rectifier, thereby avoiding the problem of the P-type gate 60 of the first PMOS transistor being directly connected to the power supply VDD, which would cause the potential of the P-type gate 60 of the first PMOS transistor to be susceptible to radiation. The PMOS transistor-triggered bidirectional silicon-controlled rectifier proposed in this embodiment detects electrostatic pulses through the electrostatic pulse detection circuit to control the first PMOS transistor. The potential of the P-type gate 60 of the first PMOS transistor is affected by the input electrostatic pulse signal and directly responds to the input electrostatic pulse signal. This avoids the problem of unstable potential of the P-type gate 60, which could cause false triggering or untimely triggering of the first PMOS transistor, thereby improving the applicability of the device and making it suitable for high-radiation environments.

[0038] In summary, in the PMOS tube triggered bidirectional silicon-controlled rectifier provided by the present invention, the first PMOS tube includes a P-type gate and P-type source / drain regions located on both sides of the P-type gate, the P-type gate is located above the second N-well, and the P-type source / drain regions on both sides of the P-type gate are respectively located at the junction of the first P-well and the second N-well and at the junction of the second N-well and the second P-well; the two N-type doped regions are respectively located in the first P-well and the second P-well, and each N-type doped region is isolated from the corresponding P-type source / drain region by a trench isolation structure; the electrostatic pulse detection circuit with the PMOS tube has a control port and two voltage ports, each voltage port is respectively connected to the corresponding P-type source / drain region and the corresponding N-type doped region The device is electrically connected, with a voltage difference between the two voltage ports. The control port is electrically connected to the P-type gate to output a control voltage to the P-type gate to control the on / off of the first PMOS tube. By controlling the conduction of the first PMOS tube, a channel current is formed in the first PMOS tube, and the channel current acts as a trigger current of the device, thereby triggering the device to work and reducing the trigger voltage of the device. In the present invention, the P-type gate is connected to the electrostatic pulse detection circuit to control the first PMOS tube with the electrostatic pulse signal input from the voltage port, thereby preventing the first PMOS tube from being affected by radiation, etc., resulting in false triggering or untimely triggering of the first PMOS tube, thereby improving the applicability of the device.

[0039] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A PMOS tube triggered bidirectional silicon controlled rectifier, characterized in that: include: substrate; a deep N-well located above the substrate; A first N-well, a first P-well, a second N-well, a second P-well and a third N-well are arranged sequentially from left to right above the deep N-well; a first PMOS transistor, comprising a P-type gate and P-type source / drain regions located on both sides of the P-type gate, wherein the P-type gate is located above the second N-well, and the P-type source / drain regions on both sides of the P-type gate are located at the junction of the first P-well and the second N-well and at the junction of the second N-well and the second P-well, respectively; two N-type doped regions, respectively located in the first P-well and the second P-well, and each of the N-type doped regions is isolated from the corresponding P-type source / drain region by a trench isolation structure, wherein the depths of the first N-well, the first P-well, the second N-well, the second P-well, and the third N-well are all greater than the depths of the P-type source / drain region and the N-type doped region; An electrostatic pulse detection circuit having a PMOS transistor has a control port and two voltage ports. Each of the voltage ports is electrically connected to the corresponding P-type source / drain region and the corresponding N-type doped region. A voltage difference exists between the two voltage ports. The control port is electrically connected to the P-type gate to output a control voltage to the P-type gate to control the on / off of the first PMOS transistor.

2. The PMOS tube triggered bidirectional silicon controlled rectifier according to claim 1, characterized in that: The electrostatic pulse detection circuit includes a first RC circuit, a second RC circuit, a second PMOS transistor and a third PMOS transistor, wherein the first RC circuit includes a first resistor and a first capacitor connected in series, and the second RC circuit includes a second resistor and a second capacitor connected in series; the gate of the second PMOS transistor is connected between the second resistor and the second capacitor, the gate of the third PMOS transistor is connected between the first resistor and the first capacitor, the drain of the second PMOS transistor and the drain of the third PMOS transistor are connected to form the control port; the first resistor, the second capacitor and the source of the second PMOS transistor are connected to form one voltage port; the first capacitor, the second resistor and the source of the third PMOS transistor are connected to form another voltage port.

3. The PMOS-triggered bidirectional silicon-controlled rectifier according to claim 2, wherein: The resistance values ​​of the first resistor and the second resistor are equal, and the capacitance values ​​of the first capacitor and the second capacitor are equal.

4. The PMOS-triggered bidirectional silicon-controlled rectifier according to claim 3, wherein: The time constant of the first RC circuit and the time constant of the second RC circuit are both 1 nS to 10 nS.

5. The PMOS-triggered bidirectional silicon-controlled rectifier according to claim 4, wherein: The resistance values ​​of the first resistor and the second resistor are 1KΩ to 10KΩ, and the capacitance values ​​of the first capacitor and the second capacitor are 0.2pF to 2pF.

6. The PMOS-triggered bidirectional silicon-controlled rectifier according to claim 2, wherein: The control voltage is obtained according to the length of the P-type gate, the doping concentration of the second N-well, the time constant of the first RC circuit, and the time constant of the second RC circuit.

7. The PMOS-triggered bidirectional silicon-controlled rectifier according to claim 1, wherein: One of the voltage ports is grounded, and the other voltage port is connected to a positive voltage.

8. The PMOS-triggered bidirectional silicon-controlled rectifier according to claim 1, wherein: Trench isolation structures are provided on the outer sides of the two N-type doping regions.

9. The PMOS-triggered bidirectional silicon-controlled rectifier according to claim 8, wherein: The depths of the first N-well, the first P-well, the second N-well, the second P-well, and the third N-well are all greater than the depth of the trench isolation structure.

Images