pmos triggered bidirectional scr

Abstract

The application provides a PMOS tube triggered bidirectional silicon controlled rectifier, which comprises a substrate, a deep N well above the substrate, a first N well, a first P well, a second N well, a second P well and a third N well arranged in sequence from left to right above the deep N well, a PMOS tube comprising a P-type gate and P-type source / drain regions on both sides of the P-type gate, two N-type doped regions in the first P well and the second P well respectively, an electrostatic pulse detection circuit with an NMOS tube, a control port and two voltage ports, each voltage port being electrically connected with a corresponding P-type source / drain region and a corresponding N-type doped region respectively, and the control port being electrically connected with the P-type gate to output a control voltage to the P-type gate to control the on-off of the PMOS tube, so that the triggering voltage of the bidirectional silicon controlled rectifier is reduced and the applicability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular to a PMOS triggered bidirectional silicon controlled rectifier. BACKGROUND

[0002] In the design of electrostatic protection of integrated circuits, the electrostatic protection design window is generally determined by the working voltage of the device and the thickness of the gate oxide layer of the internal protected circuit. However, after the electrostatic protection design window is designed according to the working voltage of the device and the thickness of the gate oxide layer of the internal protected circuit, it is often found that the triggering voltage of the device exceeds the electrostatic protection design window. If the device is directly used for electrostatic protection design, it is easy to cause reliability problems of the gate oxide layer of the device. For example, taking a 55nm process platform as an example, the working voltage of the core device (MOSFET) is 1.2V, and the thickness of the gate oxide layer is 2.5nm. Therefore, the electrostatic protection design window of the core device is usually designed to be 1.32V-5.2V. It is known by measurement that the triggering voltage of the core device is 6.7V, which exceeds the electrostatic protection design window of the core device. If the core device is directly used for electrostatic protection design, it is easy to cause reliability problems of the gate oxide layer of the core device. Therefore, the electrostatic protection design window of the core device is usually designed to be 1.32V-5.2V. It is known by measurement that the triggering voltage of the core device is 6.7V, which exceeds the electrostatic protection design window of the core device. If the core device is directly used for electrostatic protection design, it is easy to cause reliability problems of the gate oxide layer of the core device.

[0003] Figure 1 A PMOS triggered bidirectional silicon controlled rectifier is provided in the prior art. Please refer to Figure 1 , the device includes a first voltage port A, a second voltage port K and a control port D, and there is a voltage difference between the first voltage port A and the second voltage port K. The first voltage port A can be connected to positive voltage / ground, and the second voltage port K can be connected to ground / positive voltage. The control port D is the gate of the PMOS tube. The device has the characteristics of small area, small triggering voltage and high secondary breakdown current, and is suitable for electrostatic protection design of low-voltage devices. However, when applied to the electrostatic protection design of IO end to ground, when one voltage port is grounded and an electrostatic pulse is applied to the other voltage port, the gate of the PMOS tube is actually in a floating state. In general application scenarios, it can be considered that the gate of the PMOS tube is at a low potential at this time. However, in some high radiation environments, since the gate of the PMOS tube is connected to the power supply VDD, the gate of the PMOS tube is easily affected by radiation, causing the potential of the gate of the PMOS tube to become unstable, thereby causing the PMOS tube to be triggered incorrectly or not in time, resulting in damage or functional loss of the device. Therefore, an electrostatic pulse detection circuit is needed to accurately control the voltage applied to the control port D when an electrostatic pulse arrives to prevent the PMOS tube from being triggered incorrectly or not in time, resulting in damage or functional loss of the device. SUMMARY

[0004] The PMOS tube triggered bidirectional silicon controlled rectifier reduces the trigger voltage of the bidirectional silicon controlled rectifier and improves the applicability.

[0005] In order to achieve the above object, the application provides a PMOS tube triggered bidirectional silicon controlled rectifier, which comprises:

[0006] a substrate;

[0007] a deep N well above the substrate;

[0008] a first N well, a first P well, a second N well, a second P well and a third N well arranged in sequence above the deep N well from left to right;

[0009] a PMOS tube comprising a P-type gate and P-type source / drain regions on both sides of the P-type gate, the P-type gate being above the second N well, and the P-type source / drain regions on both sides of the P-type gate being respectively at the junction of the first P well and the second N well and the junction of the second N well and the second P well;

[0010] two N-type doped regions respectively in the first P well and the second P well, and each N-type doped region being isolated from the corresponding P-type source / drain region by a trench isolation structure;

[0011] an electrostatic pulse detection circuit with an NMOS tube, having a control port and two voltage ports, each voltage port being electrically connected to the corresponding P-type source / drain region and the corresponding N-type doped region respectively, and there being a voltage difference between the two voltage ports, the control port being electrically connected to the P-type gate to output a control voltage to the P-type gate to control the on-off of the PMOS tube.

[0012] Optionally, the electrostatic pulse detection circuit comprises a first RC circuit, a second RC circuit, a first NMOS tube and a second NMOS tube, wherein the first RC circuit comprises a first resistor and a first capacitor connected in series, and the second RC circuit comprises a second resistor and a second capacitor connected in series; the gate of the first NMOS tube is connected between the first resistor and the first capacitor, the gate of the second NMOS tube is connected between the second resistor and the second capacitor, and the drain of the first NMOS tube and the drain of the second NMOS tube are connected to form the control port; the first resistor, the second capacitor and the source of the first NMOS tube are connected to form one of the voltage ports; and the first capacitor, the second resistor and the source of the second NMOS tube are connected to form the other voltage port.

[0013] Optionally, the resistance values of the first resistor and the second resistor are equal, and the capacitance values of the first capacitor and the second capacitor are equal.

[0014] Optionally, the time constant of the first RC circuit and the time constant of the second RC circuit are both 1nS-10nS.

[0015] Optionally, the resistance of the first resistance and the second resistance is 1KΩ-10KΩ, and the capacitance of the first capacitance and the second capacitance is 0.2pF-2pF.

[0016] Optionally, the trigger voltage is obtained according to the length of the P-type gate, the doping concentration of the second N-well, the time constant of the first RC circuit and the time constant of the second RC circuit.

[0017] Optionally, one of the voltage ports is grounded, and the other voltage port is connected to a positive voltage.

[0018] Optionally, the depths of the first N-well, the first P-well, the second N-well, the second P-well and the third N-well are all greater than the depths of the P-type source / drain region and the N-type doped region.

[0019] Optionally, a trench isolation structure is arranged outside the two N-type doped regions.

[0020] Optionally, the depths of the first N-well, the first P-well, the second N-well, the second P-well and the third N-well are all greater than the depth of the trench isolation structure.

[0021] In the PMOS tube trigger bidirectional silicon controlled rectifier provided by the application, the PMOS tube includes a P-type gate and P-type source / drain regions on both sides of the P-type gate, the P-type gate is located above the second N-well, and the P-type source / drain regions on both sides of the P-type gate are located at the junctions of the first P-well and the second N-well and the second N-well and the second P-well, respectively; two N-type doped regions are located in the first P-well and the second P-well, respectively, and each N-type doped region is isolated from the corresponding P-type source / drain region by a trench isolation structure; the electrostatic pulse detection circuit with an NMOS tube has a control port and two voltage ports, each voltage port is electrically connected to the corresponding P-type source / drain region and the corresponding N-type doped region, respectively, there is a voltage difference between the two voltage ports, the control port is electrically connected to the P-type gate to output a control voltage to the P-type gate to control the on-off of the PMOS tube, and by controlling the conduction of the PMOS tube, the PMOS tube forms a channel current, which acts as a trigger current of the device, thereby triggering the device to work, so as to reduce the trigger voltage of the device; and in the application, the P-type gate is connected to the electrostatic pulse detection circuit to control the PMOS tube by the electrostatic pulse signal input from the voltage port, so as to avoid the mis-triggering or the non-timely triggering of the PMOS tube caused by the influence of radiation and the like, thereby improving the applicability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 The PMOS tube triggers a bidirectional silicon controlled rectifier;

[0023] Figure 2 The PMOS tube triggers a bidirectional silicon controlled rectifier for an embodiment of the present application;

[0024] In the drawings:

[0025] 10 - substrate; 11 - deep N well; 21 - first N well; 22 - first P well; 23 - second N well; 24 - second P well; 25 - third N well; 31 - first N-type doped region; 32 - second N-type doped region; 41 - first P-type doped region; 42 - second P-type doped region; 50 - trench isolation structure; 60 - P-type gate; R1 - first resistor; C1 - first capacitor; R2 - second resistor; C2 - second capacitor; N1 - first NMOS tube; N2 - second NMOS tube; A, A1 - first voltage port; K, K1 - second voltage port; D, D1 - control port. DETAILED DESCRIPTION

[0026] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. The advantages and features of the present application will be more apparent from the following description. It should be noted that the drawings are very simplified and are not drawn to scale, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0027] Figure 2 The PMOS tube triggers a bidirectional silicon controlled rectifier for the embodiment. Please refer to Figure 2 The present embodiment provides a PMOS tube triggered bidirectional silicon controlled rectifier, which comprises a substrate 10, a deep N well 11, a first N well 21, a first P well 22, a second N well 23, a second P well 24, a third N well 25, a PMOS tube, two N-type doped regions, an electrostatic pulse detection circuit with an NMOS tube, and a trench isolation structure 50. The deep N well 11 is located above the substrate 10, and the type of the substrate 10 is N-type. The first N well 21, the first P well 22, the second N well 23, the second P well 24, and the third N well 25 are arranged in order from left to right above the deep N well 11.

[0028] The PMOS tube includes a P-type gate 60 and P-type source / drain regions on both sides of the P-type gate 60. The P-type gate 60 is located above the second N-well 23, and a gate oxide layer (not shown in the figure) is provided between the P-type gate 60 and the second N-well 23. The P-type source / drain regions on both sides of the P-type gate 60 are located at the junction of the first P-well 22 and the second N-well 23 and the junction of the second N-well 23 and the second P-well 24, respectively. In this embodiment, the P-type source / drain regions on both sides of the P-type gate 60 are the first P-type doped region 41 and the second P-type doped region 42, respectively. If the P-type source region is the first P-type doped region 41, the P-type drain region is the second P-type doped region 42. If the P-type source region is the second P-type doped region 42, the P-type drain region is the first P-type doped region 41. The first P-type doped region 41 is located at the junction of the first P-well 22 and the second N-well 23, and the second P-type doped region 42 is located at the junction of the second N-well 23 and the second P-well 24. Since the device provided in this embodiment is a PMOS tube triggering a bidirectional silicon controlled rectifier, the bidirectional silicon controlled rectifier is symmetrical in structure, and therefore the positions of the P-type source region and the P-type drain region are not distinguished.

[0029] Two N-type doped regions are located in the first P-well 22 and the second P-well 24, respectively, and each N-type doped region is isolated from the corresponding P-type source / drain region by the trench isolation structure 50. In this embodiment, the two N-type doped regions are the first N-type doped region 31 and the second N-type doped region 32, respectively. The first N-type doped region 31 is located in the first P-well 22 and outside the first P-type doped region 41, and the second N-type doped region 32 is located in the second P-well 24 and outside the second P-type doped region 42. The first N-type doped region 31, the first P-type doped region 41, and the second N-type doped region 32 are all isolated from each other by the trench isolation structure 50.

[0030] In the embodiment, the trench isolation structure 50 is arranged outside the first N-type doped region 31 and the second N-type doped region 32, that is, the first N-type doped region 31 and the second N-type doped region 32 are located between the two trench isolation structures 50; the depths of the first N-well 21, the first P-well 22, the second N-well 23, the second P-well 24 and the third N-well 25 are greater than the depths of the first N-type doped region 31, the second N-type doped region 32, the first P-type doped region 41 and the second P-type doped region 42. The trench isolation structure 50 between the first N-type doped region 31 and the first P-type doped region 41 is located in the first P-well 22, and the trench isolation structure 50 between the second N-type doped region 32 and the second P-type doped region 42 is located in the second P-well 24, and the depths of the two trench isolation structures 50 are less than the depths of the first N-well 21, the first P-well 22, the second N-well 23, the second P-well 24 and the third N-well 25. The trench isolation structure 50 outside the first N-type doped region 31 is located at the junction of the first N-well 21 and the first P-well 22, and the trench isolation structure 50 outside the second N-type doped region 32 is located at the junction of the third N-well 25 and the second P-well 24, and the depths of the two trench isolation structures 50 are also less than the depths of the first N-well 21, the first P-well 22, the second N-well 23, the second P-well 24 and the third N-well 25.

[0031] The electrostatic pulse detection circuit with the NMOS tube has a control port D1 and two voltage ports, each voltage port is electrically connected with a corresponding P-type source / drain region and a corresponding N-type doped region, there is a voltage difference between the two voltage ports, the control port D1 is electrically connected with the P-type gate 60 of the PMOS tube to output a control voltage to the P-type gate 60 to control the on-off of the PMOS tube. In the embodiment, the two voltage ports are a first voltage port A1 and a second voltage port K1, the first voltage port A1 is electrically connected with the first N-type doped region 31 and the first P-type doped region 41, and the second voltage port K1 is electrically connected with the second N-type doped region 32 and the second P-type doped region 42. In the embodiment, the first voltage port A1 is grounded, and the second voltage port K1 is connected with a positive voltage; or, the first voltage port A1 is connected with a positive voltage, and the second voltage port K1 is grounded, but not limited to this, the connection of the first voltage port A1 and the second voltage port K1 is determined by the actual situation.

[0032] The electrostatic pulse detection circuit comprises a first RC circuit, a second RC circuit, a first NMOS tube N1 and a second NMOS tube N2. The first RC circuit comprises a first resistor R1 and a first capacitor C1 connected in series, and the second RC circuit comprises a second resistor R2 and a second capacitor C2 connected in series. The gate of the first NMOS tube N1 is connected between the first resistor R1 and the first capacitor C1, the gate of the second NMOS tube N2 is connected between the second resistor R2 and the second capacitor C2, the drain of the first NMOS tube N1 and the drain of the second NMOS tube N2 are connected to form a control port D1. The first resistor R1, the second capacitor C2 and the source of the first NMOS tube N1 are connected to form a first voltage port A1, and the first capacitor C1, the second resistor R2 and the source of the second NMOS tube N2 are connected to form a second voltage port K1.

[0033] In the embodiment, the time constant of the first RC circuit and the time constant of the second RC circuit are required to be equal. The time constant of the first RC circuit is the product of the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1, and the time constant of the second RC circuit is the product of the resistance value of the second resistor R2 and the capacitance value of the second capacitor C2. That is, the resistance value of the first resistor R1 and the resistance value of the second resistor R2 are required to be equal, and the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 are required to be equal. In the embodiment, the time constant of the first RC circuit and the time constant of the second RC circuit can be 1nS-10nS, the resistance value of the first resistor R1 and the resistance value of the second resistor R2 can be 1KΩ-10KΩ, and the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 can be 0.2pF-2pF, but are not limited to the time constant range, the resistance value range and the capacitance value range, and are determined according to actual conditions.

[0034] When the first voltage port A1 is connected to positive voltage and the second voltage port K1 is connected to ground, an external electrostatic pulse signal is input from the first voltage port A1, the first RC circuit forms a capacitor charging circuit, the T1 node of the first RC circuit is at low potential, i.e. the potential of the gate of the first NMOS tube N1 is at low potential, the first NMOS tube N1 is in the off state, and at this time the second RC circuit forms a voltage coupling circuit, the T2 node of the second RC circuit is at high potential, i.e. the potential of the gate of the second NMOS tube N2 is at high potential, the second NMOS tube N2 is in the on state, and since the source of the second NMOS tube N2 is connected to the second voltage port K1 which is connected to ground, the low potential of the second voltage port K1 will make the drain of the second NMOS tube N2 also at low potential, thereby making the P-type gate 60 of the PMOS tube at low potential, and the PMOS tube is turned on. After the PMOS tube is turned on, a channel current is formed between the first P-type doped region 41 and the second P-type doped region 42, the channel current flows from the first P-type doped region 41 to the second P-type doped region 42, and the channel current acts as a trigger current to reduce the trigger voltage of the PMOS tube trigger bidirectional silicon controlled rectifier. At this time, the current path formed by the PMOS tube trigger bidirectional silicon controlled rectifier is from the first voltage port A1 input, then through the first P-type doped region 41, the second N-well 23, the second P-well 24, the second N-type doped region 32 to the second voltage port K1 output, and it also includes the channel current path from the first P-type doped region 41 to the second P-type doped region 42 and then to the second voltage port K1 output. When the device is in static voltage bias or normally turned on, the T2 node is at low potential, the T1 node is at high potential, the potential of the gate of the second NMOS tube N2 is at low potential, the second NMOS tube N2 is in the off state, the potential of the gate of the first NMOS tube N1 is at high potential, the first NMOS tube N1 is in the on state, the first voltage port A1 is at high potential, thereby making the P-type gate 60 of the PMOS tube at high potential, and the PMOS tube is in the off state.

[0035] When the first voltage port A1 is grounded and the second voltage port K1 is connected to a positive voltage, an external electrostatic pulse signal is input from the second voltage port K1, the second RC circuit forms a capacitor charging circuit, and the T2 node of the second RC circuit is at a low potential, i.e., the potential of the gate of the second NMOS transistor N2 is at a low potential, and the second NMOS transistor N2 is in a cut-off state. At this time, the first RC circuit forms a voltage coupling circuit, the T1 node of the first RC circuit is at a high potential, i.e., the potential of the gate of the first NMOS transistor N1 is at a high potential, and the first NMOS transistor N1 is in a conducting state. Since the source of the first NMOS transistor N1 is connected to the first voltage port A1, the low potential of the first voltage port A1 will make the drain of the first NMOS transistor N1 also at a low potential, thereby making the P-type gate 60 of the PMOS transistor at a low potential and making the PMOS transistor conductive. After the PMOS transistor is conductive, a channel current is formed between the first P-type doped region 41 and the second P-type doped region 42, the channel current flows from the second P-type doped region 42 to the first P-type doped region 41, and the channel current acts as a trigger current to reduce the trigger voltage of the PMOS transistor trigger bidirectional silicon controlled rectifier. At this time, the current path formed by the PMOS transistor trigger bidirectional silicon controlled rectifier is from the second voltage port K1 input, then through the second P-type doped region 42, the second N-well 23, the first P-well 22, the first N-type doped region 31 to the first voltage port A1 output, and also includes the channel current path from the second P-type doped region 42 to the first P-type doped region 41 and then to the first voltage port A1 output. When the device is in a static voltage bias or normally turned on, the T1 node is at a low potential, the T2 node is at a high potential, the potential of the gate of the first NMOS transistor N1 is at a low potential, the first NMOS transistor N1 is in a cut-off state, the potential of the gate of the second NMOS transistor N2 is at a high potential, the second NMOS transistor N2 is in a conducting state, and the second voltage port K1 is at a high potential, thereby making the P-type gate 60 of the PMOS transistor at a high potential and making the PMOS transistor in a cut-off state.

[0036] In the present embodiment, the control voltage output by the control port D1 to the P-type gate 60 of the PMOS transistor can be obtained according to the length of the P-type gate 60, the doping concentration of the second N-well 23, the time constant of the first RC circuit and the time constant of the second RC circuit, wherein adjusting the time constant of the first RC circuit and the time constant of the second RC circuit can reduce the control voltage.

[0037] In the embodiment, the P-type gate 60 of the PMOS tube is connected with the first NMOS tube N1 and the second NMOS tube N2, two RC circuits are connected in parallel between the first voltage port A1 and the second voltage port K1, and the working states of the first NMOS tube N1 and the second NMOS tube N2 are controlled by the two RC circuits, so as to control the on-off of the PMOS tube by the input static pulse signal, trigger the bidirectional silicon controlled rectifier by the PMOS tube, avoid the problem that the potential of the P-type gate 60 of the PMOS tube is easily affected by radiation when the P-type gate 60 of the PMOS tube is directly connected with the power supply VDD, and make the PMOS tube be controlled by the static pulse detected by the static pulse detection circuit, so that the potential of the P-type gate 60 of the PMOS tube is affected by the input static pulse signal and directly responds to the input static pulse signal, and the problem that the PMOS tube is mis-triggered or triggered not in time due to the unstable potential of the P-type gate 60 is avoided, thereby improving the applicability of the device and enabling the device to be applicable to a high-radiation environment.

[0038] In summary, in the PMOS tube triggered bidirectional silicon controlled rectifier provided by the application, the PMOS tube comprises a P-type gate and P-type source / drain regions located on both sides of the P-type gate, the P-type gate is located above a second N-well, the P-type source / drain regions on both sides of the P-type gate are located at the junction of a first P-well and the second N-well and the junction of the second N-well and a second P-well respectively, two N-type doped regions are located in the first P-well and the second P-well respectively, and each N-type doped region is isolated from the corresponding P-type source / drain region by a trench isolation structure, the static pulse detection circuit with an NMOS tube has a control port and two voltage ports, each voltage port is electrically connected with the corresponding P-type source / drain region and the corresponding N-type doped region respectively, there is a voltage difference between the two voltage ports, the control port is electrically connected with the P-type gate to output a control voltage to the P-type gate to control the on-off of the PMOS tube, the conduction of the PMOS tube is controlled to make the PMOS tube form a channel current, the channel current acts as a trigger current of the device, and the device is triggered to work, so as to reduce the trigger voltage of the device, and in the application, the P-type gate is connected with the static pulse detection circuit to control the PMOS tube by the static pulse signal input from the voltage port, so as to avoid the problem that the PMOS tube is mis-triggered or triggered not in time due to the influence of radiation on the PMOS tube, thereby improving the applicability of the device.

[0039] The above is only the preferred embodiment of the application, and does not limit the application in any way. Any person skilled in the art can make any equivalent replacement, modification or change to the technical solutions and technical contents disclosed in the application without departing from the scope of the technical solutions of the application, and the application still falls within the protection scope of the application.

Claims

1. A PMOS triggered bidirectional silicon controlled rectifier, characterized in that, include: Substrate; A deep N-well is located above the substrate; The first N-well, the first P-well, the second N-well, the second P-well, and the third N-well are arranged from left to right above the deep N-well; A PMOS transistor includes a P-type gate and P-type source / drain regions located on both sides of the P-type gate. The P-type gate is located above the second N-well. The P-type source / drain regions on both sides of the P-type gate are located at the junction of the first P-well and the second N-well and the junction of the second N-well and the second P-well, respectively. Two N-type doped regions are located in the first P-well and the second P-well, respectively, and each N-type doped region is isolated from the corresponding P-type source / drain region by a trench isolation structure; An electrostatic pulse detection circuit with an NMOS transistor has a control port and two voltage ports. Each voltage port is electrically connected to the corresponding P-type source / drain region and the corresponding N-type doped region, respectively. There is a voltage difference between the two voltage ports. The control port is electrically connected to the P-type gate to output a control voltage to the P-type gate to control the on / off state of the PMOS transistor. The electrostatic pulse detection circuit includes a first RC circuit, a second RC circuit, a first NMOS transistor, and a second NMOS transistor. The first RC circuit includes a first resistor and a first capacitor connected in series, and the second RC circuit includes a second resistor and a second capacitor connected in series. The gate of the first NMOS transistor is connected between the first resistor and the first capacitor, and the gate of the second NMOS transistor is connected between the second resistor and the second capacitor. The drains of the first NMOS transistor and the drains of the second NMOS transistor are connected to form the control port. The first resistor, the second capacitor, and the source of the first NMOS transistor are connected to form one voltage port. The first capacitor, the second resistor, and the source of the second NMOS transistor are connected to form another voltage port.

2. The PMOS trigger bidirectional silicon controlled rectifier as claimed in claim 1, wherein, The resistance values ​​of the first resistor and the second resistor are equal, and the capacitance values ​​of the first capacitor and the second capacitor are equal.

3. The PMOS trigger bidirectional silicon controlled rectifier as claimed in claim 2, wherein, The time constants of the first RC circuit and the second RC circuit are both 1nS to 10nS.

4. The PMOS trigger bidirectional silicon controlled rectifier of claim 3, wherein, The resistance values ​​of the first resistor and the second resistor are 1KΩ~10KΩ, and the capacitance values ​​of the first capacitor and the second capacitor are 0.2pF~2pF.

5. The PMOS trigger bidirectional silicon controlled rectifier as described in claim 1, wherein, The control voltage is obtained based on the length of the P-type gate, the doping concentration of the second N-well, the time constant of the first RC circuit, and the time constant of the second RC circuit.

6. The PMOS trigger bidirectional silicon controlled rectifier as described in claim 1, wherein, One of the voltage ports is grounded, and the other voltage port is connected to a positive voltage.

7. The PMOS trigger bidirectional silicon controlled rectifier as described in claim 1, wherein, The depths of the first N-well, the first P-well, the second N-well, the second P-well, and the third N-well are all greater than the depths of the P-type source / drain region and the N-type doped region.

8. The PMOS trigger bidirectional silicon controlled rectifier as claimed in claim 1, wherein, A trench isolation structure is provided on the outer side of both N-type doped regions.

9. The PMOS trigger bidirectional silicon controlled rectifier as claimed in claim 8, wherein, The depths of the first N-well, the first P-well, the second N-well, the second P-well, and the third N-well are all greater than the depth of the trench isolation structure.

Images