Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application provides a semiconductor device manufacturing method and a semiconductor device. In the semiconductor device manufacturing method, a plurality of first dummy metal contact structures are arranged near the first metal contact structure in the semiconductor device chip to share and lead the static electricity caused by subsequent etching. In addition, in the circuit chip, an electrostatic elimination circuit electrically connected with the first dummy metal contact structure is additionally arranged to capture or eliminate the static electricity accumulated on the first dummy metal contact structure through the electrostatic elimination circuit, further strengthen the sharing and leading effect of the static electricity, thereby greatly reducing the amount of static electricity conducted to the control circuit on the circuit chip through the first metal contact structure and the second metal contact structure, effectively avoiding the damage of the static electricity caused by etching to the control circuit, and enhancing the structural stability and reliability of the control circuit on the circuit chip.

Description

[0001] [Related Applications]

[0002] This application is a divisional application of Chinese patent application CN202011169455.8, "Manufacturing method of three-dimensional memory and three-dimensional memory" (application date: October 28, 2020). Technical Field

[0003] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Technology

[0004] 3D memory is a technology for stacking data units. Currently, it is possible to stack data units of 32 layers or more. It overcomes the limitation of the actual expansion limit of planar memory, further increases storage capacity, reduces the storage cost per data bit, and reduces energy consumption.

[0005] However, in current 3D memory manufacturing methods, after the array chip and circuit chip are bonded, the substrate of the array chip still needs to be etched to bring out the metal interconnect structure from the back of the array chip. This requires processes such as plasma etching and deposition. In this process, the ions from plasma etching carry a large amount of static electricity, which will be transmitted along the metal interconnect structure to the various control circuits in the circuit chip, causing structural damage to the control circuits and leading to a decrease in the reliability of the 3D memory.

[0006] Therefore, how to effectively reduce the damage to the control circuit structure in the circuit chip caused by etching and deposition processes after bonding the array chip and the circuit chip is an urgent problem to be solved. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for manufacturing a three-dimensional memory capable of shunting and dissipating static electricity, in order to solve the above-mentioned technical problems.

[0008] To achieve the above and other related objectives, the present invention provides a method for manufacturing a three-dimensional memory, comprising:

[0009] An array chip with a first substrate is provided. The first substrate has a front side and a back side disposed opposite to each other. The front side of the first substrate includes a core array region and an edge connection region. The array chip includes a memory array structure disposed on the core array region, a first metal contact structure disposed on the edge connection region, and a first virtual metal contact structure disposed on the edge connection region and disposed around the first metal contact structure.

[0010] A circuit chip having a second substrate is provided, the circuit chip including a control circuit, an electrostatic discharge circuit, a second metal contact structure electrically connected to the control circuit, and a second virtual metal contact structure electrically connected to the electrostatic discharge circuit, disposed on the second substrate;

[0011] The array chip and the circuit chip are bonded together, such that the first metal contact structure is electrically connected to the second metal contact structure, and the first virtual metal contact structure is electrically connected to the second virtual metal contact structure.

[0012] The back side of the first substrate is etched to form a contact hole on the first substrate, the contact hole exposing the first metal contact structure.

[0013] Optionally, the step of forming the array chip includes:

[0014] A stacked structure is formed on the core array region, and a first dielectric structure is formed on the edge connection region;

[0015] The memory array structure is formed in the stacked structure, and a plurality of first metal contact structures and a plurality of first virtual metal contact structures are formed in the first dielectric structure.

[0016] Optionally, a plurality of the first virtual metal contact structures are arranged around at least one first metal contact structure, or a first virtual metal contact structure is arranged around a first metal contact structure.

[0017] Optionally, the step of forming the circuit chip includes:

[0018] Multiple independent control circuits and electrostatic elimination circuits are formed in the second substrate;

[0019] A second dielectric structure is formed on the second substrate, and a second metal contact structure and a second virtual metal contact structure are formed in the second dielectric structure.

[0020] Optionally, the plurality of second virtual metal contact structures correspond one-to-one with and are electrically connected to the plurality of electrostatic elimination circuits.

[0021] Optionally, the step of bonding the array chip to the circuit chip includes:

[0022] A first pad electrically connected to the first metal contact structure and a second pad electrically connected to the first virtual metal contact structure are formed on the surface of the first dielectric structure.

[0023] A third pad electrically connected to the second metal contact structure and a fourth pad electrically connected to the second virtual metal contact structure are formed on the surface of the second dielectric structure.

[0024] The first pad and the third pad are bonded to achieve an electrical connection between the first metal contact structure and the second metal contact structure; the second pad and the fourth pad are bonded to achieve an electrical connection between the first virtual metal contact structure and the second virtual metal contact structure.

[0025] Optionally, the first metal contact structure is electrically connected to the first pad through a first interconnect layer, the first virtual metal contact structure is electrically connected to the second pad through a first virtual interconnect layer, the second metal contact structure is electrically connected to the third pad through a second interconnect layer, and the second virtual metal contact structure is electrically connected to the fourth pad through a second virtual interconnect layer.

[0026] Optionally, the method for manufacturing the three-dimensional memory further includes:

[0027] The contact hole is filled to form a third metal contact structure, which is electrically connected to the first metal contact structure.

[0028] In addition, to achieve the above and other related objectives, the present invention also provides a three-dimensional memory, comprising:

[0029] The array chip includes a storage array structure, a first metal contact structure, and a first virtual metal contact structure disposed around the first metal contact structure.

[0030] The circuit chip includes a control circuit, a second metal contact structure electrically connected to the control circuit, an electrostatic elimination circuit, and a second virtual metal contact structure electrically connected to the electrostatic elimination circuit.

[0031] The array chip and the circuit chip are bonded together, the first metal contact structure is electrically connected to the second metal contact structure, and the first virtual metal contact structure is electrically connected to the second virtual metal contact structure.

[0032] Optionally, in the array chip, a plurality of first virtual metal contact structures are arranged around at least one first metal contact structure, or a first virtual metal contact structure is arranged around a first metal contact structure; in the circuit chip, a plurality of second virtual metal contact structures correspond one-to-one with and are electrically connected to a plurality of electrostatic elimination circuits.

[0033] Optionally, the electrostatic discharge circuit includes at least a PN junction.

[0034] Optionally, a first pad and a second pad are formed on the surface of the array chip. The first pad is electrically connected to the first metal contact structure, and the second pad is electrically connected to the first virtual metal contact structure. A third pad and a fourth pad are formed on the surface of the circuit chip. The third pad is electrically connected to the second metal contact structure, and the fourth pad is electrically connected to the second virtual metal contact structure. The first pad and the third pad are bonded together, so that the first metal contact structure is electrically connected to the second metal contact structure. The second pad and the fourth pad are bonded together, so that the first virtual metal contact structure is electrically connected to the second virtual metal contact structure.

[0035] Optionally, the substrate of the array chip includes a front side and a back side disposed opposite to each other. The storage array structure, the first metal contact structure, and the first virtual metal contact structure are disposed on the front side of the substrate of the array chip. A third metal contact structure penetrating the substrate of the array chip is also formed on the array chip. The third metal contact structure electrically leads the first metal contact structure out from the back side of the substrate of the array chip.

[0036] As described above, the manufacturing method of the three-dimensional memory provided by the present invention has the following beneficial effects:

[0037] In the array chip, a first virtual metal contact structure is arranged around the first metal contact structure. When the first substrate is subsequently etched to bring out the first metal contact structure, the first virtual metal contact structure can distribute and guide the static electricity brought by the etching ions, effectively reducing the static electricity accumulated on the first metal contact structure. At the same time, an electrostatic discharge circuit electrically connected to the first virtual metal contact structure is also provided in the circuit chip, which can eliminate or store the static electricity accumulated on the first virtual metal contact structure, further enhancing the effect of the first virtual metal contact structure in distributing and guiding static electricity. This greatly reduces the static electricity transmitted from the first metal contact structure to the control circuit on the circuit chip, effectively avoiding damage to the structure of the control circuit by large static electricity, and enhancing the structural stability and reliability of the control circuit. Attached Figure Description

[0038] Figure 1 The diagram shows a process flow chart for manufacturing a three-dimensional memory.

[0039] Figure 2 This diagram illustrates the steps of the manufacturing method of the three-dimensional memory in this invention.

[0040] Figures 3-19 The diagram shows the process flow of the manufacturing method of the three-dimensional memory in this invention.

[0041] Explanation of icon numbers

[0042] 1-Array chip, 2-Circuit chip, 3-Bonding connection between array chip 1 and circuit chip 2, 10-First substrate, 10a-Front side of first substrate 10, 10b-Back side of first substrate 10, 101, 103-Edge connection area of ​​front side 10a of first substrate 10, 102-Core array area of ​​front side 10a of first substrate 10, 1A-Stacked structure, 1B-First dielectric structure, 11-First metal contact structure, 12-First virtual metal contact structure, 20-Second substrate, 20a-Front side of second substrate 20, 20b-Back side of second substrate 20, 2B-Second dielectric structure, 21-Control circuit, 22-Isolation structure, 23-Second metal contact structure, 24-Static discharge circuit, 25-Second virtual metal contact structure, 31-First pad, 32-Second pad, 33-Third pad, 34-Fourth pad, 3B-Third dielectric structure, 41-Third metal contact structure. Detailed Implementation

[0043] The inventors discovered that in the current manufacturing process of 3D memory, such as Figure 1 As shown, after the array chip (i.e., the memory array wafer) 1 and the circuit chip (i.e., the CMOS circuit wafer) 2 are bonded together by the bonding connection part 3, it is necessary to etch the substrate 10 of the array chip 1 to bring out the first metal contact structure 11 from the back side of the array chip 1. This requires plasma etching, where the ions in the plasma etching carry electrostatic charge ( Figure 1 (with a "+" sign in the middle) Static electricity will be conducted along the first metal contact structure 11, the first pad 31, the third pad 33 and the second metal contact structure 23 to the control circuit 21 on the circuit chip 2. A large amount of static electricity accumulation will cause structural damage to the control circuit 21, resulting in a decrease in the reliability of the three-dimensional memory.

[0044] Therefore, this invention proposes a method for manufacturing a three-dimensional memory based on the design principle of electrostatic guidance, diversion, storage, or elimination: In the array chip 1, when forming the first metal contact structure 11, a first virtual metal contact structure is simultaneously formed around the first metal contact structure 11 to divert and distribute static electricity; In addition, in the circuit chip 2, an electrostatic elimination circuit independent of the control circuit 21 is added, and the electrostatic elimination circuit is electrically connected to the first virtual metal contact structure so as to eliminate or store the static electricity accumulated on the first virtual metal contact structure through the electrostatic elimination circuit, thereby enhancing the effect of diverting and distributing static electricity.

[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] Please see Figures 2 to 19 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, and sizes shown in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention. Furthermore, the terms such as "upper," "lower," "middle," "front," "back," and "first" used in this specification are only for clarity of description and are not intended to limit the scope of the present invention. Changes or adjustments in their relative relationships, without substantially altering the technical content, should also be considered within the scope of the present invention.

[0047] like Figure 2 As shown, the present invention provides a method for manufacturing a three-dimensional memory, which includes the following steps:

[0048] S1. Provide an array chip 1 having a first substrate 10. The first substrate 10 has a front side 10a and a back side 10b disposed opposite to each other. The front side 10a of the first substrate 10 includes a core array region 102 and edge connection regions 101 and 103. The array chip 1 includes a storage array structure disposed on the core array region 102, a first metal contact structure 11 disposed on the edge connection regions 101 and 103, and a first virtual metal contact structure 12 disposed on the edge connection regions 101 and 103 and disposed around the first metal contact structure 11.

[0049] S2. Provide a circuit chip 2 having a second substrate 20. The circuit chip 2 includes a control circuit 21 disposed on the second substrate 20, an electrostatic discharge circuit 24, a second metal contact structure 23 electrically connected to the control circuit 21, and a second virtual metal contact structure 25 electrically connected to the electrostatic discharge circuit 24.

[0050] S3, bonding array chip 1 and circuit chip 2, so that the first metal contact structure 11 and the second metal contact structure 23 are electrically connected, and the first virtual metal contact structure 12 and the second virtual metal contact structure 25 are electrically connected.

[0051] S4. Etch the back side 10b of the first substrate 10 to form a contact hole on the first substrate 10, and expose the first metal contact structure 11 through the contact hole.

[0052] In detail, such as Figure 3 As shown, in step S1, the provided array chip 1 has a first substrate 10, on which a stacked structure 1A and a first dielectric structure 1B are formed. A storage array structure (not shown in the figure) is formed in the stacked structure 1A, and a first metal contact structure 11 and a first virtual metal contact structure 12 disposed around the first metal contact structure 11 are formed in the first dielectric structure 1B.

[0053] More in detail, such as Figure 4 As shown, the first substrate 10 has a front side 10a and a back side 10b disposed opposite to each other, and the front side 10a of the first substrate 10 includes a core array region 102 and edge connection regions 101 and 103, with the core array region 102 located between the edge connection regions 101 and 103; wherein, the first substrate 10 can be a single crystal silicon substrate, Ge substrate, SiGe substrate, SOI substrate or GOI substrate, etc., and the appropriate semiconductor material can be selected according to the actual needs of the device, which is not limited here.

[0054] In detail, such as Figures 5-7 As shown, step S1 of forming the array chip 1 having the first substrate 10 further includes:

[0055] S11, such as Figure 5 As shown, a stacked structure 1A is formed on the core array region 102, and a first dielectric structure 1B is formed on the edge connection regions 101 and 103;

[0056] S12, such as Figures 6-7 As shown, a memory array structure (not shown) is formed in the stacked structure 1A, and a plurality of first metal contact structures 11 and a plurality of first virtual metal contact structures 12 are formed in the first dielectric structure 1B.

[0057] The stacked structure 1A includes multiple alternating stacked pseudo-gate layers and dielectric layers. One dielectric layer and an adjacent pseudo-gate layer constitute a composite layer. The number of composite layers in the stacked structure can be flexibly designed. Detailed process steps for forming the memory array substructure in the stacked structure 1A, such as forming the conductive channel structure and replacing the gate layer, can be referred to the existing technology and will not be elaborated here.

[0058] More in detail, such as Figure 7 As shown, taking the first dielectric structure 1B on the edge connection area 103 as an example, a plurality of first metal contact structures 11 and a plurality of first virtual metal contact structures 12 are formed in the first dielectric structure 1B. The first virtual metal contact structures 12 are arranged around the first metal contact structures 11. Optionally, the plurality of first virtual metal contact structures 12 are arranged around at least one first metal contact structure 11, or a first virtual metal contact structure 12 is arranged around a first metal contact structure 11, such as... Figure 6 A first virtual metal contact structure 12 is provided between two adjacent first metal contact structures 11 shown.

[0059] in, Figure 3 , Figures 6-7 The ellipsis in the figure indicates the corresponding extensions of the first metal contact structure 11 and the first virtual metal contact structure 12, which are not fully shown; optionally, a first interconnect layer (not shown in the figure) is also formed on the top of the first metal contact structure 11 for external electrical connection, and a first virtual interconnect layer (not shown in the figure) is also formed on the top of the first virtual metal contact structure 12 for external electrical connection.

[0060] It is understandable that there are several possible positions between the first metal contact structure 11 and the first virtual metal contact structure 12: one virtual metal contact structure 12 may be set around one first metal contact structure 11, or multiple virtual metal contact structures 12 may be set around one or more first metal contact structures 11 (for example, if the first metal contact structures 11 are densely packed, there is no space between two first metal contact structures 11 to set a virtual metal contact structure 12). As long as it serves the purpose of diverting the flow, it is acceptable.

[0061] Ultimately, we obtained the following: Figure 6 The array chip 1 shown is... Figure 7 Only the portion located on the edge connection area 103 is shown in the image.

[0062] In detail, such as Figure 8 As shown, in step S2, a circuit chip 2 having a second substrate 20 is provided. A second dielectric structure 2B is formed on the second substrate 20. The circuit chip 2 includes a control circuit 21, an isolation structure 22, and an electrostatic discharge circuit 24 disposed in the second substrate 20. The circuit chip 2 also includes a second metal contact structure 23 disposed in the second dielectric structure 2B and electrically connected to the control circuit 21, and a second virtual metal contact structure 25 electrically connected to the electrostatic discharge circuit 24.

[0063] More in detail, such as Figure 9As shown, the second substrate 20 has a front side 20a and a back side 20b disposed opposite to each other; wherein, the second substrate 20 can be a single crystal silicon substrate, Ge substrate, SiGe substrate, SOI substrate or GOI substrate, etc., and the appropriate semiconductor material can be selected according to the actual needs of the device, which is not limited here.

[0064] In detail, such as Figures 10-14 As shown, step S2 of forming the circuit chip 2 having the second substrate 20 further includes:

[0065] S21, such as Figures 10-13 As shown, multiple independent control circuits 21 and static elimination circuits 24 are formed in the second substrate 20;

[0066] S22, such as Figures 11-14 As shown, a second dielectric structure 2B is formed on the second substrate 20, and a second metal contact structure 23 and a second dummy metal contact structure 25 are formed in the second dielectric structure 2B. More specifically, in step S21, as... Figures 10-13 As shown, multiple independent control circuits 21, isolation structures 22, and electrostatic discharge circuits 24 are formed in the second substrate 20. The control circuits 21 can be logic device structures such as switches, and the control circuits 21 are surrounded by isolation structures (or protective rings) 22 to physically isolate and protect them. Figures 10-14 As shown, the electrostatic discharge circuit 24 can be the simplest PN junction, which can capture and store static electricity. It is understood that the electrostatic discharge circuit 24 can also be other storage circuits or ground release circuits, which will not be elaborated here.

[0067] In this configuration, multiple electrostatic discharge circuits 24 correspond one-to-one with multiple second virtual metal contact structures 12. For example, at least one electrostatic discharge circuit 24 is provided between two adjacent control circuits 21, corresponding to the first virtual metal contact structure 12 on the first substrate 10. Optionally, such as... Figure 10-13 As shown, an electrostatic elimination circuit 24 is provided between two adjacent control circuits 21.

[0068] In detail, in step S22, as Figures 11-14 As shown, a second metal contact structure 23 and a second virtual metal contact structure 25 are formed in the second dielectric structure 2B. The second metal contact structure 23 is electrically connected to the control circuit 21, and the second virtual metal contact structure 25 is electrically connected to the static elimination circuit 24. Finally, the result is as follows: Figure 12 The circuit chip 2 shown is... Figure 13 Only the portion corresponding to the edge connection area 103 is shown in the image.

[0069] in, Figure 8 , Figures 12-13The ellipsis in the figure indicates the corresponding extensions of the second metal contact structure 23 and the second virtual metal contact structure 25, which are not fully shown; optionally, a second interconnect layer (not shown in the figure) is also formed on the top of the second metal contact structure 23 for external electrical connection, and a second virtual interconnect layer (not shown in the figure) is also formed on the top of the second virtual metal contact structure 25 for external electrical connection.

[0070] In detail, such as Figures 15-17 As shown, step S3 of bonding array chip 1 and circuit chip 2 further includes:

[0071] S31, such as Figure 15 As shown, a first pad 31 electrically connected to the first metal contact structure 11 and a second pad 32 electrically connected to the first virtual metal contact structure 12 are formed on the surface of the first dielectric structure 1B.

[0072] S32, such as Figure 16 As shown, a third pad 33 electrically connected to the second metal contact structure 23 and a fourth pad 34 electrically connected to the second virtual metal contact structure 25 are formed on the surface of the second dielectric structure 2B.

[0073] S33, such as Figure 17 As shown, the first pad 31 and the third pad 33 are bonded to achieve electrical connection between the first metal contact structure 11 and the second metal contact structure 23; the second pad 32 and the fourth pad 34 are bonded to achieve electrical connection between the first virtual metal contact structure 12 and the second virtual metal contact structure 25.

[0074] The first metal contact structure 11 is electrically connected to the first pad 31 through the first interconnect layer (not shown in the figure), the first virtual metal contact structure 12 is electrically connected to the second pad 32 through the first virtual interconnect layer (not shown in the figure), the second metal contact structure 23 is electrically connected to the third pad 33 through the second interconnect layer (not shown in the figure), and the second virtual metal contact structure 25 is electrically connected to the fourth pad 34 through the second virtual interconnect layer (not shown in the figure).

[0075] It is understood that the first interconnect layer and the second interconnect layer each include one or more metal layers to electrically connect the first metal contact structure 11 and the second metal contact structure 23; similarly, the first virtual interconnect layer and the second virtual interconnect layer each include one or more metal layers to electrically connect the first virtual metal contact structure 12 and the second virtual metal contact structure 25.

[0076] Optionally, such as Figures 18-19 As shown, after the array chip 1 and the circuit chip 2 are bonded, the manufacturing method of the three-dimensional memory further includes the following steps:

[0077] S4. A third dielectric structure 3B is formed on the back side 10b of the first substrate 10, and then the third dielectric structure 3B and the first substrate 10 are etched from the back side 10b of the first substrate 10 to form a contact hole on the third dielectric structure 3B and the first substrate 10, which exposes the first metal contact structure 11.

[0078] S5. Fill the contact hole to form a third metal contact structure 41 (i.e., pad). The third metal contact structure 41 is electrically connected to the first metal contact structure 11. The third metal contact structure 41 is mainly used for the electrical connection between the three-dimensional memory and the outside world.

[0079] In detail, in step S4, since the array chip 1 has a plurality of first virtual metal contact structures 12 arranged around the first metal contact structure 11, it can divert and distribute the static electricity caused by etching. In addition, in the circuit chip 2, an electrostatic discharge circuit 24 electrically connected to the first virtual metal contact structure 12 is added. The electrostatic discharge circuit 24 can capture or eliminate the static electricity accumulated on the first virtual metal contact structure 12, further enhancing the effect of diverting and distributing static electricity. This can greatly reduce the amount of static electricity conducted to the control circuit 21 through the first metal contact structure 11 and the second metal contact structure 23, and effectively avoid damage to the control circuit 21 caused by etching.

[0080] Ultimately, we obtained the following: Figure 19 The three-dimensional memory shown includes:

[0081] The array chip 1 includes a storage array structure (not shown in the figure), a first metal contact structure 11, and a first virtual metal contact structure 12 disposed around the first metal contact structure 11;

[0082] The circuit chip 2 includes a control circuit 21, a second metal contact structure 23 electrically connected to the control circuit 21, an electrostatic elimination circuit 24, and a second virtual metal contact structure 25 electrically connected to the electrostatic elimination circuit 24.

[0083] In this configuration, array chip 1 and circuit chip 2 are bonded together, the first metal contact structure 11 is electrically connected to the second metal contact structure 23, and the first virtual metal contact structure 12 is electrically connected to the second virtual metal contact structure 25.

[0084] Optionally, in the array chip 1, a plurality of first virtual metal contact structures 12 are arranged around at least one first metal contact structure 11, or a first virtual metal contact structure 12 is arranged around a first metal contact structure 11, which is not limited to... Figure 19 As shown; in circuit chip 2, multiple second virtual metal contact structures 25 correspond one-to-one with and are electrically connected to multiple static elimination circuits 24, and are not limited to Figure 19As shown. The static electricity elimination circuit 24 includes at least a PN junction.

[0085] In detail, such as Figure 19 As shown, a first pad 31 and a second pad 32 are formed on the surface of the array chip 1. The first pad 31 is electrically connected to the first metal contact structure 11, and the second pad 32 is electrically connected to the first virtual metal contact structure 12. A third pad 33 and a fourth pad 34 are formed on the surface of the circuit chip 2. The third pad 33 is electrically connected to the second metal contact structure 23, and the fourth pad 34 is electrically connected to the second virtual metal contact structure 25. The first pad 31 and the third pad 33 are bonded together, so that the first metal contact structure 11 and the second metal contact structure 23 are electrically connected. The second pad 32 and the fourth pad 34 are bonded together, so that the first virtual metal contact structure 12 and the second virtual metal contact structure 25 are electrically connected.

[0086] Optionally, the substrate (i.e., the first substrate 10) of the array chip 1 includes a front side 10a and a back side 10b disposed opposite to each other. The storage array structure, the first metal contact structure 11 and the first virtual metal contact structure 12 are all disposed on the front side 10a of the substrate of the array chip 1. A third metal contact structure 41 is also formed on the array chip 1, penetrating the substrate of the array chip 1. The third metal contact structure 41 electrically leads the first metal contact structure 11 out from the back side 10b of the substrate of the array chip 1.

[0087] In summary, in the manufacturing method and the three-dimensional memory provided by this invention, since multiple first virtual metal contact structures are formed around the first metal contact structure in the array chip, the static electricity caused by etching can be distributed and diverted. In addition, an electrostatic discharge circuit electrically connected to the first virtual metal contact structure is added to the circuit chip, so that the static electricity accumulated on the first virtual metal contact structure can be captured or eliminated by the electrostatic discharge circuit, further enhancing the effect of distributing and diverting static electricity. This can greatly reduce the amount of static electricity conducted to the control circuit on the circuit chip through the first metal contact structure and the second metal contact structure, effectively avoid damage to the control circuit caused by etching, and enhance the structural stability and reliability of the control circuit on the circuit chip.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor device chip having a first substrate is provided, the first substrate having a front side and a back side disposed opposite to each other, the front side of the first substrate including an edge connection region, the semiconductor device chip including a first metal contact structure and a first virtual metal contact structure disposed on the edge connection region, the first virtual metal contact structure being disposed adjacent to the first metal contact structure; A circuit chip having a second substrate is provided, the circuit chip including a control circuit, an electrostatic discharge circuit, a second metal contact structure electrically connected to the control circuit, and a second virtual metal contact structure electrically connected to the electrostatic discharge circuit, disposed on the second substrate; The semiconductor device chip and the circuit chip are bonded together, such that the first metal contact structure and the second metal contact structure are electrically connected, and the first virtual metal contact structure and the second virtual metal contact structure are electrically connected. The back side of the first substrate is etched to form a contact hole on the first substrate, the contact hole exposing the first metal contact structure.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The semiconductor device chip includes an array chip, the array chip including a first metal contact structure and a first virtual metal contact structure disposed on the edge connection region, the front side of the first substrate further including a core array region, and the array chip further including a memory array structure disposed on the core array region. The steps for forming the array chip include: A stacked structure is formed on the core array region, and a first dielectric structure is formed on the edge connection region; The memory array structure is formed in the stacked structure, and a plurality of first metal contact structures and a plurality of first virtual metal contact structures are formed in the first dielectric structure.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, Multiple first virtual metal contact structures are arranged around at least one first metal contact structure, or a first virtual metal contact structure is arranged adjacent to a first metal contact structure.

4. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The steps for forming the circuit chip include: Multiple independent control circuits and electrostatic elimination circuits are formed in the second substrate; A second dielectric structure is formed on the second substrate, and a second metal contact structure and a second virtual metal contact structure are formed in the second dielectric structure.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, Each of the second virtual metal contact structures corresponds to and is electrically connected to one of the electrostatic elimination circuits.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The steps of bonding the semiconductor device chip and the circuit chip include: A first pad electrically connected to the first metal contact structure and a second pad electrically connected to the first virtual metal contact structure are formed on the surface of the first dielectric structure. A third pad electrically connected to the second metal contact structure and a fourth pad electrically connected to the second virtual metal contact structure are formed on the surface of the second dielectric structure. The first pad and the third pad are bonded to achieve an electrical connection between the first metal contact structure and the second metal contact structure; the second pad and the fourth pad are bonded to achieve an electrical connection between the first virtual metal contact structure and the second virtual metal contact structure.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The first metal contact structure is electrically connected to the first pad through the first interconnect layer, the first virtual metal contact structure is electrically connected to the second pad through the first virtual interconnect layer, the second metal contact structure is electrically connected to the third pad through the second interconnect layer, and the second virtual metal contact structure is electrically connected to the fourth pad through the second virtual interconnect layer.

8. The method for manufacturing a semiconductor device according to claim 1 or 7, characterized in that, The method for manufacturing the semiconductor device further includes: The contact hole is filled to form a third metal contact structure, which is electrically connected to the first metal contact structure.

9. A semiconductor device, characterized in that, include: A semiconductor device chip includes a device structure, a first metal contact structure, and a first virtual metal contact structure disposed adjacent to the first metal contact structure, wherein the first metal contact structure and the first virtual metal contact structure are located within a first dielectric structure. The circuit chip includes a control circuit, a second metal contact structure electrically connected to the control circuit, an electrostatic elimination circuit, and a second virtual metal contact structure electrically connected to the electrostatic elimination circuit. The second metal contact structure and the second virtual metal contact structure are located within a second dielectric structure. The first metal contact structure is electrically connected to the second metal contact structure, and the first virtual metal contact structure is electrically connected to the second virtual metal contact structure.

10. The semiconductor device according to claim 9, characterized in that, The semiconductor device chip is bonded to the circuit chip. In the semiconductor device chip, a plurality of first virtual metal contact structures are arranged around at least one first metal contact structure, or a first virtual metal contact structure is arranged adjacent to a first metal contact structure. In the circuit chip, a plurality of second virtual metal contact structures correspond one-to-one with and are electrically connected to a plurality of electrostatic elimination circuits.

11. The semiconductor device according to claim 10, characterized in that, The static electricity elimination circuit includes at least a PN junction.

12. The semiconductor device according to claim 9 or 11, characterized in that, The semiconductor device chip has a first pad and a second pad formed on its surface. The first pad is electrically connected to the first metal contact structure, and the second pad is electrically connected to the first virtual metal contact structure. The circuit chip has a third pad and a fourth pad formed on its surface. The third pad is electrically connected to the second metal contact structure, and the fourth pad is electrically connected to the second virtual metal contact structure. The first pad and the third pad are bonded together, so that the first metal contact structure is electrically connected to the second metal contact structure. The second pad and the fourth pad are bonded together, so that the first virtual metal contact structure is electrically connected to the second virtual metal contact structure.

13. The semiconductor device according to claim 12, characterized in that, The substrate of the semiconductor device chip includes a front side and a back side disposed opposite to each other. The device structure, the first metal contact structure, and the first virtual metal contact structure are disposed on the front side of the substrate of the semiconductor device chip. A third metal contact structure penetrating the substrate of the semiconductor device chip is also formed on the semiconductor device chip. The third metal contact structure electrically leads the first metal contact structure out from the back side of the substrate of the semiconductor device chip.

14. The semiconductor device according to claim 13, characterized in that, The semiconductor device chip includes an array chip, and the device structure includes a memory array structure.

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