Stacked structure, display screen and display device

Abstract

The application provides a stacking structure, a display screen and a display device. The stacking structure comprises a substrate, at least one driving chip and at least one pixel unit corresponding to each driving chip. One driving chip and the pixel unit corresponding to the driving chip form one light-emitting component. The substrate has a first surface, and the first surface is provided with a circuit layer. The driving chip and the corresponding pixel unit are arranged on the first surface of the substrate component. The sub-pixels in each pixel unit are electrically connected with the circuit layer and the corresponding driving chip, respectively. The circuit layer is electrically connected with the driving chip to form a control light-emitting loop. The stacking structure can realize the scheme of driving Micro LED by Micro IC, and is beneficial to realizing high-pixel display of the display screen.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a stacked structure, a display screen, and a display device. Background Technology

[0002] Micro LED (micro light-emitting diode) is the next generation of display technology. Micro LEDs with active driving are more suitable for high-pixel displays.

[0003] In active LED driving, the commonly used method is TFT (thin film transistor) driving, which drives Micro LEDs in a one-to-one correspondence manner through TFTs. However, its driving capability is relatively poor and cannot meet the high-pixel display requirements of screens.

[0004] Micro IC (micro integrated circuit) driving offers superior imaging quality and driving capability compared to TFT (thin film transistor) driving. Therefore, Micro IC-based driving solutions can be applied to Micro LED display technology. Summary of the Invention

[0005] This application provides a stacked structure, a display screen, and a display device to meet the high pixel display requirements of the display screen.

[0006] Firstly, this application provides a stacked structure applied in a display screen as a display structure. The structure mainly includes: a substrate, a driver chip, and pixel units. The substrate can be glass, silicon wafer, sapphire, or polyimide film. The substrate has a first surface with a circuit layer. The first surface is divided into regions, each having at least one pixel region, with no overlap between pixel regions. Within each pixel region, a driver chip and at least one corresponding pixel unit are disposed on the circuit layer. The vertical projection of the driver chip onto the first surface is outside the vertical projection of the pixel unit onto the first surface; that is, the positions of the driver chip and the pixel unit on the circuit layer are independent and do not overlap. Each pixel unit includes multiple sub-pixels, each sub-pixel being electrically connected to the circuit layer and the corresponding driver chip, and the circuit layer being electrically connected to the corresponding driver chip to form a control light-emitting circuit. This allows for an interconnected structure of pixel units, driver chips, and control drivers. The driver chip is a Micro IC, while the sub-pixels are Micro LEDs. Using a Micro IC to drive Micro LEDs is beneficial for achieving high-pixel counts in the display screen.

[0007] In a specific feasible implementation, for any pixel region, the internal traces of the circuit layer located within the pixel region are insulated from the internal traces of the circuit layer located outside the pixel region, or the circuit layer located within the pixel region does not have internal traces, so as to facilitate the replacement and maintenance of the driver chip and its corresponding pixel unit in the future.

[0008] Specifically, each sub-pixel includes an emissive layer and a P-terminal and an N-terminal respectively connected to the emissive layer, wherein the P-terminal is connected to the corresponding driving chip and the N-terminal is connected to the circuit layer; or, the P-terminal is connected to the circuit layer and the N-terminal is connected to the corresponding driving chip.

[0009] As for the structure of the subpixels, they can be stacked with a P-end, an emissive layer, and an N-end, with the emissive layer located between the P-end and the N-end; or they can be stacked with a P-end, an emissive layer, and an N-end, with the P-end and N-end on the same layer. When the former subpixel structure is used, the subpixels are essentially vertical, allowing more subpixels to be set within a unit area of ​​the display screen, thereby achieving higher display accuracy and improving the display effect.

[0010] In one specific implementation, the stacked structure further includes a separation layer disposed between the substrate and the circuit layer. In the event of a failure in the driver chip and pixel unit, the separation layer can be separated from the substrate for easy replacement or repair.

[0011] In addition, the stacked structure also includes a packaging layer corresponding to each driver chip, which covers the driver chip and the multiple sub-pixels corresponding to the driver chip to protect the driver chip and the pixel unit.

[0012] Secondly, this application provides a display screen, comprising: a housing, and a stacking structure as described above disposed within the housing. As can be seen from the above description, the use of the aforementioned stacking structure facilitates high-pixel display.

[0013] Thirdly, this application provides a display device including a body and a stacking structure as described above disposed within the body. As can be seen from the above description, the use of the stacking structure facilitates high-pixel display on the screen. Attached Figure Description

[0014] Figure 1 A schematic diagram of the structure of a display screen provided in an embodiment of this application;

[0015] Figure 2 This is a top view of the stacked structure provided in an embodiment of this application;

[0016] Figure 3 This is a schematic diagram of the pixel unit structure in an embodiment of this application;

[0017] Figure 4a for Figure 2 A schematic diagram of the cross-sectional structure of the plane containing MM;

[0018] Figure 4b and Figure 4c This is a cross-sectional schematic diagram of the stacked structure provided in an embodiment of this application;

[0019] Figure 5 for Figure 2 A schematic diagram of the cross-sectional structure of the plane containing NN;

[0020] Figure 6a and Figure 6b This is a schematic diagram of the sub-pixel structure provided in an embodiment of this application;

[0021] Figures 6c to 6e This is a cross-sectional schematic diagram of the stacked structure provided in an embodiment of this application;

[0022] Figure 7 This is a cross-sectional schematic diagram of the stacked structure provided in an embodiment of this application;

[0023] Figures 8a to 14cThis is a schematic diagram of structural changes during the fabrication process of the stacked structure provided in the embodiments of this application.

[0024] Reference numerals: 1-DDIC; 2-Display pixel; 10-Substrate; 20-Driver chip; 30-Pixel unit; 31-Sub-pixel; 311-N-terminal; 312-Light-emitting layer; 313-P-terminal; 40-Separation layer; 50-Line layer; 51-Support layer; 52-Circuit layer; 61-First connection line; 62-Second connection line; 70-Pad; 80-Encapsulation layer. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0026] First, let's introduce the application scenario of this application. Currently, the driving scheme for display pixels in the packaging structure of displays cannot meet the display effect of high pixels. Therefore, embodiments of this application provide a stacked structure. Applying this stacked structure to a display screen can change the driving method of display pixels, which is beneficial to improving the display effect of the display screen.

[0027] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more” unless the context clearly indicates otherwise.

[0028] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0029] Please refer to Figure 1The diagram illustrates the structure of a display screen. The display area A of the screen has multiple display pixels 2. A DDIC1 (display driving integrated circuit) is located below the display area A. The display pixels 2 are arranged in rows along direction a and columns along direction b. Each display pixel 2 is signal-connected to the DDIC1 via display screen lines 3. During operation, an external signal controls the DDIC1, which then drives each display pixel 2 within the display area A to emit light through the display screen lines 3, thus achieving the image display effect.

[0030] Figure 1 Each display pixel 2 in the image forms a stacked structure, which can be referred to as [reference needed]. Figure 2 The structure shown includes a substrate 10 (not shown in the diagram). Figure 2 As shown in the diagram, the stacked structure includes a circuit layer 50, a driver chip 20, and pixel units 30. The driver chip 20 and pixel units 30 form the light-emitting components. The driver chip 20 and pixel units 30 are disposed on the circuit layer 50, as shown in the diagram. Figure 2 As shown, the plane of the substrate 10 is a first plane, and the circuit layer 50 is disposed on this first plane. This first plane can be divided into at least one pixel region B. Figure 2 The diagram shows a pixel region B. Within pixel region B, a line layer 50 is provided with a driver chip 20 and at least one pixel unit 30 corresponding to the driver chip 20. The driver chip 20 is rectangular (this is just an example), and can be a Micro IC. The substrate 10 can be made of a material with a certain supporting strength. For example, the substrate 10 can be made of glass, silicon, sapphire, PI (polyimide, a polymer whose main chain contains imide groups), etc.

[0031] It should be noted that this application does not specifically limit the number of driver chips 20 carried on the substrate 10. As a specific embodiment, all stacked structures in the display screen can share a single substrate 10, and the driver chips 20 in the display screen are arranged in an array on the circuit layer 50 on the substrate 10. Furthermore, the number of pixel units 30 corresponding to one driver chip 20 is not limited; for example, one driver chip 20 can correspond to one, three, four, or other different numbers of pixel units 30. Each pixel region B has one driver chip 20 and at least one pixel unit 30 corresponding to that driver chip 20 on the circuit layer 50. Figure 2 The example uses a pixel region B, which includes a driver chip 20 and 12 corresponding pixel units 30.

[0032] In this embodiment, the structures of different pixel units 30 are the same, such as... Figure 2 As shown, each pixel unit 30 includes three sub-pixels 31 arranged in the same layer, with the three sub-pixels 31 arranged in a single row along direction a. The three sub-pixels 31 are respectively capable of emitting red, blue, and green colors. Figure 2 The three sub-pixels 31 shown can be as follows Figure 3 As shown, the sub-pixels are: a first sub-pixel 31a that emits red light, a second sub-pixel 31b that emits blue light, and a third sub-pixel 31c that emits green light. The driver chip 20 can control the pixel unit 30 to emit light of different colors by controlling the working state of the three sub-pixels.

[0033] In an optional implementation, pixel unit 30 may further include other sub-pixels 31 that enable the display to emit different colors of light, such as sub-pixels 31 using monochrome or RGB three-color sub-pixels. This application does not specifically limit the number of sub-pixels 31 in each pixel unit 30, nor the color emitted by each sub-pixel 31; in specific settings, the sub-pixels 31 can be configured as needed.

[0034] by Figure 2 The stacked structure is cut along the plane containing MM to obtain Figure 4a The diagram shows a cross-sectional structure; in this diagram, the upper surface of the substrate 10 is the first surface, the circuit layer 50 is laid on the first surface of the substrate 10, and the driving chip 20 and pixel unit 30 (here, pixel unit 30 is shown as a single sub-pixel 31) are disposed on the circuit layer 50. The vertical projection of the driving chip 20 on the first surface is outside the vertical projection of the pixel unit 30 on the first surface; that is, the positions of the driving chip 20 and the pixel unit 30 on the circuit layer 50 are independent of each other, and there is no overlapping area. The substrate 10 serves as a supporting structure, providing support for the driving chip 20 and the pixel unit 30. Figure 2 and Figure 3Each pixel unit 30 includes multiple sub-pixels 31. Each sub-pixel 31 is electrically connected to the driver chip 20 via a first connection line 61 and to the GND of the circuit layer 50 via a second connection line 62. Each sub-pixel 31 is fixed to the circuit layer 50 via a pad 70, which is electrically connected to the circuit layer 50. This achieves the technical effect of forming a control light-emitting circuit, whereby the pixel unit 30 is electrically connected to both the circuit layer 50 and the driver chip 20, and the driver chip 20 is electrically connected to the circuit layer 50 via surface traces. The first and second connection lines 61 can be made of conductive materials such as Cu pillars, ITO (indium tin oxide), or Cu and Au. It should be noted that zero, one, or more backup pads are reserved for each sub-pixel 31. It is understood that each pixel unit 30 may also include components such as sensors and vibrators. These components also have ports for electrical connection with the driver chip 20 and ports for connection with the circuit layer 50, thereby forming a circuit and realizing its corresponding function, which will not be shown in the figure here.

[0035] Furthermore, sub-pixels 31 can be assembled onto the circuit layer 50 using transfer and soldering processes. Specifically, when configuring the sub-pixels 31, each sub-pixel 31 corresponding to a driver chip 20 is arranged around an array of driver chips 20; where "corresponding" refers to the correspondence between the driver chip 20 and the sub-pixel 31 forming an electrical connection loop.

[0036] The driver chip 20 can be assembled onto the surface of the circuit layer 50 using methods such as bonding, metal bonding, or liquid material bonding; Figure 2 The stacked structure is cut along the plane containing the NN, resulting in... Figure 5 The cross-sectional structure shown is illustrated in the diagram. In this diagram, the IO contact a of the driver chip 20 can be connected to the IO contact b of the circuit layer 50 through the RDL (redistribution layer) process, or it can be connected to the IO contact b of the circuit layer 50 through the Fan-out line, so as to realize the electrical connection between the driver chip 20 and the circuit layer 52.

[0037] Figure 4a The diagram shows a structure where sub-pixel 31 and driver chip 20 are disposed on the same layer of circuit layer 50. For different driver chips 20 and sub-pixel 31 structures, alternative methods can be adopted. Figure 4b or Figure 4c The stacking structure is shown below. Please refer to... Figure 4bThe thickness of the driver chip 20 is greater than that of the sub-pixel 31. To facilitate process implementation and ensure structural integrity, a groove corresponding to the driver chip 20 can be formed on the circuit layer 50, and the driver chip 20 can be placed in the groove so that the surface of the sub-pixel 31 facing away from the circuit layer 50 can remain relatively horizontal with the surface of the driver chip 20 facing away from the circuit layer 50; similarly, as Figure 4c As shown, the thickness of sub-pixel 31 is greater than the thickness of driver chip 20, allowing a groove corresponding to sub-pixel 31 to be formed on circuit layer 50, and sub-pixel 31 to be disposed within the groove. For ease of description, the stacking structure in the following embodiments will be referred to as... Figure 4a The structure shown is used as an example for explanation.

[0038] Please continue to refer to Figure 4a or Figure 5 The circuit layer 50 includes a support layer 51 and a circuit layer 52. The support layer 51 can be made of different materials; for example, the material of the circuit layer 50 can be PI, epoxy resin, etc. The circuit layer 52 can have multiple wirings inside the support layer 51 or on the surface of the support layer 51. When the circuit layer 52 is formed on the surface of the support layer 51, the circuit layer 52 can be a single-layer wiring structure; when the circuit layer 52 is formed inside the support layer 51, the circuit layer 52 can be a multi-layer wiring structure. As an optional solution, the circuit layer 52 can be directly disposed on the substrate 10, with the substrate 10 serving as the support structure for the circuit layer 52, thus eliminating the need to fabricate an additional support layer 51 to support the circuit layer 52, such as using a printed circuit board or a substrate 10 with circuitry.

[0039] like Figure 4a and Figure 5 As shown, the stacked structure also includes a separation layer 40 disposed on the substrate 10. In this embodiment, the separation layer 40 can be an optional layer structure. A circuit layer 50 is disposed on the separation layer 40, and the separation layer 40 can be peeled off from the substrate 10. When a light-emitting component (a driving chip 20 and a pixel unit 30 corresponding to the driving chip 20) is detected to be damaged, the separation layer 40 can be separated by laser peeling to replace the damaged light-emitting component. The aforementioned separation layer 40 can be a laser photosensitive material (such as potassium nitride, arsenic nitride) or a chemical etching material. It should be understood that, in order to separate the damaged light-emitting component on the circuit layer 50, for any pixel region B, no wiring can be provided inside the circuit layer 50 located in the pixel region B, or the internal wiring of the circuit layer 50 located in the pixel region B can be set to be unconnected to the internal wiring of the circuit layer 59 located outside the pixel region B, so that the internal structure of the circuit layer 50 in each pixel region B is mutually insulated. Of course, it is understandable that the internal routing of the line layer 50 does not affect the external routing of the line layer 50, and there are no restrictions on the external routing of the line layer 50 here.

[0040] Depend on Figure 4a As can be seen, taking the example of the circuit layer 50 located in pixel region B without inner layer wiring, when separating the driver chip 20 and pixel unit 30 through the separation layer 40, the circuit layer 50 connected to the driver chip 20 and pixel unit 30 needs to be separated together. This ensures that when cutting the circuit layer 50, the portion of the circuit layer 50 stripped together with the driver chip 20 and pixel unit 30 has no circuitry. When the repaired driver chip 20 and pixel unit 30 are then repositioned onto the substrate 10, they can be placed directly in their original positions, and then external circuit connections can be made. If wiring is installed inside the circuit layer 50 in pixel region B, since this internal wiring is not electrically connected to the internal wiring of the circuit layer 50 outside pixel region B, cutting the circuit layer 50 will not affect the internal circuitry function of the circuit layer 50 outside pixel region B.

[0041] In addition, such as Figure 4a and Figure 5 As shown, the stacked structure also includes a packaging layer 80 corresponding to each driver chip 20. Each packaging layer 80 encapsulates the corresponding driver chip 20 and pixel unit 30 to protect the driver chip 20 and pixel unit 30. The area covered by the packaging layer 80 can correspond to the aforementioned pixel region B. For example, the packaging layer 80 has a trapezoidal structure and encapsulates the driver chip 20 and sub-pixel 31. The packaging layer 80 is made of a transparent molding compound to allow light emitted from the sub-pixel 31 to pass through. For example, the material of the packaging layer 80 can be COF (chip on flex, or chip on flm, flip-chip film), transparent photoresist, or other transparent epoxy resin. When the stacked structure has a packaging layer 80, the first connection line 61 between the driver chip 20 and the sub-pixel 31 can be as follows... Figure 4a The shown is disposed within the encapsulation layer 80, and is encapsulated together with the driver chip 20 and the sub-pixel 31 by the encapsulation layer 80. When the encapsulation layer 80 is included, the circuit layer 52 of the line layer 50 has no circuit in the area corresponding to the encapsulation layer 80, so as to ensure that the circuit layer 52 will not be damaged when the line layer 50 is cut.

[0042] In an alternative embodiment, in addition to the sub-pixels 31 mentioned above, other display devices or chips can be placed on the driver chip 20 to integrate more functional components in the stacked structure and reduce the area occupied by non-display devices on the substrate 10.

[0043] For the structure of sub-pixel 31 in the embodiments of this application, please refer to Figure 6aAs shown, sub-pixel 31 can be a vertically structured Micro LED. When sub-pixel 31 is mounted on the circuit layer 50, the light-emitting layer 312 can emit light to the side away from the substrate 10. Because the light-emitting layer 312 emits light to the side away from the substrate 10, detection and maintenance can be achieved when sub-pixels 31 are assembled on the substrate 10. Figure 6a The sub-pixel 31 has its P-terminal 313, light-emitting layer 312, and N-terminal 311 stacked together, with the light-emitting layer 312 located between the P-terminal 313 and the N-terminal 311. By employing this vertical stacked structure, the volume of the sub-pixel 31 can be reduced, and the size of the sub-pixel 31 can be controlled between 5*5um and 100*100um. Figure 5 The sub-pixel 31 shown is applied in Figure 4a In the stacked structure shown, the P-terminal 313 of sub-pixel 31 is soldered to the pad 70 on the circuit layer 50. The N-terminal 311 of sub-pixel 31 is connected to the GND contact of the circuit layer 50 via the second connection line 62. Alternatively, the N-terminal 311 of sub-pixel 31 can be connected to the GND contact of the circuit layer 50 via an RDL or a Fan-out line to achieve electrical connection between sub-pixel 31 and circuit layer 52. Of course, the N-terminal 311 of sub-pixel 31 can also be soldered to the pad 70 on the circuit layer 50, and the P-terminal 313 of sub-pixel 31 can be connected to the GND contact of the circuit layer 50 via the second connection line 62. This vertical structure of sub-pixel 31 is more suitable for high-pixel displays, allowing for the selection of smaller LEDs. Adjacent sub-pixels 31 can be soldered individually, preventing short circuits caused by lateral overflow of the pad 70, and improving yield during fabrication.

[0044] Please refer to Figure 6b Another sub-pixel 31 structure is shown, which is a flip-chip structure: the P-terminal 313, the light-emitting layer 312, and the N-terminal 311 are stacked, and the P-terminal 313 and the N-terminal 311 are arranged in the same layer. This sub-pixel 31 is applied... Figure 4a In the stacked structure shown, since the P-terminal 313 and the N-terminal 311 are located on the same side of the light-emitting layer 312, the connection method between the sub-pixel 31 and the driving chip 20 and the circuit layer 50 will be different from that of the P-terminal 313 and the N-terminal 311. Figure 4a The structures shown are different. Specifically, as... Figure 6cAs shown, when the P-terminal 313 and N-terminal 311 are located on the side of the light-emitting layer 312 facing the circuit layer 50, the N-terminal 311 can be electrically connected to the driver chip 20 through the first connecting line 61, and the P-terminal 313 can be electrically connected to the GND contact of the circuit layer 50 through the second connecting line 62 (of course, it is also possible that the P-terminal 313 is electrically connected to the driver chip 20 through the first connecting line 61, and the N-terminal 311 is electrically connected to the GND contact of the circuit layer 50 through the second connecting line 62; and it is understood that pads for docking the P-terminal and N-terminal are provided on the circuit layer 50, which are not shown in the figure here). Here, the first connecting line 61 and the second connecting line 62 can be basically routed along the surface of the circuit layer 50; as shown Figure 6d As shown, when the P terminal 313 and N terminal 311 are located on the side of the light-emitting layer 312 away from the circuit layer 50, the N terminal 311 can be routed to the surface of the circuit layer 50 through the first connection line 61 and then wired along the surface of the circuit layer 50 to be electrically connected to the driver chip 20. The P terminal 313 can also be routed to the surface of the circuit layer 50 through the second connection line 62 and then wired along the surface of the circuit layer 50 to be electrically connected to the GND contact of the circuit layer 50; it can also be as follows: Figure 6e As shown, the second connection line 62 of P terminal 313 is routed to the surface of the package layer 80 and then connected to the GND contact of the circuit layer 50 for electrical connection.

[0045] Understandable, Figure 6a and Figure 6b Sub-pixels 31 in the image can all be applied to... Figure 4a In the stacked structure shown.

[0046] Please refer to Figure 7 The schematic diagram of the cross-sectional structure of the stacked structure shown indicates that the length of the substrate 10 is H1, the length of the driver chip 20 is H3, and the length of a sub-pixel 31 is H2. Figure 7 As shown in the structure, the number of sub-pixels 31 along the length of the substrate 10 can be determined by the values ​​of H1 and H2. In other words, while ensuring a consistent light-emitting area (i.e., the sub-pixels 31 occupy the same area), the vertical structure of the sub-pixels 31 can reduce the overall device area compared to a flip-chip LED. Furthermore, under the same display pixel count and brightness (i.e., the same number of sub-pixels 31), more sub-pixels 31 can be placed per unit area. In other words, using a vertical structure of sub-pixels 31 can maximize the ultimate display accuracy, and when the ultimate display pixel count is not reached, the vertical structure of the sub-pixels 31 can occupy a smaller area, thereby enabling transparent display or integrating other micro-components onto the device.

[0047] To facilitate understanding of the stacked structure provided in the embodiments of this application, the specific preparation method is described in detail below with reference to the accompanying drawings.

[0048] Step 001: Provide substrate 10.

[0049] like Figure 8a and Figure 8b As shown, Figure 8a A top view of substrate 10 is shown. Figure 8b It shows Figure 8a A cross-sectional view at point QQ. A circuit layer 50 and a separation layer 40 have been formed on the substrate 10. The traces and contacts (not shown) connecting the DDIC1 control signal in the circuit layer 50 have been fabricated. The separation layer 40 between the circuit layer 50 and the substrate 10 can be made of a laser-sensitive material (such as potassium nitride or arsenic nitride) or a chemically etched material; no specific method is used here. The circuit layer 50 has IO contacts and GND contacts. The IO contacts are made of 3µm thick In, and the GND contacts are made of 0.05µm thick Au. The plating layer connecting the DDIC1 traces to the contacts can use the same plating structure.

[0050] Step 002: Set pixel unit 30.

[0051] like Figure 9a and Figure 9b As shown, Figure 9a A top view of the component is shown. Figure 9b It shows Figure 9a Sectional view at RR. Figure 9a and Figure 9b Some of the labels in the text can be referenced. Figure 9a and Figure 9b The same label in the text. Subpixel 31 uses the following... Figure 6a The vertical structure shown is illustrated. Sub-pixels 31 are assembled onto pads 70 on the surface of the circuit layer 50 via transfer and soldering processes, wherein the positive electrode of the sub-pixel 31 is in contact with the pads 70.

[0052] Step 003: Configure driver chip 20.

[0053] like Figure 10a and Figure 10b As shown, Figure 10a A top view of the component is shown. Figure 10b It shows Figure 10a Sectional view at SS. Figure 10a and Figure 10b Some of the labels in the text can be referenced. Figure 9a and Figure 9b The same reference numerals are used in the diagram. The driver chip 20 is assembled onto the circuit layer 50 using a transfer process and a chip mounting process. The transfer process, depending on the wafer fabrication process, can employ laser transfer or physical transfer. The driver chip 20 is fixed on the circuit layer 50, with the contacts of the driver chip 20 facing upwards (as shown in the diagram). Figure 10b The placement direction of the middle substrate 10 is the reference direction.

[0054] Step 004: The driver chip 20 and the pixel unit 30 are electrically connected using a rewiring process.

[0055] like Figure 11a and Figure 11b As shown, Figure 11a A top view of the component is shown. Figure 11b It shows Figure 11a Cross-sectional view at point TT. Figure 11a and Figure 11b Some of the labels in the text can be referenced. Figure 10a and Figure 10b Using the same reference numerals, the driver chip 20 is electrically connected to the positive terminal of the sub-pixel 31 through a rewiring process. Specifically, the first connection line 61 is used to connect the IO contacts on the driver chip 20 and the pads 70 under the sub-pixel 31.

[0056] Step 005: Prepare the encapsulation layer 80.

[0057] like Figure 12a and Figure 12b As shown, Figure 12a A top view of the component is shown. Figure 12b It shows Figure 12a Cross-sectional view at point UU. Figure 12a and Figure 12b Some of the labels in the text can be referenced. Figure 11a and Figure 11b The same reference numerals are used in the diagram. Sub-pixels 31 and driver chip 20 are encapsulated using a planarization process to form an encapsulation layer 80. The negative electrode of sub-pixels 31 and the I / O contacts of driver chip 20 are exposed using a photolithography process. The encapsulation layer 80 is made of a transparent material, specifically COF material, transparent photoresist material, or other transparent epoxy resin material.

[0058] Step 006: Fan-out process and wiring.

[0059] The I / O contacts of the driver chip 20 are routed to the module surface using a fan-out process, and the negative electrode of the sub-pixel 31 within each pixel unit 30 is connected to the same electrode. The specific structure can be found in [reference needed]. Figure 2 , Figure 4a as well as Figure 5 As shown. Figure 2 Taking the structure shown as an example, the eight electrodes a of the driver chip 20 are connected to the IO contacts b on the circuit layer 50 via wiring (e.g., Figure 5 As shown), the ground on the driver chip 20 is connected to the ground of the sub-pixel 31, and then connected to the GND contact on the display screen to enable all signal pins to conduct.

[0060] Thus, we can obtain the following: Figure 2 The stacked structure shown completes the process. Figure 1 After the display screen shown is manufactured, it needs to be tested, including the following steps:

[0061] Step 007: Test.

[0062] Specifically, the stacked structure is tested for illumination using DDIC1. If a faulty light-emitting component is found, its location is determined.

[0063] Step 008: Cutting the defective light-emitting component.

[0064] like Figure 13a and Figure 13b As shown, a laser is used to cut the defective light-emitting components (driver chip 20 and pixel unit 30). The laser cuts the circuit layer 50 and the separation layer 40, thus splitting the defective light-emitting components.

[0065] Step 009: Rejecting defective light-emitting components:

[0066] like Figure 14a and Figure 14b As shown, defective light-emitting components are removed from the substrate 10 by laser ablation of the separation layer 40 on the surface of the substrate 10. A top view of the entire stacked structure can be seen from [reference needed]. Figure 14c As shown, the area where defective light-emitting components were removed exposes the substrate 10.

[0067] Step 010: Transferring and fixing the light-emitting components in defective locations:

[0068] The working light-emitting components are transferred to blank positions using repair equipment and then cured and fixed onto substrate 10 by heating or UV (ultraviolet) methods, resulting in a structure as shown below. Figure 4a or Figure 5 As shown, it will not be illustrated here.

[0069] It should be noted that after transferring the repaired light-emitting component onto the substrate 10, the gaps around the repaired component need to be filled and cured using a printing device. Then, wiring is used to connect the light-emitting component to the circuit layer 50 on the substrate 10, enabling circuit conduction. This wiring can be achieved using CVD (chemical vapor deposition) or by printing silver paste.

[0070] As can be seen from the above embodiments, in this application embodiment, the separation layer 40 disposed between the circuit layer 50 and the substrate 10 allows for the replacement of the light-emitting components (driving chip 20 and pixel unit 30) on the stacked structure during fabrication, improving the reliability of the stacked structure in use. It should be understood that the order of the above steps or the order of performing certain actions is not important as long as the disclosed technology remains operable. Furthermore, two or more steps or actions can be performed simultaneously.

[0071] Secondly, this application provides a display screen, which includes: a housing, and a stacked structure as described above disposed within the housing. As can be seen from the above description, the use of the pixel unit 30 and the driver chip 20, due to the aforementioned stacked structure, facilitates high-pixel display. It is understood that during the fabrication of this display screen, a protective encapsulation layer, a planarization layer, and other structures need to be formed on the surface of the aforementioned stacked structure. To achieve better display effects, structures such as a light filter film and a polarizer (film) can also be provided as needed, which will not be elaborated here.

[0072] Thirdly, this application provides a display device including a body and a stacking structure as described above disposed within the body. As can be seen from the above description, the use of the stacking structure facilitates high-pixel display.

[0073] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A stacked structure, characterized in that, It includes a substrate, at least one driving chip, and at least one pixel unit corresponding to each driving chip; The substrate has a first surface, and a circuit layer is disposed on the first surface; The first surface has at least one pixel region, and a driver chip and at least one pixel unit corresponding to the driver chip are disposed on the line layer in each pixel region, and the vertical projection of the driver chip on the first surface is located outside the vertical projection of the pixel unit on the first surface. The sub-pixels located in each pixel unit are electrically connected to the circuit layer and the corresponding driver chip, and the circuit layer is electrically connected to the corresponding driver chip to form a control light-emitting circuit; For any given pixel region, the internal traces of the circuit layer located within the pixel region are insulated from the internal traces of the circuit layer located outside the pixel region; or, the circuit layer located within the pixel region has no internal traces. It also includes a separation layer disposed between the substrate and the circuit layer, the separation layer being peelable relative to the substrate.

2. The stacking structure as described in claim 1, characterized in that, Each of the sub-pixels includes a light-emitting layer and a P-terminal and an N-terminal respectively connected to the light-emitting layer; The P terminal is connected to the corresponding driver chip; or, the P terminal is connected to the circuit layer and the N terminal is connected to the corresponding driver chip.

3. The stacking structure as described in claim 2, characterized in that, The P-terminal, the light-emitting layer, and the N-terminal are stacked, with the light-emitting layer located between the P-terminal and the N-terminal.

4. The stacking structure as described in claim 2, characterized in that, The P-terminal, the light-emitting layer, and the N-terminal are stacked, and the P-terminal and the N-terminal are arranged in the same layer.

5. The stacking structure as described in claim 1, characterized in that, It also includes a packaging layer corresponding to each of the driver chips, the packaging layer covering the driver chip and the plurality of sub-pixels corresponding to the driver chip.

6. The stacking structure as described in any one of claims 1-5, characterized in that, The substrate is glass, silicon wafer, sapphire, or polyimide film.

7. A display screen, characterized in that, It includes: a housing and a stacking structure disposed within the housing as described in any one of claims 1-6.

8. A display device, characterized in that, It includes a body and a stacking structure disposed within the body as described in any one of claims 1-7.

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