A UWB low-noise amplifier circuit

Abstract

The present invention discloses an ultra-wideband low-noise amplifier circuit, which includes an input matching network, a cascode and negative feedback network, an improved traveling-wave network, and an output matching network connected in sequence; the improved traveling-wave network includes four paths of transistors, the gate voltage terminal of each path of transistors is connected to a microstrip line through a resistor, and the output terminal of each path of transistors is connected to an inductor through a microstrip line. The amplifier circuit of the present invention has controllable gate voltage. The circuit combines a cascode structure, a negative feedback structure, and an improved traveling-wave network, which can greatly expand the bandwidth of the amplifier circuit and has good standing waves and relatively flat gain in the full frequency band. In addition, an improved traveling-wave network is cascaded at the last stage, which can well achieve a relatively high output power and good efficiency of the circuit while ensuring that the circuit has a relatively high gain, and can effectively suppress the instability phenomenon of the circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of amplifier circuit design, and particularly relates to an ultra-wideband low-noise amplifier circuit. Background Art

[0002] In modern communication systems, the requirements for bandwidth and information capacity are increasing day by day. The emergence of ultra-wideband wireless communication technology can well solve the above problems. And the low-noise amplifier circuit, as the front-end circuit of an ultra-wideband receiver, its performance is related to key indicators such as the overall bandwidth, noise figure, sensitivity, and linearity. However, it is a challenging task to design an amplifier with flat gain, ultra-low noise, certain output power and efficiency within multiple octaves. At present, for ultra-wideband low-noise amplifiers, it is difficult to achieve both low noise and large power output; more importantly, to achieve high gain within an ultra-wide frequency band, good means are needed to suppress instability.

[0003] Moreover, in a communication system, it is often necessary to control the gain to expand the dynamic range of the received signal. The existence of signal attenuation and reflection phenomena causes changes in the signal power at the front end of the receiver. When the amplifier is used as the receiving circuit of a radio frequency system, it should have the ability to receive and process radio frequency signals with a large dynamic range. Summary of the Invention

[0004] Aiming at the above deficiencies in the prior art, the ultra-wideband low-noise amplifier circuit provided by the present invention solves the problems of difficult low-noise implementation, insufficient gain, unsatisfactory gain fluctuation, and easy instability of the amplifier within multiple octaves, and provides an amplifier circuit that takes into account low noise, higher output power and efficiency within an ultra-wideband.

[0005] To achieve the above invention purpose, the technical solution adopted by the present invention is: an ultra-wideband low-noise amplifier circuit, including an input matching network, a cascode and negative feedback network, an improved traveling wave network, and an output matching network connected in sequence;

[0006] The improved traveling wave network includes four paths of transistors. The gate voltage terminal of each path of transistor is connected to a microstrip line through a resistor, and the output terminal of each path of transistor is connected to an inductor through a microstrip line;

[0007] The input end of the input matching network is used as the input end of the ultra-wideband low-noise amplifier circuit, and the output end of the output matching network is used as the output end of the ultra-wideband low-noise amplifier circuit.

[0008] Further, the input matching network includes a capacitor C1;

[0009] One end of the capacitor C1 serves as the input end of the input matching network, the other end of the capacitor C1 is respectively connected to one end of a grounding capacitor C2 and an inductor L1, and the other end of the inductor L1 serves as the output end of the input matching network.

[0010] Further, the cascode and negative feedback network includes a transistor M1 and a transistor M2;

[0011] The gate of the transistor M1 serves as the input end of the cascode and negative feedback network, and is respectively connected to one end of a resistor R8 and one end of a resistor R1. The other end of the resistor R1 is respectively connected to a gate voltage VG1 and one end of a resistor R2 through a microstrip line TL1. The other end of the resistor R2 is connected to a grounding capacitor C3. The other end of the resistor R8 is connected to one end of a capacitor C8. The other end of the capacitor C8 is respectively connected to one end of an inductor L5 and the drain of the transistor M2 through a microstrip line TL5. The source of the transistor M1 is grounded. The drain of the transistor M1 is connected to the source of the transistor M2. The gate of the transistor M2 is respectively connected to one end of an inductor L2 and one end of a resistor R3. The other end of the inductor L2 is sequentially connected to a resistor R7 and a grounding capacitor C5. The other end of the resistor R3 is connected to one end of a microstrip line TL2. The other end of the microstrip line TL2 is respectively connected to a grounding resistor R4 and one end of a resistor R5. The other end of the resistor R5 is respectively connected to one end of a microstrip line TL4 and one end of a microstrip line TL3. The other end of the microstrip line TL3 is respectively connected to a power supply VD1 and one end of a resistor R6. The other end of the resistor R6 is connected to a grounding capacitor C4. The other end of the microstrip line TL4 is respectively connected to a grounding capacitor C6 and one end of an inductor L3. The other end of the inductor L3 is respectively connected to a grounding capacitor C7 and one end of an inductor L4. The other end of the inductor L4 is respectively connected to the other end of the inductor L5 and one end of a capacitor C9. The other end of the capacitor C9 serves as the output end of the cascode negative feedback network.

[0012] Further, the improved traveling wave network includes transistors M3 to M6;

[0013] The gate of the transistor M3 is respectively connected to one end of the capacitor C11 and one end of the resistor R11. The other end of the capacitor C11 is respectively connected to one end of the inductor L6 and one end of the microstrip line TL7. The other end of the microstrip line TL7 is connected to one end of the microstrip line TL6. The other end of the microstrip line TL6 serves as the input end of the improved traveling wave network. The other end of the resistor R11 is respectively connected to one end of the resistor R9 and one end of the microstrip line TL9. The other end of the resistor R9 is connected to one end of the microstrip line TL8. The other end of the microstrip line TL8 is respectively connected to the gate voltage VG2 and one end of the resistor R10. The other end of the resistor R10 is connected to the grounded capacitor C10. The source of the transistor M3 is grounded. The drain of the transistor M3 is connected to one end of the microstrip line TL12. The other end of the microstrip line TL12 is respectively connected to one end of the inductor L9 and one end of the inductor L12. The other end of the inductor L12 is respectively connected to one end of the resistor R18 and the power supply VD2. The other end of the resistor R18 is connected to the grounded capacitor C17;

[0014] The gate of the transistor M4 is respectively connected to one end of the capacitor C12 and one end of the resistor R12. The other end of the capacitor C12 is respectively connected to the other end of the inductor L6, one end of the inductor L7 and one end of the resistor R15. The other end of the resistor R12 is respectively connected to the other end of the microstrip line TL9 and one end of the microstrip line TL10. The source of the transistor M4 is grounded. The drain of the transistor M4 is connected to one end of the microstrip line TL13. The other end of the microstrip line TL13 is respectively connected to the other end of the inductor L9 and one end of the inductor L10;

[0015] The gate of the transistor M5 is respectively connected to one end of the capacitor C13 and one end of the resistor R13. The other end of the capacitor C13 is respectively connected to the other end of the inductor L7, the other end of the resistor R15 and one end of the inductor L8. The other end of the resistor R13 is respectively connected to the other end of the microstrip line TL10 and one end of the microstrip line TL11. The source of the transistor M5 is grounded. The drain of the transistor M5 is connected to one end of the microstrip line TL14. The other end of the microstrip line TL14 is respectively connected to the other end of the inductor L10 and one end of the inductor L11;

[0016] The gate of the transistor M6 is connected to one end of the capacitor C14 and one end of the resistor R14 respectively. The other end of the capacitor C14 is connected to the other end of the inductor L8 and one end of the resistor R16 respectively. The other end of the resistor R16 is connected to the grounded capacitor C15. The other end of the resistor R14 is connected to the other end of the microstrip line TL11. The source of the transistor M6 is grounded. The drain of the transistor M6 is connected to one end of the microstrip line TL15. The other end of the microstrip line TL15 is connected to the other end of the inductor L11 and serves as the output end of the improved traveling wave network.

[0017] Further, the output matching network includes an inductor L13;

[0018] One end of the inductor L13 serves as the input end of the output matching network. The other end of the inductor L13 is connected to the capacitor C18. The other end of the capacitor C18 is connected to the grounded capacitor C19 and serves as the output end of the output matching network.

[0019] Further, the transistor M1 is an amplifying transistor, and the transistor M2 is a cascode transistor;

[0020] The sizes of the transistor M1 and the transistor M2 are different.

[0021] Further, the gate voltages VG1 and VG2 are controllable.

[0022] Further, the sizes of the transistors M3 - M6 are the same.

[0023] The beneficial effects of the present invention are as follows:

[0024] (1) The amplifying circuit of the present invention combines the cascode structure, the negative feedback structure, and the improved traveling wave network, which can greatly expand the bandwidth of the amplifying circuit. It can achieve several octaves below the Ku band and two octaves in the K and Ka bands; and good standing waves can be achieved in the full frequency band.

[0025] (2) The amplifying circuit of the present invention adopts a cascode combined with a negative feedback structure in the front stage, which can achieve ultra - low noise in an ultra - wide frequency band and at the same time has a relatively flat gain.

[0026] (3) The amplifying circuit of the present invention adopts an improved traveling wave network at the end stage. While ensuring that the circuit has a high gain, it can well achieve a high output power and good efficiency of the circuit. At the same time, the improved traveling wave network can effectively suppress the instability phenomenon of the circuit.

[0027] (4) This circuit can change the gate voltage of the transistor by controlling the gate voltages (VG1, VG2), so that when the received signal changes, the circuit gain can be changed, and further the purpose of stabilizing the output level can be achieved; furthermore, when the amplifier is used as the receiving circuit of the radio frequency system, it enables the ability to receive and process radio frequency signals with a large dynamic range. Description of the Drawings

[0028] Figure 1 It is the schematic diagram of the ultra-wideband low-noise amplifier circuit provided by the present invention.

[0029] Figure 2 It is the schematic diagram of the gain test curve of the ultra-wideband low-noise amplifier circuit provided by the present invention.

[0030] Figure 3 It is the schematic diagram of the input return loss test curve of the ultra-wideband low-noise amplifier circuit provided by the present invention.

[0031] Figure 4 It is the schematic diagram of the output return loss test curve of the ultra-wideband low-noise amplifier circuit provided by the present invention.

[0032] Figure 5 It is the schematic diagram of the noise test curve of the ultra-wideband low-noise amplifier circuit provided by the present invention.

[0033] Figure 6 It is the schematic diagram of the output power test curve of the ultra-wideband low-noise amplifier circuit provided by the present invention. Detailed Embodiments

[0034] The following describes the detailed embodiments of the present invention to facilitate those skilled in the art to understand the present invention. However, it should be clear that the present invention is not limited to the scope of the detailed embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions made using the concept of the present invention are within the scope of protection.

[0035] Embodiment 1:

[0036] As Figure 1 shown, an ultra-wideband low-noise amplifier circuit includes an input matching network, a cascode and negative feedback network, an improved traveling wave network, and an output matching network connected in sequence;

[0037] The improved traveling wave network includes four paths of transistors. The gate voltage terminals of each path of transistors are each connected to a microstrip line through a resistor, and the output terminals of each path of transistors are each connected to an inductor through a microstrip line;

[0038] The input end of the input matching network serves as the input end of the ultra-wideband low-noise amplifier circuit, and the output end of the output matching network serves as the output end of the ultra-wideband low-noise amplifier circuit.

[0039] In this embodiment, the above four-way transistors are of the same size. The RF input and DC feeding of each transistor gate are completely separated. A capacitor is added to the RF path in front of each transistor gate, and the DC path is connected to a microstrip line through a circuit and then to the gate voltage. The output end of each transistor is connected to an inductor of a different size through a microstrip line of a different size to achieve non-uniform time matching.

[0040] In this embodiment, the amplifier circuit can change the gate voltage of the transistor by controlling the gate voltages (VG1 and VG2), so that when the received signal of the circuit changes, the circuit gain can be changed, and thus the purpose of stabilizing the output level can be achieved.

[0041] In this embodiment, Figure 1 the input matching network includes capacitor C1; one end of capacitor C1 serves as the input end of the input matching network, and the other end of capacitor C2 is respectively connected to the grounded capacitor C2 and one end of inductor L1, and the other end of inductor L1 serves as the output end of the input matching network.

[0042] In this embodiment, Figure 1 the cascode and negative feedback network includes transistor M1 and transistor M2; the gate of transistor M1 serves as the input end of the cascode and negative feedback network, and is respectively connected to one end of resistor R8 and one end of resistor R1. The other end of resistor R1 is respectively connected to gate voltage VG1 and one end of resistor R2 through microstrip line TL1. The other end of resistor R2 is connected to the grounded capacitor C3. The other end of resistor R8 is connected to one end of capacitor C8. The other end of capacitor C8 is respectively connected to one end of inductor L5 and the drain of transistor M2 through microstrip line TL5. The source of transistor M1 is grounded. The drain of transistor M1 is connected to the source of transistor M2. The gate of transistor M2 is respectively connected to one end of inductor L2 and one end of resistor R3. The other end of inductor L2 is successively connected to resistor R7 and the grounded capacitor C5. The other end of resistor R3 is connected to one end of microstrip line TL2. The other end of microstrip line TL2 is respectively connected to the grounded resistor R4 and one end of resistor R5. The other end of resistor R5 is respectively connected to one end of microstrip line TL4 and one end of microstrip line TL3. The other end of microstrip line TL3 is respectively connected to power supply VD1 and one end of resistor R6. The other end of resistor R6 is connected to the grounded capacitor C4. The other end of microstrip line TL4 is respectively connected to the grounded capacitor C6 and one end of inductor L3. The other end of inductor L3 is respectively connected to the grounded capacitor C7 and one end of inductor L4. The other end of inductor L4 is respectively connected to the other end of inductor L5 and one end of capacitor C9. The other end of capacitor C9 serves as the output end of the cascode negative feedback network.

[0043] In the above common-source common-gate and negative feedback network, transistor M1 is the amplifying transistor, and transistor M2 is the common-source common-gate transistor; the common-source common-gate structure in this network can achieve higher gain and higher reverse isolation within a relatively wide frequency range; at the same time, the common-source common-gate structure can achieve better noise matching, so that the amplifying circuit has lower noise. In the traditional circuit, the sizes of transistors M1 and M2 are the same. In this embodiment, in order to better achieve noise matching, the sizes of M1 and M2 are different; two LC networks (i.e., L3 and C6, L4 and C7) are added to the drain branch of M2, effectively improving the output matching of the transistor and broadening the bandwidth; at the same time, an inductor L2 of a certain size is introduced into the radio frequency to ground branch of the gate of transistor M2, which can effectively improve the gain flatness of the circuit, and the addition of resistor R7 suppresses the instability of the network. In addition, the negative feedback structure introduced in the above network can further broaden the bandwidth. The output of transistor M2 is connected to the gate of M1 through a feedback loop. The feedback loop couples part of the drain output signal of the transistor to the gate, thereby reducing the gain at the low-frequency end and expanding the operating bandwidth. The parameters of feedback resistor R8 and isolation capacitor C8 determine the in-band gain flatness. The above negative feedback structure can simplify the port matching circuit structure, reduce the matching sensitivity at the input end of the circuit, so that the port standing wave and noise coefficient can be taken into account in the circuit design, and at the same time improve the circuit stability.

[0044] In this embodiment, Figure 1 the improved traveling wave network includes transistors M3 to M6;

[0045] The gate of transistor M3 is respectively connected to one end of capacitor C11 and one end of resistor R11. The other end of capacitor C11 is respectively connected to one end of inductor L6 and one end of microstrip line TL7. The other end of microstrip line TL7 is connected to one end of microstrip line TL6. The other end of microstrip line TL6 is used as the input end of the improved traveling wave network. The other end of resistor R11 is respectively connected to one end of resistor R9 and one end of microstrip line TL9. The other end of resistor R9 is connected to one end of microstrip line TL8. The other end of microstrip line TL8 is respectively connected to gate voltage VG2 and one end of resistor R10. The other end of resistor R10 is connected to ground capacitor C10. The source of transistor M3 is grounded. The drain of transistor M3 is connected to one end of microstrip line TL12. The other end of microstrip line TL12 is respectively connected to one end of inductor L9 and one end of inductor L12. The other end of inductor L12 is respectively connected to one end of resistor R18 and power supply VD2. The other end of resistor R18 is connected to ground capacitor C17;

[0046] The gate of transistor M4 is connected to one end of capacitor C12 and one end of resistor R12 respectively. The other end of capacitor C12 is connected to the other end of inductor L6, one end of inductor L7 and one end of resistor R15 respectively. The other end of resistor R12 is connected to the other end of microstrip line TL9 and one end of microstrip line TL10 respectively. The source of transistor M4 is grounded, and the drain of transistor M4 is connected to one end of microstrip line TL13. The other end of microstrip line TL13 is connected to the other end of inductor L9 and one end of inductor L10 respectively;

[0047] The gate of transistor M5 is connected to one end of capacitor C13 and one end of resistor R13 respectively. The other end of capacitor C13 is connected to the other end of inductor L7, the other end of resistor R15 and one end of inductor L8 respectively. The other end of resistor R13 is connected to the other end of microstrip line TL10 and one end of microstrip line TL11 respectively. The source of transistor M5 is grounded, and the drain of transistor M5 is connected to one end of microstrip line TL14. The other end of microstrip line TL14 is connected to the other end of inductor L10 and one end of inductor L11 respectively;

[0048] The gate of transistor M6 is connected to one end of capacitor C14 and one end of resistor R14 respectively. The other end of capacitor C14 is connected to the other end of inductor L8 and one end of resistor R16 respectively. The other end of resistor R16 is connected to the grounded capacitor C15. The other end of resistor R14 is connected to the other end of microstrip line TL11. The source of transistor M6 is grounded, and the drain of transistor M6 is connected to one end of microstrip line TL15. The other end of microstrip line TL15 is connected to the other end of inductor L11 and serves as the output end of the improved traveling wave network.

[0049] The improved traveling wave network in this embodiment not only has the characteristics of flat gain, extremely wide frequency band and small voltage standing wave ratio of the traditional traveling wave structure, but also has the characteristics of high output efficiency and good stability. In this embodiment, the RF path and DC power supply of each transistor input in the improved traveling wave network are completely separated. A capacitor (C11~C14) is added to the RF path in front of the gate of each stage of transistor. The DC path is connected to the gate voltage terminal through a resistor (R11~R14) and a microstrip line (TL9~TL11), effectively improving the input matching and output efficiency of the transistor; At the same time, the RC to ground branch in the traditional traveling wave circuit is removed in the traveling wave network of this embodiment, but the capacitor (C19) in the output matching network is shared to ground, further improving the circuit output efficiency; In Figure 1In it, the input ends of each path of transistors are connected through inductors (L6 to L8), and then a microstrip line (TL12 to TL15) is added to the output end of the corresponding transistor for phase delay, and then each path is connected through an inductor (L9 to L11) for output, realizing non-uniform matching, so that the output efficiency can be maximized; further, a resistor R15 is introduced between transistors M4 and M5, and this resistor can suppress the self-excited unstable signals of the circuit, effectively improving the circuit stability.

[0050] In this embodiment, Figure 1 the output matching network in includes an inductor L13; one end of the inductor L13 serves as the input end of the output matching network, the other end of the inductor L13 is connected to a capacitor C18, and the other end of the capacitor C18 is connected to a grounded capacitor C19 and serves as the output end of the output matching network. In this embodiment, an LC output matching network is adopted, and at the same time it participates in the output radio frequency to ground in the traveling wave network, abandoning the RC to ground branch in the traditional traveling wave circuit, which can effectively improve the output efficiency of the circuit.

[0051] In this embodiment, the amplifier circuit combines the cascode, negative feedback structure and improved traveling wave network, which can greatly expand the bandwidth. It can achieve several octaves below the Ku band, and can also achieve two octaves in the K and Ka bands, and has good standing wave and relatively flat gain in the full frequency band. In addition, an improved traveling wave network is cascaded at the last stage. While ensuring that the circuit has a high gain, it can well achieve a high output power and good efficiency of the circuit, and the improved traveling wave network can effectively suppress the unstable phenomenon of the circuit. This circuit can change the gate voltage of the transistor by controlling the gate voltage (VG1, VG2), so that when the received signal changes, the circuit gain can be changed, and further the purpose of stabilizing the output level can be achieved.

[0052] Embodiment 2:

[0053] As Figures 2 - 6 shown, in this embodiment, examples of the gain, return loss, noise and output power test curves of the above amplifier circuit in the frequency band of 2 to 18 GHz are provided;

[0054] Among them, VD1 = VD2 = 4V, the gate voltage VG is variable, VG1 = VG2 = -0.45V to -0.6V, Step = 0.05V, and there is no spurious signal and no self-excitation in the full frequency band. It can be seen from the figure that the amplifier works in the ultra-wide frequency band of 2 to 18 GHz, the input return loss in the full frequency band is less than -13, and the output return loss is less than -15; its gain has a typical value of 24 dB when VG = -0.45, and has the characteristic of variable gain; the gain fluctuation in the full frequency band is less than ±1 dB, and less than ±0.2 dB in the range of 4 to 16 GHz; the typical value of the noise is 1.5 dB; the typical value of the output P1 is 17.5 dBm.

Claims

1. A ultra-wideband low-noise amplifier circuit, characterized in that, It includes an input matching network, a cascode and negative feedback network, an improved traveling wave network, and an output matching network connected in sequence; The improved traveling wave network includes four paths of transistors. The gate voltage terminal of each path of transistor is connected to a microstrip line through a resistor, and the output terminal of each path of transistor is connected to an inductor through a microstrip line; The input terminal of the input matching network serves as the input terminal of the ultra-wideband low-noise amplifier circuit, and the output terminal of the output matching network serves as the output terminal of the ultra-wideband low-noise amplifier circuit; The cascode and negative feedback network includes transistor M1 and transistor M2; The gate of transistor M1 serves as the input terminal of the cascode and negative feedback network, and is respectively connected to one end of resistor R8 and one end of resistor R1. The other end of resistor R1 is respectively connected to gate voltage VG1 and one end of resistor R2 through microstrip line TL1. The other end of resistor R2 is connected to ground capacitor C3. The other end of resistor R8 is connected to one end of capacitor C8. The other end of capacitor C8 is respectively connected to one end of inductor L5 and the drain of transistor M2 through microstrip line TL5. The source of transistor M1 is grounded. The drain of transistor M1 is connected to the source of transistor M2. The gate of transistor M2 is respectively connected to one end of inductor L2 and one end of resistor R3. The other end of inductor L2 is sequentially connected to resistor R7 and ground capacitor C5. The other end of resistor R3 is connected to one end of microstrip line TL2. The other end of microstrip line TL2 is respectively connected to ground resistor R4 and one end of resistor R5. The other end of resistor R5 is respectively connected to one end of microstrip line TL4 and one end of microstrip line TL3. The other end of microstrip line TL3 is respectively connected to power supply VD1 and one end of resistor R6. The other end of resistor R6 is connected to ground capacitor C4. The other end of microstrip line TL4 is respectively connected to ground capacitor C6 and one end of inductor L3. The other end of inductor L3 is respectively connected to ground capacitor C7 and one end of inductor L4. The other end of inductor L4 is respectively connected to the other end of inductor L5 and one end of capacitor C9. The other end of capacitor C9 serves as the output terminal of the cascode and negative feedback network; The improved traveling wave network includes transistors M3 to M6; The gate of the transistor M3 is respectively connected to one end of the capacitor C11 and one end of the resistor R11. The other end of the capacitor C11 is respectively connected to one end of the inductor L6 and one end of the microstrip line TL7. The other end of the microstrip line TL7 is connected to one end of the microstrip line TL6. The other end of the microstrip line TL6 serves as the input end of the improved traveling wave network. The other end of the resistor R11 is respectively connected to one end of the resistor R9 and one end of the microstrip line TL9. The other end of the resistor R9 is connected to one end of the microstrip line TL8. The other end of the microstrip line TL8 is respectively connected to the gate voltage VG2 and one end of the resistor R10. The other end of the resistor R10 is connected to the grounded capacitor C10. The source of the transistor M3 is grounded. The drain of the transistor M3 is connected to one end of the microstrip line TL12. The other end of the microstrip line TL12 is respectively connected to one end of the inductor L9 and one end of the inductor L12. The other end of the inductor L12 is respectively connected to one end of the resistor R18 and the power supply VD2. The other end of the resistor R18 is connected to the grounded capacitor C17; The gate of the transistor M4 is respectively connected to one end of the capacitor C12 and one end of the resistor R12. The other end of the capacitor C12 is respectively connected to the other end of the inductor L6, one end of the inductor L7, and one end of the resistor R15. The other end of the resistor R12 is respectively connected to the other end of the microstrip line TL9 and one end of the microstrip line TL10. The source of the transistor M4 is grounded. The drain of the transistor M4 is connected to one end of the microstrip line TL13. The other end of the microstrip line TL13 is respectively connected to the other end of the inductor L9 and one end of the inductor L10; The gate of the transistor M5 is respectively connected to one end of the capacitor C13 and one end of the resistor R13. The other end of the capacitor C13 is respectively connected to the other end of the inductor L7, the other end of the resistor R15, and one end of the inductor L8. The other end of the resistor R13 is respectively connected to the other end of the microstrip line TL10 and one end of the microstrip line TL11. The source of the transistor M5 is grounded. The drain of the transistor M5 is connected to one end of the microstrip line TL14. The other end of the microstrip line TL14 is respectively connected to the other end of the inductor L10 and one end of the inductor L11; The gate of the transistor M6 is respectively connected to one end of the capacitor C14 and one end of the resistor R14. The other end of the capacitor C14 is respectively connected to the other end of the inductor L8 and one end of the resistor R16. The other end of the resistor R16 is connected to the grounded capacitor C15. The other end of the resistor R14 is connected to the other end of the microstrip line TL11. The source of the transistor M6 is grounded. The drain of the transistor M6 is connected to one end of the microstrip line TL15. The other end of the microstrip line TL15 is connected to the other end of the inductor L11 and serves as the output end of the improved traveling wave network.

2. The ultra-wideband low-noise amplifier circuit according to claim 1, characterized in that The input matching network includes the capacitor C1; One end of the capacitor C1 serves as the input end of the input matching network, the other end of the capacitor C1 is respectively connected to the grounding capacitor C2 and one end of the inductor L1, and the other end of the inductor L1 serves as the output end of the input matching network.

3. The ultra-wideband low-noise amplifier circuit according to claim 1, wherein, The output matching network includes an inductor L13; One end of the inductor L13 serves as the input end of the output matching network, the other end of the inductor L13 is connected to the capacitor C18, and the other end of the capacitor C18 is connected to the grounding capacitor C19 and serves as the output end of the output matching network.

4. The ultra-wideband low-noise amplifier circuit according to claim 2, wherein The transistor M1 is an amplifying transistor, and the transistor M2 is a cascode transistor; The sizes of the transistor M1 and the transistor M2 are different.

5. The ultra-wideband low-noise amplifier circuit according to claim 1, wherein The gate voltages VG1 and VG2 are controllable.

6. The ultra-wideband low-noise amplifier circuit according to claim 1, characterized in that The sizes of the transistors M3 to M6 are the same.

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