A control circuit, a control method, a clock trigger device and related equipment

Abstract

The present invention provides a control circuit, a control method, a clock trigger device, and related equipment. The control circuit is connected to the clock trigger device and is used to detect the level states of the input signal and output signal of the clock trigger device. If the level states of the input signal and the output signal are the same, the control circuit outputs a first level signal to the clock trigger device to maintain the level state of the output signal of the clock trigger device. Because the level state of the first level signal is constant, such as the level of the first level signal is always high or low, the level state of the output signal of the clock trigger device can be maintained unchanged, eliminating the need for the clock trigger device to flip between high and low levels, thereby reducing the dynamic power consumption of the clock trigger device and, in turn, reducing the dynamic power consumption of an integrated circuit having the clock trigger device.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of integrated circuits, and in particular to a control circuit, a control method, a clock trigger device, and related equipment. Background Art

[0002] In integrated circuit design, reducing energy consumption is a key goal of low-power design. Depending on the characteristics of the circuit, energy consumption can be categorized as dynamic power consumption and static power consumption. For dynamic power consumption, the transition between high and low levels in the circuit is the primary cause of energy consumption.

[0003] During the operation of an integrated circuit (IC), the clock signal constantly switches between high and low levels. Simultaneously, the clock unit also continuously switches between high and low levels in response to the clock signal. This results in high dynamic power consumption in the IC. Therefore, reducing the dynamic power consumption of ICs is a pressing issue for those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a control circuit, a control method, a clock trigger device and related equipment to reduce the dynamic consumption of an integrated circuit.

[0005] To solve the above problems, the embodiments of the present invention provide the following technical solutions:

[0006] A first aspect of the present invention provides a control circuit, which is connected to a clock trigger device, and is used to: detect the level states of the input signal and the output signal of the clock trigger device, and if the level states of the input signal and the output signal are the same, output a first level signal to the clock trigger device to keep the level state of the output signal of the clock trigger device unchanged; wherein the level state of the first level signal remains unchanged.

[0007] A second aspect of the present invention provides a control method, comprising:

[0008] Detect the level status of the input signal and output signal of the clock trigger device;

[0009] If the level states of the input signal and the output signal are opposite, a first level signal is output to the clock trigger device to keep the level state of the output signal of the clock trigger device unchanged; wherein the level state of the first level signal remains unchanged.

[0010] A third aspect of the present invention provides a clock trigger device, comprising the control circuit as described in any one of the above items.

[0011] A fourth aspect of the present invention provides a chip comprising the clock triggering device described above.

[0012] A fifth aspect of the present invention provides an electronic device comprising the chip described above.

[0013] The control circuit, control method, clock trigger device and related equipment provided by the embodiments of the present invention, if the level states of the input signal and the output signal of the clock trigger device are opposite, it means that the clock trigger device does not need the flip trigger of the clock signal to update the level state of the output signal. The control circuit keeps the level state of the output signal of the clock trigger device unchanged by outputting a first level signal with a constant level to the clock trigger device, so that the level of the clock signal end of the clock trigger device does not need to flip between a high level and a low level, thereby reducing the dynamic power consumption of the clock trigger device, and further reducing the dynamic power consumption of the integrated circuit having the clock trigger device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0015] Figure 1 A schematic structural diagram of a clock trigger device and a control circuit provided in one embodiment of the present invention;

[0016] Figure 2 for Figure 1 The signal timing diagram of the control circuit shown;

[0017] Figure 3 A schematic structural diagram of a control circuit provided in one embodiment of the present invention;

[0018] Figure 4 A schematic structural diagram of a first control module and a second control module is provided for one embodiment of the present invention;

[0019] Figure 5 for Figure 4 The signal timing diagram of the first control module and the second control module shown;

[0020] Figure 6 A schematic structural diagram of a clock trigger device and a control circuit provided in another embodiment of the present invention;

[0021] Figure 7 for Figure 6 The signal timing diagram of the control circuit shown;

[0022] Figure 8A schematic structural diagram of a control circuit provided in one embodiment of the present invention;

[0023] Figure 9 A schematic structural diagram of a first control module and a second control module is provided for another embodiment of the present invention;

[0024] Figure 10 for Figure 9 The signal timing diagram of the control circuit shown;

[0025] Figure 11 A schematic structural diagram of a control circuit provided in another embodiment of the present invention;

[0026] Figure 12 A flow chart of a control method provided by one embodiment of the present invention;

[0027] Figure 13 A schematic diagram of the circuit structure of a clock trigger device provided in one embodiment of the present invention;

[0028] Figure 14 A schematic diagram of the circuit structure of a clock trigger device provided in another embodiment of the present invention. DETAILED DESCRIPTION

[0029] As described in the background art, during the operation of an integrated circuit, a clock trigger device will continuously switch between a high level and a low level according to a clock signal, resulting in huge dynamic power consumption of the integrated circuit.

[0030] One common approach to reducing the dynamic power consumption of integrated circuits (ICs) is to reduce the size of their internal transistors. However, this reduction in transistor size can lead to reduced IC performance. Another approach is to reduce the number of clock transitions using clock gating circuits to reduce the dynamic power consumption of the circuit. While this approach reduces the dynamic power consumption caused by clock transitions, it also increases the static power consumption of the circuit and can affect the performance of the IC.

[0031] The inventors have discovered that for clock-triggered devices, such as flip-flops, when the input signal level remains constant, the output signal level also remains constant. Clock signal flips do not affect the output signal. Reducing clock signal flips during periods when both the input and output signals remain constant not only reduces the dynamic power consumption of the clock-triggered device but also maintains its performance.

[0032] Based on the above-mentioned inventive concept, the embodiments of the present invention provide a control circuit, a control method, a clock trigger device, and related equipment. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0033] As an optional implementation of the contents disclosed in the embodiments of the present invention, the embodiments of the present invention provide a control circuit, which is connected to a clock trigger device. The clock trigger device can be a trigger, especially a trigger with a very small input signal change frequency, or other devices that require clock signal triggering.

[0034] like Figure 1 As shown, Figure 1 A schematic structural diagram of a clock trigger device and a control circuit provided for one embodiment of the present invention, wherein the control circuit is used to detect the level states of the input signal and the output signal of the clock trigger device. If the level states of the input signal and the output signal are the same, a first level signal is output to the clock trigger device to keep the level state of the output signal of the clock trigger device unchanged, wherein the level state of the first level signal remains unchanged.

[0035] Since the level state of the first-level signal remains unchanged, for example, the level of the first-level signal is always high or low, the level state of the output signal of the clock trigger device can be kept unchanged, so that the level of the clock signal end of the clock trigger device does not need to be flipped between high and low levels, thereby reducing the dynamic power consumption of the clock trigger device and further reducing the dynamic power consumption of the integrated circuit having the clock trigger device.

[0036] Since the clock trigger device does not need the clock signal to trigger the update of the output signal level state when the input signal and the output signal have the same level state, the clock signal is replaced with the first level signal whose level remains unchanged when the input signal and the output signal have the same level state. This can reduce the dynamic power consumption of the clock trigger device and the integrated circuit having the clock trigger device while maintaining the performance of the clock trigger device unchanged.

[0037] Based on the above embodiments, in some embodiments of the present invention, if the level states of the input signal and the output signal are opposite, the control circuit is further used to output a first clock signal to the clock trigger device, so that the level state of the output signal of the clock trigger device changes with the level state of the input signal; wherein the level of the first clock signal flips between a high level and a low level.

[0038] Since the first clock signal flips between a high level and a low level, the first clock signal can be used to trigger the clock trigger device to update the level state of the output signal, so that the level state of the output signal of the clock trigger device changes with the level state of the input signal, that is, the level state of the output signal is the same as the level state of the input signal, thereby realizing the normal operation of the clock trigger device such as a trigger.

[0039] Of course, the present invention is not limited to this. In other embodiments, if the level states of the input signal and the output signal are opposite, the control circuit may not output any signal. For example, a clock signal that flips between a high level and a low level may be output to the clock trigger device through other circuits to control the normal operation of the clock trigger device.

[0040] In some embodiments of the present invention, Figure 1 As shown, the clock trigger device includes a signal input terminal D, a first clock signal terminal CLKBB and a first signal output terminal Q. The signal input terminal D is used to receive an input signal, and the first signal output terminal Q is used to output an output signal.

[0041] The control circuit includes a first input terminal IN1, a second input terminal IN2, a second clock signal terminal CLK, and a first output terminal OUT1. The first input terminal IN1 is connected to the signal input terminal D, the second input terminal IN2 is connected to the first signal output terminal Q, the second clock signal terminal CLK is used to receive the first clock signal, and the first output terminal OUT1 is connected to the first clock signal terminal CLKBB for transmitting the first clock signal and the first level signal to the clock trigger device.

[0042] If the level states of the input signal and the output signal are opposite, under the control of the input signal and the output signal, the control circuit transmits the first clock signal to the first output terminal OUT1 , so as to transmit the first clock signal to the first clock signal terminal CLKBB through the first output terminal OUT1 .

[0043] If the input signal and the output signal have the same level state, under the control of the input signal and the output signal, the control circuit transmits the first level signal to the first output terminal OUT1 , so as to transmit the first level signal to the first clock signal terminal CLKBB through the first output terminal OUT1 .

[0044] like Figure 2 As shown, Figure 2 for Figure 1In the signal timing diagram of the control circuit shown in FIG, if the input signal d is a low level 0 and the output signal q is a high level 1, or if the input signal d is a high level 1 and the output signal q is a low level 0, the level states of the input signal d and the output signal q are opposite. Under the control of the input signal d and the output signal q, the control circuit transmits the first clock signal clk to the first output terminal OUT1, and the first clock signal clk is transmitted to the clock trigger device through the first output terminal OUT1 and the first clock signal terminal CLKBB.

[0045] If both the input signal d and the output signal q are at a low level of 0, or if both the input signal d and the output signal q are at a high level of 1, then the input signal d and the output signal q have the same level. Under the control of the input signal d and the output signal q, the control circuit transmits the first level signal Vt1 to the first output terminal OUT1, and the first level signal Vt1 is transmitted to the clock trigger device via the first output terminal OUT1 and the first clock signal terminal CLKBB. The level of the first level signal Vt1 can always be a high level of 1 or a low level of 0. In the embodiments of the present invention, the first level signal Vt1 is described as a low level of 0, but is not limited to this example.

[0046] In an embodiment of the present invention, by judging whether the level states of the input signal d and the output signal q are the same, it is judged whether the level state of the input signal d of the clock trigger device has changed, so as to judge whether the clock trigger device needs to flip the clock signal to trigger the update of the level state of the output signal q. Here, under the triggering of the clock signal, the level state of the output signal q will change with the level state of the input signal d, thereby reducing the flipping of the clock signal when the clock signal trigger is not required, thereby reducing the dynamic power consumption of the clock trigger device.

[0047] That is, if the levels of the input signal d and the output signal q are opposite, it indicates that the clock trigger device needs a clock signal to trigger an update of the level of the output signal q, and the control circuit transmits the first clock signal clk to the clock trigger device. If the levels of the input signal d and the output signal q are the same, it indicates that the clock trigger device does not need a clock signal to trigger an update of the level of the output signal q, and the control circuit transmits the first level signal Vt1, which remains unchanged, to the clock trigger device.

[0048] In some embodiments of the present invention, Figure 3 As shown, Figure 3This is a schematic diagram of the structure of a control circuit provided in one embodiment of the present invention. The control circuit includes a first control module 10 and a second control module 20. The first control module 10 is used to detect the level states of the input signal and the output signal of the clock trigger device. If the level states of the input signal and the output signal are the same, the first control signal K1 is output to the second control module 20. If the level states of the input signal and the output signal are opposite, the second control signal K2 is output to the second control module 20. The second control signal K1 is the output signal or a signal with a level state opposite to the output signal, and the second control signal K2 is a signal with a level state opposite to the first control signal K1. The second control module 20 outputs a first level signal to the clock trigger device based on the first control signal K1, and outputs a first clock signal to the clock trigger device based on the second control signal K2.

[0049] In some embodiments of the present invention, the first control module 10 is connected to a first input terminal IN1 and a second input terminal IN2, and is configured to transmit an input signal received by the signal input terminal to the first control module 10 via the first input terminal IN1, and to transmit an output signal output by the signal output terminal to the first control module 10 via the second input terminal IN2. The second control module 20 is connected to a second clock signal terminal CLK and a first output terminal OUT1, and is configured to receive a first clock signal via the second clock signal terminal CLK, and to transmit the first clock signal and a first level signal to the clock trigger device via the first output terminal OUT1.

[0050] Based on the above embodiments, in some embodiments of the present invention, Figure 4 As shown, Figure 4 A structural schematic diagram of a first control module 10 and a second control module 20 is provided for an embodiment of the present invention. The first control module 10 includes a first transmission gate TP1, a second transmission gate TP2, a first inverter INV1 and a second inverter INV2, and the second control module 20 includes a NAND gate NAND and a third inverter INV3.

[0051] A first input node T1 of the first transmission gate TP1 is connected to the first input terminal IN1 and the input terminal of the first inverter INV1, a second input node T2 of the first transmission gate TP1 is connected to the second input terminal IN2 and the input terminal of the second inverter INV2, and a third input node T3 of the first transmission gate TP1 is connected to the output terminal of the first inverter INV1.

[0052] A first input node P1 of the second transmission gate TP2 is connected to the output end of the first inverter INV1, a second input node P2 of the second transmission gate TP2 is connected to the output end of the second inverter INV2, a third input node P3 of the second transmission gate TP2 is connected to the first input end IN1, and the output end of the second transmission gate TP2 is connected to the output end of the first transmission gate TP1.

[0053] A first input node of the NAND gate NAND is connected to the second clock signal terminal CLK, a second input node of the NAND gate NAND is connected to the output terminal of the first transmission gate TP1, an output terminal of the NAND gate NAND is connected to the input terminal of the third inverter INV3, and an output terminal of the third inverter INV3 is connected to the first output terminal OUT1.

[0054] Optionally, the first transmission gate TP1 includes a first transistor and a second transistor connected in parallel. The structure of the second transmission gate TP2 is the same as that of the first transmission gate TP1 and is not further described here. One of the first transistor and the second transistor is a PMOS transistor and the other is an NMOS transistor. The gate of the first transistor is connected to a first input node T1 / P1 of the first transmission gate TP1, the source of the first transistor and the second transistor is connected to a second input node T2 / P2 of the first transmission gate TP1, and the gate of the second transistor is connected to a third input node T3 / P3.

[0055] Take the first transistor as a PMOS transistor and the second transistor as an NMOS transistor as an example for explanation. Figure 5 As shown, Figure 5 for Figure 4 In the signal timing diagram of the first control module and the second control module shown in the figure, if the input signal d is a low level 0 and the output signal q is a high level 1, the first input node T1 of the first transmission gate TP1 is a low level 0, the second input node T2 of the first transmission gate TP1 is a high level 1, and the third input node T3 of the first transmission gate TP1 is a high level 1. The first input node P1 of the second transmission gate TP2 is a high level 1, the second input node P2 of the second transmission gate TP2 is a low level 0, and the third input node P3 of the second transmission gate TP2 is a low level 0. At this time, the first transistor and the second transistor of the first transmission gate TP1 are both turned on, and the first transistor and the second transistor of the second transmission gate TP2 are both turned off. The first transmission gate TP1 transmits the high level 1 of the second input node T2 to the output end, that is, transmits the first control signal K1, i.e., the high level 1, to the NAND gate NAND.

[0056] If the input signal d is a high level 1 and the output signal q is a low level 0, the first input node T1 of the first transmission gate TP1 is a high level 1, the second input node T2 of the first transmission gate TP1 is a low level 0, and the third input node T3 of the first transmission gate TP1 is a low level 0. The first input node P1 of the second transmission gate TP2 is a low level 0, the second input node P2 of the second transmission gate TP2 is a high level 1, and the third input node P3 of the second transmission gate TP2 is a high level 1. At this time, the first transistor and the second transistor of the first transmission gate TP1 are both turned off, and the first transistor and the second transistor of the second transmission gate TP2 are both turned on. The second transmission gate TP2 transmits the high level 1 of the second input node P2 to the output end, that is, transmits the first control signal K1, i.e., the high level 1, to the NAND gate NAND.

[0057] If the input signal d is a low level 0 and the output signal q is a low level 0, the first input node T1 of the first transmission gate TP1 is a low level 0, the second input node T2 of the first transmission gate TP1 is a low level 0, the third input node T3 of the first transmission gate TP1 is a high level 1, the first input node P1 of the second transmission gate TP2 is a high level 1, the second input node P2 of the second transmission gate TP2 is a high level 1, and the third input node P3 of the second transmission gate TP2 is a low level 0. At this time, the first transistor and the second transistor of the first transmission gate TP1 are both turned on, and the first transistor and the second transistor of the second transmission gate TP2 are both turned off. The first transmission gate TP1 transmits the low level 0 of the second input node T2 to the output end, that is, transmits the second control signal K2, i.e., the low level 0, to the NAND gate NAND.

[0058] If the input signal d is a low level 1 and the output signal q is a low level 1, the first input node T1 of the first transmission gate TP1 is a high level 1, the second input node T2 of the first transmission gate TP1 is a high level 1, and the third input node T3 of the first transmission gate TP1 is a low level 0. The first input node P1 of the second transmission gate TP2 is a low level 0, the second input node P2 of the second transmission gate TP2 is a low level 0, and the third input node P3 of the second transmission gate TP2 is a high level 1. At this time, the first transistor and the second transistor of the first transmission gate TP1 are both turned off, and the first transistor and the second transistor of the second transmission gate TP2 are both turned on. The second transmission gate TP2 transmits the low level 0 of the second input node P2 to the output end, that is, transmits the second control signal K2, i.e., the low level 0, to the NAND gate NAND.

[0059] According to the logic principle of the NAND gate, when the first control signal K1, i.e., a high level 1, is transmitted to the NAND gate, if the first clock signal clk is a high level 1, the NAND gate outputs a low level 0, and the third inverter INV3 outputs a high level. If the first clock signal clk is a low level 0, the NAND gate outputs a high level 1, and the third inverter INV3 outputs a low level 0. In other words, the output of the third inverter INV3 is the same as the first clock signal clk, so that the first clock signal clk can be transmitted to the first output terminal OUT1.

[0060] When the second control signal K2, which is a low level 0, is transmitted to the NAND gate NAND, regardless of whether the first clock signal clk is a low level 0 or a high level 1, the output of the NAND gate NAND is always a high level 1, and the output of the third inverter INV3 is always a low level 0. That is, the output of the third inverter INV3 is a first-level signal with a fixed level.

[0061] In other embodiments of the present invention, Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of a trigger and control circuit provided in another embodiment of the present invention. The clock trigger device also includes a signal output node DB and a second signal output terminal QB. The signal output node DB is used to output a third-level signal, which has a level state opposite to that of the input signal. The second signal output terminal QB is used to output a fourth-level signal, which has a level state opposite to that of the output signal. The control circuit also includes a third input terminal IN3 and a fourth input terminal IN4. The third input terminal IN3 is connected to the signal output node DB, and the fourth input terminal IN4 is connected to the second signal output terminal QB.

[0062] If the input signal and the output signal have opposite levels, the control circuit transmits the first clock signal to the first output terminal OUT1 under the control of the input signal, the output signal, the third level signal, and the fourth level signal. If the input signal and the output signal have the same level, the control circuit transmits the first level signal to the first output terminal OUT1 under the control of the input signal, the output signal, the third level signal, and the fourth level signal.

[0063] like Figure 7 As shown, Figure 7 for Figure 6The signal timing diagram of the control circuit shown in FIG. If the level of the input signal d is low level 0, the level of the output signal q is high level 1, the third level signal db is high level 1, and the fourth level signal qb is low level 0, or if the level of the input signal d is high level 1, the level of the output signal q is low level 0, the third level signal db is low level 0, and the fourth level signal qb is high level 1, the control circuit transmits the first clock signal clk to the first output terminal OUT1, and the first clock signal clk is transmitted to the clock trigger device through the first output terminal OUT1 and the first clock signal terminal CLKBB.

[0064] If the levels of the input signal d and the output signal q are both low level 0, and the third level signal db and the fourth level signal qb are both high level 1, or the levels of the input signal d and the output signal q are both high level 1, and the third level signal db and the fourth level signal qb are both low level 0, the control circuit transmits the first level signal Vt1 to the first output terminal OUT1, and the first level signal Vt1 is transmitted to the trigger through the first output terminal OUT1 and the first clock signal terminal CLKB.

[0065] Based on the above embodiments, in some embodiments of the present invention, Figure 8 As shown, Figure 8 This is a schematic diagram of the structure of a control circuit provided in one embodiment of the present invention, which includes a first control module 11 and a second control module 21. The functions of the first control module 11 and the second control module 21 have been described in the above embodiments and will not be repeated here.

[0066] In some embodiments of the present invention, the first control module 11 is connected to the first input terminal IN1, the second input terminal IN2, the third input terminal IN3 and the fourth input terminal IN4. The second control module 21 is connected to the second clock signal terminal CLK and the first output terminal OUT1.

[0067] If the input signal and the output signal have opposite levels, the first control module 11 outputs a second control signal K2 to the second control module 21 under the control of the input signal, the output signal, the third level signal, and the fourth level signal. The second control signal K2 is an output signal or a fourth level signal. Under the control of the second control signal K2, the second control module 21 outputs a first clock signal to the first output terminal OUT1.

[0068] If the input signal and the output signal have the same level, the first control module 11 outputs a first control signal K1 to the second control module 21 under the control of the input signal, the output signal, the third level signal, and the fourth level signal. The first control signal K1 has a level opposite to that of the second control signal K2. Under the control of the first control signal K1, the second control module 21 outputs a first level signal to the first output terminal OUT1.

[0069] In some embodiments of the present invention, Figure 9 As shown, Figure 9 A structural diagram of a first control module 11 and a second control module 21 is provided for another embodiment of the present invention. The first control module 11 includes a first transmission gate TP1 and a second transmission gate TP2 , and the second control module 21 includes a NAND gate NAND and a third inverter INV3 .

[0070] A first input node T1 of the first transmission gate TP1 is connected to the first input terminal IN1, a second input node T2 of the first transmission gate TP1 is connected to the second input terminal IN2, and a third input node T3 of the first transmission gate TP1 is connected to the third input terminal IN3. A first input node P1 of the second transmission gate TP2 is connected to the third input terminal IN3, a second input node P2 of the second transmission gate TP2 is connected to the fourth input terminal IN4, a third input node P3 of the second transmission gate TP2 is connected to the first input terminal IN1, and the output terminal of the second transmission gate TP2 is connected to the output terminal of the first transmission gate TP1. A first input node of the NAND gate NAND is connected to the second clock signal terminal CLK, a second input node of the NAND gate NAND is connected to the output terminal of the first transmission gate TP1, the output terminal of the NAND gate NAND is connected to the input terminal of the third inverter INV3, and the output terminal of the third inverter INV3 is connected to the first output terminal OUT1.

[0071] same, Figure 9 The first transmission gate TP1 includes a first transistor and a second transistor connected in parallel. The structure of the second transmission gate TP2 is the same as that of the first transmission gate TP1 and is not further described here. One of the first transistor and the second transistor is a PMOS transistor and the other is an NMOS transistor. The gate of the first transistor is the first input node T1 / P1, the source of the first transistor and the second transistor is the second input node T2 / P2, and the gate of the second transistor is the third input node T3 / P3.

[0072] Take the first transistor as a PMOS transistor and the second transistor as an NMOS transistor as an example for explanation. Figure 10 As shown, Figure 10 for Figure 9As shown in the signal timing diagram of the control circuit, if the level of the input signal d is low level 0, the level of the output signal q is high level 1, the third level signal db is high level 1, and the fourth level signal qb is low level 0, then the first input node T1 of the first transmission gate TP1 is low level 0, the second input node T2 of the first transmission gate TP1 is high level 1, and the third input node T3 of the first transmission gate TP1 is high level 1, the first input node P1 of the second transmission gate TP2 is high level 1, the second input node P2 of the second transmission gate TP2 is low level 0, and the third input node P3 of the second transmission gate TP2 is low level 0. At this time, the first transistor and the second transistor of the first transmission gate TP1 are both turned on, and the first transistor and the second transistor of the second transmission gate TP2 are both turned off. The first transmission gate TP1 transmits the high level 1 of the second input node T2 to the output end, that is, transmits the second control signal K2, i.e., the high level 1, to the second control module 20.

[0073] If the level of the input signal d is low level 1, the level of the output signal q is high level 0, the third level signal db is low level 0, and the fourth level signal qb is high level 1, then the first input node T1 of the first transmission gate TP1 is high level 1, the second input node T2 of the first transmission gate TP1 is low level 0, and the third input node T3 of the first transmission gate TP1 is low level 0, the first input node P1 of the second transmission gate TP2 is low level 0, the second input node P2 of the second transmission gate TP2 is high level 1, and the third input node P3 of the second transmission gate TP2 is high level 1. At this time, the first transistor and the second transistor of the first transmission gate TP1 are both turned off, and the first transistor and the second transistor of the second transmission gate TP2 are both turned on. The second transmission gate TP2 transmits the high level 1 of the second input node P2 to the output end, that is, transmits the second control signal K2, i.e., the high level 1, to the second control module 20.

[0074] If the level of the input signal d is low level 0, the level of the output signal q is low level 0, the third level signal db is high level 1, and the fourth level signal qb is high level 1, then the first input node T1 of the first transmission gate TP1 is low level 0, the second input node T2 of the first transmission gate TP1 is low level 0, and the third input node T3 of the first transmission gate TP1 is high level 1, the first input node P1 of the second transmission gate TP2 is high level 1, the second input node P2 of the second transmission gate TP2 is high level 1, and the third input node P3 of the second transmission gate TP2 is low level 0. At this time, the first transistor and the second transistor of the first transmission gate TP1 are both turned on, and the first transistor and the second transistor of the second transmission gate TP2 are both turned off. The first transmission gate TP1 transmits the low level 0 of the second input node T2 to the output end, that is, transmits the first control signal K1, i.e., the low level 0, to the second control module 20.

[0075] If the level of the input signal d is low level 1, the level of the output signal q is low level 1, the third level signal db is low level 0, and the fourth level signal qb is low level 0, then the first input node T1 of the first transmission gate TP1 is high level 1, the second input node T2 of the first transmission gate TP1 is high level 1, and the third input node T3 of the first transmission gate TP1 is low level 0, the first input node P1 of the second transmission gate TP2 is low level 0, the second input node P2 of the second transmission gate TP2 is low level 0, and the third input node P3 of the second transmission gate TP2 is high level 1. At this time, the first transistor and the second transistor of the first transmission gate TP1 are both turned off, and the first transistor and the second transistor of the second transmission gate TP2 are both turned on. The second transmission gate TP2 transmits the low level 0 of the second input node P2 to the output end, that is, transmits the first control signal K1, i.e., the low level 0, to the second control module 20.

[0076] Similarly, according to the logic principle of the NAND gate, when the second control signal K2, i.e., a high level 1, is transmitted to the NAND gate, the output of the third inverter INV3 is the same as the first clock signal clk, thereby transmitting the first clock signal clk to the first output terminal OUT1. When the first control signal K1, i.e., a low level 0, is transmitted to the NAND gate, regardless of whether the first clock signal clk is a low level 0 or a high level 1, the output of the NAND gate NAND is always a high level 1, and the output of the third inverter INV3 is always a low level 0. In other words, the output of the third inverter INV3 is a first-level signal Vt1 with a fixed level.

[0077] In some embodiments of the present invention, Figure 11 As shown, Figure 11 A structural diagram of a control circuit provided in another embodiment of the present invention, wherein the clock trigger device further includes a third clock signal terminal, and the control circuit further includes a second output terminal OUT2, the second output terminal OUT2 is connected to the output terminal of the NAND gate NAND, and the second output terminal OUT2 is connected to the third clock signal terminal.

[0078] If the input signal and the output signal have opposite levels, the second output terminal OUT2 transmits a second clock signal with a level opposite to the first clock signal to the third clock signal terminal. If the input signal and the output signal have the same level, the second output terminal OUT2 transmits a second level signal with a level opposite to the first level signal to the third clock signal terminal. If the first level signal is a low level 0, the second level signal is a high level 1; if the first level signal is a high level 1, the second level signal is a low level 0.

[0079] In the embodiment of the present invention, only two specific structures of the control circuit are used as examples for description, but the present invention is not limited thereto. As long as the circuit structure can realize the function of the control circuit in the embodiment of the present invention, it is within the protection scope of the present invention and will not be described in detail here.

[0080] As another optional implementation of the disclosure of the embodiment of the present invention, the embodiment of the present invention also provides a control method, such as Figure 12 As shown, Figure 12 A flow chart of a control method provided in one embodiment of the present invention includes:

[0081] S121: Detecting the level states of the input signal and output signal of the clock trigger device;

[0082] S122: If the level states of the input signal and the output signal are the same, output a first level signal to the clock trigger device to keep the level state of the output signal of the clock trigger device unchanged, wherein the level state of the first level signal remains unchanged.

[0083] Since the level state of the first-level signal remains unchanged, for example, the level of the first-level signal is always high or low, the level state of the output signal of the clock trigger device can be kept unchanged, so that the level of the clock signal end of the clock trigger device does not need to be flipped between high and low levels, thereby reducing the dynamic power consumption of the clock trigger device and further reducing the dynamic power consumption of the integrated circuit having the clock trigger device.

[0084] Since the clock trigger device does not need the clock signal to trigger the update of the output signal level state when the input signal and the output signal have the same level state, the clock signal is replaced with the first level signal whose level remains unchanged when the input signal and the output signal have the same level state. This can reduce the dynamic power consumption of the clock trigger device and the integrated circuit having the clock trigger device while maintaining the performance of the clock trigger device unchanged.

[0085] Based on the above embodiments, in some embodiments of the present invention, the control method further includes:

[0086] If the level states of the input signal and the output signal are opposite, a first clock signal is output to the clock trigger device so that the level state of the output signal of the clock trigger device changes with the level state of the input signal; wherein the level of the first clock signal flips between a high level and a low level.

[0087] Since the first clock signal flips between a high level and a low level, the first clock signal can be used to trigger the clock trigger device to update the level state of the output signal, so that the level state of the output signal of the clock trigger device changes with the level state of the input signal, that is, the level state of the output signal is the same as the level state of the input signal, thereby realizing the normal operation of the clock trigger device such as a trigger.

[0088] As another optional implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention further provide a clock trigger device, which includes the control circuit provided in any of the above embodiments. Optionally, the clock trigger device is a trigger, and the clock trigger device is a trigger with a very low frequency of input signal changes.

[0089] The trigger in the embodiment of the present invention may be a rising edge trigger, a falling edge trigger, or other types of triggers. In some embodiments of the present invention, the trigger is a rising edge trigger, and, as Figure 13 and Figure 14 As shown, Figure 13 A schematic diagram of the circuit structure of a trigger provided in one embodiment of the present invention is provided. Figure 14 A schematic diagram of a circuit structure of a trigger provided in another embodiment of the present invention, wherein: Figure 13 The trigger includes a trigger circuit and a control circuit provided by an embodiment of the present invention, Figure 14 The trigger includes a trigger circuit and a control circuit provided by another embodiment of the present invention.

[0090] Furthermore, in some embodiments of the present invention, the signal input terminal D of the trigger circuit is connected to the first input terminal IN1 of the control circuit, the first signal output terminal Q is connected to the second input terminal IN2 of the control circuit, the first clock signal terminal CLKBB is connected to the first output terminal OUT1 of the control circuit, and the third clock signal terminal CLKB is connected to the second output terminal OUT2 of the control circuit. It should be noted that in order to clearly illustrate the structure of the circuit, Figure 13 and Figure 14 The above connection relationship is not shown in FIG.

[0091] like Figure 13 and Figure 14 As shown, the trigger circuit also includes a fourth inverter INV4, a third transmission gate TP3, a fifth inverter INV5, a sixth inverter INV6, a fourth transmission gate TP4, a seventh inverter INV7, an eighth inverter INV8, a ninth inverter INV9 and a tenth inverter INV10, and the sixth inverter INV6 and the tenth inverter INV10 are three-state inverters.

[0092] An input terminal of the fourth inverter INV4 is connected to the signal input terminal D, an output terminal of the fourth inverter INV4 is connected to the second input node of the third transmission gate TP3, a first input node of the third transmission gate TP3 is connected to the third clock signal terminal CLKB, a third input node of the third transmission gate TP3 is connected to the first clock signal terminal CLKBB, an output terminal of the third transmission gate TP3 is connected to the input terminal of the fifth inverter INV5, an output terminal of the fifth inverter INV5 is connected to the first input node of the sixth inverter INV6, an output terminal of the sixth inverter INV6 is connected to the input terminal of the fifth inverter INV5, a second input node of the sixth inverter INV6 is connected to the first clock signal terminal CLKBB, and a third input node of the sixth inverter INV6 is connected to the third clock signal terminal CLKB;

[0093] A first input node of the fourth transmission gate TP4 is connected to the first clock signal terminal CLKBB, a second input node of the fourth transmission gate TP4 is connected to the output terminal of the fifth inverter INV5, a third input node of the fourth transmission gate TP4 is connected to the third clock signal terminal CLKB, an output terminal of the fourth transmission gate TP4 is connected to the input terminal of the seventh inverter INV7, an output terminal of the seventh inverter INV7 is connected to the eighth inverter INV8, an output terminal of the eighth inverter INV8 is connected to the first signal output terminal Q, an input terminal of the ninth inverter INV9 is connected to the input terminal of the seventh inverter INV7, an output terminal of the ninth inverter INV9 is connected to the third clock signal terminal CLKB, a first input node of the tenth inverter INV10 is connected to the output of the seventh inverter INV7, a second input node of the tenth inverter INV10 is connected to the third clock signal terminal CLKB, and a third input node of the tenth inverter INV10 is connected to the first clock signal terminal CLKBB.

[0094] The following simulation results combine those of a flip-flop without and with a control circuit. As shown in Table 1, DFF represents the flip-flop without a control circuit, and DFF_LP represents the flip-flop with a control circuit. Q_1_to_0(fC) represents the power consumption when the output signal q flips from a high level 1 to a low level 0, Q_0_to_1(fC) represents the power consumption when the output signal q flips from a low level 0 to a high level 1, and Q_keep(fC) represents the power consumption when the output signal q does not flip. Although DFF_LP increases static power consumption (leakage current) due to the addition of transistors, and dynamic power consumption during signal flips also increases, the increase is not significant. When the output signal q remains unchanged, the dynamic power consumption of DFF_LP is much smaller than that of DFF.

[0095] tt0p95v100c DFF DFF_LP ratio Leakage current (A) 3.88E-08 4.35E-08 112.10％ Q_1_to_0(fC) 0.8889 1.159 130.39％ Q_0_to_1(fC) 9.796 10.44 106.57％ Q_keep(fC) 0.50075 0.0936 18.69％

[0096] Table 1

[0097] Based on the values ​​in Table 1, we can calculate the energy consumption of these two flip-flops during operation: If the output signal q flips from a high level 1 to a low level 0, the total power consumption of the DFF when q does not flip at all and flips once is: 0.8889 + 0.50075 = 1.38965 (fC); while the total power consumption of the DFF_LP when q does not flip at all and flips once is: 1.159 + 0.0936 = 1.2526 (fC). Therefore, as long as q does not flip more than once, the total power consumption of the DFF_LP will be less than that of the DFF. Using the same algorithm, if q flips from 0 to 1, the total power consumption of the DFF_LP will be less than that of the DFF if q does not flip more than twice. Therefore, under a certain number of clock flips, if the number of q flips is less than two times, the energy consumed by the flip-flop in the embodiment of the present invention will be less than that of a normal flip-flop.

[0098]

[0099]

[0100] Table 2

[0101] Table 2 shows the simulation results for some key performance characteristics of these two flip-flops. We can see that adding the control circuit has limited impact on the triggering and holding of the flip-flop, with a slight increase in latency. Overall, however, the low-power flip-flop provided by the embodiment of the present invention performs slightly worse than a normal flip-flop, but this slight performance difference is acceptable given the power savings.

[0102] As another optional implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention further provide a chip, which includes the clock trigger device provided by any of the above embodiments.

[0103] As another optional implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention further provide an electronic device, which includes the chip provided in any of the above embodiments. The electronic device can be a terminal device or a server device.

[0104] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0105] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A control circuit, characterized in that: The control circuit is connected to the clock trigger device, and the control circuit is used to: detecting the level states of the input signal and the output signal of the clock trigger device, and if the level states of the input signal and the output signal are the same, outputting a first level signal to the clock trigger device so that the level state of the output signal of the clock trigger device remains unchanged; wherein the level state of the first level signal remains unchanged; If the level states of the input signal and the output signal are opposite, outputting a first clock signal to the clock trigger device so that the level state of the output signal of the clock trigger device changes with the level state of the input signal; wherein the level state of the first clock signal flips between a high level and a low level; The control circuit includes a first control module and a second control module; the first control module includes: a first transmission gate, a second transmission gate, a first inverter and a second inverter; the second control module includes: a NAND gate and a third inverter; the control circuit also includes: a first input terminal, a second input terminal, a second clock signal terminal and a first output terminal; The first input node of the first transmission gate is connected to the first input terminal and the input terminal of the first inverter, the second input node is connected to the second input terminal and the input terminal of the second inverter, and the third input node is connected to the output terminal of the first inverter; The first input node of the second transmission gate is connected to the output terminal of the first inverter, the second input node is connected to the output terminal of the second inverter, the third input node is connected to the first input terminal, and the output terminal is connected to the output terminal of the first transmission gate; The first input node of the NAND gate is connected to the second clock signal terminal, the second input node is connected to the output terminal of the first transmission gate, and the output terminal is connected to the input terminal of the third inverter; the output terminal of the third inverter is connected to the first output terminal.

2. The control circuit according to claim 1, wherein: The first control module is configured to detect the level states of the input signal and the output signal of the clock trigger device; if the level states of the input signal and the output signal are the same, output a first control signal to the second control module; if the level states of the input signal and the output signal are opposite, output a second control signal to the second control module; The second control module is configured to output the first level signal to the clock trigger device based on the first control signal, or to output the first clock signal to the clock trigger device based on the second control signal.

3. The control circuit according to claim 2, characterized in that: The clock trigger device comprises: a signal input terminal, a first clock signal terminal and a first signal output terminal; the signal input terminal is used to receive the input signal; the first signal output terminal is used to output the output signal; Among them, the first input end is connected to the signal input end and the first control module to transmit the input information received by the signal input end to the first control module; the second input end is connected to the signal output end and the first control module to transmit the output signal output by the signal output end to the first control module; the second clock signal end is used to receive a first clock signal; the first output end is connected to the first clock signal end and the second control module, and is used to transmit the first clock signal or the first level signal output by the second control module to the clock trigger device.

4. The control circuit according to claim 3, characterized in that: The clock trigger device further includes: a signal output node and a second signal output terminal; the signal output node is used to output a third level signal, the third level signal having a level state opposite to that of the input signal; the second signal output terminal is used to output a fourth level signal, the fourth level signal having a level state opposite to that of the output signal; The control circuit also includes: a third input terminal and a fourth input terminal; the third input terminal is connected to the signal output node; the fourth input terminal is connected to the second signal output terminal; the first output terminal is connected to the first clock signal terminal, for transmitting the first clock signal and the first level signal to the clock trigger device.

5. The control circuit according to claim 4, characterized in that: The first control module includes: a first transmission gate and a second transmission gate; the second control module includes: a NAND gate and a third inverter; A first input node of the first transmission gate is connected to the first input terminal, a second input node is connected to the second input terminal, and a third input node is connected to the third input terminal; The first input node of the second transmission gate is connected to the third input terminal, the second input node is connected to the fourth input terminal, the third input node is connected to the first input terminal, and the output terminal is connected to the output terminal of the first transmission gate; The first input node of the NAND gate is connected to the second clock signal terminal, the second input node is connected to the output terminal of the first transmission gate, and the output terminal is connected to the input terminal of the third inverter; the output terminal of the third inverter is connected to the first output terminal.

6. The control circuit according to claim 1 or 5, characterized in that: The first transmission gate includes a first transistor and a second transistor connected in parallel; one of the first transistor and the second transistor is a PMOS transistor and the other is an NMOS transistor; the gate of the first transistor is connected to a first input node of the first transmission gate, the source of the first transistor and the second transistor is connected to a second input node of the first transmission gate, and the gate of the second transistor is connected to a third input node of the first transmission gate.

7. The control circuit according to claim 1 or 5, characterized in that: The clock trigger device further includes a third clock signal terminal; the control circuit further includes a second output terminal; the second output terminal is connected to the output terminal of the NAND gate; the second output terminal is connected to the third clock signal terminal; Among them, if the level states of the input signal and the output signal are opposite, the second output end transmits a second clock signal whose level state is opposite to the first clock signal to the third clock signal end; if the level states of the input signal and the output signal are the same, the second output end transmits a second level signal whose level state is opposite to the first level signal to the third clock signal end.

8. A control method, characterized in that: The control circuit as claimed in claim 1 comprises: Detect the level status of the input signal and output signal of the clock trigger device; If the level states of the input signal and the output signal are the same, outputting a first level signal to the clock trigger device so that the level state of the output signal of the clock trigger device remains unchanged; wherein the level state of the first level signal remains unchanged; If the level states of the input signal and the output signal are opposite, a first clock signal is output to the clock trigger device so that the level state of the output signal of the clock trigger device changes with the level state of the input signal; the level state of the first clock signal flips between a high level and a low level.

9. A clock trigger device, characterized in that: The control circuit comprises the control circuit according to any one of claims 1 to 7.

10. A chip, characterized in that: Including the clock trigger device according to claim 9.

11. An electronic device, characterized in that: Comprising the chip according to claim 10.

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