Input / Output System and Method for Superconducting Devices

Abstract

A quantum processor includes a plurality of tiles arranged in a first grid, and wherein a first tile of the plurality of tiles includes a plurality of qubits (e.g., superconducting qubits). The quantum processor further includes a shift register, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid, the shift register including at least one shift-register stage communicatively coupled to frequency multiplexed resonance (FMR) readout. The quantum processor may further include a transmission line having at least one transmission line inductor, a superconducting resonator, and a coupling capacitor communicatively coupling the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming of the first tile may be performed in parallel with programming of a second tile of the plurality of tiles.

Description

Technical Field

[0001] This disclosure generally relates to input and / or output systems and methods for superconducting devices such as superconducting quantum computers and superconducting classical computers, and more particularly to systems and methods for inputting data into a superconducting quantum processor and / or measuring the state of qubits in the superconducting quantum processor. Background Art

[0002] Frequency Multiplexing Resonance (FMR) Readout

[0003] Superconducting microwave resonators have been used in various fields, including but not limited to quantum computing and astronomy. For example, in quantum computing, superconducting resonators have been used to detect the state of qubits. In astronomy, superconducting microwave resonators have been used in microwave kinetic inductance detectors (MKIDs). In both cases, many resonators (used as detectors or in detectors) can be coupled to a common transmission line and integrated through frequency domain multiplexing (see glossary).

[0004] Using FMR technology, superconducting resonators with different resonant frequencies can be used to read out multiple qubits. By using frequency domain multiplexing, the resonators can share a common microwave transmission line. Summary of the Invention

[0005] A quantum processor can be generally summarized as including multiple tiles, a shift register, a qubit readout device, multiple digital-to-analog converter (DAC) buffer stages, and digital-to-analog converters (DACs) loadable by the multiple shift registers arranged in a second grid, the multiple tiles arranged in a first grid, a first tile among the multiple tiles including a first qubit, the shift register including at least one shift register stage communicatively coupled to frequency multiplexed resonance (FMR) readout. In some embodiments, the first qubit is communicatively coupled to the qubit readout device. In some embodiments, at least one of the multiple DAC buffer stages is communicatively coupled to at least one of the DACs loadable by the multiple shift registers.

[0006] In some embodiments, the first qubit is a superconducting qubit. In some embodiments, the superconducting qubit is a superconducting flux qubit.

[0007] In some embodiments, the quantum processor further includes a microwave transmission line communicatively coupled to the FMR readout.

[0008] In some embodiments, the FMR readout includes a superconducting resonator.

[0009] In some embodiments, the first grid and the second grid interleave with each other on the superconducting integrated circuit. The term "interleave" in this context means that the first grid and the second grid (and the devices in the grids) physically overlap, interlace, cross, braid, or mix with each other on the superconducting integrated circuit.

[0010] In some embodiments, the FMR readout and the digital-to-analog converter (DAC) that can be loaded by the plurality of shift registers are located on the same superconducting integrated circuit.

[0011] In some embodiments, the quantum processor further includes a transmission line, a superconducting resonator, and a coupling capacitor that communicatively couples the superconducting resonator to the transmission line, and the transmission line includes at least one transmission line inductor.

[0012] In some embodiments, the FMR readout is communicatively coupled to at least one other element of the quantum processor through a superconducting via. In some embodiments, the FMR readout is communicatively coupled to at least one other element of the quantum processor through at least one of a bump bond and / or a solder bond.

[0013] A hybrid computing system can be generally summarized as including the quantum processor of each of the above embodiments, and further including at least one digital processor and at least one non-transitory processor-readable medium communicatively coupled to the at least one digital processor, and the at least one non-transitory processor-readable medium stores at least one of processor-executable instructions or data, and these instructions or data, when executed by the at least one digital processor, cause the at least one digital processor to program the quantum processor.

[0014] In some embodiments, in order for the at least one digital processor to program the quantum processor, at least one of the processor-executable instructions or data, when executed by the at least one digital processor, causes the at least one digital processor to program a first tile among a plurality of tiles. In some embodiments, in order for the at least one digital processor to program the first tile among the plurality of tiles, at least one of the processor-executable instructions or data, when executed by the at least one digital processor, causes the at least one digital processor to program at least one of the DACs that can be loaded by the plurality of shift registers.

[0015] In some embodiments, in order for the at least one digital processor to program the quantum processor, at least one of the processor-executable instructions or data, when executed by the at least one digital processor, further causes the at least one digital processor to program a second tile among the plurality of tiles. In some embodiments, in order for the at least one digital processor to program the second tile among the plurality of tiles, at least one of the processor-executable instructions or data, when executed by the at least one digital processor, causes the at least one digital processor to program the first tile and the second tile among the plurality of tiles in parallel. In each of the above embodiments, causing the at least one digital processor to program the first tile and the second tile among the plurality of tiles in parallel can make a first time required to program the first tile be at least substantially the same as a second time required to program the second tile among the plurality of tiles.

[0016] In some embodiments, at least one of the processor-executable instructions or data, when executed by the at least one digital processor, further causes the hybrid computing system to read out a first qubit of a first tile among the plurality of tiles and a second qubit of the first tile among the plurality of tiles in parallel. In each of the above embodiments, at least one of the processor-executable instructions or data, when executed by the at least one digital processor, further causes the hybrid computing system to read out a first qubit of a first tile among the plurality of tiles and a third qubit of a second tile among the plurality of tiles in parallel.

[0017] In some embodiments, at least one of the processor-executable instructions or data, when executed by the at least one digital processor, further causes the hybrid computing system to read out a first qubit of a first tile among the plurality of tiles and a second qubit of a second tile among the plurality of tiles, wherein a first time required to read out the first qubit of the first tile among the plurality of tiles is at least substantially the same as a second time required to read out the second qubit of the second tile among the plurality of tiles.

[0018] In each of the above embodiments, at least one of the processor-executable instructions or data, when executed by the at least one digital processor, further causes the at least one digital processor to calibrate at least a first part of the quantum processor and a second part of the quantum processor in parallel operation, and the first part of the quantum processor is non-local with respect to the second part of the quantum processor.

[0019] A quantum computer can be generally summarized as including a first superconducting integrated circuit and a second superconducting integrated circuit. The first superconducting integrated circuit includes a quantum processor, and the quantum processor includes a plurality of superconducting flux qubits. The second superconducting integrated circuit includes an input / output system. Wherein, the input / output system includes a shift register, a qubit readout device, a plurality of DAC buffer stages, and a digital-to-analog converter (DAC) loadable by a plurality of shift registers arranged in a grid. The shift register includes at least one shift register stage communicatively coupled to a frequency multiplexed resonance readout (FMRR) module.

[0020] A method for programming a hybrid computing system, the hybrid computing system including a quantum processor and a digital processor. The quantum processor includes a plurality of tiles, a shift register, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a DAC loadable by a plurality of shift registers arranged in a second grid. The plurality of tiles are arranged in a first grid. A first tile among the plurality of tiles includes a first qubit. The shift register includes at least one shift register stage communicatively coupled to a frequency multiplexed resonance (FMR) readout. The method can be generally summarized as including: programming the quantum processor by the digital processor, and reading out the quantum processor by the digital processor.

[0021] In some embodiments, programming the quantum processor by the digital processor includes programming the first tile among the plurality of tiles. In some embodiments, programming the first tile among the plurality of tiles includes programming at least one DAC among the plurality of DACs loadable by the plurality of shift registers.

[0022] In some embodiments, programming the quantum processor by the digital processor further includes programming a second tile among the plurality of tiles. In some embodiments, programming the first tile and the second tile among the plurality of tiles includes programming the first tile and the second tile among the plurality of tiles in parallel. In each of the above embodiments, programming the first tile among the plurality of tiles maintains a first duration, and programming the second tile among the plurality of tiles maintains a second duration. The first duration is at least substantially the same as the second duration.

[0023] In some embodiments, reading out the quantum processor by the digital processor includes reading out a first qubit of a first tile among the plurality of tiles and a second qubit of the first tile among the plurality of tiles in parallel. In each of the above embodiments, reading out the quantum processor by the digital processor includes reading out a first qubit of a first tile among the plurality of tiles and a third qubit of a second tile among the plurality of tiles in parallel. In some embodiments, reading out the quantum processor by the digital processor includes reading out a first qubit of a first tile among the plurality of tiles and reading out a second qubit of a second tile among the plurality of tiles, wherein a first time required to read out the first qubit of the first tile among the plurality of tiles and a second time required to read out the second qubit of the second tile among the plurality of tiles are at least substantially the same.

[0024] In each of the above embodiments, the method further includes calibrating at least a first portion of the quantum processor and a second portion of the quantum processor in a parallel operation, the first portion of the quantum processor being non-local with respect to the second portion of the quantum processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In the drawings, like reference numerals identify similar elements or acts. The dimensions and relative positions of the elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of the various elements are not necessarily drawn to scale, and some of these elements are arbitrarily enlarged and positioned to improve the readability of the drawings. Further, the particular shapes of the drawn elements are not necessarily intended to convey any information regarding the actual shape of the particular elements, but are merely selected for ease of identification in the drawings.

[0026] Figure 1 is a schematic diagram showing an exemplary arrangement of an FMRR array in a superconducting processor.

[0027] Figure 2 is a schematic diagram showing an exemplary embodiment of a superconducting processor including a shift register.

[0028] Figure 3 is a schematic diagram showing an exemplary embodiment of a readout system for a superconducting circuit.

[0029] Figure 4 is a schematic diagram of an exemplary hybrid computing system that can incorporate FMRR technology as described herein, the hybrid computing system including a digital computer and a quantum computer.

[0030] Figure 5 is a flowchart of an exemplary method of programming a hybrid computing system (e.g., Figure 4 of the hybrid computing system). DETAILED DESCRIPTION

[0031] Glossary

[0032] Qubit: A qubit (also referred to as a quantum bit in this application) is the basic unit of quantum information and is the quantum version of a classical binary bit that can be physically implemented using a two-state device. A qubit is a two-state quantum mechanical system. A qubit also refers to the actual physical device in which information is stored. For example, a superconducting qubit is a superconducting device that can be included in a superconducting integrated circuit. A superconducting qubit can take the form of, for example, a charge-based or flux-based qubit.

[0033] Superconducting device: A superconducting device is an electronic device that utilizes the properties of superconducting materials (e.g., zero resistance and magnetic flux expulsion when cooled below the critical temperature characteristic of the superconducting material).

[0034] Superconducting circuit: A superconducting circuit is a circuit that includes one or more superconducting devices.

[0035] Superconducting microwave resonator (also referred to as a superconducting microresonator in this application): A superconducting microwave resonator is a superconducting circuit that exhibits resonance at microwave frequencies. A superconducting microresonator can be produced by depositing a superconducting thin film on an insulating substrate and applying standard lithographic patterning techniques to create the resonator structure. A superconducting microresonator can be a lumped element circuit or a transmission line resonator. Because microresonators are simple and because large arrays can be read out using frequency domain multiplexing (see FMRR below), microresonators are attractive for detector applications.

[0036] Microwave transmission line: A microwave transmission line is a cable or other structure that includes one or more conductors that are capable of operating to carry an alternating current at microwave frequencies.

[0037] Frequency division multiplexing (FDM): FDM is a technique for dividing a communication bandwidth into multiple non-overlapping subbands, each subband being used to carry a separate signal.

[0038] Frequency multiplexed resonator readout (FMRR): FMRR is a readout technique that includes superconducting resonators that are capable of operating in a frequency division multiplexing mode. The FMRR technique includes one or more frequency multiplexed resonator (FMR) readouts.

[0039] SQUID (superconducting quantum interference device): A SQUID is a superconducting device that includes a superconducting loop that contains one or more Josephson junctions. A SQUID can be used as a magnetometer capable of measuring very weak magnetic fields. A DC SQUID has two Josephson junctions connected in parallel. An RF-SQUID has a superconducting loop that contains a single Josephson junction.

[0040] Lumped element design: In lumped element design, a physically distributed system is described as a topology of discrete entities that approximate the behavior of a distributed system under certain assumptions. For example, this is useful in electrical and electronic systems.

[0041] Shift register: A shift register is a sequential logic circuit capable of manipulating data for storage and / or transfer.

[0042] Quantum flux parametric amplifier (QFP): A QFP is a logic circuit including at least one superconducting Josephson junction and a resonant circuit in which one oscillation can represent one binary digit. Although the design of a QFP utilizes quantum principles, it is an element of classical computing technology rather than quantum computing technology.

[0043] Hybrid computer: A hybrid computer is a system including at least one digital processor and at least one analog processor (e.g., a quantum processor).

[0044] Josephson junction: A Josephson junction is a device including two electrodes and a thin insulating potential barrier layer separating the two electrodes, and the materials of the two electrodes can be superconducting at the critical temperature characteristics of the material or superconducting below the critical temperature characteristics.

[0045] Flux digital-to-analog converter (DAC): A flux DAC is a superconducting device in which a magnetic flux quantum representation of a digital signal can be established, converted into an analog supercurrent, and given to another device (e.g., a programmable device).

[0046] Introduction

[0047] In the following description, some specific details are included to provide a comprehensive understanding of each disclosed embodiment and example. However, those skilled in the relevant art will recognize that an embodiment or example can be practiced without one or more of these specific details, or can be practiced using other methods, components, materials, etc. In other instances, well-known structures associated with superconducting circuits or resonators are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments and examples of the present method. Throughout this specification and the appended claims, the words "element" and "a plurality of elements" are used to encompass but not be limited to all such structures, systems, and devices associated with superconducting circuits and superconducting resonators.

[0048] Unless the context otherwise requires, throughout this specification and the appended claims, the word "comprise" is synonymous with "including" and is inclusive or open-ended (i.e., does not exclude additional, unrecited elements or acts).

[0049] References throughout this specification to "one embodiment", "an embodiment", "another embodiment", "an example", "the example", "another example", "one implementation", "another implementation", etc. mean that a particular indicated feature, structure, or characteristic described in connection with the embodiment, example, or implementation is included in at least one embodiment, example, or implementation. Thus, the phrases "in one embodiment", "in an embodiment", "in another embodiment", etc. appearing throughout this specification do not necessarily all refer to the same embodiment, example, or implementation. In addition, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, examples, or implementations.

[0050] It should be noted that, as used in this specification and the appended claims, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" include plural referents. Thus, for example, a reference to a readout system that "includes a superconducting resonator" includes a single superconducting resonator, or two or more superconducting resonators. It should also be noted that, unless the context clearly dictates otherwise, the term "or" is generally used in the sense of including "and / or".

[0051] The section headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0052] Detailed Description

[0053] In a conventional implementation of a quantum processor, qubits are arranged in one or more tiles, and the tiles in the quantum processor are arranged in a grid (e.g., a square grid of N×N tiles).

[0054] In this application, a tile refers to an array of qubits. In one implementation, a tile includes M horizontally aligned qubits and an equal number M of vertically aligned qubits. In another implementation, a tile includes at least one partial qubit (i.e., a tile includes at least one qubit whose part is located outside the boundary of the tile or whose only partial instantiation is a qubit). A part of a qubit may be a segment of the qubit. The partial instantiation of a qubit may only include some (but not all) segments of the qubit. For some examples of quantum processor topologies, see the following reference: International PCT Patent Publication No. WO 2017214331 A1, entitled SYSTEMS AND METHODS FOR QUANTUM PROCESSOR TOPOLOGY.

[0055] In the present application, a horizontally-aligned qubit is a qubit that is larger in size along a horizontal axis than along a vertical axis, where the vertical axis is perpendicular to the horizontal axis. For example, the horizontal axis can be defined as the axis parallel to the side of the integrated circuit that includes the quantum processor. In the present application, a vertically-aligned qubit is a qubit that is larger in size along the vertical axis than along the horizontal axis.

[0056] In an implementation of a quantum processor (such as the quantum processor described above (having N×N tiles, and M×M qubits in each tile)), the readout time required to read out the qubits in the quantum processor can be proportional to the product NM.

[0057] A quantum processor can be programmed using multiple programming lines to the quantum processor. In the present application, the programming lines are also referred to as addressing lines and power lines. For a description of the addressing lines and power lines, see, for example, International PCT Patent Application No. US2018 / 054306 (Publication No. WO 2019 / 070935 A2), "QUANTUM FLUX PARAMETRON BASED STRUCTURES (E.G., MUXES, DEMUXES, SHIFT REGISTERS), ADDRESSING LINES AND RELATED METHODS [Based on quantum flux parametron-based structures (e.g., multiplexers, demultiplexers, shift registers), addressing lines and related methods]".

[0058] A programming system for a quantum processor can include multiple digital-to-analog converters (DACs). In a conventional implementation of a quantum processor (such as the quantum processor described above), the programming system can include approximately (NM) 2 DACs.

[0059] Generally, it is desirable to keep the number of programming lines of the quantum processor (also referred to as the total line count in the present application) as low as practically possible. Generally, there can be at least approximately address lines and power lines, and the programming time can be proportional to (NM) 4 / 3 proportional.

[0060] Although the example implementations described above refer to a square grid of tiles and the number of horizontal and vertical qubits in each tile is equal, other implementations of the systems and methods described in the present application can have at least one of the following: a) a non-square grid of tiles; and b) the number of horizontal and vertical qubits in the tiles is not equal.

[0061] U.S. Patent Application No. 15 / 726,239, also published as US 20180101786 A1, and International PCT Application Publication No. WO 2019 / 070935 A2, both titled "QUANTUM FLUX PARAMETRON BASED STRUCTURES (E.G. MUXES, DEMUXES, SHIFT REGISTERS), ADDRESSING LINES AND RELATED METHODS", provide examples of device systems for implementing shift registers in quantum processors.

[0062] Some quantum processors use an XYZ scheme to address shift - register - controlled DACs, where the X - signal and Y - signal are represented as address (ADDR) lines and trigger (TRIG) lines respectively, and the Z - signal is represented as a power (PWR) line. DAC stages in a quantum - processor partition can be electrically communicatively coupled in series. Powering the partition, asserting the ADDR line, and toggling the TRIG line multiple times can write a corresponding number of pulses into a selected DAC.

[0063] Methods useful for the operation of scalable processors with an increasing number of logic devices (e.g., qubits) can implement shift registers, multiplexers, demultiplexers, and permanent - magnet memories, etc., using, for example, QFPs. These methods can employ XY or XYZ addressing schemes and can use control lines that extend in a "weaving" pattern over a device array. In some embodiments, a DAC can use dynamic inductance to store energy using thin - film superconducting materials and / or a series of Josephson junctions, and can use a single - loop or multi - loop design and can include meandering structures. The DAC can be communicatively coupled to other devices in a current - based and / or inductance - based manner.

[0064] This application describes systems and methods that include an arrangement of a shift register communicatively coupled to:

[0065] a) a shift - register - controlled DAC (i.e., a DAC controlled by one or more shift registers), and

[0066] b) a quantum readout device (e.g., a qubit readout quantum flux parametron [QFP]).

[0067] A shift register can be communicatively coupled to one or more frequency and sensitivity tunable resonators (FASTR) detectors (also referred to herein as FASTR or FASTR devices). For example, see "A FREQUENCY AND SENSITIVITY TUNABLE MICRORESONATOR ARRAY FOR HIGH-SPEED QUANTUM PROCESSOR READOUT" by J.D. Whittaker et al., Journal of Applied Physics 119, 014506 (2016).

[0068] One embodiment of the systems and methods described herein includes a regular grid (e.g., a rectangular grid) of shift register controlled DACs having two readout axes: one axis for reading horizontal qubits and another axis for reading vertical qubits.

[0069] The shift registers for routing data to and / or from the FASTR detectors can be communicatively coupled in at least a tree-like fashion. "Tree" as used herein refers to a set of nodes connected by a set of edges such that there is a path from any node to any other node and where there are no node cycles. The term "at least tree-like" as used herein refers to relaxing the condition of no node cycles. The FASTR detector can be the root of the tree and the shift register stages can be connected as needed. In one embodiment, the system can move data from the FASTR detector to a desired shift register stage and then back to the FASTR detector.

[0070] In another embodiment of the systems and methods described herein, there are three readout axes and a hexagonal region of DACs.

[0071] In yet another embodiment, the I / O region includes only a portion of a tile. In yet another embodiment, the I / O region includes more than one tile. In yet another embodiment, the I / O region includes only partial rows or all rows of one or more tiles. In yet another embodiment, the I / O region includes only partial columns or all columns of one or more tiles.

[0072] One advantage of the systems and methods described herein is a reduction in the programming time and / or readout time of a quantum processor. In one embodiment, the programming time can be related to M 2is proportional to M, and the readout time can be proportional to M. In one embodiment, the lines to a quantum processor including an N×N tile grid include N microwave lines. In other embodiments, the lines to a quantum processor including an N×N tile grid include more than N microwave lines. In still other embodiments, the lines to a quantum processor including an N×N tile grid include fewer than N microwave lines. The lines to the quantum processor can also include a plurality of shift register control lines.

[0073] In one embodiment, the qubits in the quantum processor are placed on an integrated circuit (also referred to as a chip in this application), and the FMR readout is placed on a separate chip. The advantage of using a separate chip for the FMR readout is that the isolation between the qubits of the quantum processor and the microwave FMRR lines can be improved. Another advantage is that the area required for the layout of the quantum processor can be reduced. Still another advantage is that the FMR readout can be tested and preselected in a cryogenic environment and then integrated with the quantum processor, thereby improving the reliability of the integrated system.

[0074] In another embodiment, the quantum processor can include a conventional readout system that includes peripheral FMRR and / or non-destructive readout (NDRO) modules for input and output. In this embodiment, both the FMR readout and the quantum processor can be tested separately before integration.

[0075] In another embodiment, the FMR readout is incorporated in-situ into the quantum processor, for example, in a tiled qubit arrangement.

[0076] In one embodiment, the FMR readout is arranged in a rectangular grid, and the grid is controlled by microwave lines arranged in parallel. For example, see Figure 1 the embodiments and the following description.

[0077] This rectangular FMR readout grid can be communicatively coupled to an integrated input / output network as shown, for example, in Figure 2 and described below with reference to Figure 2 In this arrangement, the input / output (I / O) to each internal tile can be performed separately. The control I / O to each tile and the lines controlling the I / O can be the same. The input / output to each tile can be performed in parallel to provide parallelization of the input and / or output operations to each tile. In this context, performing more than one operation (e.g., more than one input / output) in parallel means performing more than one operation simultaneously or at least partially overlapping in time. The input operation can include programming the device. The output operation can include reading out the device.

[0078] It may be desirable to calibrate one part of a quantum processor independently of another part. The term calibration in this context includes measuring the characteristics of a quantum processor and / or devices in the quantum processor. Being able to control the local environment of devices (e.g., qubits) in a quantum processor is beneficial for calibration. The local environment generally refers to a device, its associated DAC, the nearest neighboring devices and their associated DACs, and the next nearest neighboring devices and their associated DACs.

[0079] One method of calibration is to divide the calibration process into a set of local measurements that can be performed in parallel with each other. This method can be applied to various types of quantum computers, including but not limited to adiabatic quantum computers and gate model quantum computers.

[0080] To perform calibration in parallel, it may be advantageous to be able to program the processor and read out the qubits in a way that does not increase the time proportional to the number of devices being measured (otherwise, there is little advantage compared to calibrating each local region one at a time). One method uses a parallel programming scheme that matches the concept of locality (e.g., where every N×M block of devices shares a set of programming lines). In this case, devices that are not local to each other can be programmed in parallel. The readout can be performed by a parallel readout scheme that can read out non-local devices in parallel. The programming can be performed by a parallel programming scheme that uses DACs near devices that are not local to each other.

[0081] The local environment of a controlled device (e.g., qubit) can be parallelizable as long as there is a parallel programming interface. Annealing qubits can be parallelizable if the qubits share analog lines and / or if the current on individual analog lines can be varied in parallel. Using parallel readout techniques (e.g., FMR readout technique), measuring the state of a qubit (also referred to as readout of a qubit in this application) can be parallelizable. The systems and methods described in this application include the FMR readout technique.

[0082] In this context, the term parallelizable refers to an operation whose cost does not scale proportionally with the number of devices used. In some embodiments, it may be beneficial if one aspect of an operation (e.g., the most time-consuming aspect) is parallelizable even if the operation is not otherwise parallelizable.

[0083] Figure 1 is a schematic diagram showing an example embodiment of part 100 of a superconducting processor.

[0084] Portion 100 includes an array of FMR readouts 102-1, 102-2, 102-3, and 102-4 (collectively referred to as FMR readout 102 in this application), 104-1, 104-2, 104-3, and 104-4 (collectively referred to as FMR readout 104 in this application), 106-1, 106-2, 106-3, and 106-4 (collectively referred to as FMR readout 106 in this application), and 108-1, 108-2, 108-3, and 108-4 (collectively referred to as FMR readout 108 in this application). FMR readout 102 is communicatively coupled to input line 110. FMR readout 104 is communicatively coupled to input line 112. FMR readout 106 is communicatively coupled to input line 114. FMR readout 108 is communicatively coupled to input line 116.

[0085] In one embodiment, input lines 110, 112, 114, and 116 are separate input lines. In another embodiment, some or all of input lines 110, 112, 114, and 116 are communicatively coupled to each other, e.g., wired together.

[0086] FMR readout 102 is communicatively coupled to other elements of the superconducting processor (not shown in Figure 1 at 118-1, 118-2, 118-3, and 118-4, respectively. FMR readout 104 is communicatively coupled to other elements of the superconducting processor at 120-1, 120-2, 120-3, and 120-4, respectively. FMR readout 106 is communicatively coupled to other elements of the superconducting processor at 122-1, 122-2, 122-3, and 122-4, respectively. FMR readout 108 is communicatively coupled to other elements of the superconducting processor at 124-1, 124-2, 124-3, and 124-4, respectively.

[0087] In one embodiment, the FMR readout is communicatively coupled in situ to other elements of the superconducting processor. In another embodiment, the FMR readout is communicatively coupled to other elements of the superconducting processor through superconducting vias. In this application, a via (vertical interconnection path) is an electrical connection between layers in a physical multi-layer electronic circuit (e.g., an integrated circuit) that passes through the plane of one or more adjacent layers. In yet another embodiment, the FMR readout is communicatively coupled to other elements of the superconducting processor on a separate chip using a bump bond, a solder bond, or another suitable electrical communication coupling.

[0088] Figure 2 is a schematic diagram showing another exemplary embodiment of portion 200 of the superconducting processor. Portion 200 of the superconducting processor includes a plurality of shift registers.

[0089] Portion 200 of the superconducting processor includes a communicatively coupled FMRR module (e.g.,Figure 1 The shift register 202 of the FMRR module 104-1). In some embodiments, the shift register 202 is a single shift register stage. In some embodiments, the shift register 202 includes more than one shift register stage. For example, a portion 200 of a superconducting processor can be communicatively coupled to the FMRR module via multiple shift register stages.

[0090] A portion 200 of a superconducting processor includes a tee stage 204 that communicatively couples the shift register 202 to three-phase internal streets 206 and 208. In the present application, a street is a data path, i.e., a path along which data can travel through the superconducting processor. The data traveling along the street can be input data and / or output data. In one embodiment, the tee stage 204 is communicatively coupled to the FMRR module (e.g., Figure 1 the FMRR module 104-1) via the shift register 202. In another embodiment, the tee stage 204 is communicatively coupled to the FMRR module via the shift register 202, where the shift register 202 includes multiple shift register stages.

[0091] The street can have fewer phases than the three phases shown in Figure 2 . The street can have more phases than the three phases shown in Figure 2 . In some embodiments, the street has four phases.

[0092] A portion 200 of a superconducting processor includes qubit readout devices 210-1 and 210-2. The qubit readout devices 210-1 and 210-2 are members of a row of qubit readout devices. The qubit readout devices in this row of qubit readout devices that include the qubit readout devices 210-1 and 210-2 are collectively referred to as qubit readout devices 210 in the present application. Each qubit readout of the qubit readout devices 210 can include more than one stage. For clarity of illustration, Figure 2 only one stage of each qubit readout of the qubit readout devices 210 is shown in

[0093] A portion 200 of a superconducting processor includes qubit readout devices 212-1 and 212-2. The qubit readout devices 212-1 and 212-2 are members of a column of qubit readout devices, and the qubits in this column of qubit readout devices are collectively referred to as qubit readout devices 212 in the present application. A portion 200 of a superconducting processor includes a three-phase internal street 214 communicatively coupled to the qubit readout devices 212.

[0094] A portion 200 of a superconducting processor includes a DAC buffer stage 216. In some embodiments, the DAC buffer stage 216 shares a phase with a qubit readout stage (e.g., the qubit readout devices 212).

[0095] Part 200 of the superconducting processor includes shift-register-loadable DACs 218-1 and 218-2. The shift-register-loadable DACs 218-1 and 218-2 are members of a shift-register-loadable DAC grid. The shift-register-loadable DACs in the shift-register-loadable DAC grid are collectively referred to as shift-register-loadable DAC 218 in this application. In some embodiments, the DAC includes QFP-DAC.

[0096] Part 200 of the superconducting processor includes three internal lanes 206, 208, and 214, as follows: a) a horizontal internal lane 206, which is communicatively coupled to qubit readout device 210 for qubits aligned vertically; b) a vertical internal lane 214, which is communicatively coupled to qubit readout device 212 for qubits aligned horizontally; and c) a vertical internal lane 208, which is communicatively coupled to a shift-register-loadable DAC buffer stage 216. In this application, the term shift-register-loadable DAC buffer stage refers to a DAC buffer stage that can be loaded from a shift register. The shift-register-loadable DAC buffer stage 216 is communicatively coupled to the shift-register-loadable DAC 218.

[0097] In Figure 2 the example embodiment, the internal lanes 206, 208, and 214 are three-phase internal lanes, that is, there are three interleaved families of stages: A-B-C-A-B-C-A-B-C... In some embodiments, the stages belonging to one family (e.g., family A) are controlled by a first global annealing line, the stages belonging to another family (e.g., family B) are controlled by a second global annealing line, and the stages belonging to yet another family (e.g., family C) are controlled by a third global annealing line. In fact, in addition to the global annealing lines, there may be one or more global DC bias lines.

[0098] The purpose of the global annealing lines is to support two operations referred to as "suppression" and "latch" in this application. The suppression operation can set and hold the current in each shift register stage to zero (or approximately zero, i.e., below a defined threshold). The latch operation can anneal each shift register stage. In embodiments where the shift register stage is a bistable QFP, each QFP can have a normalized current of +1 or -1 at the end of the latch operation, depending on the value of the local bias experienced by each shift register stage. For example, to transmit data through the shift register, the suppression operation and the latch operation can be performed simultaneously.

[0099] In an example scenario, the system contains data in the A shift register stage, and each stage of family A has a flux state of +1 or -1. For example, family A can contain a data sequence represented as (+1, +1, -1):

[0100] A(+1)-B-C-A(+1)-B-C-A(-1)-B-C

[0101] If levels B and C are inhibited and their states are set to zero, the sequence is as follows:

[0102] A(+1)-B(0)-C(0)-A(+1)-B(0)-C(0)-A(-1)-B(0)-C(0)

[0103] If level B is annealed while level A is latched and level C is inhibited, the most significant signal in its environment may come from an adjacent level A. At the end of the annealing, level B contains the content opposite to that of the adjacent level A, as follows:

[0104] A(+1)-B(-1)-C(0)-A(+1)-B(-1)-C(0)-A(-1)-B(+1)-C(0)

[0105] By inhibiting level A, latching level B, and annealing level C, the state can be copied from B to C, as follows:

[0106] A(0)-B(-1)-C(+1)-A(0)-B(-1)-C(+1)-A(0)-B(+1)-C(-1)

[0107] At this point in the process, level C contains the original data sequence from level A, i.e., (+1, +1, -1).

[0108] As shown in the above example scenarios, by an appropriate sequence of inhibition and / or latching operations, data can be moved along the shift register in either direction.

[0109] In some embodiments, internal streets 206, 208, and 214 include more than three interleaved families of stages.

[0110] Other arrangements may be used. For example, some embodiments include one or more "cross" stages. A cross stage refers to a location in the configuration where the phase pattern can be interrupted.

[0111] For example, the cross stage can be "T-shaped". The T-shape can be used to bypass data around a corner, as follows:

[0112]

[0113] The shift registers (A, B, C) can operate simultaneously with the shift registers (P, Q, R). While always suppressing X, the shift registers A and P can be driven by the same first signal, B and Q can be driven by the same second signal, and C and R can be driven by the same third signal. In this way, data can be shifted from the upper part (A, B, C) shown in the above figure, turn around the corner via (P, Q, R) and reach the (A, B, C) on the right side.

[0114] Subsequently, while suppressing P, the shift registers (A, B, C) can operate simultaneously with (X, Y, Z), such that data can be shifted from the upper part (A, B, C) shown in the above figure to the lower part (A, B, C) via (X, Y, Z).

[0115] In both of the above cases, there are "controlled" data paths (i.e., the data paths along which data is shifted) and "uncontrolled" data paths (i.e., the data paths along which the contents of the shift registers are not controlled). If the shift registers in the uncontrolled data path are isolated from the controlled path by at least one suppressed stage (e.g., X in the first case and P in the second case), these shift registers can be ignored.

[0116] In Figure 2 In the illustrated example embodiment, there are 12 horizontal qubit readout devices, 12 vertical qubit readout devices, and a 12×12 DAC grid. In other embodiments, the processor can have a non-square DAC grid. In other embodiments, the grid size is different from the number of qubit readout devices. The example embodiment has 12 horizontal qubit readout devices, 12 vertical qubit readout devices, and a 28×14 DAC grid. In other embodiments, other suitable tile sizes are used. In the example embodiment, the DAC that the shift register can load has six stages.

[0117] In the present application, the variable m is used to represent the maximum value among the number of qubit readout devices, the width of the DAC grid, and the height of the DAC grid. In order to program a system (e.g., a system including Figure 1 part 100 of a superconducting processor or Figure 2 part 200 of a superconducting processor), the state can be first loaded into the vertical streets. In the case of a three-phase street, one-third of the data lines can be transferred to the buffer stage at a time.

[0118] Each loading operation can take m steps in magnitude, that is, each loading operation can take O(m) steps, where m is the maximum value among the total readout size, the DAC grid width, and the DAC grid height. The loading operation can be repeated O(m) times to load the DAC stages, and the time required to program the tile can be O(m2 ) Multiple tiles with the same control structure can be programmed in parallel, and thus the total programming time for these tiles can also be O(m 2 ).

[0119] In one embodiment, at least one subset of tiles has the same control structure. In some embodiments, the control structures can be operated in parallel. In this case, the subset of tiles has a programming time that is at least approximately the same as that of a single tile. Similarly, for reading out the processor, and due to the limited length of the shift register, reading out the processor may take time O(m). Reading out a single qubit may take time O(m). Since multiple qubits in a single tile can be read out in parallel, reading out multiple qubits in a single tile may take time O(m). Additionally, since qubits in multiple tiles can be read out in parallel, reading out multiple qubits in multiple tiles may also take time O(m).

[0120] In some embodiments, the shift register can be communicatively coupled between adjacent tiles in a processor grid to improve redundancy, e.g., to mitigate the risk of having inoperable devices.

[0121] Example Readout System

[0122] Figure 3 Shown is a readout system 300 for a superconducting circuit 302 according to at least one exemplary embodiment. In Figure 3 the illustrated embodiment, the superconducting circuit 302 includes one or more superconducting resonators. In one embodiment, the superconducting circuit 302 includes a superconducting quantum processor. In another embodiment, the superconducting circuit 302 includes a superconducting classical processor. In other embodiments, the superconducting circuit 302 includes superconducting devices.

[0123] The readout system 300 includes a digital board 304 and a microwave board 306. The digital board 304 includes a field programmable gate array (FPGA) 308, two digital-to-analog converters (DACs) 310a and 310b, and two analog-to-digital converters (ADCs) 312a and 312b. In some embodiments, the digital board 304 includes two FPGAs, one providing output to the DACs 310a and 310b and the other providing output to the ADCs 312a and 312b. In one embodiment, each of the DACs 310a and 310b can include a dual-channel 14-bit DAC operating at up to about 5.6 Gsps (giga samples per second). The ADCs 312a and 312b can be implemented using multi-channel devices, e.g., using four-channel 10-bit ADCs capable of operating at up to about 2.5 Gsps in dual-channel mode.

[0124] The readout system 300 advantageously enables independent addressing of both sidebands of a frequency multiplexed readout (FMR) spectrum. A complex received signal can be expressed as follows:

[0125] x(n) = I(n) + jQ(n)

[0126] where I(n) is the output of ADC 312a and Q(n) is the output of ADC 312b.

[0127] The FMR spectrum can be calculated as follows:

[0128]

[0129] where k ∈ 0, 1, 2, 3... N - 1. The second term in the argument of the sine function for the FMR spectrum in the above expression depends on τ and can be used to compensate for the phase imbalance between the two mixer channels. The phase imbalance may be caused by the analog characteristics of the mixers.

[0130] The digital board 304 further includes two loopback lines 314a and 314b, and a synchronization connection / clock connection 316a. The loopback line 314a communicatively couples the output of DAC 310a to the input of ADC 312a. The loopback line 314b communicatively couples the output of DAC 310b to the input of ADC 312b.

[0131] The microwave board 306 (also referred to as the microwave subsystem 306 in this application) further includes a loopback line 317.

[0132] The loopback lines 314a and 314b on the digital board 304 and the loopback line 317 on the microwave board 306 are optional and can be used to bypass other elements of the readout system 300.

[0133] The readout system 300 further includes two reconstruction filters 318a and 318b, and two anti-aliasing filters 320a and 320b. The reconstruction filters 318a and 318b are low-pass analog filters that can be used to generate band-limited analog signals from digital inputs. The anti-aliasing filters 320a and 320b are low-pass analog filters that can be used to band-limit the received signal so as to at least approximately satisfy the sampling theorem in the frequency band of interest.

[0134] The microwave board 306 includes a voltage controlled oscillator (VCO) / phase locked loop (PLL) 322 that provides a reference microwave signal, mixers 324 and 326, and a programmable attenuator 328. The microwave board 306 further includes amplifiers 330, 332, 334, and 336. The amplifiers 330, 332, 334, and 336 can be used to control the level of the signals received from the superconducting circuit 302. The microwave board 306 further includes a microwave switch 338 that can be controlled by a signal from the FPGA 308 on the digital board 304. In one embodiment, the mixers 324 and 326 are complex mixers.

[0135] The readout system 300 further includes amplifiers 340, attenuators 342 and 344, circulators 346 and 348, and DC blocks 350 and 352. The DC blocks 350 and 352 can serve as heat insulation regions on each of the input line and the output line to the superconducting circuit 302.

[0136] In one embodiment, the amplifiers 340 and attenuators 342 can operate at 4K. The attenuator 344 can operate at 0.6K. The circulators 346 and 348 and the DC blocks 350 and 352 can operate at 8mK.

[0137] In one exemplary embodiment, using 60 resonators and a bandwidth of 2.5 GHz, a data rate of approximately 600 Mbps can be achieved within a shift register stage operation time of 25 ns.

[0138] The PCT patent application number WO 2016US 31885 (published as international patent application publication WO 2016183213 A1) describes Figure 3 the operating method of the readout system 300.

[0139] The cryogenic subsystem ( Figure 3 not shown) can be used to cool the superconducting circuit 302 to a temperature as low as a few mK (millikelvin).

[0140] Frequency Multiplexing Readout (FMR) Technology for Superconducting Qubits

[0141] Figure 4 A hybrid computing system 400 including a digital computer 402 and a quantum computer 404 is shown, according to at least one exemplary embodiment. The hybrid computing system can incorporate the FMR technology as described above. The digital computer 402 is also referred to as a digital processor in this application.

[0142] The digital computer 402 includes a CPU 406, user interface elements 408, 410, 412, and 414, a disk 416, a controller 418, a bus 420, and a memory 422. The memory 422 includes a BIOS 424, an operating system 426, a server module 428, a computing module 430, a quantum processor module 432, a readout module 434, and other modules that can be used to operate the hybrid computing system 400.

[0143] The digital computer 402 will sometimes be referred to herein in the singular, but this is not intended to limit the application to a single digital computer. The system and method can also be practiced in a distributed computing environment where tasks or instruction sets are performed or executed by remote processing devices linked by a communication network. In a distributed computing environment, computer-readable instructions and / or processor-readable instructions (sometimes referred to as program modules), applications, and / or data can be stored in local and remote memory storage devices (e.g., non-transitory computer-readable media and / or processor-readable media).

[0144] The quantum computer 404 includes a quantum processor 436, a readout control system 438, a qubit control system 440, and a coupler control system 442. The quantum computer 404 can incorporate FMR technology including one or more superconducting resonators. The computing system 400 can include a readout system, such as Figure 3 the readout system 300.

[0145] Figure 5 is a flowchart of an exemplary method 500 for programming a hybrid computing system (e.g., Figure 4 the computing system 400). The method 500 includes acts 502 - 516, however, those skilled in the art will understand that in alternative embodiments, certain acts may be omitted and / or additional acts may be added. Those skilled in the art will also understand that the order of these acts is shown for exemplary purposes only and may be changed in alternative embodiments.

[0146] At 502, the method 500 begins. At 504, a processor-based system (e.g., a digital-processor-based system) programs a quantum processor (e.g., Figure 4 the quantum processor 436). Programming the quantum processor can include programming multiple tiles of the quantum processor in parallel. For example, as Figure 5As shown, programming a quantum processor can include performing the programming of a first tile at 506 and the programming of a second tile at 508 in parallel. The duration of programming the first tile can be at least approximately the same as the duration of programming the second tile. In this context, the term "approximately" means that the programming duration of the first tile is within 10% of the programming duration of the second tile. Programming the quantum processor can occur during the preparation of a computation (e.g., quantum annealing) to be performed by the quantum processor and / or during quantum processor calibration.

[0147] At 510, a processor-based system reads out qubits of the quantum processor, for example, via components of a quantum processor-based system. For example, the readout can occur after a computation (e.g., after quantum annealing) performed by the quantum processor and / or during quantum processor calibration. Reading out qubits of the quantum processor can include reading out multiple qubits in a single tile in parallel and / or reading out multiple qubits in multiple tiles in parallel. For example, as Figure 5 shown, reading out qubits can include performing the readout of qubits in a first tile at 512 and the readout of qubits in a second tile at 514 in parallel. At 516, method 500 ends.

[0148] The duration of reading out qubits in the first tile can be at least approximately the same as the duration of reading out qubits in the second tile. In this context, the term "approximately" means that the duration of reading out qubits in the first tile is within 10% of the duration of reading out qubits in the second tile.

[0149] The systems and methods described in this application can scalably integrate FMRR technology into the architecture of a quantum processor. In a conventional application of FMRR technology, FASTR detectors are typically located at the periphery of the quantum processor. The time required to move data from quantum devices (e.g., qubits) in the processor to the FASTR detectors at the periphery of the quantum processor can introduce an inherent readout latency. The latency can be proportional to the number of shift register stages between the quantum device and the FASTR detector. The quantum device with the maximum latency sets the lower bound of the overall readout time of the quantum processor. When FMRR technology is located at the periphery of the quantum processor, the size (e.g., width) of the quantum processor can establish the lower bound of the readout time of the quantum processor.

[0150] The techniques described in this application include more tightly integrating FASTR detectors with quantum devices (e.g., qubits) in the quantum processor compared to conventional configurations.

[0151] This technology includes a construction referred to as a tile (also referred to as a unit tile in this application). A tile can have a substantially fixed latency and a substantially fixed readout time. A tile grid can have the same total latency and the same total readout time as a single tile.

[0152] An advantage of this technology is that it provides a scalable readout system. In some embodiments, the readout system can scale without incurring a runtime cost that scales with the number of devices to be read out. In one embodiment, the scalability of the readout system is limited by the number of FASTR detectors that can be attached to a single microwave line and the number of microwave lines in the readout system.

[0153] The systems and methods described in this application integrate FASTR detectors with DACs that can load states from a shift register. Conventionally, programming a quantum processor can use a large number of analog lines to control a DAC grid. For example, see U.S. Patent Application No. 15 / 726,239 (also published as US 20180101786 A1). In practice, there may be a constraint on the number of available analog lines. In an example embodiment, 185 analog lines can be used to program the DACs in a quantum processor. Using fewer analog lines increases the programming time.

[0154] Scaling conventional technologies can be particularly complex (e.g., in the case where more analog lines must be added) or particularly slow (e.g., in the case where scaling increases the programming time).

[0155] Compared with conventional input / output technologies, the systems and methods described in this application can use a reduced number of analog lines to program and control a large processor. In an example embodiment, 10 to 30 analog lines can be used to program the DACs in a quantum processor. One embodiment includes a set of tiles, each tile including a corresponding set of shift registers that can be jointly controlled by a single set of analog lines. The programming time of a tile can be substantially fixed, and the programming time of the set of tiles can be substantially the same as the programming time of a single tile. The scalability of a system including a quantum processor can be determined at least in part by the number of FASTR detectors that can be attached to a single microwave line and the number of microwave lines in the system.

[0156] The various embodiments described above can be combined to provide further embodiments. To the extent that these embodiments are not inconsistent with the specific teachings and definitions herein, all U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned and / or listed in the application data sheet in this specification include, but are not limited to, the following: PCT Patent Application No. PCT / US2019 / 18792, filed on February 20, 2018, entitled "SYSTEMS AND METHODS FOR COUPLING A SUPERCONDUCTING TRANSMISSION LINE TO AN ARRAY OF RESONATORS"; PCT Patent Application No. PCT / US2016 / 031885, filed on May 11, 2016, entitled "FREQUENCY MULTIPLEXED RESONATOR INPUT AND / OR OUTPUT FOR A SUPERCONDUCTING DEVICE" (published as International Patent Application Publication WO 2016183213 A1); U.S. Patent No. 8,854,074, entitled "SYSTEMS AND METHODS FOR SUPERCONDUCTING FLUX QUBIT READOUT", issued on October 7, 2014; U.S. Patent No. 8,169,231, entitled "SYSTEMS, METHODS, AND APPARATUS FOR QUBIT STATE READOUT", issued on May 1, 2012; all entitled "QUANTUM FLUX PARAMETRON BASED STRUCTURES (E.G.U.S. Patent Application No. 15 / 726,239, filed Oct. 5, 2017 (also published as US20180101786 A1) and International PCT Application Publication No. WO 2019 / 070935A2, filed Oct. 4, 2018; U.S. Provisional Patent Application Serial No. 62 / 851,377, filed May 22, 2019, entitled "SYSTEMS AND METHODS FOR EFFICIENT INPUT AND OUTPUT TO QUANTUM PROCESSORS"; and U.S. Provisional Patent Application Serial No. 62 / 860,098, filed Jun. 11, 2019, entitled "INPUT / OUTPUT SYSTEMS AND METHODS FOR SUPERCONDUCTING DEVICES", the entire disclosures of which are hereby incorporated by reference in their entirety. Aspects of the embodiments may be modified, if necessary, to employ the various patents, applications, and disclosed systems, circuits, and concepts to provide further embodiments.

[0157] In view of the foregoing detailed description, these and other changes may be made to the embodiments. Generally, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments and the entire scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A quantum processor, comprising: Multiple tiles, with multiple of such tiles arranged in a first grid, and each of the multiple tiles includes a shift register that includes multiple shift register stages communicatively coupled to frequency multiplexed resonant readout; one or more qubits of the multiple qubits of the quantum processor; one or more qubit readout devices, where one or more of the qubit readout devices are communicatively coupled to the shift register, and each of the one or more qubit readout devices is communicatively coupled to a corresponding one of the one or more qubits; multiple digital-to-analog converter buffer stages communicatively coupled to the shift register; and digital-to-analog converters loadable by multiple shift registers arranged in a second grid, where each digital-to-analog converter loadable by a shift register is communicatively coupled to one of the multiple digital-to-analog converter buffer stages; and multiple control structures, where each control structure is operable to control a corresponding one of the multiple tiles, and a subset of the multiple control structures share an analog line that is coupled in the same manner to at least one of the following: corresponding multiple shift register stages of the correspondingly coupled tiles and corresponding digital-to-analog converters loadable by the corresponding multiple shift registers, such that the subset of the multiple control structures is operable to perform parallel input / output operations in a subset of the multiple tiles including the correspondingly coupled tiles.

2. The quantum processor according to claim 1, wherein, The multiple qubits are superconducting qubits.

3. The quantum processor according to claim 2, wherein, The superconducting qubit is a superconducting flux qubit.

4. The quantum processor according to claim 1, further comprising a microwave transmission line communicatively coupled to the frequency multiplexed resonance readout.

5. The quantum processor according to claim 1, wherein, The frequency multiplexed resonant readout includes a superconducting resonator.

6. The quantum processor according to claim 1, wherein, The first grid and the second grid interleave each other on a superconducting integrated circuit.

7. The quantum processor according to claim 1, wherein, The frequency multiplexed resonant readout and the multiple digital-to-analog converters loadable by the shift registers are located on the same superconducting integrated circuit.

8. The quantum processor according to claim 1, further comprising: A transmission line that includes at least one transmission line inductor; A superconducting resonator; And A coupling capacitor that communicatively couples the superconducting resonator to the transmission line.

9. The quantum processor according to claim 1, wherein, The frequency multiplexed resonant readout is communicatively coupled to at least one other element of the quantum processor through a superconducting via.

10. The quantum processor according to claim 1, wherein, The frequency multiplexed resonant readout is communicatively coupled to at least one other element of the quantum processor through at least one of a bump bond or a wire bond.

11. A hybrid computing system, comprising the quantum processor according to any one of claims 1 to 10, and further comprising: At least one digital processor; And At least one non-transitory processor-readable medium communicatively coupled to the at least one digital processor, where the at least one non-transitory processor-readable medium stores at least one of processor-executable instructions or data, and the instructions or data, when executed by the at least one digital processor, cause the at least one digital processor to program the quantum processor.

12. The hybrid computing system according to claim 11, wherein, To cause the at least one digital processor to program the quantum processor, at least one of the processor-executable instructions or data, when executed by the at least one digital processor, causes the at least one digital processor to program a first one of the multiple tiles.

13. The hybrid computing system according to claim 12, wherein, To enable at least one of the digital processors to program a first tile among a plurality of the tiles, at least one of the executable instructions or data, when executed by at least one of the digital processors, causes at least one of the digital processors to program at least one of the digital-to-analog converters loadable by a plurality of the shift registers.

14. The hybrid computing system according to claim 12, wherein, To enable at least one of the digital processors to program the quantum processor, at least one of the executable instructions or data, when executed by at least one of the digital processors, further causes at least one of the digital processors to program a second tile among a plurality of the tiles.

15. The hybrid computing system according to claim 14, wherein, To enable at least one of the digital processors to program a second tile among a plurality of the tiles, at least one of the executable instructions or data, when executed by at least one of the digital processors, causes at least one of the digital processors to program the first tile and the second tile among a plurality of the tiles in parallel.

16. The hybrid computing system according to claim 14 or 15, wherein, To enable at least one of the digital processors to program the first tile and the second tile among a plurality of the tiles in parallel, at least one of the executable instructions or data, when executed by at least one of the digital processors, causes a first time required to program the first tile to be the same as a second time required to program a second tile among a plurality of the tiles.

17. The hybrid computing system according to claim 11, wherein, At least one of the executable instructions or data, when executed by at least one of the digital processors, further causes the hybrid computing system to read out a first qubit of a first tile among a plurality of the tiles and a second qubit of the first tile among a plurality of the tiles in parallel.

18. The hybrid computing system according to any one of claims 12 and 16, wherein, At least one of the executable instructions or data, when executed by at least one of the digital processors, further causes the hybrid computing system to read out a first qubit of a first tile among a plurality of the tiles and a third qubit of a second tile among a plurality of the tiles in parallel.

19. The hybrid computing system according to claim 11, wherein, At least one of the executable instructions or data, when executed by at least one of the digital processors, further causes the hybrid computing system to read out a first qubit of a first tile among a plurality of the tiles and a second qubit of a second tile among a plurality of the tiles, and wherein a first time required to read out the first qubit of the first tile among a plurality of the tiles is the same as a second time required to read out the second qubit of the second tile among a plurality of the tiles.

20. The hybrid computing system according to any one of claims 11 to 15, 17, and 19, wherein, At least one of the executable instructions or data, when executed by at least one of the digital processors, further causes at least one of the digital processors to calibrate at least a first part and a second part of the quantum processor in parallel operation, the first part of the quantum processor being non-local with respect to the second part of the quantum processor.

21. A method for programming a hybrid computing system, the hybrid computing system including a quantum processor and a digital processor, the quantum processor including a plurality of tiles, the plurality of tiles being arranged in a first grid, and each tile of the plurality of tiles including: A shift register, the shift register including a plurality of shift register stages communicatively coupled to frequency multiplexed resonant readout; one or more qubits of a plurality of qubits of the quantum processor; one or more qubit readout devices, each of the one or more qubit readout devices communicatively coupled to the shift register, wherein each of the one or more qubit readout devices is communicatively coupled to a corresponding one of the one or more qubits; a plurality of digital-to-analog converter buffer stages communicatively coupled to the shift register; and a plurality of shift-register-loadable digital-to-analog converters arranged in a second grid, wherein each of the plurality of shift-register-loadable digital-to-analog converters is communicatively coupled to one of the plurality of digital-to-analog converter buffer stages; the quantum processor further includes a plurality of control structures, wherein each control structure is operable to control a corresponding tile of the plurality of tiles, and a subset of the plurality of control structures share an analog line, the analog line being coupled in the same manner to at least one of the following: corresponding coupled respective plurality of shift register stages of the tile and the corresponding plurality of shift-register-loadable digital-to-analog converters, such that the subset of the plurality of control structures is operable to perform parallel input / output operations in a subset of the plurality of tiles including the correspondingly coupled tile, the method includes: Programming the quantum processor by the digital processor, and Reading out the quantum processor by the digital processor.

22. The method according to claim 21, wherein, Programming the quantum processor by the digital processor includes programming a first tile of the plurality of tiles.

23. The method according to claim 22, wherein, Programming the first tile of the plurality of tiles includes programming at least one of the plurality of shift-register-loadable digital-to-analog converters.

24. The method according to claim 22, wherein, Programming the quantum processor by the digital processor further includes programming a second tile of the plurality of tiles.

25. The method according to claim 24, wherein, Programming the first tile and the second tile of the plurality of tiles includes programming the first tile and the second tile of the plurality of tiles in parallel.

26. The method according to claim 24 or 25, wherein, Programming the first tile of the plurality of tiles is maintained for a first duration, and programming the second tile of the plurality of tiles is maintained for a second duration, the first duration being the same as the second duration.

27. The method according to claim 21, wherein, Reading out the quantum processor by the digital processor includes reading out a first qubit of the first tile of the plurality of tiles and a second qubit of the first tile of the plurality of tiles in parallel.

28. The method according to claim 26, wherein, Reading out the quantum processor by the digital processor includes reading out a first qubit of the first tile of the plurality of tiles and a third qubit of the second tile of the plurality of tiles in parallel.

29. The method according to claim 21, wherein, Reading out the quantum processor by the digital processor includes reading out a first qubit of the first tile of the plurality of tiles and reading out a second qubit of the second tile of the plurality of tiles, wherein a first time required to read out the first qubit of the first tile of the plurality of tiles is the same as a second time required to read out the second qubit of the second tile of the plurality of tiles.

30. The method according to any one of claims 21 to 25, 27, and 29, further including calibrating at least a first portion of the quantum processor and a second portion of the quantum processor in parallel operation, the first portion of the quantum processor being non-local with respect to the second portion of the quantum processor.

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