Method and device for running task based on multi-core CPU

Abstract

The application discloses a kind of FreeRTOS running task method and device based on multi-core CPU, it is related to embedded real-time operating system technical field, so that FreeRTOS real-time operating system supports the multitasking operation of multi-core CPU.The main technical scheme of the application is: if target core preempts spin lock to access global task ready list, first task can be determined according to the priority of task in global task ready list and the task in the core task ready list of itself, global task ready list stores the task not bound with core, each core has the core task ready list corresponding to itself and stores the task bound with core;Target core runs first task and releases spin lock;While target core runs first task, if other core preempts spin lock to access global task ready list, second task can also be determined according to the priority of task in global task ready list and the task in the core task ready list of itself, and runs second task.

Description

Technical Field

[0001] This invention relates to the field of embedded real-time operating system technology, and in particular to a method and apparatus for running FreeRTOS based on a multi-core CPU. Background Technology

[0002] The open-source embedded real-time operating system (Free Real-Time Operating System, FreeRTOS) is a lightweight operating system with features including task management, time management, semaphores, message queues, memory management, logging, software timers, and coroutines. Using FreeRTOS can make more reasonable and effective use of CPU resources, simplify application software design, shorten system development time, and better ensure the real-time performance and reliability of the system.

[0003] Currently, FreeRTOS supports CPUs with various architectures, including the RISC-V architecture. RISC-V (pronounced "risk-five") is a completely new instruction set architecture, originally invented in 2010 by Professor Krste Asanovic, Andrew Waterman, and Yunsup Lee of the Computer Science Department at the EECS division of the University of California, Berkeley. "RISC" stands for Reduced Instruction Set Computing, and "V" indicates that Berkeley has designed the fifth-generation instruction set since RISC-V.

[0004] However, the existing FreeRTOS real-time operating system can only run on a single-core CPU and does not support multi-core CPUs. For example, it cannot support the simultaneous execution of multiple tasks, which means that the CPU performance cannot be fully utilized on multi-core CPUs. Summary of the Invention

[0005] In view of this, the present invention provides a method and apparatus for running FreeRTOS tasks based on a multi-core CPU. The main purpose is to support the simultaneous running of multiple tasks when the FreeRTOS real-time operating system is running on a multi-core CPU, thereby ensuring that the multi-core CPU can fully utilize its performance.

[0006] To achieve the above objectives, the present invention mainly provides the following technical solutions:

[0007] The first aspect of this application provides a method for running tasks on FreeRTOS based on a multi-core CPU, the method comprising:

[0008] Initialize and configure a multi-core CPU, wherein the multi-core includes a target core and at least one other core;

[0009] If the target core preempts the spinlock to access the global task ready table, the target core determines the first task based on the priority of tasks in the global task ready table and its own core task ready table. The global task ready table stores tasks not bound to the core. Each core has its own corresponding core task ready table, which is used to store tasks bound to the core.

[0010] The target core executes the first task and releases the spinlock;

[0011] While the target core is running the first task, if another core preempts the spinlock to access the global task ready table, the other core determines the second task based on the priority of tasks in the global task ready table and its own core task ready table, and runs the second task.

[0012] In some modified embodiments of the first aspect of this application

[0013] The target core determines the first task based on the priority of tasks in the global task readiness table and its own core task readiness table, including: the target core

[0014] By comparing the tasks in the global task ready list with the tasks in its own kernel task ready list, the task with the highest execution priority is determined as the first task.

[0015] The other cores determine the second task based on the priority of tasks in the global task readiness table and their own core task readiness table, including: the other cores

[0016] By comparing tasks in the global task ready list with tasks in its own kernel task ready list, the task with the highest execution priority is determined as the second task.

[0017] In some modified embodiments of the first aspect of this application, the step of comparing tasks in the global task ready table with tasks in its own kernel task ready table includes:

[0018] Obtain the first priority identifier corresponding to the highest priority task in the global task ready table;

[0019] The target core or the other core obtains the second priority identifier corresponding to the highest priority task in its own core task ready table;

[0020] The first priority identifier and the second priority identifier are compared to obtain the higher priority identifier, wherein the task corresponding to the higher priority identifier is the task with the highest task execution priority.

[0021] In some modified embodiments of the first aspect of this application, when the target core runs the first task, the method further includes:

[0022] If the target core waits for a preset threshold for the duration of the trigger message corresponding to the first task, then the first task is added to the blocking list of the target core.

[0023] When the other cores detect the trigger message, the other cores release a semaphore to the target core, the semaphore being used to notify the target core to release the blocked signal;

[0024] If the first task is not bound to the target core, the target core, after acquiring the semaphore, will release the first task from the blocking list and return it to the global task ready list.

[0025] In some modified embodiments of the first aspect of this application, if the first task is bound to the target core, the method further includes:

[0026] After acquiring the semaphore, the target core releases the first task from the blocking list and adds it to the target core's kernel task ready list.

[0027] The other cores transmit the trigger message to the target core and trigger an inter-core interrupt instruction, which is used to notify the target core to perform a task switch.

[0028] According to the inter-core interrupt instruction, the target core obtains the first task from the core task ready table;

[0029] Based on the trigger message, the target core re-runs the first task.

[0030] In some modified embodiments of the first aspect of this application, the method further includes:

[0031] When the target core receives a timer interrupt instruction, the target core terminates the execution of the current task;

[0032] According to the timed interrupt instruction, the target core performs a task switching operation.

[0033] In some modified embodiments of the first aspect of this application, the step of the target core performing a task switching operation according to the timer interrupt instruction includes:

[0034] The target core obtains access to the global task ready table by preempting the spinlock;

[0035] The target kernel determines the third task with the highest current task execution priority by comparing the tasks in the global task ready table with the tasks in its own core task ready table.

[0036] The target core executes the third task and releases the spinlock.

[0037] A second aspect of this application provides a FreeRTOS running task device based on a multi-core CPU, the device comprising:

[0038] A configuration unit is used to initialize and configure a multi-core CPU, wherein the multi-core CPU includes a target core and at least one other core;

[0039] The determining unit is used to enable the target core to determine the first task based on the priority of tasks in the global task ready table and its own core task ready table when the target core preempts the spinlock to access the global task ready table. The global task ready table stores tasks not bound to the core, and each core has its own corresponding core task ready table to store tasks bound to the core.

[0040] The execution unit is used to enable the target core to run the first task and release the spinlock;

[0041] The determining unit is further configured to, while the target core is running the first task, when other cores preempt the spinlock to access the global task ready table, cause the other cores to determine the second task based on the priority of tasks in the global task ready table and their own core task ready table.

[0042] The operating unit is also used to enable the other cores to run the second task.

[0043] In some modified embodiments of the second aspect of this application, the determining unit includes: a comparison module and a determining module.

[0044] The comparison module is used to enable the target core to compare the tasks in the global task ready table with the tasks in its own core task ready table.

[0045] The determining module is used to determine the task with the highest task execution priority as the first task;

[0046] The comparison module is also used to enable the other cores to compare tasks in the global task ready table with tasks in their own core task ready table.

[0047] The determining module is also used to determine the task with the highest task execution priority as the second task.

[0048] In some modified embodiments of the second aspect of this application, the comparison module includes:

[0049] The acquisition submodule is used to obtain the first priority identifier corresponding to the highest priority task in the global task ready table;

[0050] The acquisition submodule is also used to enable the target core or the other core to obtain the second priority identifier corresponding to the highest priority task in its own core task ready table;

[0051] The comparison submodule is used to compare the first priority identifier and the second priority identifier;

[0052] The acquisition submodule is also used to acquire a higher priority identifier, wherein the task corresponding to the higher priority identifier is the task with the highest task execution priority.

[0053] In some modified embodiments of the second aspect of this application, the apparatus includes:

[0054] The adding unit is used to add the first task to the blocking list of the target core when the target core waits for the corresponding trigger message of the first task for a preset threshold while the first task is running on the target core.

[0055] A release unit is used to cause the other cores to release a semaphore to the target core when the other cores detect the trigger message. The semaphore is used to notify the target core to release the blocked signal.

[0056] The return unit is used to release the first task from the blocking list and return it to the global task ready table when the first task is not bound to the target core, after the target core acquires the semaphore.

[0057] In some modified embodiments of the second aspect of this application, the apparatus further includes:

[0058] The adding unit is further configured to, when the first task has a binding relationship with the target core, release the first task from the blocking list and add it to the core task ready table of the target core after the target core acquires the semaphore;

[0059] The transmission unit is used to enable the other cores to transmit the trigger message to the target core and trigger an inter-core interrupt instruction, wherein the inter-core interrupt instruction is used to notify the target core to perform a task switch.

[0060] The acquisition unit is configured to, according to the inter-core interrupt instruction, cause the target core to acquire the first task from the core task ready table;

[0061] The running unit is also configured to cause the target core to rerun the first task according to the trigger message.

[0062] In some modified embodiments of the second aspect of this application, the apparatus further includes:

[0063] The termination unit is used to terminate the current task of the target core when the target core receives a timer interrupt instruction.

[0064] The switching unit is used to cause the target core to perform a task switching operation according to the timer interrupt instruction.

[0065] In some modified embodiments of the second aspect of this application, the switching unit includes:

[0066] The acquisition module is used to enable the target core to acquire the permission to access the global task ready table by preempting the spinlock;

[0067] The determination module is used to enable the target core to determine the third task with the highest current task execution priority by comparing the tasks in the global task ready table with the tasks in its own core task ready table.

[0068] The execution module is used to enable the target core to run the third task and release the spinlock.

[0069] A third aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the FreeRTOS running task method based on a multi-core CPU as described above.

[0070] A fourth aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the FreeRTOS running task method based on a multi-core CPU as described above.

[0071] By employing the above-described technical solution, the technical solution provided by the present invention has at least the following advantages:

[0072] This invention provides a method and apparatus for running tasks in FreeRTOS based on a multi-core CPU. First, the multi-core CPU needs to be initialized and configured. Multiple cores acquire access to the global task ready table by preempting spinlocks. The core that acquires the spinlock can be called the target core, while the cores waiting for the spinlock to be released are called other cores. Thus, each core has the opportunity to acquire the spinlock and gain access to the global task ready table. Each core can then select a task based on the priority of tasks in the global task ready table and its own core's task ready table. Each core can then independently run the selected task. Only one core executes the operation when the spinlock is preempted. However, since the target core releases the spinlock after acquiring the selected task (i.e., runs the selected task and releases the spinlock), the spinlock time is not prolonged, and the task acquisition operations of other cores are not delayed. This allows multiple cores to run their respective tasks simultaneously and independently. Compared to existing technologies, this invention solves the problem that the existing FreeRTOS real-time operating system does not support multi-core CPUs. For FreeRTOS running on multi-core CPUs, this invention truly supports simultaneous multitasking, ensuring that multi-core CPUs can fully utilize their performance.

[0073] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0074] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0075] Figure 1 A flowchart of a FreeRTOS task execution method based on a multi-core CPU is provided for embodiments of the present invention.

[0076] Figure 2 Flowchart of another FreeRTOS task running method based on a multi-core CPU provided in this embodiment of the invention;

[0077] Figure 3 A block diagram of a FreeRTOS running task device based on a multi-core CPU provided in this embodiment of the invention;

[0078] Figure 4This is a block diagram of another FreeRTOS running task device based on a multi-core CPU, provided as an embodiment of the present invention. Detailed Implementation

[0079] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0080] This invention provides a method for running tasks on FreeRTOS based on a multi-core CPU, such as... Figure 1 As shown, this method enables multiple tasks to run simultaneously when the FreeRTOS real-time operating system is running on a multi-core CPU. The specific steps provided in this embodiment of the invention are as follows:

[0081] 101. Initialize the configuration of a multi-core CPU, which includes a target core and at least one other core.

[0082] In this embodiment of the invention, multiple CPU cores acquire the right to access the global task ready table by preempting spinlocks. The core that preempts the spinlock can be called the target core, while the cores waiting for the spinlock to be released are called other cores.

[0083] In this embodiment of the invention, a pre-written startup file can be used to initialize the CPU. This startup file can be pre-programmed into the chip. When the chip is running, this file will be run directly. The startup file is mainly for the initialization of the chip. In this embodiment of the invention, it is mainly for the initialization of the cores of the multi-core CPU, that is, to use the startup file to configure the multi-core CPU.

[0084] The process of initializing a multi-core CPU using the startup file mainly includes: initializing each core to allocate its own stack space. Specifically, the startup file will store at least one data table, which records how much stack space each core is allocated, so that the initialization operation of the core resource allocation can be completed according to the data table; in addition, some clocks need to be set, such as the CPU's operating frequency and the operating frequency of various peripherals (such as graphics cards), which is equivalent to the initialization of peripheral clocks.

[0085] In this embodiment of the invention, for a multi-core CPU, any one of the multiple cores can be designated as the first core, while the other cores are designated as second cores. The terms "first" and "second" are merely for convenience in distinguishing one core from others. The first core can then perform the aforementioned initialization operation, while the second core remains in a waiting state. Once the first core's initialization operation is complete, it sends a message to the second core, notifying it that the initialization operation has been completed. The second core can then directly copy the relevant configuration information from the first core to complete its own initialization configuration. Therefore, in this embodiment of the invention, only the startup file needs to be used to perform the initialization operation on any one core, significantly saving time and processing costs associated with initializing and configuring a multi-core CPU.

[0086] It should be noted that in this embodiment of the invention, the concepts of "first core" and "second core" are only introduced during the initialization phase of the multi-core CPU. After the initialization phase is completed, the working principle of each core in the multi-core CPU is the same.

[0087] 102. If the target core preempts the spinlock to access the global task ready table, the target core determines the first task based on the priority of tasks in the global task ready table and its own core task ready table.

[0088] The global task ready table stores at least two tasks to be run. Each task is designed based on actual task requirements; for example, a task might be "When key A is pressed, execute 'turn the light on / off'". Tasks stored in the global task ready table are not pre-bound to any specific core, and different priorities can be set for each task in the table so that tasks are retrieved by the core according to their priority. Additionally, each core has its own corresponding core task ready table, which stores tasks bound to the core. Each task in this table is designed using the same method as tasks in the global task ready table. Priorities can also be added to each task in the core task ready table so that tasks are retrieved by the core according to their priority.

[0089] In this embodiment of the invention, the global task ready table can be stored in memory. For example, for a 4GB or 8GB memory module, 1GB of space can be allocated to store the global task ready table. Each CPU core can then access this space to retrieve tasks to be run from the global task ready table. However, it should be noted that only one core is allowed to access the global task ready table to retrieve tasks at a time. This is where spinlocks come in. Spinlocks are locks specifically introduced to prevent multiprocessor concurrency and are widely used in kernels, such as in interrupt handling.

[0090] Specifically, in this embodiment of the invention, for multiple CPU cores, only by acquiring a spinlock can the task scheduler retrieve tasks from the global task ready table. There is only one spinlock, and other cores can only acquire it after one core releases it. Therefore, by utilizing spinlocks, the phenomenon of simultaneous task switching due to multiple cores running concurrently can be avoided, thus preventing kernel data corruption and system malfunctions, achieving the goal of protecting kernel data.

[0091] The task scheduler mentioned above is the scheduler running under the FreeRTOS real-time operating system. In this embodiment of the invention, there is only one task scheduler, but there are multiple interfaces. After the multi-core CPU initialization is completed in step 101, whichever CPU core starts first can create this task scheduler. Each core can connect to the task scheduler through the above-mentioned interface, enter the task scheduler, and use the task scheduler to obtain tasks, perform task switching, or control the running status of tasks, etc.

[0092] In this embodiment of the invention, if a target core preempts a spinlock, it gains access to the global task ready table and can also access its own core task ready table. Based on the priority of tasks in the global task ready table and its own core task ready table, the target core can select a task, which can be identified as the "first task". The terms "first task" and "second task" below are used to distinguish the different tasks obtained by different cores.

[0093] 103. The target core performs the first task and releases the spinlock.

[0094] In this embodiment of the invention, multiple CPU cores acquire access to the global task ready table by preempting spinlocks. The core that preempts the spinlock can be called the target core, while the cores waiting for the spinlock to be released are called other cores. After the target core acquires the first task, it runs the first task and simultaneously releases the spinlock, relinquishing its opportunity to acquire it. Thus, the target core's task execution does not affect the time other cores can acquire spinlocks or acquire other tasks.

[0095] 104. While the target core is running the first task, if other cores preempt the spinlock to access the global task ready table, the other cores determine the second task based on the priority of tasks in the global task ready table and their own core task ready table, and run the second task.

[0096] In this embodiment of the invention, while the target core is running the first task, it does not occupy the spinlock but releases it. Therefore, if another core preempts the spinlock, it will also gain access to the global task ready table. After gaining this access, other cores will select a task based on the priority of tasks in the global task ready table and their own core task ready table. This operation is the same as the target core's operation of comparing the two task ready tables to select a task. To distinguish this, the task selected by other cores is marked as the second task. After acquiring the second task, other cores will run the second task and release the spinlock, relinquishing their opportunity to acquire the spinlock.

[0097] In this embodiment of the invention, each core in a multi-core CPU has the opportunity to preempt a spinlock and access the global task ready table. Then, each core can select a task to run by comparing the global task ready table with its own core task ready table, thereby enabling multiple tasks to be deployed and run on multiple cores simultaneously, fully utilizing the CPU's performance.

[0098] The above embodiments of the present invention provide a FreeRTOS task running method based on a multi-core CPU. First, the multi-core CPU needs to be initialized and configured. Multiple cores acquire access to the global task ready table by preempting spinlocks. The core that acquires the spinlock can be called the target core, while the cores waiting for the spinlock to be released are called other cores. Thus, each core has the opportunity to preempt the spinlock and acquire access to the global task ready table. Each core can then select a task based on the priority of tasks in the global task ready table and its own core's task ready table. Each core can then independently run the selected task. Only one core performs this operation when the spinlock is preempted. However, since the target core releases the spinlock after acquiring the selected task (i.e., runs the selected task and releases the spinlock), the spinlock time is not prolonged, and the operation of other cores acquiring tasks is not delayed. This allows multiple cores to run their respective tasks simultaneously and independently. Compared to existing technologies, this invention solves the problem that the existing FreeRTOS real-time operating system does not support multi-core CPUs. For FreeRTOS running on multi-core CPUs, this invention truly supports the simultaneous operation of multiple tasks, ensuring that the multi-core CPU can fully utilize its performance.

[0099] To provide a more detailed explanation of the above embodiments, this invention also provides another method for running FreeRTOS tasks based on a multi-core CPU, such as... Figure 2 As shown, the following specific steps are provided in this embodiment of the invention:

[0100] 201. Initialize the configuration of a multi-core CPU, which includes a target core and at least one other core.

[0101] In this embodiment of the invention, the description of this step is the same as step 101, and will not be repeated here.

[0102] 202. If the target core preempts the spinlock to access the global task ready table, the target core determines the first task based on the priority of tasks in the global task ready table and its own core task ready table.

[0103] The global task ready table stores tasks not bound to a core, while each core has its own corresponding core task ready table, which stores tasks bound to the core.

[0104] In this embodiment of the invention, under FreeRTOS, whether a core is running an initial task or acquiring a new task due to task switching, each core selects the highest priority task by comparing the global task ready table with its own core task ready table. Specific implementation steps may include the following:

[0105] First, after the target core preempts the spinlock and gains access to the global task ready table, it retrieves the first priority identifier corresponding to the highest priority task in the global task ready table.

[0106] Secondly, the target core retrieves the second priority identifier corresponding to the highest priority task in its own kernel task ready table.

[0107] Finally, the first priority identifier and the second priority identifier are compared to obtain the higher priority identifier. The task corresponding to the higher priority identifier is the task with the highest task execution priority.

[0108] In this embodiment of the invention, task priority identifiers in different tables are compared to determine which task has the highest priority identifier in the two tables, instead of directly extracting tasks from the two tables for comparison. This avoids wasting processing resources by repeatedly extracting or returning tasks and improves the efficiency of identifying the task with the highest priority identifier.

[0109] 203. The target core performs the first task and releases the spinlock.

[0110] In this embodiment of the invention, it is necessary to further explain that the task is designed such that after the target core obtains the task, it will run the task on the target core, but the completion of the task requires a "message" trigger. For example, the task "Keyboard key A is pressed, execute 'turn the light on / off'".

[0111] After the target core receives this task, it will run the task, but it needs to wait for a trigger message (i.e., detect "key A is pressed"). Only if this trigger message is received can the task be executed (i.e., execute "turn the light on / off"). If the task running on the target core does not receive the corresponding trigger message and the waiting time reaches a preset threshold, the task will be added to the blocking list within the target core.

[0112] It should be noted that, in this embodiment of the invention, because multiple cores within the CPU have the right to preempt spinlocks to access the global task ready list, each core can obtain the highest priority task by comparing the global task ready list with its own core task ready list. Each core can then acquire and run the task. In other words, even if the previous task on the target core is added to the core's blocking list, the target core can still acquire tasks, and other cores can also acquire and run tasks. Both the target core and other cores are still active.

[0113] Therefore, if other cores detect the aforementioned trigger message (i.e., the trigger message required by the task on the target core), they release a semaphore to the target core. The semaphore is used to notify the target core to release the blocked signal. When the target core receives the semaphore, it will release the task previously placed in the core's blocking list. However, subsequent operations may involve the following two scenarios:

[0114] In one scenario, if the released task is not bound to the target core, the target core, after acquiring the semaphore, will release the task from the blocking list and return it to the global task ready list. In this case, the task cannot be run immediately. It must wait for a core to acquire access to the global task ready list, compare the global task ready list with its own core's task ready list, and select the highest priority task as the target core. Only then can the target core retrieve the task from the global task ready list and place it into that core. Furthermore, when that core runs the task, it must wait for the corresponding trigger message.

[0115] In another scenario, if the released task is bound to the target core, the target core, after acquiring the semaphore, releases the task from the blocking list and adds it to its own kernel task ready list. Other cores then send a trigger message to the target core and trigger an inter-core interrupt instruction. This instruction notifies the target core to perform a task switch, essentially instructing it to suspend other currently running tasks. Instead, based on the interrupt instruction, the target core retrieves the previously released task from its kernel task ready list and, according to the trigger message, re-runs it.

[0116] 204. While the target core is running the first task, if other cores preempt the spinlock to access the global task ready table, the other cores determine the second task based on the priority of tasks in the global task ready table and their own core task ready table, and run the second task.

[0117] In this embodiment of the invention, under FreeRTOS, whether a core is running an initial task or acquiring a new task due to task switching, each core selects the highest priority task by comparing the global task ready table with its own core task ready table. Accordingly, other cores also determine the task with the highest execution priority as the second task by comparing tasks in the global task ready table with tasks in their own core task ready table. The specific implementation steps are as follows:

[0118] First, retrieve the first priority identifier corresponding to the highest priority task in the global task ready table; second, the target core or other cores retrieve the second priority identifier corresponding to the highest priority task in their own core task ready table; finally, compare the first priority identifier and the second priority identifier to obtain the higher priority identifier, and the task corresponding to the higher priority identifier is the task with the highest task execution priority.

[0119] It should be noted that the specific implementation steps for other cores to acquire the second task are actually the same as those for the target core to acquire the first task. Therefore, the details of the corresponding steps will not be repeated here.

[0120] 205. When the target core receives a timer interrupt instruction, the target core terminates the execution of the current task.

[0121] In this embodiment of the invention, interrupt instruction types are divided into two categories: software interrupts and timed interrupts. Software interrupts refer to inter-core interrupt instructions, such as the aforementioned interrupt instruction where the target core receives an inter-core interrupt instruction and suspends other currently running tasks, instead retrieving a previously released blocked task from the core task ready table and running that task. However, timed interrupts correspond to periodic interrupt instructions set by FreeRTOS. Timed interrupts utilize interrupt control implemented with a timer; the timer interrupt is generated by a system tick and is used to periodically check for task switching and maintain system delay functionality.

[0122] 206. Based on the timer interrupt instruction, the target core performs a task switching operation.

[0123] In this embodiment of the invention, this step can be further refined to include: the target core acquires access to the global task ready table by preempting a spinlock; the target core compares the tasks in the global task ready table with the tasks in its own core task ready table to determine the third task with the highest current task execution priority; the target core runs the third task and releases the spinlock. This "third task" is conveniently used to distinguish it from the "first task" and "second task" mentioned above.

[0124] Below, using specific example scenarios, steps 205-206 will be explained, which may include the following:

[0125] For example, if a target core is running task A, it will continue running in a loop unless interrupted by other events. The purpose of a timed interrupt is to interrupt task A and switch to another task. Specifically, a timing device (such as a timer) can be set on the chip to trigger every 1 millisecond. For a target core running task A, when the timer triggers a timed interrupt, it will interrupt task A running on the target core. Regardless of whether task A has completed, another task to be run will be obtained from the global task ready table or the target core's kernel task ready table. Specifically, the standard for obtaining another task to be run is still: each core obtains the highest priority task by comparing the tasks in the global task ready table with the tasks in its own kernel task ready table.

[0126] For a further example, task A is "to perform a summation operation, accumulating consecutive natural numbers from 1 to 10000". When the target core is running task A, if it has already accumulated to 1000, and then receives a timer interrupt instruction, the target core will stop running task A regardless of whether task A has been completed. Instead, it will perform a task switching operation to acquire another task. Specifically, to acquire which task, it needs to reacquire the spinlock to obtain permission to access the global task ready table. It then compares the tasks in the global task ready table with the tasks in its own core task ready table to acquire the highest priority task, let's say task B. The target core will then acquire task B and run task B.

[0127] Furthermore, as a response to the above Figure 1 , Figure 2 The present invention provides a FreeRTOS running task device based on a multi-core CPU, as illustrated in the implementation of the method. This device embodiment corresponds to the aforementioned method embodiment. For ease of reading, this device embodiment will not repeat the details of the aforementioned method embodiment, but it should be understood that the device in this embodiment can implement all the contents of the aforementioned method embodiment. This device is used to enable the FreeRTOS real-time operating system to run on a multi-core CPU, specifically as follows... Figure 3 As shown, the device includes:

[0128] Configuration unit 301 is used to initialize and configure a multi-core CPU, wherein the multi-core includes a target core and at least one other core;

[0129] The determining unit 302 is used to determine the first task based on the priority of tasks in the global task ready table and its own core task ready table when the target core preempts the spin lock to access the global task ready table. The global task ready table stores tasks not bound to the core, and each core has its own corresponding core task ready table to store tasks bound to the core.

[0130] The operation unit 303 is used to enable the target core to run the first task and release the spinlock;

[0131] The determining unit 302 is further configured to, while the target core is running the first task, when other cores preempt the spinlock to access the global task ready table, cause the other cores to determine the second task based on the priority of the tasks in the global task ready table and their own core task ready table.

[0132] The operating unit 303 is also used to enable the other cores to run the second task.

[0133] Furthermore, such as Figure 4 As shown, the determining unit 302 includes: a comparison module 3021 and a determining module 3022.

[0134] The comparison module 3021 is used to enable the target core to compare the tasks in the global task ready table with the tasks in its own core task ready table.

[0135] The determining module 3022 is used to determine the task with the highest task execution priority as the first task;

[0136] The comparison module 3021 is also used to enable the other cores to compare the tasks in the global task ready table with the tasks in their own core task ready table.

[0137] The determining module 3022 is also used to determine the task with the highest task execution priority as the second task.

[0138] Furthermore, such as Figure 4 As shown, the comparison module 3021 includes:

[0139] The acquisition submodule 30211 is used to obtain the first priority identifier corresponding to the highest priority task in the global task ready table;

[0140] The acquisition submodule 30211 is also used to enable the target core or the other core to obtain the second priority identifier corresponding to the highest priority task in its own core task ready table;

[0141] The comparison submodule 30212 is used to compare the first priority identifier and the second priority identifier;

[0142] The acquisition submodule 30212 is also used to acquire a higher priority identifier, wherein the task corresponding to the higher priority identifier is the task with the highest task execution priority.

[0143] Furthermore, such as Figure 4 As shown, the device includes:

[0144] The adding unit 304 is used to add the first task to the blocking list of the target core when the target core waits for the corresponding trigger message of the first task for a preset threshold while the first task is running on the target core.

[0145] Release unit 305 is used to cause other cores to release a semaphore to the target core when the other cores detect the trigger message, the semaphore being used to notify the target core to release the blocked signal;

[0146] The return unit 306 is used to release the first task from the blocking list and return it to the global task ready table when the first task is not bound to the target core, after the target core acquires the semaphore.

[0147] Furthermore, such as Figure 4 As shown, the device further includes:

[0148] The adding unit 304 is also used to release the first task from the blocking list and add it to the core task ready table of the target core after the target core acquires the semaphore when the first task has a binding relationship with the target core.

[0149] The transmission unit 307 is used to enable the other cores to transmit the trigger message to the target core and trigger an inter-core interrupt instruction, wherein the inter-core interrupt instruction is used to notify the target core to perform a task switch.

[0150] The acquisition unit 308 is configured to, according to the inter-core interrupt instruction, cause the target core to acquire the first task from the core task ready table;

[0151] The running unit 303 is also configured to cause the target core to rerun the first task according to the trigger message.

[0152] Furthermore, such as Figure 4 As shown, the device further includes:

[0153] The termination unit 309 is used to terminate the current task of the target core when the target core receives a timer interrupt instruction;

[0154] The switching unit 310 is used to cause the target core to perform a task switching operation according to the timer interrupt instruction.

[0155] Furthermore, such as Figure 4 As shown, the switching unit 310 includes:

[0156] The acquisition module 3101 is used to enable the target core to acquire the permission to access the global task ready table by preempting the spinlock;

[0157] The determination module 3102 is used to enable the target core to determine the third task with the highest current task execution priority by comparing the tasks in the global task ready table with the tasks in its own core task ready table.

[0158] The execution module 3103 is used to enable the target core to run the third task and release the spinlock.

[0159] In summary, this invention provides a method and apparatus for running FreeRTOS tasks based on a multi-core CPU. First, the multi-core CPU needs to be initialized and configured. Multiple cores acquire access to the global task ready table by preempting spinlocks. The core that acquires the spinlock can be called the target core, while the cores waiting for the spinlock to be released are called other cores. Thus, each core has the opportunity to preempt the spinlock and acquire access to the global task ready table. Each core can then select a task based on the priority of tasks in the global task ready table and its own core's task ready table. Each core can then independently run the selected task. Only one core executes the operation when the spinlock is preempted. However, since the target core releases the spinlock after acquiring the selected task (i.e., runs the selected task and releases the spinlock), the spinlock time is not prolonged, and the task acquisition operations of other cores are not delayed. This allows multiple cores to run their respective tasks simultaneously and independently. Compared to existing technologies, this invention solves the problem that the existing FreeRTOS real-time operating system does not support multi-core CPUs. For FreeRTOS running on multi-core CPUs, this invention truly supports the simultaneous operation of multiple tasks, ensuring that the multi-core CPU can fully utilize its performance.

[0160] The FreeRTOS running task device based on a multi-core CPU includes a processor and a memory. The configuration unit, determination unit, and running unit mentioned above are all stored as program units in the memory. The processor executes the program units stored in the memory to realize the corresponding functions.

[0161] The processor contains a kernel, which retrieves the corresponding program units from memory. One or more kernels can be configured, and by adjusting kernel parameters, the FreeRTOS real-time operating system can run on a multi-core CPU, truly supporting simultaneous multitasking and ensuring that the multi-core CPU fully utilizes its performance.

[0162] This invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the FreeRTOS running task method based on a multi-core CPU as described above.

[0163] This invention provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the FreeRTOS running task method based on a multi-core CPU as described above.

[0164] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0165] In a typical configuration, the device includes one or more processors (CPUs), memory, and a bus. The device may also include input / output interfaces, network interfaces, etc.

[0166] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, like read-only memory (ROM) or flash RAM, and memory includes at least one memory chip. Memory is an example of computer-readable media.

[0167] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0168] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0169] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0170] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for running a FreeRTOS task based on a multi-core CPU, characterized in that, The method comprises: initializing a multi-core CPU, the multi-core comprising a target core and at least one other core, the target core being a core that preempts a spin lock to access a global task ready list, the spin lock being used to acquire the right to access the global task ready list by preemption of the spin lock; if the target core preempts the spin lock to access the global task ready list, the target core determines a first task according to the priority of the tasks in the global task ready list and the priority of the tasks in the core task ready list of the target core, the global task ready list storing tasks that are not bound to a core, each core having a corresponding core task ready list for storing tasks bound to the core; wherein the target core determines the first task according to the priority of the tasks in the global task ready list and the priority of the tasks in the core task ready list of the target core, comprising: the target core comparing the tasks in the global task ready list with the tasks in the core task ready list of the target core to determine the task with the highest running priority as the first task; the target core running the first task and releasing the spin lock; while the target core is running the first task, if the other core preempts the spin lock to access the global task ready list, the other core determines a second task according to the priority of the tasks in the global task ready list and the priority of the tasks in the core task ready list of the other core, and runs the second task; wherein the other core determines the second task according to the priority of the tasks in the global task ready list and the priority of the tasks in the core task ready list of the other core, comprising: the other core comparing the tasks in the global task ready list with the tasks in the core task ready list of the other core to determine the task with the highest running priority as the second task; wherein the comparing the tasks in the global task ready list with the tasks in the core task ready list comprises: obtaining, from the global task ready list, a first priority identifier corresponding to the task with the highest priority in the table; obtaining, by the target core or the other core, a second priority identifier corresponding to the task with the highest priority in the table from the core task ready list of the target core or the other core; comparing the first priority identifier and the second priority identifier to obtain the higher priority identifier, wherein the task corresponding to the higher priority identifier is the task with the highest running priority.

2. The method of claim 1, wherein, while the target core is running the first task, the method further comprises: if the target core waits for a trigger message corresponding to the first task for a duration reaching a preset threshold, adding the first task to a blocking list of the target core; when the other core monitors the trigger message, the other core releases a semaphore to the target core, the semaphore being used to notify the target core to release the blocked signal; if the first task has no binding relationship with the target core, after the target core obtains the semaphore, the target core releases the first task from the blocking list and returns the first task to the global task ready list.

3. The method of claim 2, wherein, if the first task has a binding relationship with the target core, the method further comprises: after the target core obtains the semaphore, the target core releases the first task from the blocking list and adds the first task to the core task ready list of the target core. The other core delivers the trigger message to the target core and triggers an inter-core interrupt instruction, which is used to inform the target core to perform a task switch; According to the inter-core interrupt instruction, the target core acquires the first task from the core task ready list; According to the trigger message, the target core re-runs the first task.

4. The method of claim 1, wherein, The method further comprises: When the target core receives a timing interrupt instruction, the target core terminates running a current task; According to the timing interrupt instruction, the target core performs a task switch operation.

5. The method of claim 4, wherein, According to the timing interrupt instruction, the target core performs a task switch operation, which comprises: The target core acquires the right to access the global task ready list by pre-empting the spin lock; The target core determines a third task with the highest task running priority by comparing tasks in the global task ready list with tasks in the core task ready list of the target core; The target core runs the third task and releases the spin lock.

6. A device for running a FreeRTOS task based on a multi-core CPU, characterized in that, The apparatus comprises: A configuration unit configured to initialize a multi-core CPU, the multi-core CPU comprising a target core and at least one other core, the target core being a core that pre-empts a spin lock to acquire the right to access a global task ready list; A determination unit configured to, when the target core pre-empts the spin lock to access the global task ready list, cause the target core to determine a first task according to priorities of tasks in the global task ready list and in a core task ready list of the target core, the global task ready list storing tasks that are not bound to cores, each core having a corresponding core task ready list storing tasks bound to the core; A running unit configured to cause the target core to run the first task and release the spin lock; The determination unit is further configured to, while the target core runs the first task, when the other core pre-empts the spin lock to access the global task ready list, cause the other core to determine a second task according to priorities of tasks in the global task ready list and in a core task ready list of the other core. The determination unit comprises a comparison module and a determination module; The comparison module is configured to cause the target core to compare tasks in the global task ready list with tasks in the core task ready list of the target core; and the determination module is configured to determine the first task as a task with the highest task running priority. The comparison module is further configured to cause the other core to compare tasks in the global task ready list with tasks in the core task ready list of the other core; and the determination module is further configured to determine the second task as a task with the highest task running priority. The comparison module comprises: an acquisition submodule, configured to acquire a first priority identifier corresponding to a highest-priority task in the global task ready list; the acquisition submodule is also configured to cause the target core or the other core to acquire a second priority identifier corresponding to a highest-priority task in a core task ready list of the target core or the other core; a comparison submodule, configured to compare the first priority identifier and the second priority identifier; the acquisition submodule is also configured to acquire a higher priority identifier, wherein the task corresponding to the higher priority identifier is a task with the highest task running priority; The running unit is also configured to cause the other core to run the second task.

7. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the multi-core CPU-based FreeRTOS running task method in any one of claims 1-5.

8. An electronic device, comprising: Comprise: a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor implements the multi-core CPU-based FreeRTOS running task method in any one of claims 1-5 when executing the computer program.

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