Methods and apparatus for wear equalization

Abstract

This invention relates to methods and apparatus for wear leveling. Various embodiments of this disclosure relate to a method of operating non-volatile memory, the method comprising having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and the second set of non-volatile memory cells are associated with host addresses. A voltage level for erasing the first and second sets of non-volatile memory cells is determined. The first and second sets of non-volatile memory cells are de-associated with host addresses. Furthermore, the first set of non-volatile memory cells is associated with another address based on the voltage level of the effectively erased non-volatile memory cells.

Description

Technical Field

[0001] The present invention relates to a method and apparatus for wear leveling in non-volatile memory. Background Technology

[0002] Wear leveling for non-volatile memory devices can consume more memory resources than expected. Wear leveling methods use cycle counts to approximate wear. It may also require utilizing the voltage level used to perform erase operations to approximate wear. Summary of the Invention

[0003] According to an embodiment of the present invention, a method for operating a non-volatile memory includes: a non-volatile memory having a first set of non-volatile memory cells and a second set of non-volatile memory cells, the first set of non-volatile memory cells being associated with a first host address and the second set of non-volatile memory cells being associated with a second host address; determining a first voltage level for effectively erasing the first set of non-volatile memory cells; determining a second voltage level for effectively erasing the second set of non-volatile memory cells; deassociating the first set of non-volatile memory cells with the first host address; deassociating the second set of non-volatile memory cells with the second host address based on the first voltage level for effectively erasing the first set of non-volatile memory cells; and associating the first set of non-volatile memory cells with the second host address based on the first voltage level for effectively erasing the first set of non-volatile memory cells.

[0004] According to an embodiment of the present invention, a non-volatile memory device includes: a voltage level indicator configured to store a data value indicating a voltage level for performing an erase operation on a first set of non-volatile memory cells; and a controller communicating with the voltage level indicator and configured to update a lookup table based on the data value to associate the first set of non-volatile memory cells with host addresses.

[0005] According to an embodiment of the present invention, a method for wear leveling includes: having a plurality of memory locations, each memory location corresponding to a set of non-volatile memory cells in a plurality of sets of non-volatile memory cells; storing a data value in each of the plurality of memory locations, the data value indicating a voltage level for performing an erase operation on the set of non-volatile memory cells corresponding to the memory location where the data value is stored; and mapping a plurality of host addresses to a plurality of sets of non-volatile memory cells in a lookup table based on the data value in each of the plurality of memory locations. Attached Figure Description

[0006] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, wherein:

[0007] Figure 1A schematic cross-sectional view of a floating gate memory cell in a non-volatile flash memory device is shown.

[0008] Figure 2A A plot of the voltage applied to the memory cell during the erase operation is shown;

[0009] Figure 2B The diagram shows that the voltage required to perform the erase operation increases with the number of cycles.

[0010] Figure 3A A plot of the voltage pulses applied during the initial erase operation is shown;

[0011] Figure 3B A plot of the voltage pulses applied during subsequent erase operations is shown;

[0012] Figure 4A The figure illustrates the distribution of threshold voltages of multiple memory cells in a set of memory cells before and after a single pulse is applied to a memory cell to perform an erase operation using a known method.

[0013] Figure 4B The figure illustrates the distribution of threshold voltages of multiple memory cells in a memory cell set before and after a single pulse of a subsequent erase operation using a known method.

[0014] Figure 4C The illustration shows the distribution of threshold voltages of multiple memory cells in a memory cell set before and after the second pulse of a subsequent erase operation using a known method that requires a second voltage pulse.

[0015] Figure 5A , Figure 5B and Figure 5C The illustration shows a known method for allocating sets of non-volatile memory for wear leveling;

[0016] Figure 6A , Figure 6B and Figure 6C The diagram illustrates a method for allocating sets of non-volatile memory for wear leveling.

[0017] Figure 7 A schematic diagram of a non-volatile memory device is depicted.

[0018] Figure 8 An embodiment of a dedicated memory location is described;

[0019] Figure 9A It depicts the 16-bit data values ​​in the initial configuration;

[0020] Figure 9B It describes the 16-bit data value in the incremental configuration;

[0021] Figure 9C It describes the 16-bit data value in the incremental configuration;

[0022] Figure 10 A flowchart depicting a method for operating non-volatile memory is provided; and

[0023] Figure 11 A flowchart is depicted for a method used for wear equalization. Detailed Implementation

[0024] As more memory cycles are performed using non-volatile memory cells, individual non-volatile memory cells in a non-volatile memory device degrade over time. With more memory operations performed on the non-volatile memory cells, higher voltages are required to erase them. When a non-volatile memory device cannot apply sufficiently high voltage to erase one or more of its non-volatile memory cells, the non-volatile memory device may become inoperable. Uneven wear among the various non-volatile memory cells can cause a non-volatile memory device to stop operating, even if many of its non-volatile memory cells show little wear.

[0025] Non-volatile memory devices employ various wear-leveling techniques to redistribute non-volatile memory cells, thereby extending the device's lifespan. Known methods involve counting the number of cycles performed on a non-volatile memory cell. Cycle counting is used to approximate the wear on an individual non-volatile memory cell, and non-volatile memory cells are allocated for use based on the cycle count associated with each cell. However, counting the cycles performed on a non-volatile memory cell may require more memory than desired, as each cell may be used hundreds of thousands of times before wear. A more efficient and direct method can be used to approximate wear on memory cells: by utilizing the voltage level used for erase operations, thus avoiding reliance on cycle counting.

[0026] Figure 1 A schematic cross-sectional view of a floating gate memory cell in a non-volatile memory device is shown.

[0027] As is well known, and as Figure 1As schematically shown, a floating-gate type memory cell 1 of a non-volatile memory device (e.g., flash memory type) may include a body region 2 with p-type doping, which is provided in a substrate 3 of a semiconductor material such as silicon. The memory cell 1 may also include: a source region 4 and a drain region 5, for example having n-type doping, provided within a surface portion of the body region 2; a floating gate region 6 disposed above the body region 2 and separated from the body region 2 by a tunneling oxide region 7; and a control gate region 8 disposed above the floating gate region 6 and separated from it by an intermediate oxide (so-called "ONO") region 9.

[0028] In order to store information, charge can be injected from substrate 3 into floating gate region 6 (programming operation), thereby changing the threshold of memory cell 1, that is, a voltage is applied between control gate region 8 and source region 4 to turn on memory cell 1, and to achieve current conduction between source region 4 and drain region 5.

[0029] For sensing or reading operations, when an appropriate bias voltage is applied to the control gate region 8, the sensing circuit can detect the conduction characteristics of the memory cell 1 and obtain the stored information from it.

[0030] The erasure operation for erasing information is expected to remove the charge stored in the floating gate region 6 via electronic extraction. Specifically, this operation is expected to (e.g., Figure 1 As shown, a high electric field is applied between body region 2 (which can be brought to a positive high voltage (e.g., +10V)) and control gate region 8 (which can be brought to a negative high voltage (e.g., -10V)). In a known manner, the high electric field can trigger the Fowler-Nordheim (“FN”) tunneling effect, which causes the movement of electrons that migrate from floating gate region 6 through tunneling oxide region 7 (again, as shown). Figure 1 (as shown in the image).

[0031] In particular, in a known manner, an erase operation can be performed simultaneously on a set of memory cells 1, such as those belonging to the same block, sector, or page of a non-volatile memory device, and these cells are thus erased together in the same erase operation.

[0032] The erasure process can be effective when the applied electric field is strong enough to trigger the FN tunneling effect.

[0033] However, due to the natural process of degradation of memory cell 1 (e.g., due to charge trapping in tunnel oxide region 7), this value increases with the increase of so-called “cycles” (i.e., the number of programming cycles, erase cycles, or both experienced by memory cell 1).

[0034] To account for degradation, a method typically used to perform an erase operation on a set of memory cells (sectors or pages) involves iteratively applying a number of pulses with increasing voltage values ​​and fixed durations. Each pulse is followed by a verification operation to confirm whether the erase was successful. Once the verification operation determines that the erase has been performed correctly, the method is interrupted.

[0035] Figure 2A A plot of the voltage applied to the memory cell during the erase operation is shown.

[0036] This method is in Figure 2A The diagram in the middle is schematic. Figure 2A The plot of the body voltage Vpp is shown in incrementing pulses, where the control gate region 8 is negatively selected (i.e., set to a high negative voltage VCG, such as -10V). As previously mentioned, the potential difference between body region 2 and control gate region 8 can determine the electric field designed to trigger the FN tunneling effect.

[0037] The pulses of the body voltage Vpp can begin with a minimum value Vpp_min determined in the design or characterization circuitry of the non-volatile memory device, and gradually increase in equal increments until a maximum value Vpp_max, which can also be determined during the design or characterization of the memory device. Between consecutive pulses, the method can be expected to include verification steps to confirm whether the erase was successful via read or sensing operations.

[0038] If the verification does not produce a positive result, subsequent pulses are applied iteratively with incrementing values; otherwise, when the verification has been successful (i.e., when the verification has reached or exceeded the electric field value required to activate the FN tunneling effect), as if again... Figure 2A (As shown in the image), the process ends.

[0039] The envelopes of all applied pulses (represented by dashed lines) determine the slope of the erase operation, i.e., the temporal variation of the electric field applied to memory cell 1, and the rate at which the electric field reaches and / or surpasses the value required to activate the FN tunneling effect. A high slope can exert stress on memory cell 1 and accelerate memory cell degradation; this slope can affect the duration of the erase operation and the long-term performance of the memory cell.

[0040] As the number of programming / erasing cycles performed on memory cell 1 increases, the value of the electric field required to activate the FN tunneling effect also increases, and therefore the number of pulses required to effectively erase memory cell 1 also increases.

[0041] Figure 2B The diagram shows that the voltage required to perform the erase operation increases with the number of cycles.

[0042] like Figure 2BAs illustrated in the diagram, the number of pulses required for the erase operation increases with each cycle. For example, as... Figure 2B As shown, the number of pulses required can be increased from one or two pulses required to erase a memory cell in cycles of less than 10Kc or 50Kc to N-1 or N pulses (where N is equal to 10, for example) required to erase a memory cell in cycles of 450Kc or 500Kc.

[0043] A method for reducing the number of pulses includes: storing information associated with an operation configuration that allows a past memory operation to complete successfully, such as a voltage level applied to perform an erase operation or a parameter defining the voltage level applied to perform an erase operation, and using the information to restore the corresponding operation configuration as the starting point for subsequent memory operations.

[0044] Figure 3A A plot of the voltage pulses applied during the initial erase operation of a known method is shown.

[0045] Figure 3A The known method shown includes: increasing the value of the pulse until the actual pulse level of the body voltage Vpp reaches or exceeds a threshold used to trigger the FN tunneling effect, and recording information about the voltage level at which the FN tunneling effect was successfully triggered (which may include parameters defining the voltage level). This information is accessed at the start of a subsequent erase step, so the first pulse for the subsequent erase process can be equal to the last pulse from the previous erase operation, which was sufficient to trigger the FN tunneling effect in the previous cycle.

[0046] Consistent with this method, in Figure 3A In the example shown, three pulses are used to successfully perform the erase process. An erase verification performed between the first and second pulses does not indicate that a valid erase operation has been successfully performed. Therefore, an additional voltage pulse increasing the voltage level is executed. An erase verification performed after the third pulse determines that memory cell 1 of the desired set (e.g., page or sector) has been successfully erased, and the voltage level of this pulse triggers the FN tunneling effect for the erase operation. Information associated with the actual bias configuration (e.g., the actual level or digital representation of the body voltage Vpp) is then stored for subsequent erase steps. The bias configuration may also include data to be provided to the DAC, which provides... Figure 3A and Figure 3B The bias is depicted by a dashed horizontal line. The first voltage level may correspond to DAC_IN-00, the second voltage level may correspond to DAC_IN=01, and so on.

[0047] Figure 3B A plot of the voltage pulses applied during a subsequent erase operation in a known method is shown.

[0048] Subsequent erase operations can be performed on the same set of memory cells 1. Previously stored information about the previous bias configuration can be used to determine the bias configuration for the first step of the iterative process of the subsequent erase operation based on the retrieved information. Figure 3B In the example, the level of the first pulse of the body voltage Vpp can be the stored value (for which a previous erase operation was successful). If the first pulse is unsuccessful in a new erase operation, a second pulse can be applied to successfully perform the erase operation (its level will be stored by control circuit 14 for future memory operations).

[0049] Figure 4A The figure illustrates the distribution of threshold voltages of multiple memory cells in the memory cell set before and after a single pulse is applied to memory cell 1 using a known method to perform an erase operation.

[0050] Figure 4A Two curves are plotted to represent the distribution of threshold voltages for multiple memory cells 1. The first curve 402A represents the distribution of threshold voltages before a single pulse has been applied during the erase operation. The second curve 404A represents the distribution of threshold voltages after a single pulse has been applied during the erase operation. To determine whether the erase operation has been successfully performed, an erase verification test can be performed, in which the distribution of threshold voltages for the multiple memory cells 1 after the application of the single pulse is compared with an erase verification voltage 406.

[0051] The first curve 402A is greater than the erase verification voltage 406. A single voltage pulse of the erase operation shifts the distribution of the threshold voltage of memory cell 1 to the second curve 404B. The second curve 404A is less than the erase verification voltage 406, therefore the erase operation is successfully performed. A second pulse is not needed. Furthermore, the pulse configuration of the erase operation can be saved for subsequent erase operations. However, as more erase operations are performed, the distribution of the threshold voltage of memory cell 1 becomes less sensitive to voltage pulses at previously successful levels. The distribution of the threshold voltage of the memory cells shifts less and less. Eventually, the voltage level previously used to successfully execute the previous erase operation will not shift the distribution of the threshold voltage of memory cell 1 far enough to successfully execute the erase operation for subsequent erase operations. In this case, the voltage level must be increased, and a second pulse must be applied to complete the erase operation. Furthermore, the new voltage level can be stored for future erase operations.

[0052] Figure 4B The distribution of threshold voltages in a set of memory cells is shown before and after a single pulse of a subsequent erase operation using a known method.

[0053] The first curve 402B represents the distribution of the threshold voltage of memory cell 1 before the single voltage pulse of the subsequent erase operation. Again, before the erase operation, the first curve 402B is greater than the erase verification voltage. However, in the previous... Figure 4A The application of the voltage pulse at the level of the erase operation described in the diagram no longer shifts the distribution of the threshold voltage of memory cell 1 far enough to clear the erase verification voltage 406. The voltage pulse at the previous level now only shifts the distribution of the threshold voltage of memory cell 1 from the first curve 402B to the second curve 404B. Only a portion of the second curve 404B is smaller than the erase verification voltage 406. Therefore, the first voltage pulse fails to successfully perform the erase operation.

[0054] Figure 4C The figure illustrates the distribution of threshold voltages for multiple memory cells in the memory cell set before and after the second pulse of the subsequent erase operation.

[0055] A second voltage pulse at a higher level may be needed to complete the erasure operation. Figure 4C The distribution of the threshold voltage of memory cell 1 after the second pulse is illustrated using the third curve 408B. After the second pulse, the distribution of the threshold voltage of the memory cell has shifted from the second curve 404B to the third curve 408B, which is completely below the erase verification voltage 406. The voltage used for the second pulse (or a parameter defining the voltage level) can be stored so that future operations can begin with an initial pulse at the voltage level used to successfully complete the erase operation.

[0056] Known wear leveling techniques are used to increase the lifespan of non-volatile memory devices and compensate for the degradation experienced by memory cells during the lifetime of the memory device. Some known methods include, but are not limited to, dynamic wear leveling and static wear leveling. Known methods utilize tables to translate host addresses (such as logical block addresses) into physical addresses (such as physical block addresses) of sets of memory cells. This table is used as a mapping table and must be managed and maintained as the sets of memory cells corresponding to the physical block addresses are cycled.

[0057] Figure 5A , Figure 5B and Figure 5C The illustration shows a known method for allocating sets of non-volatile memory for wear leveling.

[0058] Figure 5AThe initial configuration of lookup table 502, which associates host addresses with physical addresses corresponding to sets of non-volatile memory cells, is depicted. The memory array 12 is divided into a first group of non-volatile memory cells 00, a second group of non-volatile memory cells 01, a third group of non-volatile memory cells 10, and a fourth group of non-volatile memory cells 11. The first column of lookup table 502 lists a first host address AA, a second host address AB, a third host address BA, and a fourth host address BB. The first host address AA is arranged side-by-side with the physical addresses used to associate the sets of non-volatile memory cells (in this case, the first group of non-volatile memory cells 00). The second host address AB, the third host address BA, and the fourth host address BB are arranged similarly with respect to the physical addresses corresponding to the second group of non-volatile memory cells 01, the third group of non-volatile memory cells 10, and the fourth group of non-volatile memory cells 11. The third column shows the counting cycle for each set of non-volatile memory cells.

[0059] Instructions received from the host device, identifying a first host address AA for performing memory operations, are compared with lookup table 502 to determine the physical address of the associated set of non-volatile memory cells (in this case, the first set of non-volatile memory cells 00), so that memory operations can be performed on the first set of non-volatile memory cells 00. Instructions identifying other host addresses for performing memory operations are also compared with lookup table 502 to determine where to perform the memory operation based on the association between the host address and the physical address defined by lookup table 502. The association between lookup table 502 and the physical set of non-volatile memory is also... Figure 5A , Figure 5B And as shown by the arrows pointing from the lookup table to the memory array 12 in Figure 5c. As the set of non-volatile memory cells is cycled, the corresponding cycle count is incremented to approximate the wear on the set of non-volatile memory cells.

[0060] Figure 5B This describes how lookup table 502 remains in its initial configuration if no reallocation occurs after multiple loops. Figure 5B In the example shown, the various sets of non-volatile memory cells are cycled unevenly. The third set of non-volatile memory cells 10 has been cycled 500,000 times, while the fourth set of non-volatile memory cells 11 has not been cycled at all. This uneven use can cause the third set of non-volatile memory cells 10 to stop operating, while the fourth set of non-volatile memory cells 11 is hardly used. To extend the lifespan of the non-volatile memory device, the sets of non-volatile memory cells can be redistributed.

[0061] Figure 5CLookup table 502 is depicted after the sets of non-volatile memory cells have been reassigned so that they are associated with different host addresses. The first set of non-volatile memory cells 00 is now associated with the second host address AB. The second set of non-volatile memory cells 01 is now associated with the first host address AA. An instruction identifying the first host address AA, received from the host device, will now be executed on the second set of non-volatile memory cells 01 for performing memory operations. An instruction identifying the third host address BA will now be executed on the fourth set of non-volatile memory cells 11.

[0062] However, the non-volatile memory set of a non-volatile memory device may need to cycle thousands of times. Furthermore, a single non-volatile memory device can have many sets of non-volatile memory cells. This may require the non-volatile memory device to retain more memory than is needed to maintain a count of all the non-volatile memory device sets.

[0063] This burden can be mitigated by tracking the voltage used to perform the erase operation instead of counting individual cycles. As discussed with reference to the foregoing figures of this disclosure, the voltage level required to induce FN tunneling in a memory cell increases as the memory cell is used. Eventually, the non-volatile memory device may fail when the voltage level required to induce FN tunneling becomes greater than the voltage that the non-volatile memory device can withstand. Compared to cycle counting, the voltage level required to perform an erase operation is more directly tied to wear on the memory cell, and therefore can replace cycle counting as a metric for reallocating sets of non-volatile memory cells in a lookup table. This also saves memory resources because it eliminates the need to increase the voltage level for each erase operation.

[0064] Figure 6A , Figure 6B and Figure 6C The diagram illustrates a method for allocating sets of non-volatile memory for wear leveling.

[0065] Figure 6A The initial configuration of lookup table 602, which associates host addresses with physical addresses corresponding to sets of non-volatile memory cells, is depicted. For example... Figure 5A , Figure 5B and Figure 5C Similar to lookup table 502, the first column of lookup table 602 lists the first host address AA, the second host address AB, the third host address BA, and the fourth host address BB. Host addresses can be associated with physical addresses in lookup table 602. Figure 6A , Figure 6B and Figure 6C In the first host address AA, the associated set of non-volatile memory cells (in Figure 6AIn the table, the physical addresses of the first group of non-volatile memory cells 01, 10, and 11 are arranged side-by-side. The second host address AB, the third host address BA, and the fourth host address BB are similarly arranged relative to the physical addresses corresponding to the second group of non-volatile memory cells 01, the third group of non-volatile memory cells 10, and the fourth group of non-volatile memory cells 11. It should be noted that lookup table 602 is presented for illustrative purposes and should not be considered as limiting the application of this disclosure by the size or organization of lookup table 602.

[0066] The third column displays the voltage level used for an erase operation on the set of non-volatile memory cells or for a future erase operation. The third column may or may not be part of lookup table 602. In various embodiments, the voltage level used for the erase operation may be stored elsewhere and retrieved when needed, thus the association between host addresses and physical addresses can be reallocated. In various embodiments, the voltage level corresponding to the set of non-volatile memory cells may be stored in a dedicated memory region for the corresponding set of non-volatile memory cells. Figure 6A In this context, the voltage level depicted for each set of non-volatile memory cells can represent the initial configuration. This can correspond to the voltage level applied at the beginning of the memory device's lifetime before memory cell degradation. Figure 6A In this context, the voltage level is represented by the number of bits "1111". Furthermore, an increase in the voltage level used to perform the erase operation can be indicated by switching a bit to "0". For example, the number of bits "1110" can represent a voltage level increased by one bit compared to the level applied at the beginning of the memory device's lifetime, and the number of bits "1000" can represent a voltage level that has been increased three times. Various embodiments may include more or fewer bits. More bits can allow for more voltage levels. And it should be understood that voltage levels can be represented in many other ways in various embodiments.

[0067] The instruction received from the host device, identifying the first host address AA for performing memory operations, can be compared with lookup table 602 to determine the physical address of the associated set of non-volatile memory cells. Figure 6A In the table 602, instructions identified by host address AA will direct memory operations to the first set of non-volatile memory cells 00. Instructions identifying other host addresses used to perform memory operations can also be compared with lookup table 602 to determine where to perform the memory operation based on the association between the host address and the physical address defined by lookup table 602. The association between lookup table 602 and the physical set of non-volatile memory is also... Figure 6A , Figure 6B and Figure 6C This is indicated by an arrow pointing from the lookup table to memory array 12.

[0068] As the set of non-volatile memory cells is cycled, the voltage level used to perform an erase operation on the set of non-volatile memory devices will increase. Information about the voltage level used to perform the non-volatile erase operation can be stored, for example, in a dedicated memory area corresponding to the set of non-volatile memory, or it can be sensed so that lookup table 602 can be rearranged for wear leveling purposes.

[0069] Figure 6B A lookup table 602 is depicted after several cycles, and the voltage level used to perform the erase operation has been increased for some sets of non-volatile memory cells, but there has been no reallocation of host address and physical address associations. The voltage level for the third set of non-volatile memory cells 10 is now represented by "1000", while the voltage level for the fourth set of non-volatile memory cells 11 remains at the initial level "1111", and the voltage levels for the remaining sets have been changed as depicted. The sets of non-volatile memory cells can be reallocated to allow for more even wear.

[0070] Figure 6C A lookup table 602 is depicted, associating non-volatile memory cells with different host addresses after the set of non-volatile memory cells has been reallocated. The first set of non-volatile memory cells 00 is now associated with the second host address AB. The second set of non-volatile memory cells 01 is now associated with the first host address AA. An instruction receiving from the host device, identifying the first host address AA, will now be executed on the second set of non-volatile memory cells 01 for performing memory operations. An instruction identifying the third host address BA will now be executed on the fourth set of non-volatile memory cells 11. The remaining associations have been reallocated as indicated to allow for uniform wear of the non-volatile memory cell set.

[0071] The allocation and reallocation of memory cell sets in lookup table 602 may or may not be performed on all memory cell sets simultaneously. In various embodiments, the reallocation of non-volatile memory cell sets (or their corresponding physical block addresses) to host addresses can be implemented in multiple ways. In various embodiments, allocation can be performed as needed. Once a set of memory cells associated with a host address has cycled excessively relative to other memory sets, a different memory set with less wear (e.g., using erase voltage as an indicator) can be associated with a host address in lookup table 602. The contents of the first set of memory cells can also be transferred to a replacement set of memory cells to maintain the memory state. Various embodiments can utilize different reallocation schemes to achieve uniform wear (e.g., using erase voltage as an indicator), including but not limited to swapping host addresses associated with the most and least worn memory sets. In various embodiments, the association can be updated periodically, triggered by changes in voltage levels, or updated due to continuous monitoring.

[0072] Figure 7 Schematic diagrams of memory device 13 in various embodiments are depicted.

[0073] In various embodiments, memory device 13 may include a non-volatile memory device, such as flash memory or page flash memory. Memory device 13 may include memory array 12. Memory array 12 may include a first group of non-volatile memory cells 00, a second group of non-volatile memory cells 01, a third group of non-volatile memory cells 10, and a fourth group of non-volatile memory cells 11. It should be understood that the number of sets of non-volatile memory cells may vary in various embodiments. The memory cells in the sets of non-volatile memory cells may include floating-gate type memory cells (e.g., as referenced). Figure 1 (As described). Memory cells 1 can be arranged by rows (word lines) and columns (bit lines) and operably combined together in sets (e.g., sectors, blocks, or pages). In various embodiments, the set of non-volatile memory cells may include different numbers of memory cells 1. In various embodiments, each memory cell 1 in the set of memory cells may include a floating gate type. Memory cells 1 can be configured to lose the information stored therein when the threshold voltage of the non-volatile memory cell is less than the erase verification voltage. This can be achieved by an erase operation that applies a voltage between the control region and the body region of the memory cell, as described in reference. Figure 1 As described.

[0074] Various memory operations of memory device 13 can be performed simultaneously on all memory cells 1 of the set. For example, for all memory cells 1 belonging to set 12A (e.g., sector or page), an erase operation for erasing information stored in memory cells 1 can be performed simultaneously in memory device 13.

[0075] The memory device 13 may also include control circuitry 14, which in various embodiments may include a microprocessor or microcontroller operatively associated with the memory array 12 and designed to control the operation of the memory array 12, and particularly to control the execution of memory operations, such as erase operations and erase verification operations.

[0076] Control circuitry 14 can also control the operation of lookup table 602. In various embodiments, lookup table 602 may be stored in memory array 12. In various embodiments, lookup table 602 may be stored in another location. Lookup table 602 may include columns with fields filled with host addresses such as logical block addresses (LBAs). The host addresses may include a first host address AA, a second host address AB, a third host address BA, and a fourth host address BB. It should be understood that the host addresses themselves may take different forms in different embodiments. Furthermore, lookup table 602 may include more or fewer host addresses.

[0077] Lookup table 602 may also include columns with fields containing physical addresses that identify a set of non-volatile memory cells. Figure 7 In the provided example, the physical addresses in the lookup table are the same as the corresponding set of non-volatile memory cells. However, this may not be true in various embodiments, and different values ​​may be used for the physical addresses. Depending on the design of memory device 13, lookup table 602 may include any number of physical addresses.

[0078] Fields in a lookup table containing host addresses can be associated with fields containing physical addresses. For example, a first host address AA can be associated with a physical address corresponding to a first set of non-volatile memory cells 00, a second host address AB can be associated with a physical address corresponding to a second set of non-volatile memory cells 01, and so on. In other words, host addresses in lookup table 602 can be mapped to physical addresses to allow memory operations identified by host addresses to be performed on the set of non-volatile memory cells corresponding to the physical addresses.

[0079] For example, memory device 13 can communicate with host device 704. Instructions received from host device 704 can identify a host address to perform a memory operation on a first host address AA. Control circuitry 14 can consult lookup table 602 to determine that the first host address AA is associated with a physical address that identifies a first non-volatile memory location set 00, and direct the execution of a memory operation on the first non-volatile memory location set 00.

[0080] The control circuit 14 can also be configured to update the contents of lookup table 602 to separate the set of non-volatile memory locations from the host address and associate the set of non-volatile memory cells with another host address. For example, the control circuit can unassociate the first set of non-volatile memory cells 00 with the first host address AA and associate the first set of non-volatile memory cells 00 with the second host address BA. Then, the instruction identified by the second host address BA received from the host device 704 will be executed on the first set of non-volatile memory cells 00.

[0081] The memory device 13 may further include a bias circuit 15, which communicates with and is controlled by the control circuit 14. The bias circuit 15 may provide an appropriate bias signal (e.g., the aforementioned pulse body voltage Vpp during an erase operation) to the memory cells 1 of the memory array 12 during memory operations. The bias circuit 15 may be configured to apply an erase voltage to the memory array 12 to perform an erase operation on a selected set of memory cells 1. This may erase a dataset stored on the selected set of non-volatile memory cells. The selected set may be selected based on an instruction received by the control circuit identifying which set should be erased. This may be performed by translating the host address in the instruction into a physical address identifying the selected set of non-volatile memory cells. In various embodiments, the erase voltage may be applied to more than one set of memory cells simultaneously. In various embodiments, the bias circuit may include a digital-to-analog converter (“DAC”) that receives a control signal DAC_IN from the control circuit. The control signal DAC_IN may determine the voltage level for the erase operation. The control signal DAC_IN may also determine the voltage level for the read operation. The control signal DAC-IN determines the voltage level used for test operations.

[0082] The bias circuit can be configured to apply an erase voltage to each memory cell 1 in the set 12A of memory cells, between the control gate region 8 and the body region 2 of each memory cell 1 in the set of memory cells, for performing an erase operation on the set 12A of memory cells 1. The erase voltage can be varied by changing the voltage applied to the control gate region 8, the body region 2, or both. The bias circuit 15 can be configured to apply a control voltage to the control gate-gate region of each memory cell 1 in the set 12A of memory cells to perform an erase verification operation, a read operation, or a test operation.

[0083] The memory device 13 may also include a sensing circuit 16, which is also in communication with the control circuit 14. The sensing circuit 16 may detect the conduction characteristics of the memory cell 1 (e.g., for comparing a control voltage with a threshold voltage of the memory cell 1 or the set of memory cells 1 during an erase verification operation, an erase verification operation, or both).

[0084] The conduction characteristics of memory cell 1 can indicate whether the threshold voltage of memory cell 1 is less than the control voltage applied to the control gate region 8 of memory cell 1. In various embodiments, this can be used during an erase verification operation to determine whether the erase operation was successful. In various embodiments, the sensing circuit 16 may include a sensing amplifier that detects the current flowing through the channel formed between the source region 4 and the drain region 5 of the memory cell when an appropriate voltage is applied to the control gate region 8. The region in memory cell 1 where the channel is formed is... Figure 1 The middle is represented by 17.

[0085] Memory device 13 may include a dedicated memory location 18 managed and in communication with control circuitry 14. Dedicated memory location 18 may include a plurality of memory cells 1. In various embodiments, a user of memory device 13 may not be able to access dedicated memory location 18 for memory operations. Configuration information of memory device 13 (such as the voltage level of a successful erase voltage on a corresponding memory set) may be stored in this dedicated memory location 18. In various embodiments, dedicated memory location 18 may be a portion of memory array 12 that is not accessible to the user.

[0086] Figure 8 An embodiment of a dedicated memory location is described.

[0087] Control circuit 14 can be configured to retrieve data values ​​from dedicated memory location 18. For example... Figure 8As schematically shown, dedicated memory location 18 may include a lookup table (LUT) with a first column “sector” of field 18a, which contains references associated with sectors (or pages, sets, or other types of groups) of memory cell 1. In various embodiments, dedicated memory location 18 may include a column of field 18b labeled “data value”, wherein the column of field 18b may store voltage levels used for memory operations (e.g., the final level of the body voltage Vpp used to successfully perform an erase operation, the digital value of the corresponding digital control signal DAC_IN delivered to the DAC of bias circuit 15 for an erase operation or a future erase operation). The fields of the “data value” column may include a voltage level indicator configured to store data values ​​indicating the voltage used to perform an erase operation on a set of non-volatile memory cells of memory array 12, corresponding to the set of non-volatile memory cells.

[0088] In various embodiments, as referenced Figure 6A , Figure 6B and Figure 6C As described, data values ​​can be retrieved by control circuitry 14 to update lookup table 602. Memory device 13 can be configured to receive instructions from host device 704 that identify a host address to perform a memory operation, and control circuitry 14 is configured to use the lookup table to perform memory operations on the appropriate set of non-volatile memory cells.

[0089] In various embodiments, as referenced Figure 3A and Figure 3B As described, the data value can also be retrieved by the control circuitry to set the level of the initial pulse for the erase operation. The data value stored in the second field 18B can include various forms.

[0090] The control circuit 14 can be configured to: perform an erase operation by retrieving data values ​​corresponding to the set of non-volatile memory cells from a dedicated memory location 18, to instruct the bias circuit 15 to provide an erase voltage to the set of non-volatile memory cells, the erase voltage being determined by the data values; and perform an erase verification operation by applying an erase verification voltage to the set of non-volatile memory cells, and update the data values ​​corresponding to the set of non-volatile memory cells according to the erase verification operation. The erase verification voltage can be applied to the control gate of a cell in the set of non-volatile memory cells to determine whether the threshold voltage of the cell is less than the erase verification voltage by sensing the conduction characteristics of the cell when a test voltage is applied.

[0091] When the voltage level used to perform the erase operation increases, the data value at dedicated memory location 18 can be updated by control circuitry 14. In various embodiments, different methods can be used to determine the voltage level used to perform the erase operation. See reference... Figure 2A and Figure 2B As described, in some embodiments, the voltage pulse can be repeatedly increased until the erase verification operation confirms the erase operation was successful. The voltage level of the last pulse for the non-volatile memory cell set can be stored in dedicated memory location 18. In various embodiments, compared with reference to... Figure 3A and Figure 3B Similar to the described embodiments, the voltage level is stored to set the voltage level for future erase operations and is updated when the erase verification operation determines that it is no longer high enough to erase the corresponding set of non-volatile memory cells. This data can be stored in dedicated memory location 18 and can be retrieved to set the voltage level for future erase operations and to update lookup table 602. In various embodiments, when it has been determined that a subsequent erase operation will require a higher voltage level, the voltage level for the erase operation and the corresponding data value can be updated in advance before the erase operation is performed.

[0092] In different embodiments, the data values ​​in the dedicated memory may include different forms.

[0093] Figure 9A It depicts the 16-bit data values ​​in the initial configuration.

[0094] In various embodiments, data value 902 may correspond to the value used for the erase voltage of an erase operation for a corresponding set of non-volatile memory cells. It may be retrieved by control circuitry 14 to update lookup table 602, where a higher voltage level is used as an indicator of wear on the set of non-volatile memory cells. In various embodiments, it may also be retrieved by control circuitry 14 to set the value of the voltage applied to the set of non-volatile memory cells during the erase operation. The voltage applied to the control gate region 8 of the memory cell, the voltage applied to the body region 2 of the memory cell, or both may preferably be varied to change the erase voltage used for the erase operation. In some embodiments, a first portion 902A including the three most significant bits depicted in FIG. 9 may determine the voltage value to be applied to the control gate region 8 of the memory cell 1 for the erase operation. A second portion 902B including the 13 least significant bits depicted in FIG. 9 may correspond to the voltage value to be applied to the body region 2 of the memory cell 1 for the erase operation.

[0095] The initial setting of data value 902 may correspond to the initial voltage level of the erase voltage used for the first erase operation at the start of the lifetime of memory device 13. The initial level may be determined during the manufacture or testing of memory device 13. In various embodiments, the initial value of the data value may include all "1"s. However, it should be understood that the initial value may include any combination of desired digital values. Data value 902 can be changed by varying the bits of data value 902. This can also be used to change the level of the erase voltage based on data value 902. First portion 902A, second portion 902B, or both may be changed to vary the level of the erase voltage. This value may also be used by control circuitry 14 as a proxy for wear on memory cells, thus allowing lookup table 602 to be updated for wear leveling.

[0096] Figure 9B It describes the 16-bit data value in the incremental configuration.

[0097] The data value 902 can be incremented by changing the value of one bit in the data value 902. Figure 9B In the second part 902B of data value 902, the least significant bit has been switched from "1" to "0". This new configuration can correspond to an increased erase voltage level. In various embodiments, the incrementing voltage value at 902B can indicate an increased voltage level to be applied to the body region 2 of memory cell 1 for an erase operation. Each possible value of data value 902 can correspond to an erase voltage level. These values ​​can also correspond to input values ​​used for the DAC, such as... Figure 3A and Figure 3B As depicted in [the document]. In various embodiments, the bits of data value 902 can be changed only once, thus allowing for increments in the 16-bit data value, each increment corresponding to a different possible value for the erase voltage.

[0098] Figure 9C It describes the 16-bit data value in the incremental configuration.

[0099] The least significant bit of the first part of 902A is at Figure 9C The values ​​have been incremented. This corresponds to the change in the voltage applied to the control gate region 8 of memory cell 1 during the erase operation. The five least significant bits of the second part 902B have also been incremented. The configuration of the data value 902 in Figure 9c corresponds to the change in the value of the control gate region 8 of memory cell 1 during the erase operation. Figure 9A The data value 902 is incremented by six increments starting from its initial value. However, it should be understood that the data value 902 can be incremented in any desired manner. In various embodiments, the data value may include more or fewer bits, may have more or fewer parts, and these parts may include different lengths.

[0100] return Figure 7The control circuitry 14 of the memory device can be configured to retrieve data value 902 or multiple data values ​​to update lookup table 602 or determine how to allocate memory resources. The higher the voltage level reflected by data value 902, the more wear and tear on the set of non-volatile memory cells. The set of non-volatile memory cells can be arranged and allocated to host addresses according to their wear so that they are worn evenly. In some embodiments, this can involve allocating a set of low-wear non-volatile memory cells to a high-utilization host address. In various embodiments, this can involve allocating a set of low-wear non-volatile memory cells when an instruction from the host device requests memory resources.

[0101] The control circuit 14 can also be configured to perform an erase operation after retrieving the data value 902 from a dedicated memory location 18 corresponding to the set of memories 12. Based on the data value 902, the control circuit 14 can deliver a control signal to the bias circuit 15. In various embodiments, the control signal may include DAC_IN for the DAC used by the bias circuit. Then, under the guidance of the control circuit 14, the bias circuit 15 can apply an erase voltage to the memory cell 1 of the set 12A of memories selected for the erase operation.

[0102] The control circuit 14 can also be configured to perform an erase verification operation to determine whether the distribution of threshold voltages of memory cells 1 in the selected set of memory cells is less than the erase verification voltage. This can be achieved by controlling the bias circuit 15 to apply a control voltage equal to the erase verification voltage to the set of memory cells 1 in the memory array 12. The sensing circuit 16 can detect the conduction characteristics of memory cells 1 in the set of non-volatile memory cells of the memory array 12, which can be used to determine whether the distribution of threshold voltages of memory cells 1 is greater than or less than the erase verification voltage. If it is determined that the threshold voltages of all, a predetermined number, or a percentage of memory cells have been moved sufficiently to clear the erase verification voltage, it can be determined that the set of non-volatile memory cells has passed the test operation. If the set of non-volatile memory cells passes the erase verification operation, it is not necessary to increase the erase voltage level. If the set of non-volatile memory cells fails the erase verification operation, the data value 902 can be incremented and another voltage pulse can be applied to the set of non-volatile memory cells.

[0103] If the current detected by sensing circuit 16 during the erase verification operation is less than the reference current, it can be determined that the non-volatile memory cell set has failed the erase verification operation. This can indicate that the erase verification voltage has not turned on the memory cell, which may mean that no conductive channel has been formed between the source region 4 and drain region 5 of the memory cell to allow current. This can also indicate that the threshold voltage of the memory cell being tested is greater than the erase verification voltage. In response to determining that the non-volatile memory cell set has failed the erase verification operation, the voltage level can be increased, and a second pulse can be applied to memory cell 1 in the non-volatile memory cell set of memory array 12 to complete the erase operation.

[0104] Figure 10 A flowchart depicts a method for operating non-volatile memory.

[0105] Method 1000 may include: at step 1002, having a non-volatile memory including a first set of non-volatile memory cells and a second set of non-volatile memory cells, the first set of non-volatile memory cells being associated with a first host address, and the second set of non-volatile memory cells being associated with a second host address. Method 1000 may include: at step 1004, determining a first voltage level for effectively erasing the first set of non-volatile memory cells. Method 1000 may include: at step 1006, determining a second voltage level for effectively erasing the second set of non-volatile memory cells. Method 1000 may include: at step 1008, deassociating the first set of non-volatile memory cells with the first host address. Method 1000 may include: at step 1010, deassociating the second set of non-volatile memory cells with the second host address. Method 1000 may include: at step 1012, associating the first set of non-volatile memory cells with the second host address based on the first voltage level for effectively erasing the first set of non-volatile memory cells.

[0106] In various embodiments of method 1000, associating the first set of non-volatile memory cells with the second host address may include determining that a first voltage level is higher than a second voltage level.

[0107] In various embodiments, method 1000 may further include: cycling a first set of non-volatile memory cells; and determining that a first voltage level is no longer effective in erasing the first set of non-volatile memory cells.

[0108] In various embodiments, method 1000 may further include associating the second set of non-volatile memory cells with a first host address based on a second voltage level that effectively erases the second set of non-volatile memory cells.

[0109] In various embodiments, method 1000 may further include: receiving an instruction from a host device that identifies a second host address for performing a memory operation; and performing a memory operation on a first set of non-volatile memory cells.

[0110] In various embodiments of method 1000, associating the first set of non-volatile memory cells with the second host address may include: corresponding the first set of non-volatile memory cells with the second host address in a lookup table.

[0111] In various embodiments, method 1000 may further include performing an erase operation on the first group of non-volatile memory cells by applying a first voltage level to the first group of non-volatile memory cells.

[0112] In various embodiments, method 1000 may further include: storing a first voltage level in a dedicated memory region; determining a new voltage level that effectively erases the first set of non-volatile memory cells; and replacing the first voltage level in the dedicated memory region with the new voltage level.

[0113] In various embodiments, method 1000 may further include performing a second erase operation on the first set of non-volatile memory cells by applying a new voltage level to the first set of non-volatile memory cells.

[0114] Figure 11 A flowchart of method 1100 for wear equalization is depicted.

[0115] Method 1100 may include: at step 1102, having a plurality of memory locations, each memory location corresponding to a set of non-volatile memory cells in a plurality of non-volatile memory cell sets; at step 1104, method 1100 may include: storing a data value in each of the plurality of memory locations, the data value indicating a voltage level for performing an erase operation on the set of non-volatile memory cells corresponding to the memory location where the data value is stored; and at step 1106, method 1100 may include: mapping a plurality of host addresses to a plurality of non-volatile memory cell sets in a lookup table based on the data value in each of the plurality of memory locations.

[0116] In various embodiments, method 1100 may further include: receiving a set of instructions from a host device to perform memory operations on a selected set of nonvolatile memory cells identified by a host address among a plurality of host addresses; and performing memory operations on a set of memory locations that are mapped to host addresses among a plurality of host addresses in a lookup table.

[0117] Method 1100 may further include: updating a first data value of a first memory location among a plurality of memory locations.

[0118] Method 1100 may further include updating a lookup table that maps multiple host addresses to multiple sets of nonvolatile memory cells based on data values ​​in each of the multiple memory locations.

[0119] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the entire specification and the claims submitted herein.

[0120] Example 1. A method for operating non-volatile memory, the method comprising:

[0121] The system includes the non-volatile memory comprising a first group of non-volatile memory cells and a second group of non-volatile memory cells, the first group of non-volatile memory cells being associated with a first host address and the second group of non-volatile memory cells being associated with a second host address; determining a first voltage level for effectively erasing the first group of non-volatile memory cells; determining a second voltage level for effectively erasing the second group of non-volatile memory cells; deassociating the first group of non-volatile memory cells with the first host address; deassociating the second group of non-volatile memory cells with the second host address; and associating the first group of non-volatile memory cells with the second host address based on the first voltage level for effectively erasing the first group of non-volatile memory cells.

[0122] Example 2. The method according to Example 1, wherein associating the first group of non-volatile memory cells with the second host address includes: determining that the first voltage level is higher than the second voltage level.

[0123] Example 3. The method according to Example 1 or Example 2 further includes: cyclically cycling the first group of non-volatile memory cells; and determining that the first voltage level is no longer effective in erasing the first group of non-volatile memory cells.

[0124] Example 4. The method according to Examples 1 to 3 further includes: associating the second set of non-volatile memory cells with the first host address based on the second voltage level of effectively erasing the second set of non-volatile memory cells.

[0125] Example 5. The method according to Examples 1 to 4 further includes: receiving an instruction from a host device, the instruction identifying the second host address for performing a memory operation; and performing the memory operation on the first group of non-volatile memory cells.

[0126] Example 6. The method according to Examples 1 to 5, wherein associating the first group of non-volatile memory cells with the second host address includes: mapping the first group of non-volatile memory cells to the second host address in a lookup table.

[0127] Example 7. The method according to Examples 1 to 6 further includes: performing an erase operation on the first group of non-volatile memory cells by applying the first voltage level to the first group of non-volatile memory cells.

[0128] Example 8. The method according to Examples 1 to 7 further includes: storing the first voltage level in a dedicated memory region; determining a new voltage level that effectively erases the first set of non-volatile memory cells; and replacing the first voltage level in the dedicated memory region with the new voltage level.

[0129] Example 9. The method according to Examples 1 to 8 further includes: performing a second erase operation on the first group of non-volatile memory cells by applying the new voltage level to the first group of non-volatile memory cells.

[0130] Example 10. A non-volatile memory device comprising: a voltage level indicator configured to store a data value indicating a voltage level for performing an erase operation on a first set of non-volatile memory cells; and a controller communicating with the voltage level indicator and configured to: update a lookup table based on the data value to associate the first set of non-volatile memory cells with a host address.

[0131] Example 11. The non-volatile memory device according to Example 10, wherein the controller is configured to update the voltage level indicator to store a new voltage level for performing a subsequent erase operation on the first group of non-volatile memory cells.

[0132] Example 12. A non-volatile memory device according to Example 10 or Example 11, wherein the controller is configured to receive instructions from a host device, the instructions identifying the host address to perform a memory operation, and wherein the controller is configured to use the lookup table to perform the memory operation on the first set of non-volatile memory cells.

[0133] Example 13. A non-volatile memory device according to Examples 10 to 12, wherein the first group of non-volatile memory cells includes a plurality of floating gate memory cells.

[0134] Example 14. The non-volatile memory device according to Examples 10 to 13 further includes: a bias circuit configured to: apply an erase voltage to the first group of non-volatile memory cells to erase a dataset stored on the first group of non-volatile memory cells; apply a read voltage to the first group of non-volatile memory cells to read the dataset stored on the first group of non-volatile memory cells; and apply a programming voltage to the first group of non-volatile memory cells to program the dataset on the first group of non-volatile memory cells; and a sensing circuit configured to read the first group of non-volatile memory cells.

[0135] Example 15. The non-volatile memory device according to Examples 10 to 14, wherein the bias circuitry includes a digital-to-analog converter.

[0136] Example 16. A non-volatile memory device according to Examples 10 to 15, wherein the controller is configured to perform the erase operation by: retrieving the data value from the voltage level indicator to instruct the bias circuit to provide the erase voltage to the first group of non-volatile memory cells, the erase voltage being determined by the data value; and performing an erase verification operation by applying an erase verification voltage to the first group of non-volatile memory cells, and updating the data value based on the result of the erase verification operation.

[0137] Example 17. A method for wear leveling, comprising: having a plurality of memory locations, each memory location corresponding to a set of non-volatile memory cells in a plurality of sets of non-volatile memory cells; storing a data value in each of the plurality of memory locations, the data value indicating a voltage level for performing an erase operation on the set of non-volatile memory cells corresponding to the memory location where the data value is stored; and mapping a plurality of host addresses to the plurality of sets of non-volatile memory cells in a lookup table based on the data value in each of the plurality of memory locations.

[0138] Example 18. The method according to Example 17 further includes: receiving a set of instructions from a host device to perform a memory operation on a selected set of non-volatile memory cells identified by a host address among the plurality of host addresses; and performing the memory operation on a set of memory locations, the set of memory locations being mapped to the host address among the plurality of host addresses in the lookup table.

[0139] Example 19. The method according to Example 17 or Example 18 further includes: updating a first data value of a first memory location among the plurality of memory locations.

[0140] Example 20. The method according to Examples 17 to 19 further includes: updating the lookup table that maps the plurality of host addresses to the plurality of nonvolatile memory cell sets based on the data value in each of the plurality of memory locations.

[0141] Finally, it is evident that modifications and variations can be made to the content described and illustrated herein without departing from the scope of the invention as defined in the appended claims.

[0142] References to illustrative embodiments in this description are not intended to be limiting. Various modifications and combinations of illustrative and other embodiments will be apparent to those skilled in the art upon reference to this description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method for operating a non-volatile memory, the method comprising: The non-volatile memory includes a first group of non-volatile memory cells and a second group of non-volatile memory cells, wherein the first group of non-volatile memory cells is associated with a first host address and the second group of non-volatile memory cells is associated with a second host address. Determine a first voltage level that will effectively erase the first group of non-volatile memory cells; Determine the second voltage level that will effectively erase the second group of non-volatile memory cells; Remove the association between the first group of non-volatile memory cells and the first host address; Remove the association between the second group of non-volatile memory cells and the second host address; Based on the first voltage level that effectively erases the first group of non-volatile memory cells, the first group of non-volatile memory cells are associated with the second host address; Determine a new voltage level that will effectively erase the first group of non-volatile memory cells; as well as The new voltage level is used as an initial voltage pulse to perform future erase operations on the first group of non-volatile memory cells.

2. The method of claim 1, wherein associating the first group of non-volatile memory cells with the second host address comprises: It is determined that the first voltage level is higher than the second voltage level.

3. The method according to claim 1, further comprising: The first group of non-volatile memory cells is cyclical; as well as It was determined that the first voltage level was no longer effective in erasing the first group of non-volatile memory cells.

4. The method according to claim 1, further comprising: The second set of non-volatile memory cells is associated with the first host address based on the second voltage level that effectively erases the second set of non-volatile memory cells.

5. The method according to claim 1, further comprising: Receive an instruction from the host device, the instruction identifying the second host address for performing a memory operation; as well as The memory operation is performed on the first group of non-volatile memory cells.

6. The method of claim 1, wherein associating the first group of non-volatile memory cells with the second host address comprises: The first group of non-volatile memory units is mapped to the second host address in the lookup table.

7. The method according to claim 1, further comprising: An erase operation is performed on the first group of non-volatile memory cells by applying the first voltage level to the first group of non-volatile memory cells.

8. The method according to claim 7, further comprising: The first voltage level is stored in a dedicated memory area; as well as After determining the new voltage level that will effectively erase the first set of non-volatile memory cells, the first voltage level in the dedicated memory region is replaced with the new voltage level.

9. A non-volatile memory device, comprising: A voltage level indicator is configured to store a data value indicating the voltage level used to perform an erase operation on the first set of non-volatile memory cells; The controller communicates with the voltage level indicator and is configured to: Remove the association between the first group of non-volatile memory cells and the first host address; Based on the data value, the first group of non-volatile memory cells is associated with a second host address, wherein the second host address is originally associated with the second group of non-volatile memory cells; The lookup table is updated based on the data value to associate the first group of non-volatile memory cells with the second host address; After performing an erase operation on the first group of non-volatile memory cells, determine the new voltage level that effectively erases the first group of non-volatile memory cells; as well as When performing an erase operation on the first group of non-volatile memory cells, the new voltage level is used as the initial voltage pulse.

10. The non-volatile memory device of claim 9, wherein the controller is configured to update the voltage level indicator to store a new voltage level for performing a subsequent erase operation on the first group of non-volatile memory cells.

11. The non-volatile memory device of claim 9, wherein the controller is configured to receive an instruction from a host device, the instruction identifying the second host address to perform a memory operation, and wherein the controller is configured to use the lookup table to perform the memory operation on the first set of non-volatile memory cells.

12. The non-volatile memory device of claim 9, wherein the first group of non-volatile memory cells comprises a plurality of floating gate memory cells.

13. The non-volatile memory device according to claim 9, further comprising: The bias circuit is configured to apply an erase voltage to the first group of non-volatile memory cells to erase the dataset stored on the first group of non-volatile memory cells. A read voltage is applied to the first group of non-volatile memory cells to read the dataset stored in the first group of non-volatile memory cells; And apply a programming voltage to the first group of non-volatile memory cells to program the dataset onto the first group of non-volatile memory cells; as well as The sensing circuit is configured to read the first set of non-volatile memory cells.

14. The non-volatile memory device of claim 13, wherein the bias circuitry includes a digital-to-analog converter.

15. The non-volatile memory device of claim 13, wherein the controller is configured to: The erase operation is performed by: retrieving the data value from the voltage level indicator to instruct the bias circuit to provide the erase voltage, determined by the data value, to the first group of non-volatile memory cells; and An erase verification operation is performed by applying an erase verification voltage to the first group of non-volatile memory cells, and the data value is updated based on the result of the erase verification operation.

16. A method for wear leveling, comprising: It has multiple memory locations, each memory location corresponding to a set of non-volatile memory cells in a set of multiple non-volatile memory cells; In each of the plurality of memory locations, a data value is stored, the data value indicating a voltage level for performing an erase operation on the set of non-volatile memory cells corresponding to the memory location where the data value is stored; The association between the first set of non-volatile memory cells and the first host address is removed, and the association between the second set of non-volatile memory cells and the second host address is also removed. Based on the data value corresponding to the first set of non-volatile memory cells, the first set of non-volatile memory cells is associated with the second host address; Based on the data value in each of the plurality of memory locations, a plurality of host addresses are mapped to the plurality of non-volatile memory cell sets in a lookup table; After performing an erase operation on the set of non-volatile memory cells, a new voltage level is determined to effectively erase the set of non-volatile memory cells; as well as When performing an erase operation on the non-volatile memory cell set in a subsequent step, the new voltage level is used as the initial voltage pulse.

17. The method of claim 16, further comprising: Receive a set of instructions from the host device to perform memory operations on a selected set of non-volatile memory cells identified by a host address from the plurality of host addresses; as well as The memory operation is performed on a set of memory locations, which are mapped to host addresses in the plurality of host addresses in the lookup table.

18. The method of claim 17, further comprising: Update the first data value of the first memory location among the plurality of memory locations.

19. The method of claim 18, further comprising: The lookup table that maps the plurality of host addresses to the plurality of nonvolatile memory cell sets is updated based on the data value in each of the plurality of memory locations.

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