Managing execution of clean operations in a memory sub-system

Abstract

The present disclosure relates to managing execution of clean operations in a memory sub-system. A value corresponding to an operating characteristic of a memory sub-system is determined. The value is compared to a first threshold level to determine whether a first condition is satisfied. The value is also compared to a second threshold level to determine whether a second condition is satisfied. In response to the first condition being satisfied, a read clean operation associated with the memory sub-system is performed. In response to the second condition being satisfied, a write clean operation associated with the memory sub-system is performed.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to a memory subsystem, and more specifically, to managing the execution of cleanup operations within a memory subsystem. Background Technology

[0002] A memory subsystem can be a storage system, a memory module, or a combination of storage devices and memory modules. A memory subsystem can contain one or more memory devices for storing data. Memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] In one aspect, this disclosure provides a method comprising: determining, by a processing means, a value corresponding to an operating characteristic of a memory subsystem; comparing the value with a first threshold level to determine whether a first condition is satisfied; comparing the value with a second threshold level to determine whether a second condition is satisfied; performing a read cleanup operation associated with the memory subsystem in response to satisfying the first condition; and performing a write cleanup operation associated with the memory subsystem in response to satisfying the second condition.

[0004] In another aspect, this disclosure further provides a non-transitory computer-readable medium including instructions that, when executed by a processing device, cause the processing device to perform operations including: identifying a first read cleanup frequency level and a first write cleanup frequency level associated with a memory subsystem; determining a value corresponding to an operating characteristic of the memory subsystem; comparing the value with a threshold level to determine whether a condition is satisfied; and, in response to satisfying the condition, adjusting the first read cleanup frequency level to a second read cleanup frequency level and adjusting the first write cleanup frequency level to a second write cleanup frequency level.

[0005] In another aspect, this disclosure further provides a system comprising: a memory component; and a processing means operatively coupled to the memory component to perform the following operations: determining a value corresponding to an operating characteristic of a memory subsystem; comparing the value with a first threshold level to determine whether a first condition is satisfied; comparing the value with a second threshold level to determine whether a second condition is satisfied; performing a read cleanup operation associated with the memory subsystem in response to satisfying the first condition; and performing a write cleanup operation associated with the memory subsystem in response to satisfying the second condition. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description given below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart of an example method for performing read cleanup and write cleanup operations based on the operational characteristics of a memory subsystem according to some embodiments.

[0009] Figure 3 This is a flowchart of an example method for adjusting read and write cleanup frequencies based on the operational characteristics of a memory subsystem according to some embodiments.

[0010] Figure 4 The description includes a table containing instance cleanup frequency levels according to some embodiments, wherein the instance cleanup frequency levels include corresponding read cleanup frequencies and write cleanup frequencies for adjusting the memory subsystem.

[0011] Figure 5 This is a block diagram of an example computer system in which the embodiments of this disclosure can be operated. Detailed Implementation

[0012] This disclosure relates to the management of the execution of cleanup operations in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more memory devices. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0013] The memory device can be a non-volatile memory device, such as a three-dimensional cross-point (“3D cross-point”) memory device that is a cross-point array of non-volatile memory, which can perform bit storage based on changes in volume resistance by combining a stackable cross-grid data access array. Another example of a non-volatile memory device is a NAND memory device. (The following section will discuss this further.) Figure 1 Other examples of non-volatile memory devices are described.

[0014] Each memory device may contain one or more arrays of memory cells. A memory cell (“cell”) is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states related to the number of bits stored. Logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of such values. For example, a single-level cell (SLC) may store one bit of information and have two logic states. Each logic state has a corresponding threshold voltage level. The threshold voltage (VT) is a voltage applied to the cell circuitry (e.g., the control gate of a transistor to turn on) to set the cell state. The cell is set to one of its logic states based on the VT applied to it. For example, if a high VT is applied to an SLC, then there will be charge in the cell, and the SLC is set to store logic 0. If a low VT is applied to an SLC, then there will be no charge in the cell, and the SLC is set to store logic 1.

[0015] For certain memory types (i.e., memory subsystems employing certain types of storage media), the error rate can change over time. Specifically, some non-volatile memories have a threshold voltage programming distribution that shifts or "drifts" higher over time. At a given read voltage level (i.e., the value of the voltage applied to a memory cell as part of a read operation), if the threshold voltage programming distribution shifts, certain reliability statistics may also be affected. One example of a reliability statistic is the bit error rate (BER). BER can be defined as the ratio of the number of faulty bits to the total number of data bits stored in a cell within a memory subsystem, where a cell can be the entire memory subsystem, the die of a memory device, a collection of codewords, or any other meaningful part of the memory subsystem.

[0016] A read operation can be performed at a read voltage level. The read threshold voltage level or value (referred to herein as "read voltage level") can be a specific voltage applied to a memory cell of the memory device to read data stored at that memory cell. For example, if the threshold voltage of a particular memory cell is identified as being lower than the read voltage level applied to that memory cell, then the data stored at that memory cell can be a specific value (e.g., '1'), and if the threshold voltage of a particular memory cell is identified as being higher than the read voltage level, then the data stored at that memory cell can be another value (e.g., '0'). Therefore, a read voltage level can be applied to the memory cell to determine the value stored at the memory cell.

[0017] In a conventional memory subsystem, when the threshold voltage programming distribution of a memory cell changes, the applied read voltage level may be inaccurate relative to the changed threshold voltage. For example, a memory cell can be programmed to have a threshold voltage lower than the read voltage level. The programmed threshold voltage can change over time and may transition to a level higher than the read voltage level. For instance, the threshold voltage of a memory cell may change from initially being lower than the read voltage level to being higher than the read voltage level. Therefore, when a read voltage level is applied to the memory cell, the data stored at the memory cell may be misread or misinterpreted as an incorrect value compared to the initially stored value before the threshold voltage transition.

[0018] The rate or speed at which the threshold voltage programming distribution drifts, and the corresponding BER of a typical memory subsystem, can be affected by one or more operating characteristics of the memory subsystem, such as changes in die temperature. In such systems, the high-temperature retry rate increases much faster over time compared to the low-temperature retry rate. Furthermore, threshold voltage drift and degradation occur due to thermal interference errors and read interference errors.

[0019] These errors can occur during memory access operations (e.g., read operations, write operations, etc.) at the memory device. For example, during a read operation, the memory subsystem controller may misread a bit representing data stored at the memory device (i.e., the stored value is read incorrectly). In another instance, one or more bits representing data stored at the memory device may contain errors (i.e., incorrectly stored values). Either situation can cause an error during the execution of a read operation (e.g., a memory access error). After a memory access error has been detected, the memory subsystem controller can perform an error correction operation to correct the error in the data and then perform the memory access operation again to access the corrected data. In some cases, the error correction operation may be a memory cleanup operation, in which the memory subsystem controller corrects the error in the data and writes the corrected data back to the memory device.

[0020] To address errors caused by threshold voltage drift due to high temperatures, conventional memory subsystems typically employ periodic read cleanup operations (e.g., a three-hour read cleanup, where the entire memory subsystem is read once at a predetermined read cleanup frequency of every three hours) and periodic write cleanup operations (i.e., write operations that cause a switch between '0' and '1' values ​​and vice versa at a predetermined write cleanup frequency, e.g., every twelve hours) to refresh or push the threshold voltage programming distribution down to counteract drift.

[0021] However, unnecessary read and write cleanup operations (e.g., over-cleaning) degrade the quality of service of the memory subsystem due to the frequent execution of background read and write operations. Furthermore, 3D crosspoint systems employ the same or static read and write cleanup frequencies throughout the lifetime of the memory device. In this regard, conventional systems apply the same read and write cleanup frequencies to all memory devices, regardless of whether they are in the beginning-of-life (BOL) or end-of-life (EOL) phase (e.g., where the memory device largely cycles, causing a very rapid increase in codeword error rate (CWER)). In such cases, predetermined frequencies are insufficient to recover the required CWER, resulting in a large number of errors. Additionally, the use of predetermined frequencies for read and write cleanup operations can lead to insufficient cleanup, causing data errors. Therefore, due to the operating characteristics of memory devices, such as temperature variations and other memory device variations, the use of predetermined and static read and write cleanup frequencies in conventional 3D crosspoint systems does not allow for frequency adjustment.

[0022] The present disclosure addresses the above and other deficiencies by having a memory subsystem that manages the execution of read and write cleanup operations based on one or more operational characteristics of the memory subsystem. Specifically, the frequency of read and write cleanup operations can be adjusted based on one or more operational characteristics of the memory subsystem, such as measures or values ​​describing temperature changes and memory device variations (e.g., lifetime cycle stages of the memory device, such as BOL, EOL, etc.).

[0023] The advantages of this disclosure include, but are not limited to, dynamically performing cleanup operations (e.g., read cleanup, write cleanup, or both) based on one or more operating characteristics of the memory subsystem. Furthermore, the frequencies associated with read and write cleanup operations can be adjusted based on one or more operating characteristics. Advantageously, the identification of current operating characteristics and the execution of cleanup operations, or the adjustment of one or more of the read and write cleanup frequencies based on operating characteristics, enable the application of optimized cleanup frequencies that take into account changes in the memory device (e.g., the lifetime cycle stage of the memory device) and temperature variations. Therefore, the cleanup operation frequency can be adjusted to manage less reliable memory devices requiring higher frequency cleanup operations. Furthermore, the cleanup operation frequency can be adjusted to manage temperature variations in the memory device, allowing for high-frequency cleanup operations for higher-temperature operation of the memory device. Additionally, the systems and methods of this disclosure reduce or eliminate read cleanup frequencies and avoid unnecessary read interference errors.

[0024] Figure 1This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0027] Host system 120 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, vehicle (e.g., airplane, drone, train, car, or other means of transportation), Internet of Things (IoT) device, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment, or networked business device), or such computing device containing memory and processing power. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect High Speed ​​(PCIe) interface, Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface may be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via PCIe interface, host system 120 may further utilize NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface can provide an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120.

[0028] The memory device may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., memory device 140) may be, but is not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them.

[0030] Although a non-volatile memory component, such as a 3D cross-point type memory, is described, the memory device 130 may be based on any other type of non-volatile memory, such as NAND, ROM, phase-change memory (PCM), auto-memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0031] One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory component may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages or codewords, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks. Some types of memory (e.g., 3D cross-connect) may group pages across the die and channels to form management units (MUs).

[0032] The memory subsystem controller 115 can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic that performs the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0034] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations associated with the memory device 130, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical block addresses and physical block addresses. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0037] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] The memory subsystem 110 includes a cleanup operation management component 113, which can be used to adjust the frequency of read cleanup operations and the frequency of write cleanup operations based on one or more operating characteristics of the memory subsystem 110. In one embodiment, the operating characteristic may be a measure of a parameter representing a measure of the reliability of the memory device, such as a threshold voltage retry rate or an error correction failure rate. In one embodiment, performing a read retry operation to reread data is part of an error correction process. In one embodiment, multiple different read threshold voltages may be applied (e.g., read retry threshold voltage 1 (V)). t1 ), Read the retry threshold voltage 2 (V) t2 ), Read the retry threshold voltage 3 (V) t3 As part of the error correction process, the cleanup operation management component 113 maintains a counter to determine the appropriate read retry threshold voltage (e.g., V) to be applied for each corresponding read. t1 V t2 and V t3 The number of times it is part of the error correction process.

[0039] In one embodiment, a read retry rate can be determined for each of a plurality of read retry threshold voltages. In one embodiment, the cleanup operation management component 113 identifies the read retry rate as an operational characteristic of the memory subsystem to be monitored and used for comparison purposes. In one embodiment, the read retry threshold voltage can be preset to a V value associated with the read retry error correction process. t1 V t2 or V t3 One of them. In one embodiment, the cleanup operation management component 113 uses the second read retry threshold voltage (V) of the error correction process. t2 The value of ) is used as the selected read retry threshold voltage (i.e., operating characteristic) to determine the adjustment of the read cleanup frequency, write cleanup frequency, or both, as described in more detail below.

[0040] In one embodiment, the cleanup operation management component 113 compares a selected read retry rate (e.g., an operational characteristic) with a first threshold level to determine whether a first condition is met. In one embodiment, if the read retry rate is greater than the first threshold level, then the first condition is met. In one embodiment, the first threshold level is a predetermined or preset level (e.g., 1x10). -7This is used for comparison with values ​​of operational characteristics (e.g., read retry rate). In one embodiment, a first threshold level may represent an acceptable (e.g., maximum) read retry rate, such that when the operational characteristics exceed the acceptable read retry rate, the cleanup operation management component 113 manages read cleanup operations of the memory subsystem 110. For example, in response to determining that a first condition is met (e.g., the measured read retry rate exceeds the acceptable read retry rate), the cleanup operation management component 113 performs a read cleanup operation. In one embodiment, the cleanup operation management component 113 compares a selected read retry rate with a second threshold level to determine whether a second condition is met. In one embodiment, if the read retry rate is greater than the second threshold level, then the second condition is met. In response to determining that the second condition is met, the cleanup operation management component 113 performs a write cleanup operation. In one embodiment, the second threshold level is a predetermined or preset level (e.g., 1x10). -6 This is used to compare the measured read retry rate value to determine whether cleanup operation management is needed. For example, if the measured read retry rate exceeds the second current level (e.g., 1x10),... -6 If the cleanup operation management component 113 performs a write cleanup operation as part of the error correction process, then the cleanup operation management component 113 can perform a write cleanup operation as part of the error correction process. In one embodiment, the second threshold level can be predetermined or preset to any value representing the maximum acceptable read retry rate, which, if exceeded, triggers or causes a cleanup management operation (e.g., the execution of a write cleanup operation).

[0041] In another embodiment, the cleanup operation management component 113 can establish an initial or first read cleanup frequency level and a first write cleanup frequency level associated with the memory subsystem. The initial or first read cleanup frequency (e.g., performed every 3 hours) and the first write cleanup frequency (e.g., performed every 12 hours) can be established during the BOL phase of the memory device. In this embodiment, the cleanup operation management component 113 can determine values ​​corresponding to the operating characteristics of the memory subsystem, such as a read retry threshold voltage (e.g., V). t2 The read retry rate is compared to a threshold level to determine if a condition is met (e.g., the read retry rate is greater than the threshold level). If the condition is met and the read retry rate exceeds the threshold level, then the cleanup operation management component 113 performs a write cleanup operation. In one embodiment, the threshold level is a predetermined or preset level representing the maximum acceptable read retry rate (e.g., 1x10). -7 This is used to compare with a value of an operational characteristic (e.g., a measured read retry rate). In one embodiment, if the value is greater than a threshold level (e.g., the measured read retry rate exceeds a maximum acceptable read retry rate), then the condition is met. In one embodiment, if it corresponds to V...t2 If the read retry rate is greater than the threshold level, then the condition is met.

[0042] Additionally, after the condition is met, the cleanup operation management component 113 adjusts the first or initial read cleanup frequency level to an adjusted read cleanup frequency level as described in the data structure. In one embodiment, the data structure identifies multiple read cleanup frequency levels, and after the condition is met, the cleanup operation management component 113 determines the current read cleanup frequency level and adjusts the read cleanup frequency level to the next level as identified in the data structure. The cleanup operation management component 113 also adjusts the first or initial write cleanup frequency level to an adjusted write cleanup frequency level (e.g., a reduced write cleanup frequency value determined by the data structure that identifies multiple different write cleanup frequency levels, as described in...). Figure 4 (As shown in the example).

[0043] In one embodiment, the cleanup operation management component 113 maintains a data structure (e.g., a lookup table) containing multiple levels or thresholds for different read and write cleanup frequencies, established as changes in conditions and parameters of the memory subsystem 110 that cause changes in operational characteristics (e.g., measured read retry rate). In one embodiment, the data structure may contain read and write cleanup frequency levels with predetermined values ​​representing different adjustments or changes to the cleanup frequencies. These values ​​may be set in a way that reflects desired or optimized write and read cleanup frequency values ​​corresponding to changes in operational characteristics (e.g., read retry rate). For example, values ​​for different levels may be set such that the write and read cleanup frequencies decrease at each level. After determining that the read retry rate is greater than a threshold level, the cleanup operation management component 113 identifies the next level or threshold (e.g., the execution of a lookup operation via the table) and applies the read and write cleanup frequencies corresponding to the next level. In one embodiment, the cleanup operation management component 113 iteratively checks the selected read retry rate and compares it with a threshold level to determine whether further adjustment of the read cleanup and write cleanup frequencies will be made by moving to the next step or level as illustrated in the table. This allows the read cleanup and write cleanup frequencies to be adjusted throughout the entire lifetime of the memory devices 130, 140 to account for device and temperature variations.

[0044] Figure 2This is a flowchart of an example method 200 for managing the execution of read cleanup and write cleanup operations based on one or more operational characteristics of a memory subsystem according to some embodiments. Method 200 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200... Figure 1 The cleanup operation management component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0045] like Figure 2 As shown, in operation 210, processing logic (e.g., clearing operation management component 113) determines a value corresponding to an operating characteristic of the memory subsystem. In one embodiment, the operating characteristic may include a selected read retry rate. In one embodiment, the selected read retry rate may be a selected read retry threshold voltage (e.g., V). t2 The count (e.g., the number of times the selected read retry threshold voltage is applied as part of the read retry operation) and the total read retry threshold voltage count (e.g., the count with V) t1 V t2 and V t3 The selected read retry rate can be compared to a set of read retry threshold voltages (e.g., including a first read retry threshold voltage (V)). t1 ), second read retry threshold voltage (V) t2 ) and the third read retry threshold voltage (V t3 The second read retry threshold voltage (V) of the set) t2 The associated read retry rate. In one embodiment, the value corresponding to the second read retry rate (e.g., the selected operating characteristic) can be represented by the following equation:

[0046] V t2 Read retry rate = V t2 Read retry count / (V) t1 Read retry count +V t2 Read retry count +V t3 (Read the retry count).

[0047] In operation 220, the processing logic compares the value with a first threshold level to determine whether a first condition is met. In one embodiment, the first threshold level is a predetermined or preset level (e.g., 1x10). -7 This is used to compare with a value of an operational characteristic (e.g., a selected read retry rate). In one embodiment, if the identified value is greater than a first threshold level, then a first condition is met. In one embodiment, if a second read retry rate (e.g., corresponding to V) is used... t2 If the rate is greater than the first threshold level, then the first condition is satisfied.

[0048] In operation 230, the processing device compares the value with a second threshold level to determine whether a second condition is met. In one embodiment, the second threshold level is a predetermined or preset level (e.g., 1x10). -6 This is used to compare with a value of an operational characteristic (e.g., a selected read retry rate). In one embodiment, if the identified value is greater than a second threshold level, then a second condition is met. In one embodiment, if the second read retry rate (e.g., corresponding to V...) t2 If the rate is greater than the second threshold level, then the second condition is satisfied.

[0049] In operation 240, in response to the satisfaction of a first condition, the processing logic performs a read cleanup operation associated with the memory subsystem. In one embodiment, if the Vt2 read retry rate exceeds a first threshold level, then the processing logic performs the read cleanup operation.

[0050] In operation 250, in response to the satisfaction of the second condition, the processing logic performs a write cleanup operation associated with the memory subsystem. In one embodiment, if the Vt2 read retry rate exceeds a second threshold level, then the processing logic performs the write cleanup operation.

[0051] Advantageously, operations 210-250 can be dynamically managed and executed by processing logic in a cyclical manner throughout the lifetime of the memory device, taking into account the changing operational characteristics caused by variations in the memory device and temperature.

[0052] Figure 3 This is a flowchart of an example method 300 for adjusting read and write cleanup frequencies based on one or more operational characteristics of a memory subsystem according to some embodiments. Method 300 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300... Figure 1The cleanup operation management component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0053] like Figure 3 As shown, in operation 310, the processing logic identifies a first read cleanup frequency level and a first write cleanup frequency level associated with the memory subsystem. In one embodiment, the first read cleanup frequency level may be an initial frequency established during the BOL phase of the memory device, indicating the frequency at which read cleanup operations are performed. For example, the first read cleanup frequency level may indicate that read cleanup operations will be performed every X number of hours (e.g., where X equals 3).

[0054] In one embodiment, the processing logic can maintain a data structure with multiple levels or thresholds, including read cleanup frequencies and write cleanup frequencies, such as in... Figure 4 As shown in example table 400. Figure 4 As shown, multiple levels or levels (referred to as cleanup frequency levels 410) are established, each level having a corresponding write cleanup frequency value 420 and read cleanup frequency value 430. For example, a first read cleanup frequency level and a first write cleanup frequency level of operation 310 can be identified by determining the frequency value corresponding to level 0 (e.g., BOL stage setting). Figure 4 In the example shown, the first read cleanup frequency level is 3 hours (e.g., a read cleanup operation is performed every 3 hours when the memory device is set to level 0) and the first write cleanup frequency level is 12 hours (e.g., a write cleanup operation is performed every 12 hours when the memory device is set to level 0).

[0055] In operation 320, the processing logic determines a value corresponding to the operating characteristic of the memory subsystem. In one embodiment, the operating characteristic may be a value related to a selected read retry threshold voltage level (e.g., V). t2 The associated read retry rate, as described above... Figure 1 As described. In one embodiment, multiple counters can be maintained to monitor and record read retry counts for multiple different read retry threshold voltage levels (e.g., for V). t1 A counter for counting, used for V t2 A counter for counting, and for V t3(Counter for counting). In one embodiment, after a write cycle with a set number of writes, the processing logic may check multiple counters to determine operational characteristics (e.g., V). t2 (Read retry rate) (For example, a loop check counter every 20K writes).

[0056] In operation 330, the processing logic compares the value with a threshold level to determine whether a condition is met. In one embodiment, the threshold level is a predetermined or preset level (e.g., 1x10). -7 This is used to compare with a value of an operational characteristic (e.g., a measured read retry rate). In one embodiment, if the value is greater than a threshold level, then the condition is met. In one embodiment, if the second read retry rate (e.g., corresponding to V...) t2 If the read retry rate is greater than the threshold level, then the condition is met.

[0057] In operation 340, in response to a condition being met, the processing logic adjusts the first read cleanup frequency level to the second read cleanup frequency level and the first write cleanup frequency level to the second write cleanup frequency level. In one embodiment, the processing logic determines the second read cleanup frequency (e.g., the next read cleanup frequency) and the second read cleanup frequency by using, for example... Figure 4 The data structure of example table 400 shown performs a lookup operation. In one embodiment, the processing logic checks table 400 to determine the next cleanup frequency level. Continuing with the above example where the current level is level 0, the processing logic identifies level 1 as the next level in the process. The processing logic then identifies the read cleanup frequency level (e.g., read cleanup frequency 2) and the write cleanup frequency level (e.g., write cleanup frequency 2) corresponding to level 1. In this example, the processing logic adjusts the read cleanup frequency from 3 hours to 2 hours. In this example, the processing logic adjusts the write cleanup frequency from 12 hours to 8 hours.

[0058] In one embodiment, operations 310-350 can be performed iteratively (e.g., every set number of write cycles) so that the processing logic can repeatedly adjust the read cleanup frequency and write cleanup frequency throughout the lifetime of the memory device. Continuing with the above example, after identifying an operational characteristic value exceeding a threshold, the processing logic can adjust the read cleanup frequency of level 1 to an adjusted read cleanup frequency associated with level 2 (e.g., every 1 hour) and adjust the write cleanup frequency of level 1 to an adjusted write cleanup frequency associated with level 2 (e.g., every 4 hours). Iteration can continue to allow the process to adjust multiple levels and the read cleanup and write cleanup frequencies. In one embodiment, in response to a condition being met, the processing logic can also perform a write cleanup operation in addition to adjusting the read cleanup and write cleanup frequencies.

[0059] Figure 5 This describes an example machine of computer system 500, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein can be executed. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute the operating system to perform corresponding...). Figure 1 (The operation of the cleanup operation management component 113). In an alternative embodiment, the machine may be connected (e.g., network connected) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0060] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network equipment, server, network router, switch or bridge, digital or non-digital circuit system, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be performed by that machine. Furthermore, while a single machine is described, the term "machine" should also be understood to include any set of machines that individually or jointly execute a set (or sets of sets) of instructions to perform any one or more of the methods discussed herein.

[0061] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0062] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More precisely, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a network processor, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication over network 520.

[0063] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein are stored. Instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, both of which also constitute machine-readable storage media. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0064] In one embodiment, instruction 526 includes instructions for implementing a component corresponding to the read voltage regulation (e.g., Figure 1 The cleanup operation management component 113) provides functional instructions. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. It should also be considered that the term "machine-readable storage medium" includes any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0065] Some parts of the previously described algorithms and symbolic representations of the manipulation of data bits within computer memory have already been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and are generally considered, a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes, primarily for general reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0066] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0067] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0068] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices for performing the methods described herein. The structures of a wide variety of these systems will be presented as illustrated below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using a wide variety of programming languages.

[0069] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0070] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for performing memory operations, comprising: determining, by a processing device, a value corresponding to an operating characteristic of a memory sub-system; comparing the value to a first threshold level to determine if a first condition is satisfied; comparing the value to a second threshold level to determine if a second condition is satisfied; in response to the first condition being satisfied, performing a read scrub operation associated with the memory sub-system; and in response to the second condition being satisfied, performing a write scrub operation associated with the memory sub-system.

2. The method of claim 1, wherein the operating characteristic comprises a read retry rate associated with a read retry threshold voltage level.

3. The method of claim 2, wherein the read retry threshold voltage level is selected from a set of read retry threshold voltage levels comprising a first read retry threshold voltage level, a second read retry threshold voltage level, and a third read retry threshold voltage level.

4. The method of claim 2, wherein the read retry rate is determined based on comparing a first count of read retry operations associated with a second read retry threshold voltage level to a sum of counts of read retry operations associated with a plurality of read retry threshold voltage levels.

5. The method of claim 1, wherein the first condition is satisfied upon determining that the value is greater than the first threshold level.

6. The method of claim 1, wherein the second condition is satisfied upon determining that the value is greater than the second threshold level.

7. The method of claim 1, further comprising: determining another value corresponding to the operating characteristic of the memory sub-system; in response to determining that the other value is greater than the first threshold level, performing another read scrub operation associated with the memory sub-system; and in response to determining that the other value is greater than the second threshold level, performing another write scrub operation associated with the memory sub-system.

8. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: identifying a first read scrub frequency level and a first write scrub frequency level associated with a memory sub-system; determining a value corresponding to an operating characteristic of a memory sub-system; comparing the value to a threshold level to determine if a condition is satisfied; and in response to the condition being satisfied, adjusting the first read scrub frequency level to a second read scrub frequency level and adjusting the first write scrub frequency level to a second write scrub frequency level.

9. The non-transitory computer-readable medium of claim 8, the operations further comprising maintaining a data structure comprising a plurality of scrub frequency levels, wherein each scrub frequency level comprises a read scrub frequency level and a write scrub frequency level.

10. The non-transitory computer-readable medium of claim 9, the operations further comprising: in response to the condition being satisfied, performing a lookup operation of the data structure to identify the second read scrub frequency level and the second write scrub frequency level. ​ ​ ​ 11. The non-transitory computer-readable medium of claim 8, the operations further comprising: performing a write scrub operation in response to the condition being satisfied.

12. The non-transitory computer-readable medium of claim 8, the operations further comprising: determining another value corresponding to the operating characteristic of the memory sub-system; comparing the other value to the threshold level to determine whether the condition is satisfied; adjusting the second read scrub frequency level to a third read scrub frequency level in response to the condition being satisfied; and adjusting the second write scrub frequency level to a third write scrub frequency level in response to the condition being satisfied.

13. The non-transitory computer-readable medium of claim 12, wherein the second read scrub frequency level is greater than the third read scrub frequency level, and wherein the second write scrub frequency level is greater than the third write scrub frequency level.

14. The non-transitory computer-readable medium of claim 12, wherein the operating characteristic comprises a read retry rate associated with a read retry threshold voltage level.

15. A memory system, comprising: a memory component; and a processing device, operatively coupled with the memory component, to: determine a value corresponding to an operating characteristic of a memory sub-system; compare the value to a first threshold level to determine whether a first condition is satisfied; compare the value to a second threshold level to determine whether a second condition is satisfied; perform a read scrub operation associated with the memory sub-system in response to the first condition being satisfied; and perform a write scrub operation associated with the memory sub-system in response to the second condition being satisfied.

16. The memory system of claim 15, wherein the first condition is satisfied upon determining that the value is greater than the first threshold level.

17. The memory system of claim 15, wherein the operating characteristic comprises a read retry rate associated with a read retry threshold voltage level.

18. The memory system of claim 17, wherein the read retry threshold voltage level is selected from a set of read retry threshold voltage levels comprising a first read retry threshold voltage level, a second read retry threshold voltage level, and a third read retry threshold voltage level.

19. The memory system of claim 17, wherein the read retry rate is determined based on comparing a first count of read retry operations associated with a second read retry threshold voltage level to a sum of counts of read retry operations associated with a plurality of read retry threshold voltage levels.

20. The memory system of claim 15, wherein the processing device is further to: determine another value corresponding to the operating characteristic of the memory sub-system; perform another read scrub operation associated with the memory sub-system in response to determining that the other value is greater than the first threshold level; and perform another write scrub operation associated with the memory sub-system in response to determining that the other value is greater than the second threshold level. ​ ​

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