Memory device and method of operation thereof

Abstract

A memory device includes an array of memory cells including a plurality of memory cells, a voltage generator configured to generate voltages for program operations and verify operations of the memory cells, and control logic configured to perform a plurality of program loops while writing data to the array of memory cells such that a first through an Nth (e.g., N > 1) program loop including a program operation and a verify operation are performed, and when a pass / fail determination of the program operation in the Nth program loop indicates a pass, at least two program loops in which the verify operation is skipped are performed.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2020-0085683, filed on July 10, 2020, and Korean Patent Application No. 10-2020-0154579, filed on November 18, 2020, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to memory devices, and more specifically, to memory devices having improved write operation speeds and methods of operating thereof. Background Technology

[0004] Semiconductor memory is a digital electronic semiconductor memory used for storing digital data. Semiconductor memory can include non-volatile memory devices that retain stored information even after power is lost. Flash memory is an example of a non-volatile memory device. For example, flash memory is used in mobile phones, digital cameras, portable digital assistants (PDAs), mobile computing devices, and fixed computing devices.

[0005] Multiple program loops can be executed to write data to a non-volatile memory device. Each program loop can perform both a program operation and a verification operation. The write operation can take a long time due to the individual verification operations. In particular, increasing the number of verification operations can significantly increase the time required to complete the write operation. Summary of the Invention

[0006] At least one embodiment of the present invention provides a memory device and a method of operating the same that have improved write operation speed by performing optimal programming and verification operations.

[0007] According to an exemplary embodiment of the present invention, a memory device is provided, comprising: a memory cell array including a plurality of memory cells; a voltage generator configured to generate voltages for programming operations and verification operations of the memory cells; and control logic configured to execute a plurality of programming loops while writing data to the memory cell array, such that a first to Nth programming loop including programming operations and verification operations are executed, and when a pass / fail determination indication for a programming operation in the Nth programming loop passes, at least two programming loops in which the verification operation is skipped are executed. N is an integer equal to or greater than 1.

[0008] According to an exemplary embodiment of the present invention, a method for operating a memory device is provided, the method comprising: executing an Nth programming cycle including a programming operation and a verification operation; determining whether a programming operation is successful or unsuccessful by counting the number of memory cells of the memory device having a threshold voltage level below a predetermined threshold voltage; when it is determined that the programming operation is successful, executing a (N+1)th programming cycle, the (N+1)th programming cycle including a normal programming operation on a first memory cell among the memory cells using a normal programming voltage, and a forced programming operation on a second memory cell among the memory cells using a forced programming voltage; and executing a (N+2)th programming cycle, the (N+2)th programming cycle including a forced programming operation on the first memory cell using a forced programming voltage, wherein a verification operation is skipped in each of the (N+1)th and (N+2)th programming cycles. N is an integer equal to or greater than 1.

[0009] According to an exemplary embodiment of the present invention, a method for operating a memory device is provided. The method includes: executing first to Nth programming cycles, each programming cycle including a programming operation and a verification operation for memory cells of the memory device; determining whether a programming operation is successful or unsuccessful based on the programming result in the Nth programming cycle; and, when it is determined that the programming operation is successful, executing (N+1) to (N+A)th programming cycles excluding the verification operation for memory cells. In each of the (N+1) to (N+A)th programming cycles, at least one of a normal programming operation using a normal programming voltage and a forced programming operation using a forced programming voltage is performed. N is an integer equal to or greater than 2, and A is an integer equal to or greater than 2. Attached Figure Description

[0010] Embodiments of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram illustrating an example embodiment of a memory system according to a concept of the present invention;

[0012] Figure 2 It is shown Figure 1 A block diagram illustrating an example implementation of a memory device;

[0013] Figure 3 This is a diagram illustrating an example of a two-step verification operation according to an exemplary embodiment of the concept of the present invention;

[0014] Figure 4 This is a flowchart of a method for operating a memory device according to an exemplary embodiment of the present invention;

[0015] Figure 5This is a block diagram illustrating an example implementation of a memory device according to an exemplary embodiment of the concept of the present invention;

[0016] Figure 6 This is a flowchart illustrating a detailed implementation of a write operation according to an exemplary embodiment of the present invention.

[0017] Figure 7A , Figure 7B and Figure 7C An example of threshold voltage distribution fluctuations during the execution of a programming loop is shown, according to an exemplary embodiment of the present invention.

[0018] Figure 8 , Figure 9A and Figure 9B This is a flowchart illustrating a write operation of an example embodiment of the concept according to the present invention;

[0019] Figure 10 This is a diagram illustrating an example implementation of a memory device according to an exemplary embodiment of the concept of the present invention;

[0020] Figure 11 This is a block diagram illustrating an example of a memory device according to an embodiment of the present invention being applied to a solid-state drive (SSD) system;

[0021] Figure 12 This is an embodiment of the concept of the present invention. Figure 2 A perspective view of an example implementation of a memory block; and

[0022] Figure 13 This is a cross-sectional view of a memory device according to an embodiment of the present invention. Detailed Implementation

[0023] Figure 1 This is a block diagram illustrating an example embodiment of a memory system according to a concept of the present invention.

[0024] refer to Figure 1 The memory system 10 includes a memory controller 100 (e.g., control circuitry) and a memory device 200. The memory device 200 includes a memory cell array 210, a voltage generator 220 (or voltage controller), and control logic 230 (e.g., logic circuitry). The control logic 230 includes a programming loop controller 231 (e.g., control circuitry). Although... Figure 1An example is shown in which the programmable loop controller 231 is included in the control logic 230; however, the programmable loop controller 231 according to embodiments of the present invention may be a separate component located outside the control logic 230. Furthermore, the programmable loop controller 231 may perform the functions of embodiments of the present invention in various ways. For example, the programmable loop controller 231 may be implemented as hardware circuitry, processor-executable software, or a combination of hardware circuitry and software.

[0025] According to an example embodiment, memory device 200 includes a non-volatile memory device. In some embodiments, memory system 10 may be implemented as a memory that can be embedded in or removed from an electronic device. For example, memory system 10 may be implemented in various forms, such as embedded universal flash memory (UFS) devices, embedded multimedia cards (eMMC), solid-state drives (SSDs), UFS memory cards, compact flash (CF) cards, secure digital (SD) memory cards, micro-secure digital (Micro-SD) memory cards, mini-secure digital (Mini-SD) memory cards, extreme digital (xD) memory cards, or memory sticks.

[0026] The memory controller 100 can control the memory device 200 to read data stored in or write data to the memory device 200 in response to write / read requests from the host. Specifically, the memory controller 100 can provide the memory device 200 with an address (ADDR), a command (CMD), and a control signal (CTRL) to control write, read, and erase operations on the memory device 200. Furthermore, data to be stored in the memory device 200 and data read from the memory device 200 can be sent and received between the memory controller 100 and the memory device 200.

[0027] The memory cell array 210 may include a plurality of memory cells. For example, a memory cell may be a flash memory cell. In the following, embodiments of the inventive concept will be described in detail based on the example case where the memory cell is a NAND flash memory cell. However, the inventive concept is not limited thereto, and in some embodiments, the memory cell may be a resistive memory cell, such as a resistive RAM (ReRAM) cell, a phase-change RAM (PRAM) cell, and a magnetic RAM (MRAM) cell.

[0028] In one embodiment, the memory cell array 210 includes a three-dimensional memory cell array. The three-dimensional memory cell array may include multiple NAND strings, and each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. The disclosures of U.S. Patent Publications 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application Publication 2011 / 0233648 are incorporated herein by reference in their entirety and disclose detailed suitable configurations of three-dimensional memory arrays including multiple levels in which word lines and / or bit lines are shared between levels. However, the inventive concept is not limited thereto. In some embodiments, the memory cell array 210 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include multiple NAND arrays arranged in a row-wise and column-wise direction.

[0029] When a write command requesting a write operation is provided from the memory controller 100 to the memory device 200, the write operation can be performed under the control of the control logic 230. The write operation can be performed through multiple programming cycles, and the period during which the programming cycles are executed can be referred to as a program cycle. In other words, the operation for writing data to the memory cells of the memory cell array 210 can include multiple programming cycles within a programming cycle. A programming operation using a programming voltage and a verification operation using a verification voltage can be performed in any programming cycle. In an exemplary embodiment of the inventive concept, the programming and verification operations are performed together in some programming cycles, while the programming operation is performed selectively only in other programming cycles.

[0030] Voltage generator 220 can generate various voltages used in memory device 200. For example, it can generate a programming voltage supplied to selected word lines for programming operations, and an inhibit voltage supplied to unselected word lines. Furthermore, voltage generator 220 can also generate a verification voltage for verifying programming operations and an erase voltage supplied to word lines during erase operations. Additionally, although not in... Figure 1 As shown, voltage generator 220 can also generate series select voltage and ground select voltage that are respectively provided to series select line and ground select line.

[0031] Control logic 230 can control the overall operation of memory device 200. For example, based on the command CMD, address ADDR, and control signal CTRL received from memory controller 100, control logic 230 can output various internal control signals for programming data into or reading data from memory cell array 210. Furthermore, control logic 230 can output voltage control signals (not shown) for adjusting the levels of various voltages output from voltage generator 220 relative to programming, reading, and erasing operations.

[0032] According to an example embodiment, the programming cycle controller 231 controls the programming cycle executed to write data to the memory cell array 210. For example, the programming cycle controller 231 can control the programming cycle in various ways. For example, the programming cycle controller 231 can control the number of programming cycles within a programming cycle, or control various voltage levels for the programming and verification operations used in each programming cycle. For example, the programming cycle controller 231 can perform a determination operation to determine whether a programming operation passes or fails during the execution of a programming cycle. Based on the determination result, subsequent programming cycles can be controlled to skip the verification operation. Furthermore, according to an embodiment of the present invention, when the determination result is pass, subsequent programming cycles are controlled such that the verification operation is skipped in at least two subsequent programming cycles. In other words, in an embodiment of the present invention, because the number of programming cycles in which the verification operation is executed within a programming cycle is reduced, the time taken for the data writing operation can be reduced.

[0033] Figure 2 It is shown Figure 1 A block diagram illustrating an example implementation of a memory device.

[0034] refer to Figure 1 and Figure 2 The memory device 200 includes a memory cell array 210, a voltage generator 220, control logic 230, a row decoder 240 (e.g., decoder circuitry), and a page buffer 250. Although not explicitly stated... Figure 2 As shown, however, memory device 200 may also include various other components related to memory operation, such as data input / output circuitry or input / output interfaces.

[0035] The memory cell array 210 may include multiple memory blocks BLK1 to BLKz and may be connected to word line WL, serial select line SSL, ground select line GSL, and bit line BL. The memory cell array 210 can be connected to the row decoder 240 via word line WL, serial select line SSL, and ground select line GSL, and can be connected to the page buffer 250 via bit line BL. Each memory cell can store one or more bits. For example, each memory cell may correspond to a single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), or four-level cell (QLC).

[0036] Control logic 230 can output various internal control signals based on the command CMD, address ADDR, and control signal CTRL received from memory controller 100, for programming data to or reading data from memory cell array 210. Control logic 230 can also output a voltage control signal CTRL_vol to control the levels of various voltages generated by voltage generator 220. Furthermore, Figure 2 The programmable loop controller 231 and pass / fail determiner 232 (e.g., determination circuitry) are shown as components included in control logic 230. However, embodiments of the inventive concept are not necessarily limited thereto, and at least one of the programmable loop controller 231 and pass / fail determiner 232 may be located outside of control logic 230.

[0037] Control logic 230 can provide row address X_ADDR to row decoder 240 and column address Y_ADDR to page buffer 250. During programming operations, in response to row address X_ADDR, row decoder 240 can provide programming voltage to the word line of the selected memory cell and disable voltage to the word line of the unselected memory cell.

[0038] According to an exemplary embodiment of the present invention, the memory device 200 performs a programming operation based on a two-step verification operation. For example, multiple programming cycles can be executed within a programming cycle, and after a programming operation is performed in any programming cycle, a verification operation can be performed using at least two verification voltages. For example, the two-step verification operation may include a first verification operation using a pre-verification voltage VV_P and a second verification operation using a main verification voltage VV_M. In an embodiment, the main verification voltage VV_M has a value greater than the pre-verification voltage VV_P.

[0039] From a plurality of memory cells to which programming operations have been performed, a first memory cell having a threshold voltage less than a predetermined first threshold voltage can be determined by a first verification operation, and this first memory cell can be referred to as a coarse-on cell. Furthermore, by a second verification operation, memory cells having a threshold voltage less than a predetermined second threshold voltage (e.g., the second threshold voltage is set to be greater than the first threshold voltage) can be determined, and these memory cells can be referred to as fine-on cells. Moreover, in the following embodiments, based on the first and second verification operations, a memory cell having a threshold voltage greater than the first threshold voltage and less than the second threshold voltage can be defined as a second memory cell.

[0040] Furthermore, the above description describes performing the main verification operation and the pre-verification operation using a main verification voltage VV_M and a pre-verification voltage VV_P with different levels, respectively. However, embodiments of the inventive concept are not limited thereto. For example, in the verification operation, the operation of determining data based on different threshold voltage levels can be performed in various ways. For example, the verification operation can be performed in various ways by setting the level of the current used in the verification operation or by setting the sensing timing of the data.

[0041] In the next programming cycle, programming operations can be performed based on the results of the above verification. During programming operations, different types of programming operations can be performed on the memory cells identified as the first and second memory cells. For example, a normal programming operation can be performed on the first memory cell, while a forced programming operation can be performed on the second memory cell. Compared to a normal programming operation, in a forced programming operation, the difference between the voltage levels applied between the word lines and bit lines connected to the memory cell is smaller than the difference between the voltage levels applied between the word lines and bit lines in a normal programming operation. Therefore, the threshold voltage level changed due to the forced programming operation can be smaller than the threshold voltage level of the normal programming operation. For example, various voltage levels can be set for the bit lines (BL) during programming operations. When BL is forced during a forced programming operation, the voltage level set to the bit lines can be greater than the voltage level of the normal programming operation. Alternatively, the programming voltage level applied to the word lines during a forced programming operation can be set to a level lower than the programming voltage level of the normal programming operation.

[0042] In the following embodiments, it is assumed that the voltage level applied to the word lines during a forced programming operation (e.g., forced programming voltage VP_F) is relatively small compared to the voltage level applied to the word lines during a normal programming operation (e.g., normal programming voltage VP_N). However, as described above, embodiments of the inventive concept are not necessarily limited to this. When a forced programming operation is performed by setting a bit line setup, the bit line setup levels are set differently in normal and forced programming operations. In embodiments, the word lines are provided with substantially the same or identical voltage levels in both forced and normal programming operations.

[0043] According to an embodiment of the present invention, the programming loop controller 231 can control the operation of the programming loop within a programming cycle. According to an example embodiment, in each programming loop, the programming loop controller 231 can perform control operations on various environmental settings (such as voltage levels associated with programming and verification operations). Furthermore, the programming loop controller 231 can determine whether to perform a verification operation in each programming loop and perform control operations such that the verification operation is performed or skipped.

[0044] In an embodiment, the pass / fail determiner 232 receives data DATA through the page buffer 250 and determines the pass / fail of the programming operation based on the result of determining the state of the data DATA. In an example embodiment, the pass / fail of the programming operation is determined by determining the number of memory cells (e.g., coarse-conducting cells) with a threshold voltage less than a first threshold voltage or the number of memory cells (e.g., fine-conducting cells) with a threshold voltage less than a second threshold voltage. In an example embodiment of the inventive concept, when a predetermined reference value is set and the number of coarse-conducting cells or the number of fine-conducting cells (or the number of failed memory cells) is less than the reference value, the corresponding programming operation can be determined to be pass.

[0045] According to an exemplary embodiment of the present invention, after the pass / fail determiner 232 determines that the programming operation has passed, at least two more programming cycles can be further executed. For example, when the number of failed memory cells is less than a reference value, this can indicate that by performing a small number of additional programming cycles, all memory cells have a threshold voltage corresponding to the threshold voltage of the passed memory cells, and in an embodiment of the present invention, the verification operation is skipped in the additional programming cycles. In other words, compared to terminating the programming cycle after a pass has been determined following the execution of a general programming cycle, in an embodiment of the present invention, the verification operation is skipped in the additional programming cycle after a pass has been determined. Therefore, because the number of verification operations performed in a single programming cycle can be reduced, the overall write operation time can be reduced.

[0046] Simultaneously, the page buffer 250 can operate as a write driver or a sense amplifier depending on the operating mode. The page buffer 250 may include multiple buffer units connected to multiple bit lines BL. Each buffer unit may include one or more latches storing read data via a corresponding bit line BL. The aforementioned bit line setting operations can be performed through the page buffer 250, and the bit lines BL can be set to different levels for memory cells that are disabled for programming, memory cells to which normal programming operations are to be performed, and memory cells to which forced programming operations are to be performed. For example, data read during pre-verification operations and data read during main verification operations can be stored in the page buffer 250. Based on the data stored in the page buffer 250, a first memory cell and a second memory cell can be determined, and a pass / fail determination operation can be performed based on this data.

[0047] Figure 3 This is a diagram illustrating an example of a two-step verification operation according to an exemplary embodiment of the concept of the present invention. Figure 3 An example of the threshold voltage distribution of a memory cell to which programming operations have been performed is shown.

[0048] refer to Figure 2 and Figure 3 In the case of a memory cell to which data is to be written, multiple programming cycles can be executed such that, based on the data value, the memory cell has a threshold voltage greater than a second threshold voltage Vth2. Within any programming cycle, a two-step verification operation can be performed after the programming operation, and coarse-conducting cells and fine-conducting cells can be determined by performing the verification operation based on a first threshold voltage Vth1 and a second threshold voltage Vth2. The two-step verification operation can be performed based on the first threshold voltage Vth1, which can be referred to as a coarse read. Furthermore, the two-step verification operation can be performed based on the second threshold voltage Vth2, which can be referred to as a fine read. Due to the characteristics of the memory cell, the memory cell can exhibit different threshold voltage fluctuations depending on the execution of the programming operation, and even when the memory cells undergo the same programming cycle, some slower cells may have a lower threshold voltage level than other memory cells. Therefore, coarse-conducting cells and fine-conducting cells can coexist.

[0049] After the two-step verification operation described above is completed, the programming operation can be performed in the next programming cycle. For example, a normal programming operation using the normal programming voltage VP_N can be performed on the first memory cell corresponding to the coarse-on cell, and a forced programming operation using the forced programming voltage VP_F can be performed on the second memory cell corresponding to the coarse-off / fine-on cell. Furthermore, the two-step verification operation can be performed based on the first threshold voltage Vth1 and the second threshold voltage Vth2. Through the programming operation, the memory cell MC1 previously corresponding to the coarse-on cell can be changed to a fine-on cell, and the memory cell MC2 previously corresponding to the coarse-off / fine-on cell can be changed to a fine-off cell.

[0050] Figure 4 This is a flowchart of a method for operating a memory device according to an exemplary embodiment of the present invention.

[0051] refer to Figure 4 In a memory system including a memory controller and memory devices, in response to a write request from the host, the memory controller 100 provides a write command to the memory device 200, and the memory device 200 performs a write operation including multiple programming cycles in response to the write command. Furthermore, in an example embodiment, after executing a specific number of programming cycles, the threshold voltage of multiple memory cells in the memory cell array 210 among the memory cells to be programmed can be increased above a target voltage. Therefore, the timing (or time) for determining the success / failure of the programming operation can be performed after executing the aforementioned specific number of programming cycles.

[0052] In response to the write command, the first to Nth programming cycles are executed (operation S11), and in each of the first to Nth programming cycles, a programming (PGM) operation and a verification operation are performed. Furthermore, in the example embodiment, the first to Nth programming cycles are controlled such that initially only programming operations are performed, and subsequently, verification operations are performed from a specific point in time. Furthermore, in the example embodiment, the first to Nth programming cycles are controlled such that initially only normal programming operations using the normal programming voltage are performed, and subsequently, forced programming operations are performed from a specific point in time. Furthermore, according to the above embodiments, a two-step verification operation can be applied to the verification operation; therefore, a verification operation using a pre-verification voltage and a main verification voltage can be performed. As a result, coarse conduction units and fine conduction units can be determined.

[0053] During the execution of the first to Nth programming cycles described above, it is determined whether a timing (or time) is used to determine pass / fail. For example, it can be determined that the timing (or time) for determining pass / fail is after the Nth programming cycle is executed (operation S12). In the case of timing for determining pass / fail, a coarse conducting unit or a fine conducting unit is determined based on the result of executing the Nth programming cycle (operation S13), and the programming operation is determined to be passed based on the determined result (operation S14). For example, the pass / fail determination operation can be performed by determining whether the number of coarse conducting units is less than a predetermined reference value or whether the number of fine conducting units is less than a predetermined reference value. In other words, when the number of coarse conducting units or fine conducting units is less than a predetermined reference value, this can indicate a state where the threshold voltage of a relatively large number of memory cells in the memory cells to be programmed increases above the target voltage and the programming operation is completed normally. At the same time, Figure 4 In this embodiment, it is assumed that the pass / fail determination operation results in a pass. However, if the programming operation is determined to be a failure, an additional programming loop and the aforementioned pass / fail determination operation are executed again.

[0054] According to an exemplary embodiment of the present invention, when it is determined that the programming operation is successful, the write operation can be completed by executing a programming loop in which multiple verification operations are skipped. For example, after determining that the programming operation is successful, programming loops (N+1) to (N+A) can be executed sequentially (operations S15 and S16), and verification operations can be skipped in programming loops (N+1) to (N+A). Furthermore, in the exemplary embodiment, a programming operation using at least one of a normal programming voltage and a forced programming voltage is performed in each of programming loops (N+1) to (N+A), and the write operation can be completed after executing programming loops (N+1) to (N+A).

[0055] According to an example embodiment of the inventive concept described above, multiple programming loops excluding verification operations can be executed based on the result of determining that the programming operation has passed. Since multiple programming loops in which verification operations are not performed are executed during the entire write operation, the total number of verification operations can be reduced. Furthermore, by appropriately applying the normal programming voltage and forcing programming operations based on the number of coarse and fine conducting cells in the (N+1) to (N+A)th programming loops in which verification operations are skipped, the programming operation can be adjusted such that when the threshold voltage distribution of the memory cells increases above the target voltage, the threshold voltage does not increase much more than the target voltage, thus preventing the distribution width from widening.

[0056] Furthermore, in the following description of embodiments of the inventive concept, terminating the programming operation upon completion of the programming cycle can indicate that the write operation in response to a write command from the memory controller is terminated.

[0057] Figure 5 This is a block diagram illustrating an example implementation of a memory device according to an exemplary embodiment of the concept of the present invention. Figure 5 An example of how the control logic provided in a memory device is implemented is shown.

[0058] refer to Figure 5 The control logic 300 includes a programmable control circuit 310, a loop counter 320 (e.g., a counter circuit), a two-step verification circuit 330, and a pass / fail determination circuit 340. Figure 1 The programmable loop controller shown may include Figure 5 At least some of the components of the control logic 300 shown.

[0059] The programming control circuit 310 can perform various control operations related to data writing in the memory device and output control signals for controlling other components. For example, the programming control circuit 310 can output a voltage control signal CTRL_vol to control the voltage generator 301 in the memory device, output a row address X-ADDR to the row decoder, and output a column address Y-ADDR to the column decoder (or page buffer). Based on the row address X-ADDR and the column address Y-ADDR, two-step verification operations and programming operations based on the two-step verification operations can be controlled. For example, normal programming operations can be performed on some memory cells among the memory cells to be programmed, forced programming operations can be performed on some other memory cells, and programming operations on other memory cells can be prohibited.

[0060] The loop counter 320 may be internally set with at least one reference value to count the number of times the programming loop is executed to generate a counting result and provide a result comparing the counting result with the reference value. In an example embodiment, based on the counting result of the loop counter 320, it can be determined whether to start execution at a time determined by pass / fail while executing the programming loop. Furthermore, after determining that the programming operation is successful, a counting operation can be performed to further execute the programming loop a predetermined number of times.

[0061] The two-step verification circuit 330 can determine coarse and fine conduction units through the verification operation according to the above embodiment. For example, the two-step verification circuit 330 can receive data DATA read using the pre-verification voltage VV_P and data DATA read using the main verification voltage VV_M from the page buffer, and determine the coarse and fine conduction units based on the data DATA. Furthermore, through the above two-step verification operation, a first memory cell corresponding to the coarse conduction unit and a second memory cell corresponding to the coarse cutoff / fine conduction unit can be determined. Furthermore, the pass / fail determination circuit 340 can determine whether the programming operation passes or fails based on the verification result of the two-step verification circuit 330. According to the above embodiment, by comparing the number of coarse or fine conduction units with a predetermined reference value, the pass / fail determination circuit 340 can determine whether the programming operation passes or fails.

[0062] The programming control circuit 310 can perform various control operations based on the determination result of the pass / fail determination circuit 340. For example, when the determination result is failure, the programming control circuit 310 can output a voltage control signal CTRL_vol, causing the output of the normal programming voltage VP_N, the forced programming voltage VP_F, the main verification voltage VV_M, and the pre-verification voltage VV_P. As a result, programming and verification operations can be performed in the next programming cycle. On the other hand, when the determination result is pass, the programming control circuit 310 can output a voltage control signal CTRL_vol, causing the verification operation to be skipped in the next programming cycle, and only the normal programming voltage VP_N and the forced programming voltage VP_F to be output. Figure 5 An example is shown in which the normal programming voltage VP_N and the forced programming voltage VP_F are generated in the first through (N+A) programming cycles, while the main verification voltage VV_M and the pre-verification voltage VV_P are selectively generated in the first through N programming cycles.

[0063] According to the example embodiment described above, a counter (not shown) capable of counting the bit values ​​of multiple memory cells can be provided in the pass / fail determination circuit 340. Whether a programming operation passes or fails can be determined in advance based on the counter's count result, and the write operation can be completed by performing at least two programming operations while skipping the verification operation based on the determined result. Therefore, the total time used for the write operation can be reduced.

[0064] Figure 6 This is a flowchart illustrating a detailed implementation of a write operation according to an exemplary embodiment of the present invention.

[0065] refer to Figure 6During operation S21, a normal programming cycle is executed. This normal programming cycle can correspond to a programming cycle that includes the programming and verification operations described in the above embodiments. Furthermore, the memory device can be pre-configured so that a pass / fail determination is performed in the (N-2)th programming cycle. In the (N-2)th programming cycle, a normal programming operation is performed on the first memory cell corresponding to the coarse turn-on unit, while a forced programming operation (operation S22) is performed on the second memory cell corresponding to the coarse turn-off / fine turn-on unit. Because incremental step pulse program (ISPP) is applied during the normal programming operation, in which the level of the programming pulse gradually increases as the programming cycle is executed, the normal programming operation... Figure 6 This is referred to as the ISPP programming operation.

[0066] On the other hand, the success or failure of the programming operation can be determined in the (N-2)th programming loop (operation S23). For example, the success or failure of the programming operation can be determined by comparing the number of coarse or fine conduction units determined by the previous verification operation with the reference value Ref. According to an embodiment, the success or failure of the programming operation can be determined in the (N-2)th programming loop based on the data stored in the page buffer by the previous verification operation (e.g., the verification operation performed in the (N-3)th programming loop). Furthermore, in an example embodiment, the success / failure determination operation in the (N-2)th programming loop can be executed in parallel with the programming operation in the next (N-1)th programming loop.

[0067] When a programming operation is determined to have failed, the programming loop, which includes a two-step verification operation (operation S24) and a programming operation (operation S22), can be executed again, and the success or failure of the programming operation can be determined again based on the result of the verification operation. On the other hand, when a programming operation is determined to have succeeded, according to an example embodiment of the present invention, two or more additional programming loops in which the two-step verification operation is skipped can be executed.

[0068] When it is determined in the (N-1)th programming cycle that the programming operation is successful without performing a verification operation, a normal programming operation can be performed on the first memory cell corresponding to the coarsely turned-on cell, while a forced programming operation can be performed on the second memory cell corresponding to the coarsely turned-off / finely turned-on cell (operation S25). Furthermore, the next programming cycle (e.g., the Nth programming cycle) can be executed. In the Nth programming cycle, a programming operation can be selectively performed on the memory cells that were determined to be coarsely turned-on cells in the previous verification process, where the programming operation can be a forced programming operation (operation S26).

[0069] According to the example embodiment described above, a write operation can be completed by performing two or more programming operations without performing a separate verification operation after confirming that the programming operation has passed. For example, after confirming that the programming operation has passed, there may be a first memory cell corresponding to a coarse turn-on unit and a second memory cell corresponding to a coarse turn-off / fine turn-on unit, and the write operation can be completed by performing a normal programming operation and a forced programming operation on the first memory cell and a forced programming operation on the second memory cell.

[0070] Figure 7A , Figure 7B and Figure 7C An example of threshold voltage distribution fluctuations during the execution of a programming loop is shown, according to an exemplary embodiment of the present invention. Figure 7A , Figure 7B and Figure 7C An operational example in a memory device comprising multiple levels of cells is shown.

[0071] A memory cell can be programmed, based on its data value, into any one of a plurality of states corresponding to a plurality of threshold voltage distributions. For example, a threshold voltage distribution can have four or more states. Figure 7A An example of a threshold voltage distribution with first state P1 to (n+3)th state P(n+3) is illustrated. First state P1 may correspond to an erase state, and when a programming cycle is executed, the threshold voltage of the memory cell can change from first state P1 to second state P2 to (n+3)th state P(n+3). In each programming cycle, programming operations for programming the memory cell into multiple states can be performed. Furthermore, in each programming cycle, a verification operation can be performed relative to each state to verify the programming operations for each state.

[0072] Figure 7B An example is shown of the voltage (or voltage pulse) applied to the selected word line during a programming loop. Figure 7B For ease of explanation, the programming operations related to state Pn in the Nth to (N+2th)th programming loops and the verification operations for states n to (n+3th)th are illustrated. Furthermore, Figure 7C An example of threshold voltage distribution fluctuations based on programming operations associated with state n Pn is shown. Furthermore, pass / fail can be determined at predetermined timings (or times). In the example embodiment, pass / fail of a state can be determined at different timings (or times). For example, it is assumed that pass / fail determination of state n Pn is performed in the Nth programming loop, pass / fail determination of state (n+1) Pn+1 is performed in the (N+1)th programming loop, and pass / fail determination of state (n+2) Pn+2 is performed in the (N+2)th programming loop. Furthermore, Figure 7CExamples of programming operations performed in each programming loop of the programming operations used to program to the nth state Pn and the (n+1)th state Pn+1 are also shown.

[0073] First, a programming voltage for programming operations can be applied in the Nth programming cycle, and the two-step verification operation described in the above embodiment can be performed for each of the nth to (n+3)th states. Furthermore, the coarse turn-on unit (first memory unit) and the coarse turn-off / fine turn-on unit (second memory unit) can be determined relative to the nth state, and it is assumed that the programming operation is determined to be successful based on the result of the pass / fail determination of the programming operation in the nth state.

[0074] Based on the operations in the Nth programming loop as described above, the verification operations related to the nth state can be skipped in subsequent programming loops, as shown by the dashed lines. Furthermore, in the (N+1)th programming loop, normal programming operations can be performed on the first memory cell, and forced programming operations can be performed on the second memory cell. Figure 7C An example is shown where, based on the programming operation in the (N+1)th programming loop, the first memory cell is changed to a coarse cutoff / fine on cell, and the second memory cell is changed to a fine cutoff cell. Furthermore, in the (N+1)th programming loop, a pass / fail determination can be performed relative to the (n+1)th state. When the programming operation is determined to be pass, the verification operation associated with the (n+1)th state can be skipped in the next programming loop (e.g., the (N+2)th programming loop).

[0075] In the (N+2)th programming loop, a forced programming operation can be selectively performed only on the coarse cutoff / fine on unit associated with the nth state, and the coarse cutoff / fine on unit can be changed to a fine cutoff unit based on the forced programming operation. Furthermore, in the (N+2)th programming loop, normal programming and forced programming operations can be performed relative to the (n+1)th state, and the forced programming operation can be performed in the next programming loop. Additionally, regarding the (n+2)th state, a pass / fail determination can be performed in the (N+2)th programming loop. According to the above embodiment, when the programming operation is determined to be pass, the verification operation can be skipped in at least two programming loops where the programming operation up to the (n+2)th state is executed.

[0076] Figure 8 , Figure 9A and Figure 9B This is a flowchart illustrating a write operation of an example embodiment of the concept according to the present invention.

[0077] refer to Figure 8The first to Nth programming cycles are executed (operation S31), and programming and verification operations according to the above embodiments can be performed in the first to Nth programming cycles. Furthermore, the success or failure of the programming operation is determined at a predetermined time (or period), and it can be determined that the programming operation is successful (operation S32).

[0078] When executing the Nth programming loop, the memory cells can have various threshold voltages, and through a two-step verification operation, the first memory cell corresponding to the coarse-on cell and the second memory cell corresponding to the coarse-off / fine-on cell can be determined. Furthermore, it is determined whether the first memory cell does not exist and only the second memory cell exists (operation S33). When the first memory cell does not exist and only the second memory cell exists, a programming loop using a forced programming voltage is executed without additional verification operations (operation S34). Therefore, after performing a forced programming operation on the second memory cell, the write operation is completed.

[0079] On the other hand, when a first memory cell and a second memory cell are present, at least two programming cycles can be executed without performing additional verification operations. For example, in the (N+1)th programming cycle, a normal programming operation can be performed on the first memory cell using a normal programming voltage, and a forced programming operation can be performed on the second memory cell using a forced programming voltage (operation S35). Furthermore, by using a forced programming voltage in the (N+2)th programming cycle, a forced programming operation can be performed on the first memory cell (operation S36).

[0080] According to the above embodiments, the number of additional programming loops that do not perform verification operations can vary based on the threshold voltage distribution of the memory cells in the pass / fail determination operation. Therefore, the threshold voltage distribution of multiple memory cells can be effectively adjusted during a write operation.

[0081] Figure 9A and Figure 9B This illustrates a case where three or more programming loops are executed, in which the verification operation is skipped.

[0082] refer to Figure 9A The first to Nth programming cycles are executed (operation S41), and programming and verification operations according to the above embodiments can be performed in the first to Nth programming cycles. Furthermore, it is determined whether the programming operation succeeds or fails at a predetermined time (or period). It can be determined that the programming operation succeeds (operation S42).

[0083] When the Nth programming loop is executed, the memory cells can have various threshold voltages, and the number of first memory cells corresponding to the coarse-conduction cells is determined (operation S43). For example, the number of first memory cells can be compared with a predetermined reference value Ref_1. When the number of first memory cells is less than the reference value Ref_1, this indicates that the number of memory cells with threshold voltages less than the first threshold voltage is relatively small, which is the standard for coarse-conduction cells. In other words, when the number of coarse-conduction cells is relatively small, the write operation can be completed by executing two additional programming loops. For example, the write operation can be completed by executing the (N+1)th programming loop and the (N+2)th programming loop (operation S44).

[0084] On the other hand, when the number of first memory cells is greater than the reference value Ref_1, this indicates that the number of memory cells with a threshold voltage less than the first threshold voltage is relatively large, which is the standard for coarsely turned-on cells. In other words, when the number of coarsely turned-on cells is relatively large, more additional programming loops in which verification operations are skipped can be executed. For example, a write operation can be completed by executing programming loops (N+1) to (N+3) (operation S45).

[0085] Meanwhile, in operation S45, which executes programming loops (N+1) to (N+3), programming operations can be performed in various ways. (See reference) Figure 9B In the (N+1)th programming loop, a normal programming operation using the normal programming voltage can be performed on the first memory cell, and a forced programming operation using the forced programming voltage can be performed on the second memory cell (operation S45_1). Furthermore, in the (N+2)th programming loop, programming of the second memory cell can be disabled, and a normal programming operation using the normal programming voltage can be selectively performed only on the first memory cell (operation S45_2). Furthermore, in the (N+3)th programming loop, programming of the second memory cell can be disabled, and a forced programming operation using the forced programming voltage can be selectively performed only on the first memory cell (operation S45_3).

[0086] Figure 9B The illustrated embodiments are descriptions of possible operations, and embodiments of the inventive concept are not necessarily limited thereto. For example, additional programming loops that skip verification operations can be performed, and different types of programming operations can be applied to the corresponding programming loops. For example, the programming loops can also be controlled such that forced programming operations are performed on the first memory cell in the (N+2)th and (N+3)th programming loops. Alternatively, the programming loops can also be controlled such that forced programming operations are performed on the first memory cell in the (N+1)th through (N+3)th programming loops.

[0087] Figure 10 This is a diagram illustrating an example implementation of a memory device according to an exemplary embodiment of the concept of the present invention. Figure 10 The page buffer 400 provided in the memory device and examples of the operation of the page buffer 400 in multiple programming loops are shown.

[0088] Page buffer 400 may include multiple buffer units (e.g., first buffer unit BU1 to Kth buffer unit BUK) corresponding to bit lines BL1 to BLK respectively. Each buffer unit can be used as a sense amplifier during data read or verification operations, and can also perform the functions of a write driver during write operations. Furthermore, although not in Figure 10 As shown in the figure, each buffer unit may include one or more latches (not shown) for storing written data and / or read data.

[0089] In the Nth programming loop, which performs programming and verification operations, a setting operation can be performed on bit lines BL1 to BLK to execute the programming operation. Through the setting operation, bit lines BL1 to BLK can be set to various voltage levels. For example, in a normal programming operation, the bit lines corresponding to memory cells that are disabled for programming can be set to the power supply voltage, while the bit lines corresponding to memory cells to be programmed can be set to ground. Furthermore, in a forced programming operation based on BL, the bit lines corresponding to memory cells that are disabled for programming can be set to the power supply voltage, while the bit lines corresponding to memory cells to be programmed can be set to a voltage with a level between ground and the power supply voltage.

[0090] Simultaneously, in the Nth programming loop, when performing the 2-step verification operation, data can be read based on at least two threshold voltages, and the read data can be provided to the page buffer 400 via bit lines BL1 to BLK. For example, data can be read based on a first threshold voltage and provided to the page buffer 400 via bit lines BL1 to BLK, while data can also be read based on a second threshold voltage greater than the first threshold voltage and provided to the page buffer 400 via lines BL1 to BLK. For example, coarse turn-on and coarse turn-off units can be determined based on the data DATA_C read based on the first threshold voltage, and fine turn-on and fine turn-off units can be determined based on the data DATA_F read based on the second threshold voltage. Furthermore, the data DATA_C and data DATA_F can be stored in latches (not shown) in the page buffer 400.

[0091] On the other hand, in the (N+1)th and (N+2)th programming loops where verification operations are skipped, setup operations for bit lines BL1 to BLK can be selectively performed without receiving data through the page buffer 400. For example, in each of the (N+1)th and (N+2)th programming loops, at least one of a bit line setup operation for performing normal programming operations and a bit line setup operation for performing forced programming operations can be performed.

[0092] Figure 11 This is a block diagram illustrating an example of a memory device according to an embodiment of the present invention being applied to a solid-state drive (SSD) system.

[0093] refer to Figure 11 The SSD system 500 includes a host 510 and an SSD 520. The SSD 520 exchanges signals SIG with the host 510 via a signal connector and receives power PWR via a power connector. The SSD 520 includes an SSD controller 521, an auxiliary power supply 522, and memory devices 523_1 to 523_n. The memory devices 523_1 to 523_n can be vertically stacked NAND flash memory devices. The SSD controller 521 can be connected to the memory devices 523_1 to 523_n via multiple channels Ch1 to Chn. In this case, the memory devices 523_1 to 523_n can each be configured according to the above reference. Figures 1 to 10 The described embodiments are implemented as follows. In other words, memory devices 523_1 to 523_n can each execute multiple programming loops during a write operation, and in at least two programming loops within the programming loops, programming operations can be performed without performing the two-step verification operation.

[0094] The SSD controller 521 may include error-correcting code (ECC) circuitry 521_1 and Advanced Encryption Standard (AES) circuitry 521_2. Furthermore, although not in... Figure 11 As shown, the SSD controller 521 may also include components such as a processor, buffer, random access memory (RAM), host interface, and memory interface for controlling the overall operation of the SSD 520.

[0095] ECC circuit 521_1 can perform ECC encoding and ECC decoding on data stored in or read from memory devices 523_1 to 523_n. For example, ECC circuit 521_1 can generate a parity check for detecting and correcting errors by ECC encoding the data to be written, and can perform error detection and correction operations based on the data read from memory devices 523_1 to 523_n and the parity check. Furthermore, AES circuit 521_2 can use various types of encryption / decryption algorithms (e.g., symmetric key algorithms) to perform at least one of encryption and decryption operations on data input to / output from SSD controller 521.

[0096] Figure 12 This is an embodiment of the concept of the present invention. Figure 2 A perspective view of an example implementation of a memory block.

[0097] refer to Figure 12 The memory block BLK is formed vertically relative to the substrate SUB. The substrate SUB has a first conductivity type (e.g., p-type), and a common source line CSL extending in a second horizontal direction HD2 and doped with impurities of a second conductivity type (e.g., n-type) is disposed in the substrate SUB. A plurality of insulating films IL extending in the second horizontal direction HD2 are sequentially arranged in the vertical direction VD on a region of the substrate SUB between two adjacent common source lines CSL, and the insulating films IL are spaced apart from each other in the vertical direction VD. For example, the insulating films IL may comprise an insulating material, such as silicon oxide.

[0098] Multiple pillars P, sequentially arranged in the second horizontal direction HD2 and penetrating the insulating film IL in the vertical direction VD, are disposed on the region of the substrate SUB between two adjacent common source lines CSL. For example, the pillars P can contact the substrate SUB by penetrating the insulating film IL. Specifically, the surface layer S of each pillar P may include a silicon-based material doped with impurities of a first conductivity type and serve as a channel region. On the other hand, the inner layer I of each pillar P may include an insulating material, such as silicon oxide or an air gap.

[0099] In the region between two adjacent common source lines CSL, a charge storage layer CS is disposed along the exposed surfaces of the insulating film IL, the pillar P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (also referred to as a "tunnel insulating layer"), a charge trapping layer, and a barrier insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Furthermore, in the region between the two adjacent common source lines CSL, gate electrodes GE, such as selected gate lines GSL and SSL, and word lines WL0 to WL7, are provided on the exposed surfaces of the charge storage layer CS.

[0100] Drains or drain contacts (DRs) are disposed on pillars P. For example, the drain or drain contact DR may comprise a silicon-based material doped with impurities of a second conductivity type. Bit lines BL0 to BL2, extending in a first horizontal direction HD1 and spaced apart from each other in a second horizontal direction HD2, may be disposed on the drain contacts DR.

[0101] Figure 13 This is a diagram illustrating a memory device 600 according to another example embodiment.

[0102] refer to Figure 13 The memory device 600 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) separately on a second wafer, and then bonding the upper and lower chips together. Here, the bonding process may include a method of electrically connecting bonding metals formed on the topmost metal layer of the upper chip and bonding metals formed on the topmost metal layer of the lower chip. For example, the bonding metal may include copper (Cu) using a copper-to-copper (Cu) bonding. However, the example embodiment is not limited to this. For example, the bonding metal may also be formed of aluminum (Al) or tungsten (W). For example, referenced above... Figures 1 to 12 The page buffer described can be set in the Peripheral Circuits Area (PERI).

[0103] Each of the peripheral circuit region PERI and cell region CELL of the memory device 600 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0104] The Peripheral Circuit Region (PERI) may include a first substrate 710, an interlayer insulating layer 715, a plurality of circuit elements 720a, 720b, and 720c formed on the first substrate 710, first metal layers 730a, 730b, and 730c respectively connected to the plurality of circuit elements 720a, 720b, and 720c, and second metal layers 740a, 740b, and 740c formed on the first metal layers 730a, 730b, and 730c. In an example embodiment, the first metal layers 730a, 730b, and 730c may be formed of tungsten, which has a relatively high resistivity, and the second metal layers 740a, 740b, and 740c may be formed of copper, which has a relatively low resistivity.

[0105] exist Figure 13 In the example embodiments shown, although only the first metal layers 730a, 730b, and 730c and the second metal layers 740a, 740b, and 740c are shown and described, the example embodiments are not limited thereto, and one or more additional metal layers may be further formed on the second metal layers 740a, 740b, and 740c. At least a portion of the one or more additional metal layers formed on the second metal layers 740a, 740b, and 740c may be formed of aluminum or the like, having a lower resistivity than the copper that forms the second metal layers 740a, 740b, and 740c.

[0106] An interlayer insulating layer 715 may be disposed on a first substrate 710 and cover a plurality of circuit elements 720a, 720b and 720c, first metal layers 730a, 730b and 730c and second metal layers 740a, 740b and 740c. The interlayer insulating layer 715 may include an insulating material, such as silicon oxide, silicon nitride, etc.

[0107] Lower bonding metals 771b and 772b can be formed on the second metal layer 740b in the word line bonding area (WLBA). In the WLBA, the lower bonding metals 771b and 772b in the peripheral circuit area (PERI) can be electrically bonded to the upper bonding metals 871b and 872b in the cell area (CELL). The lower bonding metals 771b and 772b, as well as the upper bonding metals 871b and 872b, can be formed of aluminum, copper, tungsten, or the like. Furthermore, the upper bonding metals 871b and 872b in the cell area (CELL) can be referred to as first metal pads, and the lower bonding metals 771b and 772b in the peripheral circuit area (PERI) can be referred to as second metal pads.

[0108] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 810 and a common source line 820. On the second substrate 810, multiple word lines 831 to 838 (i.e., 830) may be stacked in a direction perpendicular to the upper surface of the second substrate 810 (Z-axis direction). At least one string select line and at least one ground select line may be arranged above and below the multiple word lines 830, respectively, and the multiple word lines 830 may be positioned between the at least one string select line and the at least one ground select line.

[0109] In the bit line bonding area BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 810 (Z-axis direction) and pass through multiple word lines 830, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 850c and the second metal layer 860c. For example, the first metal layer 850c may be a bit line contact, and the second metal layer 860c may be a bit line. In an example embodiment, the bit line 860c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 810.

[0110] exist Figure 13 In the illustrated example embodiment, the area where the channel structure CH, bit line 860c, etc., are provided can be defined as a bit line bonding area BLBA. In the bit line bonding area BLBA, bit line 860c can be electrically connected to circuit element 720c that provides a page buffer 893 in the peripheral circuit area PERI. Bit line 860c can be connected to upper bonding metals 871c and 872c in the cell area CELL, and upper bonding metals 871c and 872c can be connected to lower bonding metals 771c and 772c of the circuit element 720c connected to the page buffer 893. In exemplary embodiments of this disclosure, bit lines can be connected to the page buffer 893, and various setup operations can be performed on the bit lines to perform normal programming and forced programming. Furthermore, according to embodiments of this disclosure, in order to perform a two-step verification operation, data read based on a first threshold voltage and data read based on a second threshold voltage can be provided to the page buffer 893 via the bit lines. That is, in programming loops where verification operations are skipped, data read based on the first and second threshold voltages is not provided to the page buffer 893.

[0111] In the Word Line Bonding Area (WLBA), multiple word lines 830 can extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 810 and perpendicular to the first direction, and can be connected to multiple cell contact plugs 841 to 847 (i.e., 840). The multiple word lines 830 and the multiple cell contact plugs 840 can be connected to each other in pads provided by at least a portion of the multiple word lines 830 extending in the second direction at different lengths. A first metal layer 850b and a second metal layer 860b can be sequentially connected to the multiple cell contact plugs 840 connected to the multiple word lines 830. The multiple cell contact plugs 840 can be connected to the peripheral circuit area PERI via upper bonding metals 871b and 872b of the cell area CELL in the Word Line Bonding Area (WLBA) and lower bonding metals 771b and 772b of the peripheral circuit area PERI.

[0112] Multiple unit contact plugs 840 may be electrically connected to circuit elements 720b forming a line decoder 894 in the peripheral circuitry region PERI. In an example embodiment, the operating voltage of circuit elements 720b of the line decoder 894 may differ from the operating voltage of circuit elements 720c forming a page buffer 893. For example, the operating voltage of circuit elements 720c forming a page buffer 893 may be greater than the operating voltage of circuit elements 720b forming a line decoder 894.

[0113] A common source line contact plug 880 can be disposed in the external pad bonding region PA. The common source line contact plug 880 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 820. A first metal layer 850a and a second metal layer 860a can be sequentially stacked on the common source line contact plug 880. For example, the region where the common source line contact plug 880, the first metal layer 850a, and the second metal layer 860a are disposed can be defined as the external pad bonding region PA.

[0114] Input-output pads 705 and 805 can be set in the external pad bonding area PA. (See reference) Figure 13 A lower insulating film 701 covering the lower surface of the first substrate 710 may be formed below the first substrate 710, and a first input-output pad 705 may be formed on the lower insulating film 701. The first input-output pad 705 can be connected to at least one of a plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI via a first input-output contact plug 703, and can be separated from the first substrate 710 via the lower insulating film 701. Furthermore, a side insulating film may be disposed between the first input-output contact plug 703 and the first substrate 710 to electrically isolate the first input-output contact plug 703 and the first substrate 710.

[0115] refer to Figure 13 An upper insulating film 801 covering the upper surface of the second substrate 810 can be formed on the second substrate 810, and a second input-output pad 805 can be disposed on the upper insulating layer 801. The second input-output pad 805 can be connected to at least one of a plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI via a second input-output contact plug 803. In an example embodiment, the second input-output pad 805 is electrically connected to circuit element 720a.

[0116] According to the embodiment, the second substrate 810 and the common source line 820 are not disposed in the region where the second input-output contact plug 803 is disposed. Furthermore, the second input-output pad 805 does not overlap with the word line 830 in the third direction (Z-axis direction). Reference Figure 13 The second input-output contact plug 803 can be separated from the second substrate 810 in a direction parallel to the upper surface of the second substrate 810, and can pass through the interlayer insulation layer 815 of the cell region to connect to the second input-output pad 805.

[0117] According to embodiments, the first input-output pad 705 and the second input-output pad 805 can be selectively formed. For example, the memory device 600 may include only the first input-output pad 705 disposed on the first substrate 710 or the second input-output pad 805 disposed on the second substrate 810. Alternatively, the memory device 600 may include both the first input-output pad 705 and the second input-output pad 805.

[0118] In each of the external pad bonding area PA and bit line bonding area BLBA included in the cell area CELL and peripheral circuit area PERI respectively, the metal pattern provided on the topmost metal layer can be provided as a dummy pattern, or the topmost metal layer may not exist.

[0119] In the external pad bonding area PA, the memory device 600 may include a lower metal pattern 773a corresponding to an upper metal pattern 872a formed in the uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern 872a of the cell region CELL in the uppermost metal layer of the peripheral circuit region PERI, so as to be connected to each other. In the peripheral circuit region PERI, the lower metal pattern 773a formed in the uppermost metal layer of the peripheral circuit region PERI is not connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern 872a corresponding to the lower metal pattern 773a formed in the uppermost metal layer of the peripheral circuit region PERI and having the same shape as the lower metal pattern 773a of the peripheral circuit region PERI may be formed in the uppermost metal layer of the cell region CELL.

[0120] Lower bonding metals 771b and 772b can be formed on the second metal layer 740b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 771b and 772b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 871b and 872b of the cell region CELL via copper-to-copper bonding.

[0121] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 892, corresponding to the lower metal pattern 752 formed in the uppermost metal layer of the peripheral circuit region PERI and having the same cross-sectional shape as the lower metal pattern 752 of the peripheral circuit region PERI, can be formed in the uppermost metal layer of the cell region CELL. No contacts are formed on the upper metal pattern 892 formed in the uppermost metal layer of the cell region CELL.

[0122] In an example embodiment, a reinforcing metal pattern having the same cross-sectional shape as the metal pattern formed in the uppermost metal layer of one of the cell region (CELL) and the peripheral circuit region (PERI) can be formed in the uppermost metal layer of the other. In this embodiment, no contact is formed on the reinforcing metal pattern.

[0123] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, comprising: A memory cell array, comprising multiple memory cells; A voltage generator is configured to generate voltages for programming and verification operations of the memory cells; as well as The control logic is configured to execute multiple programming loops while writing data to the memory cell array, such that a first programming loop to an Nth programming loop, comprising programming and verification operations, are executed, and when a pass / fail determination indication for the programming operation in the Nth programming loop passes, at least two programming loops in which the verification operation is skipped are executed. Where N is an integer equal to or greater than 1. The at least two programming cycles include a (N+1)th programming cycle, which includes a normal programming operation on a first memory cell in the memory cells using a normal programming voltage, and a forced programming operation on a second memory cell in the memory cells using a forced programming voltage.

2. The memory device according to claim 1, wherein, The at least two programming loops also include: The (N+2)th programming cycle includes a forced programming operation on the first memory cell using a forced programming voltage.

3. The memory device according to claim 2, wherein, The control logic is configured to: control the voltage generator to generate voltages for programming and verification operations in the first to Nth programming cycles, and The voltage generator is controlled to selectively generate the voltage used in the programming operations of the at least two programming cycles.

4. The memory device according to claim 2, wherein, The verification operation includes: operations for determining coarse on-state and coarse off-state units based on a first threshold voltage, and operations for determining fine on-state and fine off-state units based on a second threshold voltage. The second threshold voltage is greater than the first threshold voltage.

5. The memory device according to claim 4, wherein, A memory cell having a threshold voltage level lower than the first threshold voltage corresponds to the first memory cell, and a memory cell having a threshold voltage level greater than the first threshold voltage and less than the second threshold voltage corresponds to the second memory cell.

6. The memory device according to claim 4, wherein, The pass / fail determination is performed by counting the number of memory cells with a threshold voltage level lower than the first threshold voltage or the number of memory cells with a threshold voltage level lower than the second threshold voltage.

7. The memory device of claim 1, further comprising a page buffer connected to the memory cell array via multiple bit lines. in, The page buffer receives data related to the verification operations in the first to the Nth programming cycles, read from the memory cell array via bit lines, and In the at least two programming loops, the operation of providing data to the page buffer via bit lines is skipped.

8. A method of operating a memory device, the method comprising: Execute the Nth programming loop, which includes programming operations and verification operations, where N is an integer equal to or greater than 1; The success or failure of the programming operation is determined by counting the number of memory cells in a memory device with a threshold voltage level below a predetermined threshold voltage. When it is determined that the programming operation is successful, the (N+1)th programming cycle is executed, the (N+1)th programming cycle including a normal programming operation on a first memory cell in the memory cells using a normal programming voltage, and a forced programming operation on a second memory cell in the memory cells using a forced programming voltage; and Execute the (N+2)th programming cycle, which includes a forced programming operation on the first memory cell using a forced programming voltage. In each of the (N+1)th and (N+2)th programming loops, the verification operation is skipped.

9. The method according to claim 8, wherein, The verification operations performed in the Nth programming loop include: operations for determining coarse on-cell and coarse off-cell units based on a first threshold voltage, and operations for determining fine on-cell and fine off-cell units based on a second threshold voltage. The second threshold voltage is greater than the first threshold voltage.

10. The method according to claim 9, wherein, A memory cell having a threshold voltage level lower than the first threshold voltage corresponds to the first memory cell, and a memory cell having a threshold voltage level greater than the first threshold voltage and less than the second threshold voltage corresponds to the second memory cell.

11. The method according to claim 9, wherein, The determination of whether the programming operation succeeds or fails is performed by counting the number of memory cells with a threshold voltage level lower than the first threshold voltage or the number of memory cells with a threshold voltage level lower than the second threshold voltage.

12. The method of claim 8, further comprising, in the operation of determining whether the programming operation is successful or failed, when it is determined that the programming operation is a failure, Before executing the (N+1)th programming loop, at least one additional programming loop, including programming operations and verification operations, is executed.

13. The method according to claim 8, wherein, Each of the memory cells is connected to a word line and a bit line, and The voltage level difference between the word line and bit line of the memory cell to which the normal programming operation is performed is greater than the voltage level difference between the word line and bit line of the memory cell to which the forced programming operation is performed.

14. The method according to claim 13, wherein, During the forced programming operation, a voltage of the same level as the voltage applied to the word line during the normal programming operation is provided to the word line, and a voltage of a higher level than the voltage set to the bit line during the normal programming operation is provided to the bit line.

15. The method according to claim 8, wherein, The operation used to determine whether the programming operation is successful or failed is executed in parallel with the normal programming operation or the forced programming operation in the (N+1)th programming loop.

16. The method according to claim 8, wherein, The memory device includes a page buffer, and when the verification operation is performed in the Nth programming loop, data read from the memory cell is provided to the page buffer, and... When the verification operation is skipped in each of the (N+1)th and (N+2)th programming loops, data is not provided to the page buffer.

17. A method of operating a memory device, the method comprising: The first programming cycle is executed to the Nth programming cycle, each programming cycle including programming operations and verification operations for memory cells of the memory device, where N is an integer equal to or greater than 2; The success or failure of the programming operation is determined based on the programming result in the Nth programming loop; and... When the programming operation is determined to be successful, programming loops (N+1) through (N+A) are executed, excluding verification operations for the memory cell, where A is an integer equal to or greater than 2. In each of the (N+1)th to (N+A)th programming cycles, at least one of a normal programming operation using a normal programming voltage and a forced programming operation using a forced programming voltage is performed.

18. The method according to claim 17, wherein, The memory cell corresponds to a multi-level cell, and each of the programming loops includes a programming operation for programming the memory cell into multiple threshold voltage states, and... In each of the (N+1)th to (N+A)th programming cycles, a verification operation associated with at least one of the threshold voltage states is skipped.

19. The method of claim 17, wherein, The verification operation in the Nth programming loop determines a first memory cell with a threshold voltage level lower than the first threshold voltage and a second memory cell with a threshold voltage level greater than the first threshold voltage and less than the second threshold voltage.

20. The method according to claim 19, wherein, The programming loops from the (N+1)th to the (N+A)th include: A programming loop for performing normal programming operations on the first memory cell and forced programming operations on the second memory cell; and A programming loop for performing the forced programming operation on the first memory cell.

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